Query Method, Device, Electronic Device and Storage Medium for Interruption Information

Abstract

The present invention discloses a method, apparatus, electronic device, and storage medium for querying interruption information, relating to the field of computer technologies, including: classifying the obtained interruption signals according to categories and storing them in interruption aggregation register devices corresponding to the categories, detecting at least one interruption aggregation register device based on a preset polling mechanism, if an interruption event is detected, locating the target interruption aggregation register device and the target interruption event corresponding to the interruption event, and obtaining the interruption information source of the target interruption event by using an interruption detailed information register device. It solves the problems such as resource waste, poor real-time performance of interruption query, and low accuracy caused by querying all interruption signals based on a fixed polling mechanism. By detecting each interruption aggregation register device based on a polling mechanism that adjusts the polling period according to the interruption frequency, resource occupancy can be reduced and detection accuracy can be improved, so as to find the best balance between resource occupancy and real-time requirements.

Description

Technical Field

[0001] The present invention relates to the field of computer technologies, and in particular, to a method, apparatus, electronic device, and storage medium for querying interrupt information. Background Art

[0002] In modern computers and embedded systems, the interrupt mechanism is one of the core technologies for realizing efficient task scheduling and event response. Especially in devices such as switches and network cards, CPLD (Complicated Programmable Logic Device) or FPGA (Field Programmable Gate Array), as underlying devices, are important components of switches, responsible for managing interrupt signals of various peripherals and transmitting them to the upper-layer system. The interrupt processing method affects the reliability and performance of the upper-layer system.

[0003] In related technologies, the interrupt processing method usually adopts a polling mechanism, that is, the underlying device directly transmits the interrupt signal to the upper-layer system, and the upper-layer system determines whether an interrupt occurs by periodically querying the status of the underlying device.

[0004] However, the above polling interrupt processing method has the following problems: (1) High upper-layer system resource occupancy: The underlying device directly transmits the interrupt signal to the upper-layer system, and the upper-layer system queries the interrupt status through the polling mechanism, which will occupy a large amount of CPU (Central Processor Unit) resources; (2) Poor real-time performance: If the polling period is too long, fast-changing interrupt signals may be missed, resulting in a decline in the performance of the upper-layer system, which urgently needs to be solved. Summary of the Invention

[0005] The present invention provides a method, apparatus, electronic device, and storage medium for querying interrupt information, so as to at least solve the technical problems such as waste of CPU resources, poor real-time performance of interrupt query, and low accuracy caused by querying the interrupt status of all interrupt signals based on a fixed polling mechanism in related technologies.

[0006] The present invention provides a method for querying interrupt information, including:

[0007] Obtaining at least one interrupt signal, classifying based on the category of each interrupt signal, and storing them separately in corresponding interrupt aggregation register devices;

[0008] Based on a preset polling mechanism, detecting at least one interrupt aggregation register device to determine whether there is an interrupt event in at least one interrupt aggregation register device;

[0009] If there is an interrupt event in at least one interrupt aggregation register device, locate the target interrupt aggregation register device corresponding to the interrupt event, locate the target interrupt event in the target interrupt aggregation register device, and use the interrupt detail information register device to obtain the interrupt information source of the target interrupt event.

[0010] The present invention also provides an interrupt information query device, including:

[0011] A first acquisition module, configured to acquire at least one interrupt signal, classify the interrupt signals based on the category of each interrupt signal, and store them in the interrupt aggregation register devices corresponding to the respective categories.

[0012] A judgment module, configured to detect at least one interrupt aggregation register device based on a preset polling mechanism, and judge whether there is an interrupt event in the at least one interrupt aggregation register device.

[0013] A second acquisition module, configured to, if there is an interrupt event in at least one interrupt aggregation register device, locate the target interrupt aggregation register device corresponding to the interrupt event, locate the target interrupt event in the target interrupt aggregation register device, and use the interrupt detail information register device to obtain the interrupt information source of the target interrupt event.

[0014] The present invention also provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of any of the above-mentioned interrupt information query methods when executing the computer program.

[0015] The present invention also provides a computer-readable storage medium, in which a computer program is stored, and wherein the computer program implements the steps of any of the above-mentioned interrupt information query methods when executed by a processor.

[0016] The present invention also provides a computer program product, including a computer program, and the computer program implements the steps of any of the above-mentioned interrupt information query methods when executed by a processor.

[0017] With the present invention, since the obtained interrupt signals are classified according to categories and stored in the corresponding interrupt aggregation register devices respectively, and based on a preset polling mechanism, at least one interrupt aggregation register device is detected. If an interrupt event is detected in at least one interrupt aggregation register device, the target interrupt aggregation register device and the target interrupt event corresponding to the interrupt event are located, and the interrupt information source of the target interrupt event is obtained by using the interrupt detail information register device. This solves the technical problems such as waste of CPU resources, poor real-time performance of interrupt query, and low accuracy caused by querying the interrupt status of all interrupt signals based on a fixed polling mechanism. By introducing a polling mechanism that adjusts the polling period based on the interrupt frequency to detect each category of interrupt aggregation register devices, resource occupancy is reduced and detection accuracy is improved, so as to find the best balance between resource occupancy and real-time requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] To more clearly illustrate the embodiments of the present invention, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 It is a flowchart of a method for querying interrupt information provided by an embodiment of the present invention;

[0020] Figure 2 It is a signal transmission schematic diagram of interrupt aggregation classification and status record query according to an embodiment of the present invention;

[0021] Figure 3 It is a block diagram example of a device for querying interrupt information according to an embodiment of the present invention;

[0022] Figure 4 It is a schematic structural diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0024] It should be noted that in the description of the present invention, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0025] In order to enable those skilled in the art of the present technology to better understand the solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0026] An embodiment of the present invention provides a method for querying interruption information. The method will be described in detail in combination with the execution flow of the method for querying interruption information.

[0027] Before introducing the embodiments of the present invention, first introduce the relevant technical background of the present invention. CPLD / FPGA is a semi-custom application-specific integrated circuit, which has a series of advantages such as flexible programming, fast response, and high integration. It has been more and more widely used in the fields of national defense, computers, switches, vehicles, and AI (Artificial Intelligence) for pre-development verification and control applications. In a switch system, the entire data layer management of the switch system is mainly implemented through CPLD / FPGA, including I2C (Inter-Integrated Circuit) devices, MDC (Modular Digital Converter) / MDIO (Management Data Input / Output) devices, SPI (Serial Peripheral Interface) devices, etc. Among them, CPLD / FPGA is an important part of the switch and also an important part in aspects such as collecting and reporting underlying device information. The way of interrupt handling is an important part affecting the reliability and performance of the system. The way of interrupt aggregation and reporting is an important content of CPLD / FPGA design, which affects the interrupt handling speed and efficiency of the entire switch system. Therefore, the embodiments of the present invention detect each type of interrupt aggregation register device by introducing a polling mechanism based on adjusting the polling period according to the interrupt frequency, thereby reducing resource occupancy and improving detection accuracy, so as to find the best balance between resource occupancy and real-time requirements.

[0028] Specifically, Figure 1 It is a schematic flow chart of a method for querying interruption information provided by an embodiment of the present invention.

[0029] As Figure 1 shown, the method for querying the interrupt information includes the following steps:

[0030] In step S101, at least one interrupt signal is obtained, classified based on the category of each interrupt signal, and respectively stored in the interrupt aggregation register device corresponding to the category.

[0031] Specifically, in the embodiment of the present invention, it mainly includes two parts: interrupt aggregation classification and status record query. Among them, interrupt aggregation classification refers to classifying and summarizing the obtained interrupt signals, and respectively storing the same-type interrupt signals in the interrupt aggregation register device corresponding to the category. The interrupt aggregation register device is a register dedicated to summarizing the interrupt status, used to implement the "OR" operation of all the same-type interrupts, that is, in the same category, any one of the interrupt signals will be recorded in the corresponding interrupt aggregation register device; status record query refers to accessing the interrupt signal status information in various register devices, log files, databases or other data storage media to obtain the target interrupt aggregation register device with an interrupt event and the target interrupt event in the target interrupt aggregation register device, and recording and querying the interrupt information source of the target interrupt event, so as to effectively monitor, fault diagnose and optimize the performance of the preset upper-layer system.

[0032] Specifically, as Figure 2 shown, the embodiment of the present invention is based on the logic design of CPLD / FPGA. The related logic devices mainly include an interrupt aggregation register device (interrupt aggregation register), an interrupt status register device (interrupt status register), and an interrupt change register device (interrupt change register). To solve the technical problems such as waste of CPU resources, poor real-time performance of interrupt query, and low accuracy caused by querying the interrupt status of all interrupt signals based on a fixed polling mechanism, the embodiment of the present invention classifies based on at least one obtained interrupt signal, and respectively stores each type of interrupt signal in the interrupt aggregation register device corresponding to the category. At this time, only a few interrupt aggregation register devices need to be polled and detected, avoiding the preset upper-layer system from polling to obtain all interrupt signals, thereby reducing the resource occupancy of the preset upper-layer system and improving the query efficiency. At the same time, the interrupt aggregation classification and status record query mechanism involved in the embodiment of the present invention can make the classification of interrupt signals clearer, and at the same time avoid repeated polling through a few interrupt aggregation register devices, I / O or the mechanism of in-band transfer of interrupts.

[0033] In step S102, based on a preset polling mechanism, at least one interrupt aggregation register device is detected to determine whether there is an interrupt event in the at least one interrupt aggregation register device.

[0034] Among them, the preset polling mechanism can be set by those skilled in the art based on actual test requirements, or obtained through a limited number of computer simulations, and specific limitations are not made here.

[0035] Specifically, as Figure 2 shown, in the embodiment of the present invention, the preset upper-layer system can synthesize all the obtained interrupt signals into one signal and transmit it through I / O (Input / Output) or in-band interrupt, or communicate through protocols such as I2C, LPC (Low Pin Count), SPI, PCIe (Peripheral Component Interconnect Express), etc. Specific limitations are not made here. Thus, the preset upper-layer system can communicate with the CPLD / FPGA based on the above information communication method, detect at least one interrupt aggregation register device through the preset polling mechanism, and determine whether there is an interrupt event in at least one interrupt aggregation register device. Thus, when it is detected that there is an interrupt event in at least one interrupt aggregation register device, further locate the target interrupt aggregation register device where the interrupt event exists. Among them, the target interrupt aggregation register device where the interrupt event exists can be one or multiple, and scan the detailed information of the target interrupt event in the target interrupt aggregation register device, and the interrupt information source of the target interrupt event can be obtained. The following will specifically introduce related implementation manners.

[0036] According to an embodiment of the present invention, detecting at least one interrupt aggregation register device based on a preset polling mechanism includes: respectively setting a preset initial polling mechanism for each interrupt aggregation register device based on the design requirements and functional characteristics of the preset upper-layer system and the type of the interrupt aggregation register device; monitoring the interrupt frequency of the interrupt event in each interrupt aggregation register device, and dynamically adjusting the preset initial polling mechanism according to the interrupt frequency; obtaining the preset polling mechanism based on the dynamically adjusted preset initial polling mechanism.

[0037] According to an embodiment of the present invention, dynamically adjusting the preset initial polling mechanism according to the interrupt frequency includes: determining whether the interrupt frequency is greater than a preset frequency threshold; if the interrupt frequency is greater than the preset frequency threshold, shorten the preset initial polling mechanism, otherwise, extend the preset initial polling mechanism.

[0038] Among them, the preset upper-layer system, the preset initial polling mechanism, and the preset frequency threshold can all be set by those skilled in the art based on actual test requirements, and specific limitations are not made here.

[0039] Specifically, since different preset upper-layer systems may have different design requirements, such as real-time requirements and resource limitations of the upper-layer system, embodiments of the present invention can respectively set the preset initial polling mechanism for each interrupt aggregation register device based on the design requirements and functional characteristics of the preset upper-layer system and the type of the interrupt aggregation register device, so as to meet the design requirements and functional characteristics of different preset upper-layer systems, and improve the performance and reliability of the preset upper-layer system. At the same time, in order to quickly respond to high-frequency interrupts, avoid missed reports or delays, and reduce resource consumption, embodiments of the present invention can use an interrupt frequency monitoring algorithm (such as time interval statistics method, adaptive threshold algorithm, etc.) to monitor the interrupt frequency of interrupt events in each interrupt aggregation register device, and dynamically adjust the preset initial polling mechanism based on the interrupt frequency of interrupt events in each interrupt aggregation register device, so as to avoid that in a high-frequency interrupt scenario, a fixed polling period may cause system overload, thus affecting stability, and at the same time avoid that in a low-frequency interrupt scenario, a fixed polling period may cause CPU resource waste. Therefore, dynamically adjusting the preset initial polling mechanism can reduce unnecessary resource consumption while ensuring real-time performance by optimizing the polling period in real time, can more accurately reflect the actual requirements, reduce the risk of misjudgment caused by a fixed polling period, and finally obtain the optimal preset polling mechanism based on the dynamically adjusted preset initial polling mechanism.

[0040] Among them, if the interrupt frequency is greater than the preset frequency threshold, that is, a scenario that requires quick response (such as high-speed data acquisition or real-time control), at this time, the polling period can be shortened to ensure timely capture of interrupt events. If the interrupt frequency is less than or equal to the preset frequency threshold, that is, for low-frequency or infrequent interrupt events, the polling period can be appropriately extended, so as to reduce the number of CPU queries and resource consumption, so as to flexibly balance resource occupancy and real-time requirements in different scenarios and achieve the optimization of system performance.

[0041] For example, taking the state change of a switch port as an example, since the state change of the switch port may be relatively frequent in the case of large network traffic, therefore, its preset initial polling mechanism can be set to 10 ms / time. If it is detected that the state change frequency of the switch port is high (such as more than 10 times per second), at this time, the preset initial polling mechanism can be shortened to 5 ms / time. If the state change frequency of the switch port is low (such as less than 1 time per second), the preset initial polling mechanism can be extended to 20 ms / time. Thus, by monitoring the interrupt frequency in real time and flexibly adjusting the query frequency, the preset upper-layer system can better adapt to different application scenarios and load changes, thereby improving the overall performance and user experience.

[0042] According to an embodiment of the present invention, after detecting at least one interrupt aggregation register device based on a preset polling mechanism, it further includes: determining whether a preset interrupt signal is monitored; if the preset interrupt signal is monitored, the preset interrupt signal is recorded and stored based on an interrupt edge recording register device.

[0043] Among them, the preset interrupt signal can be a rapidly changing interrupt signal. Rapidly changing interrupt signals often have a high frequency or a short pulse width. Such signals may come from external sensors, clock sources, or other high-speed devices, and specific rapidly changing interrupt signals can be identified based on the detection experience of historical data.

[0044] Specifically, to avoid missing rapidly changing interrupt signals due to the low detection frequency of the preset polling mechanism, the present invention realizes the rapid change recording of some interrupt signals based on CPLD / FPGA. The interrupt edge recording register device can be set through CPLD / FPGA. The interrupt edge recording register device records the rapidly changing interrupt signals and stores the detailed information of the rapidly changing interrupt signals in the corresponding interrupt detailed information register device. The interrupt edge recording register device is a hardware register specifically used to capture the edge changes (rising edge or falling edge) of signals. When the input signal undergoes an edge change, the edge recording register automatically records the event and saves the detailed information of each edge event (such as timestamp and status) to provide complete data for subsequent analysis. Then, through an interrupt or other mechanisms, it notifies the target upper-layer system for further processing, thereby realizing the capture of the edge events of rapidly changing interrupt signals, ensuring that no important state changes are missed. At the same time, the interrupt edge recording register device can work automatically in the background without the CPU frequently querying the signal status, thereby reducing system resource consumption.

[0045] According to an embodiment of the present invention, determining whether there is an interrupt event in at least one interrupt aggregation register device includes: determining whether the value of at least one interrupt aggregation register device is a preset value; if the value of at least one interrupt aggregation register device is the preset value, it is determined that there is an interrupt event in at least one interrupt aggregation register device.

[0046] Among them, the preset value can be set by those skilled in the art based on actual test requirements or obtained through a limited number of computer simulations, and no specific limitation is made here.

[0047] Specifically, after detecting at least one interrupt aggregation register device through a preset polling mechanism in an embodiment of the present invention, it is necessary to further determine whether there is an interrupt event in the at least one interrupt aggregation register device. The interrupt status register device can be used to identify the interrupt aggregation register device where the interrupt event occurs. Therefore, first, read the values of the at least one interrupt aggregation register device through the interrupt status register device; secondly, determine whether the values of the at least one interrupt aggregation register device are preset values (such as 1). If the values of the at least one interrupt aggregation register device are preset values, it can be determined that there is an interrupt event in the at least one interrupt aggregation register device. That is to say, when the values of the at least one interrupt aggregation register device are 1, it can be determined that there is an interrupt event in the at least one interrupt aggregation register device. At this time, if an interrupt event is detected, the preset upper-layer system obtains the interrupt event through the interrupt aggregation register device, I / O, or in-band transfer interrupt, and immediately enters the interrupt processing flow. If no interrupt event is detected, other tasks are continued to be executed or the low-power mode is entered.

[0048] For example, as an implementable method, based on non-zero detection, if the values of the at least one interrupt aggregation register device are 1, it means that the at least one interrupt aggregation register device has triggered an interrupt. At this time, it can be indicated that there is an interrupt event in the at least one interrupt aggregation register device.

[0049] As another implementable method, for bitwise operation, bitwise logical operations (such as OR or AND) can be used to quickly detect the status of a specific interrupt aggregation register device.

[0050] Thus, by quickly detecting the status of the at least one interrupt aggregation register device, the preset upper-layer system can determine whether there is an interrupt event in the at least one interrupt aggregation register device in the shortest time, so as to respond in a timely manner, reduce the number of queries, and reduce the CPU load.

[0051] It should be noted that in a multi-task environment, the preset upper-layer system can also quickly determine whether there is an interrupt event through the interrupt aggregation register device and give priority to processing high-priority tasks.

[0052] In step S103, if there is an interrupt event in the at least one interrupt aggregation register device, locate the target interrupt aggregation register device corresponding to the interrupt event, locate the target interrupt event in the target interrupt aggregation register device, and obtain the interrupt information source of the target interrupt event by using the interrupt detailed information register device.

[0053] Among them, the target interrupt aggregation register device is the interrupt aggregation register device where the interrupt event occurs, and the target interrupt event is the specific interrupt event existing in the target interrupt aggregation register device.

[0054] Specifically, when an interrupt event is detected in at least one interrupt aggregation register device, it indicates that during the detection of at least one interrupt aggregation register device based on a preset polling mechanism, the value of at least one interrupt aggregation register device is detected as 1, that is, there is an interrupt event in at least one interrupt aggregation register device. At this time, it is necessary to further locate the corresponding interrupt aggregation register device with the interrupt event, that is, to locate the target interrupt aggregation register device. After locating the target interrupt aggregation register device, further use the interrupt detail information register device to obtain the interrupt information source of the target interrupt event in the target interrupt aggregation register device, that is, to obtain the detailed information of the target interrupt information.

[0055] According to an embodiment of the present invention, locating the target interrupt aggregation register device corresponding to the interrupt event includes: obtaining the interrupt type of the interrupt event, the interrupt timestamp of the interrupt event, and the data information of the interrupt event; determining the target address of the interrupt aggregation register device according to the interrupt type, the timestamp of the interrupt event, and the data information of the interrupt event, so as to locate the target interrupt aggregation register device according to the target address.

[0056] Specifically, during the process of locating the target interrupt aggregation register device corresponding to the interrupt event, first, the interrupt type of the interrupt event can be obtained based on the interrupt type information carried by the interrupt signal itself; second, when the interrupt event occurs, the value of the hardware timer is written into the interrupt timestamp register device, and the relevant hardware devices also write the relevant data information of the interrupt event into a specific data register device. At this time, the preset upper-layer system reads the interrupt timestamp register device to obtain the interrupt timestamp of the interrupt event, and at the same time, queries the corresponding data register device according to the interrupt type of the interrupt event to obtain the data information of the interrupt event, such as the sensor value or link state of the interrupt event, etc., so as to determine the target address of the interrupt aggregation register device according to the interrupt type, timestamp, and data information of the interrupt event, and locate the target interrupt aggregation register device with the interrupt event according to the target address. This target address is the target address of the target interrupt aggregation register device.

[0057] Further, to ensure the accuracy of identifying the target interrupt aggregation register device with an interrupt event, after the embodiment of the present invention locates the target interrupt aggregation register device with an interrupt event, it can be further verified. For example, a hardware simulation tool (such as an FPGA development board or an embedded emulator) can be used to simulate the interrupt event to verify whether the behavior of the target interrupt aggregation register device meets the expectations. Or, at the software level, verification is performed by verifying the read / write and status consistency of the target interrupt aggregation register device. When performing read / write verification, read / write operations can be performed on the target interrupt aggregation register device to verify whether its behavior meets the expectations. When performing status consistency verification, after triggering an interrupt, check whether the status of the target interrupt aggregation register device is consistent with the actual interrupt source. If a certain GPIO (General Purpose Input / Output) pin triggers an interrupt, confirm that the relevant bit in the corresponding interrupt aggregation register device is set to 1. At this time, based on the above verification method, the accuracy of the target interrupt aggregation register device with an interrupt event can be determined.

[0058] Optionally, if an error occurs in the target interrupt aggregation register device identified with an interrupt event, re-detection can be performed through error handling or a fault tolerance mechanism at this time. For example, if two target interrupt aggregation register devices report the same interrupt source at the same time, it may be necessary to re-check the hardware connection or software configuration. Or, in the case of a failed identification, an automatic retry mechanism can be implemented to ensure correctness, and record the process and results of each interrupt identification for subsequent analysis and debugging.

[0059] It should be noted that the above verification mechanism is only exemplary, and the specific verification mechanism selection can be determined based on actual test requirements and is not specifically limited herein.

[0060] Thus, by accurately locating the target interrupt aggregation register device with an interrupt event, it is possible to quickly enter the corresponding interrupt service program, shorten the interrupt response time, improve the real-time performance of the system, and avoid misjudgment or omission of interrupt events, ensuring that the preset upper-layer system correctly responds to all interrupts.

[0061] According to an embodiment of the present invention, locating the target interrupt event in the target interrupt aggregation register device includes: detecting the interrupt signal status of each bit in the target interrupt aggregation register device; determining whether the interrupt signal status is a preset status; if the interrupt signal status is the preset status, obtaining the target interrupt event in the target interrupt aggregation register device based on the interrupt signal status.

[0062] Among them, the preset status can be set by those skilled in the art based on actual test requirements or obtained through a limited number of computer simulations, and is not specifically limited herein.

[0063] Specifically, after locating the target interrupt convergence register device where an interrupt event exists, to achieve refined identification of the interrupt event, the embodiments of the present invention need to further locate the target interrupt event in the target interrupt convergence register device, so as to accurately identify the status of each interrupt signal, avoid omission or misjudgment. At the same time, only processing the target interrupt events that meet the preset status can also reduce unnecessary query operations and lower the CPU load.

[0064] Specifically, the target interrupt convergence register device is a register that summarizes the statuses of multiple interrupt signals. Each bit usually corresponds to an interrupt signal. First, by reading the value of the target interrupt convergence register device, check the status of the interrupt signal for each bit of the target interrupt convergence register device one by one, and then determine which interrupt signals have triggered the interrupt event. Secondly, determine whether the status of the interrupt signal is the preset status, that is, whether the status of the interrupt signal is 1. If the status of the interrupt signal is 1, it indicates that there is an interrupt at this bit, that is, there is a target interrupt event. Finally, since each target interrupt event corresponds to an interrupt detailed information register device to store the detailed information of the target interrupt event. At the same time, the present invention can implement the mapping of writing to the interrupt detailed information register device through a read-only memory, so that the preset upper-layer system can obtain the detailed information of the written target interrupt event. Therefore, according to the position or identifier of this bit, further use the interrupt detailed information register device to obtain the interrupt information source of this target interrupt event, that is, the detailed information of this target interrupt event (such as interrupt type, timestamp, data information, etc.), so as to accurately locate and process the specific target interrupt event. Among them, the interrupt detailed information register device includes two parts: an interrupt status register device and an interrupt record register device, to record information such as the detailed information, interrupt status, and interrupt record of the interrupt information source of the target interrupt event.

[0065] It should be noted that if there are multiple interrupt signals in the target interrupt convergence register device that simultaneously meet the preset status, they can be processed according to the priority order of each interrupt signal. For example, a hardware priority mechanism or a software scheduling algorithm can be used. At the same time, in a multitasking environment, it is also necessary to ensure data consistency between the interrupt handling program and the main program. Mutex locks or disabling interrupts can be used to protect shared resources.

[0066] Thus, by checking the status of the interrupt signals in the target interrupt convergence register device bit by bit, accurately identifying the status of each interrupt signal, it is possible to accurately identify which bit in the target interrupt convergence register device has an interrupt and correspond it to a specific target interrupt event. Then, according to the interrupt detailed information register device corresponding to this target interrupt event, obtain the detailed information of the target interrupt event, improving the stability and robustness of the preset upper-layer system.

[0067] According to one embodiment of the present invention, after obtaining the interrupt information source of the interrupt event using the interrupt detailed information storage device, it also includes: judging whether the interrupt information source is recorded successfully; if the interrupt information source is recorded successfully, writing a clear instruction to the interrupt clearing storage device according to the target interrupt aggregation storage device; based on the clear instruction, clearing the interrupt information source in the target interrupt aggregation storage device using the interrupt clearing storage device.

[0068] Specifically, in the embodiment of the present invention, after the interruption detailed information storage device obtains the interruption information source of the interruption event, it is necessary to actively clear the content of the target interruption aggregation storage device to ensure that the target interruption aggregation storage device can be recycled to provide space for the next interruption record.

[0069] Specifically, first, after obtaining the interrupt information source of the interrupt event, the CPLD / FPGA records and saves it to the interrupt detailed information storage device, that is, the interrupt record storage device in the interrupt detailed information storage device records it, and after the interrupt information source is successfully recorded, space is provided for the next interrupt record to ensure that the interrupt record storage device can record the next interrupt. The preset upper system needs to determine the address of the interrupt record storage device that has been successfully recorded, and after determining the address of the interrupt record storage device that has been successfully recorded, write a clear instruction to the interrupt clearing storage device according to the target interrupt aggregation storage device. Based on the clear instruction, the interrupt clearing storage device is used to clear the interrupt information source in the target interrupt aggregation storage device, that is, the CPLD / FPGA determines that the preset upper system automatically clears after reading the interrupt information source, or the preset upper system writes to this interrupt record storage device, so that after the clearing operation is completed, a confirmation signal is transmitted upward to ensure that the preset upper system knows that the clearing is completed, and at the same time allows the preset upper system to clear the contents of multiple interrupt record registers at one time, simplifying the operation process. At this time, the interrupt record register is restored to an idle state and can record the next interrupt behavior.

[0070] Therefore, in order to avoid the situation where a new interrupt event may overwrite old data, resulting in the loss of important information, or when the interrupt information source is not cleared, it may be mistakenly believed that the same interrupt event has occurred again, resulting in repeated processing, it is necessary to use an active clearing mechanism after obtaining the interrupt information source based on the interrupt detailed information storage device to ensure that the interrupt record storage device can be used continuously, and each interrupt event can be correctly recorded and processed without errors caused by data overwriting or repeated processing, supporting the recording of more interrupt events.

[0071] It should be noted that, in the embodiment of the present invention, the control can be made more flexible by using an interrupt shielding register device. When the preset upper layer system does not pay attention to the interrupt, the interrupt shielding register device is directly used for shielding to prevent interrupts from occurring during critical operations.

[0072] According to an embodiment of the present invention, before clearing the interrupt information source in the target interrupt aggregation register device by using the interrupt clearing register device based on a clearing instruction, it further includes: obtaining a clearing identity identifier of the interrupt information source; determining whether the clearing identity identifier passes verification; if the clearing identity identifier passes verification, obtaining a clearing key of the interrupt information source and determining whether the clearing key meets a preset clearing condition; if the clearing key meets the preset clearing condition, recording the verification passed information and the clearing key information, and generating clearing instruction execution information.

[0073] Among them, the preset clearing condition can be set by those skilled in the art based on actual test requirements, or can be obtained through a limited number of computer simulations, and no specific limitation is made here.

[0074] Specifically, to avoid data loss caused by accidental triggering of the clearing operation or unauthorized operation execution. For example, unprocessed interrupt information may be wrongly cleared, resulting in the system being unable to correctly respond to certain events, or it may cause instability of the preset upper-layer system. For example, unauthorized clearing operations may damage the normal operating state of the system, affecting real-time performance or functional integrity. Therefore, to improve the security and reliability of the preset upper-layer system, the embodiment of the present invention further adds a verification mechanism before clearing the interrupt information source in the target interrupt aggregation register device by using the interrupt clearing register device to ensure that only authorized operations can trigger the clearing.

[0075] Specifically, first, clarify which operations or users have the permission to trigger the clearing operation, that is, obtain the clearing identity identifier of the interrupt information source and verify the clearing identity identifier of the interrupt information source. For example, verify the user ID (Identification) and device ID, and verify whether the operation occurs within an allowed time window. If both the user ID and device ID pass verification and the operation occurs within the allowed time window, it can be stated that the clearing identity identifier passes verification at this time. Then, further obtain the clearing key of the interrupt information source and determine whether the clearing key meets the preset clearing condition, that is, determine whether the clearing key is correct. If the clearing key meets the preset clearing condition, record the verification passed information and the clearing key information, and at this time, clearing instruction execution information can be generated to clear the interrupt information source.

[0076] Among them, the clearing key can be static (fixed value) or dynamic (generated based on time or other factors), and no specific limitation is made here.

[0077] Thus, based on the above-mentioned identity verification mechanism for clearing, illegal or accidental clearing operations can be prevented, important data in the interrupt record storage device can be protected, ensuring that the clearing operation is initiated only by legitimate operations, avoiding data loss or system anomalies caused by misoperations or malicious attacks. In a multi-user or multi-task system, the verification mechanism can distinguish the permissions of different users, ensuring that each user can only clear the interrupt records related to them.

[0078] According to an embodiment of the present invention, after determining whether the clearing identity verification passes, it further includes: if the clearing identity verification fails, generating an instruction to prohibit clearing the interrupt information source and recording the reason for the failure of the clearing identity verification; obtaining the number of times of clearing identity verification and determining whether the number of times of clearing identity verification is greater than a first preset verification threshold; if the number of times of clearing identity verification is greater than the first preset verification threshold, generating a first alarm prompt.

[0079] Among them, the first preset verification threshold can be set by those skilled in the art based on actual test requirements or obtained through a limited number of computer simulations, and no specific limitation is made here.

[0080] Specifically, if the clearing identity verification fails, it indicates that there is a risk in the user's operation. At this time, an instruction to prohibit clearing the interrupt information source needs to be generated and the reason for the failure of the clearing identity verification is recorded for subsequent verification and analysis. For example, record the operation source, operation timestamp, specific operation content, and failure reason, etc. If the user conducts verification multiple times, at this time, obtain the number of times of clearing identity verification. If the number of times of clearing identity verification is greater than the first preset verification threshold, it indicates that there is an illegal or malicious clearing operation. At this time, a first alarm prompt can be generated, such as triggering a high-priority alarm, notifying the administrator to check the system security, and the clearing permission of the user can be temporarily disabled for 10 minutes.

[0081] Thus, by verifying the clearing identity, it can be ensured that all operation attempts are strictly recorded and monitored, so that an alarm prompt can be given when the verification fails, preventing unauthorized operations from affecting the system stability.

[0082] According to an embodiment of the present invention, after determining whether the clearing key meets the preset clearing conditions, it further includes: if the clearing key does not meet the preset clearing conditions, recording the timestamp of the clearing key, the clearing key request address, and the reason why the clearing key does not meet the preset clearing conditions; obtaining the number of times of clearing key verification and determining whether the number of times of clearing key verification is greater than a second preset verification threshold; if the number of times of clearing identity verification is greater than the second preset verification threshold, generating a second alarm prompt.

[0083] Among them, the second preset verification threshold can be set by those skilled in the art based on actual test requirements, or obtained through a limited number of computer simulations, and no specific limitation is made here.

[0084] Specifically, if the clearing key does not meet the preset clearing conditions, it indicates that the provided key is invalid or incorrect, the operation source lacks necessary permissions, or the operation does not conform to a specific time window or other restrictive conditions, etc. At this time, to protect the preset upper-layer system from the impact of illegal operations, it is necessary to immediately terminate the clearing operation process, and return a clear rejection message (such as "Clearing failed: invalid key") and other prompt messages to the requesting party, and record the timestamp of the clearing key, the clearing key request address, and the reason why the clearing key does not meet the preset clearing conditions. At the same time, obtain the number of clearing key verification times. If the number of clearing key verification times is greater than the second preset verification threshold, it indicates that there is an illegal or malicious clearing operation. At this time, generate a second alarm prompt. For example, prompt through a low-level alarm or a high-level alarm. Among them, the high-level alarm can send an email, a text message, or start a sound alarm, etc., and the low-level alarm can be recorded in the log without further notification.

[0085] Thus, through the key verification mechanism, it can be ensured that all operation attempts are strictly recorded and monitored, so that an alarm prompt can be given when the verification fails, preventing unauthorized operations from affecting the system stability.

[0086] According to an embodiment of the present invention, after clearing the interrupt information source in the target interrupt aggregation register device by using the interrupt clearing register device based on the clearing instruction, it further includes: judging whether the interrupt information source is cleared; if the interrupt information source is cleared, generate a clearing confirmation signal, otherwise, record an uncleared log or an error log for clearing, and clear again.

[0087] Specifically, after clearing the interrupt information source in the target interrupt aggregation register device by using the interrupt clearing register device, it is necessary to read the relevant register devices of the interrupt information source and check whether the values of these register devices meet the standard of clearing completion, such as all relevant bits being 0, to ensure that the interrupt information source is cleared. If the interrupt information source is cleared, generate a clearing confirmation signal, and send the clearing confirmation signal to the relevant module or record it in the log to notify other parts of the system that the interrupt processing has been completed, so as to facilitate subsequent coordinated task scheduling and resource allocation.

[0088] Thus, through the multiple check and re-clearing mechanism, it is ensured that the status of the interrupt information source is completely cleared, and a corresponding clearing confirmation signal is generated based on the clearing status of the interrupt information source, providing clear feedback to other parts of the system, thus facilitating problem troubleshooting and system maintenance.

[0089] In summary, based on the above-mentioned method for querying interruption information, through the design of a complete interruption aggregation register device, an interruption detailed information register device, and an interruption edge recording register device for recording rapidly changing signals, the entire interruption design becomes clearer, thereby improving the access efficiency of the upper-layer system and the overall machine performance.

[0090] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0091] An embodiment of the present invention also provides a device for querying interruption information.

[0092] Figure 3 It is a block diagram example of the device for querying interruption information according to an embodiment of the present invention.

[0093] As Figure 3 shown, the device 10 for querying interruption information includes: a first acquisition module 100, a judgment module 200, and a second acquisition module 300.

[0094] Among them, the first acquisition module 100 is used to acquire at least one interruption signal, classify it based on the category of each interruption signal, and store it in the corresponding interruption aggregation register device respectively;

[0095] The judgment module 200 is used to detect at least one interruption aggregation register device based on a preset polling mechanism, and judge whether there is an interruption event in at least one interruption aggregation register device;

[0096] The second acquisition module 300 is used to, if there is an interruption event in at least one interruption aggregation register device, locate the target interruption aggregation register device corresponding to the interruption event, locate the target interruption event in the target interruption aggregation register device, and use the interruption detailed information register device to acquire the interruption information source of the target interruption event.

[0097] According to an embodiment of the present invention, after detecting at least one interruption aggregation register device based on a preset polling mechanism, the judgment module 200 further includes:

[0098] A first judgment unit, used to judge whether a preset interruption signal is detected;

[0099] A storage unit, used to, if a preset interruption signal is detected, record and store the preset interruption signal based on the interruption edge recording register device.

[0100] According to an embodiment of the present invention, the second acquisition module 300 includes:

[0101] A first acquisition unit, configured to acquire the interrupt type of an interrupt event, the interrupt timestamp of the interrupt event, and the data information of the interrupt event;

[0102] A positioning unit, configured to determine the target address of an interrupt aggregation register device according to the interrupt type of the interrupt event, the timestamp of the interrupt event, and the data information of the interrupt event, so as to locate the target interrupt aggregation register device according to the target address.

[0103] According to an embodiment of the present invention, the judgment module 200 includes:

[0104] A second judgment unit, configured to judge whether the values of at least one interrupt aggregation register device are preset values;

[0105] A determination unit, configured to determine that there is an interrupt event in at least one interrupt aggregation register device if the values of at least one interrupt aggregation register device are preset values.

[0106] According to an embodiment of the present invention, the second acquisition module 300 includes:

[0107] A detection unit, configured to detect the interrupt signal status of each bit in the target interrupt aggregation register device;

[0108] A third judgment unit, configured to judge whether the interrupt signal status is a preset status;

[0109] A second acquisition unit, configured to obtain a target interrupt event in the target interrupt aggregation register device based on the interrupt signal status if the interrupt signal status is a preset status.

[0110] According to an embodiment of the present invention, after obtaining the interrupt information source of the interrupt event based on the interrupt detailed information register device, the second acquisition module 300 includes:

[0111] A fourth judgment unit, configured to judge whether the interrupt information source is successfully recorded;

[0112] An instruction writing unit, configured to write a clear instruction to the interrupt clear register device according to the target interrupt aggregation register device if the interrupt information source is successfully recorded;

[0113] A clearing unit, configured to clear the interrupt information source in the target interrupt aggregation register device by using the interrupt clear register device based on the clear instruction.

[0114] According to an embodiment of the present invention, before clearing the interrupt information source in the target interrupt aggregation register device by using the interrupt clear register device based on the clear instruction, the clearing unit further includes:

[0115] An acquisition sub-component, configured to acquire the clearing identity identifier of the interrupt information source;

[0116] The first judgment component is used to judge whether the verification of the clearing identity identifier is passed;

[0117] The second judgment component is used to, if the verification of the clearing identity identifier is passed, obtain the clearing key of the interruption information source and judge whether the clearing key meets the preset clearing conditions;

[0118] The first generation component is used to, if the clearing key meets the preset clearing conditions, record the verification passed information and the clearing key information, and generate the clearing instruction execution information.

[0119] According to an embodiment of the present invention, after judging whether the verification of the clearing identity identifier is passed, the first judgment component further includes:

[0120] The first generation sub-component is used to, if the verification of the clearing identity identifier fails, generate an instruction to prohibit clearing the interruption information source and record the reason for the failure of the verification of the identity identifier.

[0121] The first judgment sub-component is used to obtain the verification times of the clearing identity identifier and judge whether the verification times of the clearing identity identifier are greater than the first preset verification threshold;

[0122] The second generation sub-component is used to, if the verification times of the clearing identity identifier are greater than the first preset verification threshold, generate the first alarm prompt.

[0123] According to an embodiment of the present invention, after judging whether the clearing key meets the preset clearing conditions, the second judgment component further includes:

[0124] The recording sub-component is used to, if the clearing key does not meet the preset clearing conditions, record the timestamp of the clearing key, the clearing key request address, and the reason why the clearing key does not meet the preset clearing conditions;

[0125] The second judgment sub-component is used to obtain the verification times of the clearing key and judge whether the verification times of the clearing key are greater than the second preset verification threshold;

[0126] The third generation sub-component is used to, if the verification times of the clearing identity identifier are greater than the second preset verification threshold, generate the second alarm prompt.

[0127] According to an embodiment of the present invention, after clearing the interruption information source in the target interruption aggregation storage device by using the interruption clearing storage device based on the clearing instruction, the clearing unit further includes:

[0128] The third judgment component is used to judge whether the interruption information source is cleared;

[0129] The second generation component is used to, if the interruption information source is cleared, generate a clearing confirmation signal, otherwise, record the clearing incomplete log or the clearing error log, and clear again.

[0130] According to an embodiment of the present invention, the determination module 200 includes:

[0131] A setting unit, configured to respectively set a preset initial polling mechanism for each interrupt aggregation register device based on the design requirements and functional characteristics of a preset upper-layer system and the type of the interrupt aggregation register device;

[0132] A dynamic adjustment unit, configured to monitor the interrupt frequency of interrupt events in each interrupt aggregation register device, and dynamically adjust the preset initial polling mechanism according to the interrupt frequency;

[0133] A third acquisition unit, configured to obtain a preset polling mechanism based on the preset initial polling mechanism after dynamic adjustment.

[0134] According to an embodiment of the present invention, the dynamic adjustment unit includes:

[0135] A fifth determination unit, configured to determine whether the interrupt frequency is greater than a preset frequency threshold;

[0136] A dynamic adjustment unit, configured to shorten the preset initial polling mechanism if the interrupt frequency is greater than the preset frequency threshold, otherwise, extend the preset initial polling mechanism.

[0137] In summary, for the description of the features in the corresponding embodiment of the query device for interrupt information, reference may be made to the relevant description in the corresponding embodiment of the query method for interrupt information, which will not be elaborated here one by one.

[0138] Figure 4 The following is a schematic structural diagram of an electronic device provided by an embodiment of the present invention. The electronic device may include:

[0139] A memory 401, a processor 402, and a computer program stored on the memory 401 and executable on the processor 402.

[0140] When the processor 402 executes the program, it implements the multi-device communication method provided in the above embodiment.

[0141] Further, the electronic device further includes:

[0142] A communication interface 403, configured for communication between the memory 401 and the processor 402.

[0143] The memory 401 is used to store a computer program executable on the processor 402.

[0144] The memory 401 may include a high-speed RAM memory, and may also include a non-volatile memory, such as at least one disk memory.

[0145] If the memory 401, the processor 402, and the communication interface 403 are implemented independently, the communication interface 403, the memory 401, and the processor 402 can be interconnected through a bus and communicate with each other. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 4 only a thick line is used to represent it in Figure 4 , but it does not mean that there is only one bus or one type of bus.

[0146] Optionally, in a specific implementation, if the memory 401, the processor 402, and the communication interface 403 are integrated on a single chip, the memory 401, the processor 402, and the communication interface 403 can communicate with each other through an internal interface.

[0147] The processor 402 may be a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention.

[0148] Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described embodiments of the method for querying interruption information when running.

[0149] Embodiments of the present invention also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, and the computer program implements the steps in any of the above-described embodiments of the method for querying interruption information when executed by a processor.

[0150] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered as exceeding the scope of the present invention.

[0151] The above has introduced in detail a method for querying interruption information provided by the present invention. Specific examples are used herein to illustrate the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present invention, several improvements and modifications can still be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A method for querying interruption information, characterized in that: The following steps are involved: Obtain at least one interrupt signal, and classify each interrupt signal based on its category, and store them in interrupt aggregation register devices of corresponding categories respectively; Based on a preset polling mechanism, at least one interrupt aggregation storage device is detected to determine whether there is an interrupt event in the at least one interrupt aggregation storage device; If the interrupt event exists in the at least one interrupt aggregation register, locate the target interrupt aggregation register corresponding to the interrupt event, locate the target interrupt event in the target interrupt aggregation register, and obtain the interrupt information source of the target interrupt event by using the interrupt detailed information register; Among them, all interrupt signals are combined into one signal and transmitted through I / O or in-band interrupt, or communicated through I2C, LPC, SPI, PCIe protocol; An interrupt edge record register is set up through CPLD / FPGA, and the interrupt edge record register records the rapidly changing interrupt signal, and stores the detailed information of the rapidly changing interrupt signal in the corresponding interrupt detailed information register. When the input signal has an edge change, the interrupt edge record register automatically records the event, and saves the detailed information of each edge event, and notifies the target upper-layer system to process through the interrupt mechanism. At the same time, the interrupt edge record register works automatically in the background; When an error occurs in the target interrupt aggregation register device that identifies the presence of an interrupt event, re-detection is performed through error handling or fault tolerance mechanism, or if identification fails, an automatic retry mechanism is performed and the process and result of each interrupt identification is recorded.

2. The method for querying interruption information according to claim 1, characterized in that: After detecting at least one interrupt aggregation register device based on the preset polling mechanism, the method further includes: Determine whether a preset interrupt signal is detected; If the preset interrupt signal is detected, the preset interrupt signal is recorded and stored based on the interrupt edge recording and storage device.

3. The method for querying interruption information according to claim 1, characterized in that: The locating the target interrupt aggregation register device corresponding to the interrupt event includes: Obtaining an interrupt type of the interrupt event, an interrupt timestamp of the interrupt event, and data information of the interrupt event; The target address of the interrupt aggregation register device is determined according to the interrupt type of the interrupt event, the timestamp of the interrupt event and the data information of the interrupt event, so as to locate the target interrupt aggregation register device according to the target address.

4. The method for querying interruption information according to claim 1, characterized in that: The determining whether there is an interrupt event in at least one interrupt aggregation register device includes: Determining whether the at least one interrupt aggregation register value is a preset value; If the value of the at least one interrupt aggregation register device is the preset value, it is determined that the interrupt event exists in the at least one interrupt aggregation register device.

5. The method for querying interruption information according to claim 1, characterized in that: The locating the target interrupt event in the target interrupt aggregation register device includes: Detecting the interrupt signal status of each bit in the target interrupt aggregation register; Determining whether the interrupt signal state is a preset state; If the interrupt signal state is the preset state, a target interrupt event in the target interrupt aggregation register device is obtained based on the interrupt signal state.

6. The method for querying interruption information according to claim 1, characterized in that: After obtaining the interruption information source of the target interruption event by using the interruption detailed information storage device, the method further includes: Determining whether the interruption information source is recorded successfully; If the interrupt information source is recorded successfully, a clear instruction is written to the interrupt clear register device according to the target interrupt aggregation register device; Based on the clear instruction, the interrupt clear register device is used to clear the interrupt information source in the target interrupt aggregation register device.

7. The method for querying interruption information according to claim 6, characterized in that: Before clearing the interrupt information source in the target interrupt aggregation register device using the interrupt clearing register device based on the clearing instruction, the method further includes: Obtaining a clearing identity of the interruption information source; Determine whether the clearing identity is verified; If the clearing identity verification is passed, obtaining the clearing key of the interruption information source, and determining whether the clearing key satisfies a preset clearing condition; If the clear key satisfies the preset clear condition, the verification pass information and the clear key information are recorded, and clear instruction execution information is generated.

8. The method for querying interruption information according to claim 7, characterized in that: After determining whether the clearing identity is verified, the method further includes: If the clearing identity verification fails, generating an instruction to prohibit clearing the interrupt information source and recording the reason why the identity verification fails; Obtaining the number of times of clearing identity verification, and determining whether the number of times of clearing identity verification is greater than a first preset verification threshold; If the number of times of clearing identity verification is greater than the first preset verification threshold, a first alarm prompt is generated.

9. The method for querying interruption information according to claim 7, characterized in that: After determining whether the clearing key satisfies a preset clearing condition, the method further includes: If the clear key does not meet the preset clear condition, then record the timestamp of the clear key, the clear key request address and the reason why the clear key does not meet the preset clear condition; Obtaining the number of clear key verification times, and determining whether the number of clear key verification times is greater than a second preset verification threshold; If the number of times of clearing identity verification is greater than the second preset verification threshold, a second alarm prompt is generated.

10. The method for querying interruption information according to claim 6, characterized in that: After clearing the interrupt information source in the target interrupt aggregation register device by using the interrupt clearing register device based on the clearing instruction, the method further includes: Determine whether the interrupt information source has been cleared; If the interrupt information source is cleared, a clearing confirmation signal is generated; otherwise, a clearing incomplete log or a clearing error log is recorded and cleared again.

11. The method for querying interruption information according to claim 1, characterized in that: The detecting of at least one interrupt aggregation register device based on a preset polling mechanism includes: Based on the preset design requirements and functional characteristics of the upper layer system and the type of the interrupt aggregation register device, respectively set a preset initial polling mechanism for each interrupt aggregation register device; Monitoring the interrupt frequency of the interrupt event in each interrupt aggregation register device, and dynamically adjusting the preset initial polling mechanism according to the interrupt frequency; The preset polling mechanism is obtained based on the dynamically adjusted preset initial polling mechanism.

12. The method for querying interruption information according to claim 11, characterized in that: The dynamically adjusting the preset initial polling mechanism according to the interruption frequency includes: Determining whether the interruption frequency is greater than a preset frequency threshold; If the interruption frequency is greater than the preset frequency threshold, the preset initial polling mechanism is shortened; otherwise, the preset initial polling mechanism is prolonged.

13. A device for querying interruption information, characterized in that: include: A first acquisition module, used for acquiring at least one interrupt signal, and classifying each interrupt signal based on its category, and storing them in interrupt aggregation register devices of corresponding categories respectively; A judgment module, configured to detect at least one interrupt aggregation storage device based on a preset polling mechanism, and judge whether there is an interrupt event in the at least one interrupt aggregation storage device; A second acquisition module is used to locate the target interrupt aggregation storage device corresponding to the interrupt event if the interrupt event exists in the at least one interrupt aggregation storage device, locate the target interrupt event in the target interrupt aggregation storage device, and use the interrupt detailed information storage device to obtain the interrupt information source of the target interrupt event; Among them, all interrupt signals are combined into one signal and transmitted through I / O or in-band interrupt, or communicated through I2C, LPC, SPI, PCIe protocol; An interrupt edge record register is set up through CPLD / FPGA, and the interrupt edge record register records the rapidly changing interrupt signal, and stores the detailed information of the rapidly changing interrupt signal in the corresponding interrupt detailed information register. When the input signal has an edge change, the interrupt edge record register automatically records the event, and saves the detailed information of each edge event, and notifies the target upper-layer system to process through the interrupt mechanism. At the same time, the interrupt edge record register works automatically in the background; When an error occurs in the target interrupt aggregation register device that identifies the presence of an interrupt event, re-detection is performed through error handling or fault tolerance mechanism, or if identification fails, an automatic retry mechanism is performed and the process and result of each interrupt identification is recorded.

14. An electronic device, characterized in that: include: The invention comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method for querying interrupt information according to any one of claims 1 to 12.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method for querying interrupt information according to any one of claims 1 to 12.

16. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for querying interrupt information according to any one of claims 1 to 12 are implemented.

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