System and method for improving operation throughput rate of distribution network monitoring control chip

Abstract

The embodiment of the invention provides a system and method for improving the operation throughput rate of a distribution network monitoring control chip, and belongs to the technical field of data processing. The system comprises a master core module, a slave core module and a task scheduling module, the main core module is used for distributing calculation tasks; the slave core module comprises a universal slave core and a special slave core; the universal slave core is used for executing control logic and operation; the special slave core is used for executing signal analysis and encryption tasks; and the task scheduling module is used for scheduling the tasks according to the calculation density. The memory access delay can be reduced, the data throughput rate can be improved, and the performance and reliability of the storage system can be integrally improved.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a system and method for improving the computing throughput of a distribution network monitoring and control chip. Background Art

[0002] As the demand for efficient real-time processing in distribution network monitoring and control systems increases, traditional single-core architectures can no longer meet the requirements in terms of computing power and task processing efficiency. Once a hardware failure or processor abnormality occurs in a single-core architecture system, the function of the entire system may be affected or fail to operate normally, and there is a lack of effective fault tolerance mechanisms and backup capabilities. Single-core processors have poor scalability when facing the expansion of network scale or increased demand. Once the system scale increases, the processing power is likely to fall short of the expected requirements. In order to increase processing power, it is usually necessary to replace a more powerful single-core processor or upgrade the hardware, but this is often costly and limited by the hardware architecture. Summary of the invention

[0003] The main purpose of the embodiments of the present application is to provide a system and method for improving the computing throughput of a distribution network monitoring control chip.

[0004] The technical solution adopted by the present invention is:

[0005] On the one hand, an embodiment of the present invention provides a system for improving the computing throughput of a distribution network monitoring control chip, the system comprising a master core module, a slave core module, and a task scheduling module;

[0006] The main core module is used to distribute computing tasks;

[0007] The slave core module includes a general slave core and a dedicated slave core; the general slave core is used to execute control logic and operations; the dedicated slave core is used to execute signal analysis and encryption tasks;

[0008] The task scheduling module is used to schedule tasks according to computing density.

[0009] Furthermore, the main core module uses a static priority scheduling algorithm to allocate tasks to corresponding modules according to the characteristics of the tasks.

[0010] Furthermore, the general slave core adopts a pipeline architecture to process logic and matrix operations; the dedicated slave core is used to perform fast Fourier transform signal analysis and advanced encryption standard encryption tasks.

[0011] Furthermore, the task scheduling module uses a dynamic scheduling algorithm to allocate high computing load tasks to the dedicated slave cores and low computing load tasks to the general slave cores based on the computing density of the tasks.

[0012] Furthermore, the system for improving the computing throughput of the distribution network monitoring control chip also includes a reconfigurable computing unit;

[0013] The reconfigurable computing unit is used to load hardware configuration.

[0014] Furthermore, the system for improving the computing throughput of the distribution network monitoring control chip further includes a computing unit;

[0015] The computing unit is used to perform calculations and data processing and execute computing tasks.

[0016] Furthermore, the system for improving the computing throughput of the distribution network monitoring control chip also includes an on-chip storage module and an off-chip storage module;

[0017] The on-chip storage module includes a first cache submodule and a second cache submodule; the first cache submodule is used for high-speed access to instructions and small data; the second cache submodule is used for caching large-scale data;

[0018] The off-chip storage module is used to store data and system boot programs.

[0019] Furthermore, the system for improving the computing throughput of the distribution network monitoring control chip also includes a data management module;

[0020] The data management module is used to perform data sharing, exchange, synchronization and transmission.

[0021] On the other hand, an embodiment of the present invention further provides a method for improving the computing throughput of a distribution network monitoring control chip, which is implemented by the system for improving the computing throughput of a distribution network monitoring control chip as described above, and the method comprises the following steps:

[0022] Improve the computing throughput of the distribution network monitoring and control chip through the main core module, slave core module, and task scheduling module;

[0023] Allocate computing tasks;

[0024] Execute control logic and operations; perform signal analysis and encryption tasks;

[0025] Schedule tasks according to computing density.

[0026] Furthermore, the method for improving the computing throughput of the distribution network monitoring control chip further includes the following steps:

[0027] Through dynamic voltage and frequency adjustment technology, the working state of the computing unit is adjusted to balance performance and energy consumption;

[0028] Use semaphore mechanism to manage data status;

[0029] Use exclusive lock mechanism to modify data in shared memory.

[0030] The embodiments of the present application include at least the following beneficial effects: The present application provides a system and method for improving the computing throughput of a distribution network monitoring control chip. The system of the present invention includes a master core module, a slave core module, and a task scheduling module; the master core module is used to allocate computing tasks; the slave core module includes a general slave core and a dedicated slave core; the general slave core is used to execute control logic and operations; the dedicated slave core is used to execute signal analysis and encryption tasks; the task scheduling module is used to schedule tasks according to computing density. The present invention can reduce memory access latency and improve data throughput, and improve the performance and reliability of the storage system as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a workflow diagram of a multi-core heterogeneous chip architecture provided by an embodiment of the present invention;

[0032] Figure 2 is a schematic diagram of an inter-core communication mechanism in a multi-core system provided by an embodiment of the present invention;

[0033] Figure 3 It is a schematic diagram of a workflow for optimizing memory architecture and data transmission efficiency provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0035] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0036] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0038] The present invention takes into account that with the increasing demand for efficient real-time processing in distribution network monitoring and control systems, traditional single-core architectures have been unable to meet the requirements in terms of computing power and task processing efficiency. The distribution network monitoring and control system requires real-time monitoring and data processing of a large number of sensors and devices. In a single-core system, scheduling between multiple tasks is prone to delays, and data processing and response cannot be completed within the specified time, affecting the real-time and reliability of the system, especially in the event of a failure or emergency, and countermeasures cannot be taken quickly. The multi-core heterogeneous architecture can significantly improve the computing throughput and resource utilization by integrating multiple processing units and optimizing communication and storage designs, better supporting complex functions such as monitoring, control, protection, and communication management, meeting the application requirements of distribution network terminals at high performance and low power consumption, and providing technical support for the intelligent development of power systems.

[0039] Before describing the embodiments of the present application in detail, some nouns and terms involved in the embodiments of the present application are first described. The nouns and terms involved in the embodiments of the present application are subject to the following explanations.

[0040] 1) Cache is a high-speed storage device.

[0041] 2) DDR (Double Data Rate) is a memory technology.

[0042] 3) NAND Flash is a non-volatile storage technology.

[0043] 4) DMA (Direct Memory Access), DMA is a technology that allows peripherals or internal components of a computer to directly access memory.

[0044] 5) DVFS (Dynamic Voltage and Frequency Scaling), DVFS is an energy-saving technology.

[0045] 6) FFT (Fast Fourier Transform), FFT is an algorithm used to quickly calculate the discrete Fourier transform (DFT) of a signal.

[0046] 7) AES (Advanced Encryption Standard), AES is a symmetric key encryption algorithm.

[0047] 8) FPGA (Field-Programmable Gate Array) is an integrated circuit that can be programmed at the hardware level.

[0048] 9) NoC (Network on Chip) is an architecture used for communication between different processing units in an integrated circuit.

[0049] 10) SRAM (Static Random Access Memory) is a random access memory that does not require periodic refresh to retain data.

[0050] 11) P / V mechanism (Power / Voltage Mechanism) is a technology for adjusting system power consumption and voltage.

[0051] The embodiments of the present invention are further described below in conjunction with the accompanying drawings.

[0052] On the one hand, an embodiment of the present invention provides a system for improving the computing throughput of a distribution network monitoring control chip, the system comprising a master core module, a slave core module, and a task scheduling module;

[0053] The main core module is used to distribute computing tasks;

[0054] The slave core module includes a general slave core and a dedicated slave core; the general slave core is used to execute control logic and operations; the dedicated slave core is used to execute signal analysis and encryption tasks;

[0055] The task scheduling module is used to schedule tasks according to computing density.

[0056] The main core module disclosed in the embodiment of the present invention adopts a static priority scheduling algorithm to allocate tasks to corresponding modules according to the characteristics of the tasks.

[0057] As an optional implementation, the task allocation of the present invention: the main core is responsible for global task scheduling, and a static priority scheduling algorithm is used to allocate computing tasks to different types of cores (dedicated cores, general-purpose cores, etc.) according to the priority and computing requirements of the tasks.

[0058] The general slave core disclosed in the embodiment of the present invention adopts a pipeline architecture to process logic and matrix operations; the dedicated slave core is used to perform fast Fourier transform signal analysis and encryption tasks of the Advanced Encryption Standard.

[0059] As an optional implementation, the general slave core of the embodiment of the present invention is responsible for processing complex logic and matrix operations, and the dedicated slave core processes computationally intensive tasks such as FFT signal analysis and AES encryption, thereby improving efficiency through vectorized processing.

[0060] The task scheduling module disclosed in the embodiment of the present invention uses a dynamic scheduling algorithm to allocate high computing load tasks to dedicated slave cores and low computing load tasks to general slave cores based on the computing density of the tasks.

[0061] As an optional implementation, the embodiment of the present invention allocates high-computational tasks to dedicated slave cores (such as for FFT or matrix operations) and low-load tasks to general slave cores (such as logic control and scheduling tasks) according to the computing density and load requirements of the tasks, thereby ensuring efficient use of resources.

[0062] By combining general-purpose slave cores with dedicated slave cores, the overall system performance is improved through parallel execution of tasks.

[0063] The system for improving the computing throughput of a distribution network monitoring control chip disclosed in an embodiment of the present invention further includes a reconfigurable computing unit;

[0064] The reconfigurable computing unit is used to load the hardware configuration.

[0065] The system for improving the computing throughput of a distribution network monitoring control chip disclosed in an embodiment of the present invention further includes a computing unit;

[0066] The computing unit is used to perform calculations and data processing and execute computing tasks.

[0067] The system for improving the computing throughput of a distribution network monitoring control chip disclosed in an embodiment of the present invention further includes an on-chip storage module and an off-chip storage module;

[0068] The on-chip storage module includes a first cache submodule and a second cache submodule; the first cache submodule is used for high-speed access to instructions and small data; the second cache submodule is used for caching large-scale data;

[0069] The off-chip memory module is used to store data and system boot programs.

[0070] As an optional implementation, the on-chip storage and cache of an embodiment of the present invention: design a three-level pipeline architecture (task splitting and scheduling, data preprocessing and caching, result transmission), cooperate with the on-chip L1, L2 Cache and the off-chip DDR4, NAND Flash storage system to reduce data access delays and data transmission bottlenecks.

[0071] The system for improving the computing throughput of a distribution network monitoring control chip disclosed in an embodiment of the present invention further includes a data management module;

[0072] The data management module is used to perform data sharing, exchange, synchronization and transmission.

[0073] As an optional implementation, the data exchange mechanism of the embodiment of the present invention uses a shared memory and semaphore mechanism to manage data exchange between cores. The sending core writes the calculation result into the shared memory and marks the data status through the semaphore; the receiving core reads the data after checking the semaphore to ensure the sequential and real-time nature of data transmission.

[0074] On the other hand, an embodiment of the present invention further provides a method for improving the computing throughput of a distribution network monitoring control chip, which is implemented by a system for improving the computing throughput of a distribution network monitoring control chip as described above, and the method includes the following steps:

[0075] Improve the computing throughput of the distribution network monitoring and control chip through the main core module, slave core module, and task scheduling module;

[0076] Allocate computing tasks;

[0077] Execute control logic and operations; perform signal analysis and encryption tasks;

[0078] Schedule tasks according to computing density.

[0079] The method for improving the computing throughput of the distribution network monitoring control chip disclosed in the embodiment of the present invention further includes the following steps:

[0080] Through dynamic voltage and frequency adjustment technology, the working state of the computing unit is adjusted to balance performance and energy consumption;

[0081] Use semaphore mechanism to manage data status;

[0082] Use exclusive lock mechanism to modify data in shared memory.

[0083] As an optional implementation, a method for improving the computing throughput of a distribution network monitoring control chip of the present invention comprises the following steps:

[0084] 1. Design a multi-core heterogeneous chip architecture, using a master core and multiple slave cores to work together. The master core is responsible for global task scheduling and assigns computing tasks according to task priority. The slave cores handle different types of computing tasks respectively. The dedicated core is responsible for complex algorithm processing, and the general core is responsible for logic control and scheduling.

[0085] 2. Adopt dynamic scheduling algorithm to allocate high-computation tasks to dedicated cores and low-load tasks to general cores according to the computing density of tasks, so as to achieve efficient utilization of resources;

[0086] 3. Design a three-level pipeline architecture in the chip, which is used for task splitting and scheduling, data preprocessing and caching, and result transmission, to reduce data transmission bottlenecks;

[0087] 4. Introducing two-level on-chip cache (L1 Cache and L2 Cache) and off-chip storage architecture optimization. The on-chip cache is used for high-speed data cache, and the off-chip storage uses a combination of DDR4 and NAND Flash for temporary data and long-term data storage, respectively. DMA technology is used to improve data interaction efficiency;

[0088] 5. Use dynamic voltage and frequency scaling (DVFS) technology to adjust the processor operating frequency and voltage according to the task load to achieve a balance between performance and energy consumption.

[0089] As an optional implementation, the present invention designs a multi-core heterogeneous chip architecture, in which the master core uses a static priority scheduling algorithm for global task allocation and is responsible for the coordination of monitoring, analysis and control tasks. The general slave core uses a pipeline architecture to process complex logic and matrix operations, and the dedicated slave core performs tasks such as FFT signal analysis and AES encryption, using vectorized processing to improve efficiency. The reconfigurable computing unit uses part of the reconfigurable FPGA technology to dynamically load hardware configurations to achieve accelerated processing such as fault detection and data compression. The chip uses a two-dimensional grid network-on-chip (NoC) connection and uses a token ring protocol to ensure efficient inter-core communication; the storage structure uses a double-layer cache combined with an on-chip high-speed SRAM design to reduce memory access latency and improve data throughput.

[0090] The efficient inter-core communication mechanism of the present invention significantly improves the data transmission efficiency of the multi-core system by combining shared memory and semaphores. In this mechanism, the sending core writes the calculation results to the specified area of ​​the shared memory and uses a semaphore (P / V mechanism) to identify the data status. The receiving core checks the semaphore, reads the data in the shared memory after confirming that the data is ready, and resets the semaphore to release resources. In order to avoid data conflicts, an exclusive lock mechanism is used to ensure that only one core can modify the shared memory data at the same time. In addition, a lightweight task identification protocol is used, and the task priority is managed in combination with semaphores to ensure the sequentiality and real-time nature of data transmission.

[0091] Aiming at the high throughput requirements of the chip, the present invention designs an optimized on-chip and off-chip storage architecture. A two-level cache architecture is adopted on the chip, L1 Cache is used for high-speed instruction access, and L2 Cache is used for caching large-scale data; off-chip storage adopts a mode combining DDR4SDRAM and NAND Flash, DDR4 is used to store temporary data, and NAND Flash stores long-term data and system boot programs. By optimizing the memory capacity allocation and access strategy, the on-chip cache reduces the access frequency to the off-chip storage, and the off-chip storage improves the data interaction efficiency through wide bus design and direct memory access (DMA) technology, which improves the performance and reliability of the storage system as a whole.

[0092] The present invention optimizes the chip data throughput rate through a multi-core heterogeneous architecture, and allocates high computing density tasks to dedicated cores and low load tasks to general cores based on the dynamic scheduling algorithm of task requirements, thereby improving resource utilization. Heterogeneous computing integration technology is adopted, and dedicated cores process complex calculations such as matrix operations and FFT, while general cores are responsible for logic control and scheduling, and performance improvement is achieved through efficient task decomposition and parallel execution. A three-level pipeline architecture is designed, which is used for task splitting and scheduling, data preprocessing and caching, and result transmission, respectively. The hierarchical cache architecture of DDR and on-chip SRAM is combined to reduce data transmission bottlenecks. Dynamic voltage and frequency adjustment technology (DVFS) is adopted to balance high-performance computing and energy consumption requirements.

[0093] As an optional implementation, refer to Figure 1 The workflow diagram of the multi-core heterogeneous chip architecture shows the interaction and data flow between modules. The following is a detailed description and sequence of each step in the flowchart:

[0094] 1. Task allocation:

[0095] Step 1: The main core is responsible for allocating tasks to appropriate computing units through a static priority scheduling algorithm.

[0096] Step 2: The task scheduling module further allocates tasks to specific cores based on the core type and task characteristics.

[0097] 2. Task execution and data transmission:

[0098] Step 3: The computing unit performs the computing task and transmits the processing results through the on-chip network.

[0099] Step 4: The data is transmitted to the storage structure (including L1 Cache, L2Cache, SRAM) or external storage (such as DDR4, NAND Flash) through the on-chip network for caching or storage.

[0100] 3. Data exchange and management:

[0101] Step 5: The data management module is responsible for managing data exchange between cores to ensure synchronization and efficient transmission of data between computing units.

[0102] Step 6: The storage structure (including Cache, SRAM, etc.) stores and accesses data as needed to reduce data transmission bottlenecks.

[0103] 4. Dynamic scheduling and voltage and frequency adjustment:

[0104] Step 7: Based on the task requirements and energy consumption requirements, the system can adjust the working state of the computing unit through dynamic voltage and frequency scaling (DVFS) technology to balance performance and energy consumption.

[0105] As an optional implementation, refer to Figure 2 , shows the inter-core communication mechanism in a multi-core system, including the detailed workflow of task scheduling, data transmission, semaphore management and lock mechanism. This figure describes how to ensure efficient task coordination and data consistency in a multi-core processor through shared memory, semaphores, exclusive lock mechanisms, etc. The steps include:

[0106] 1. Data writing and status marking:

[0107] Step 1: The sending core writes the computation result to the shared memory and marks the data status (via a semaphore) to indicate that the data is ready for the receiving core to read.

[0108] 2.Semaphore and data preparation:

[0109] Step 2: The semaphore mechanism manages the data status to ensure that the receiving core can read only when the data is ready, avoiding data conflicts.

[0110] Step 3: The receiving core checks the semaphore value to confirm whether the data is ready and reads the data in the shared memory.

[0111] 3. Resource reset and task scheduling:

[0112] Step 4: After the data is read, the core reset signal is received, resources are released and the task is marked as completed. At this time, the task identification protocol manages task scheduling and priority to ensure task order and real-time performance.

[0113] Step 5: The task identification protocol controls the order and real-time of data transmission to ensure efficient operation of the system.

[0114] 4. Lock mechanism ensures data consistency:

[0115] Step 6: The exclusive lock mechanism ensures that only one core can modify the data in the shared memory at the same time during multi-core concurrent processing, thus avoiding conflicts and data inconsistencies.

[0116] As an optional implementation, refer to Figure 3 , showing the workflow for optimizing memory architecture and data transmission efficiency, covering the synergy of on-chip cache, off-chip memory, DMA technology, multi-core heterogeneous architecture and other technologies. Through the combination of these technologies, memory performance and task processing efficiency are effectively improved.

[0117] 1. Cache system and memory optimization:

[0118] Step 1: On-chip L1 Cache and on-chip L2 Cache provide high-speed instruction and data access, reducing access latency.

[0119] Step 2: The on-chip L2 Cache caches large amounts of data. If the cached data is insufficient, the off-chip DDR4 memory is accessed to store temporary data to improve data interaction efficiency.

[0120] Step 3: The off-chip DDR4 memory cooperates with the off-chip NAND Flash to store temporary data and long-term data (such as system boot program) respectively to ensure stable data storage.

[0121] 2. Memory optimization and access strategy:

[0122] Step 4: Reduce frequent access to off-chip storage through on-chip storage optimization, optimize access strategies, and improve the overall efficiency of the memory.

[0123] 3.DMA technology and task scheduling:

[0124] Step 5: Use DMA technology to achieve efficient data transmission, reduce the burden on the CPU, and improve the overall transmission efficiency of the system.

[0125] 4. Multi-core heterogeneous architecture and task allocation:

[0126] Step 6: The multi-core heterogeneous architecture assigns high-computation density tasks to dedicated cores, while low-computation tasks are processed by general-purpose cores, ensuring the dynamic and efficient scheduling of tasks.

[0127] Step 7: Dedicated cores and general-purpose cores perform task decomposition and parallel execution to improve the overall system performance.

[0128] 5. Three-level pipeline and data processing:

[0129] Step 8: The three-level pipeline architecture optimizes task splitting and scheduling, performs data preprocessing, caching, and result transmission, and improves processing capabilities.

[0130] 6. On-chip SRAM and data cache:

[0131] Step 9: On-chip SRAM acts as an efficient cache, providing fast storage for the system and ensuring fast data transmission and access.

[0132] 7.DVFS technology and energy efficiency management:

[0133] Step 10: DVFS technology dynamically adjusts voltage and frequency to balance system performance and energy consumption, ensuring optimized power consumption under different loads.

[0134] The present invention proposes a multi-core heterogeneous chip architecture and key technologies for distribution network monitoring and control, aiming to solve the performance bottleneck of traditional single-core architecture in complex task processing. By integrating multiple types of cores (including general-purpose processors, dedicated computing units and reconfigurable resources), combined with the efficient communication mechanism of shared memory and message passing, flexible resource allocation and optimized computing power allocation are realized. The on-chip memory architecture and off-chip storage selection are optimized to improve data access performance and system stability. The present invention significantly improves the computing throughput and processing efficiency of the distribution network monitoring and control chip. Under the multi-core heterogeneous architecture, through the division of labor and cooperation between the master and slave cores and the efficient deployment of reconfigurable computing units, the parallel processing of complex multi-task scenarios is realized to meet the real-time requirements of distribution network monitoring, control, protection and communication management functions. At the same time, the optimized inter-core communication mechanism effectively reduces data interaction delay and improves the response speed of multi-task switching and data processing. In terms of storage architecture, through hierarchical cache design and reasonable on-chip and off-chip storage capacity configuration, data access delay is greatly reduced, and system storage performance and reliability are improved. Combined with high-bandwidth DDR storage and non-volatile Flash storage, efficient storage and call of task data are achieved, ensuring system stability. By optimizing the main frequency, cache parameters and number of cores, the chip achieves a good balance between computing power and power consumption, providing core technical support for the intelligent development of power distribution network systems.

[0135] On the other hand, an embodiment of the present invention also provides a device for improving the computing throughput of a distribution network monitoring and control chip, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the method for improving the computing throughput of a distribution network monitoring and control chip as described above is implemented.

[0136] The processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc.

[0137] The memory may include various types of storage units, such as system memory, read-only memory (ROM), and permanent storage. Among them, ROM can store static data or instructions required by the processor or other modules of the computer. The permanent storage device may be a readable and writable storage device. The permanent storage device may be a non-volatile storage device that does not lose the stored instructions and data even after the computer is powered off. In some embodiments, the permanent storage device uses a large-capacity storage device (such as a magnetic or optical disk, flash memory) as a permanent storage device. In some other embodiments, the permanent storage device may be a removable storage device (such as a floppy disk, optical drive). The system memory may be a readable and writable storage device or a volatile readable and writable storage device, such as a dynamic random access memory. The system memory may store some or all instructions and data required by the processor at run time. In addition, the memory may include any combination of computer-readable storage media, including various types of semiconductor memory chips (DRAM, SRAM, SDRAM, flash memory, programmable read-only memory), and disks and / or optical disks may also be used. In some embodiments, the memory may include a readable and / or writable removable storage device, such as a laser disc (CD), a read-only digital versatile disc (e.g., DVD-ROM, double-layer DVD-ROM), a read-only Blu-ray disc, an ultra-density optical disc, a flash memory card (e.g., SD card, mini SD card, Micro-SD card, etc.), a magnetic floppy disk, etc. The computer-readable storage medium does not include carrier waves and transient electronic signals transmitted wirelessly or wired.

[0138] The memory stores executable codes, and when the executable codes are processed by the processor, the processor can execute part or all of the methods described above.

[0139] On the other hand, an embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the method for improving the computing throughput of a distribution network monitoring control chip as described above.

[0140] It will be appreciated by those skilled in the art that all or some of the steps and systems in the disclosed method above may be implemented as software, firmware, hardware and appropriate combinations thereof. Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or may be implemented as hardware, or may be implemented as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or a non-transitory medium) and a communication medium (or a temporary medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that may be used to store desired information and may be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0141] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0142] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0143] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A system for improving the computing throughput of a distribution network monitoring and control chip, characterized in that: The system includes a master core module, a slave core module, and a task scheduling module; The main core module is used to distribute computing tasks; The slave core module includes a general slave core and a dedicated slave core; the general slave core is used to execute control logic and operations; the dedicated slave core is used to execute signal analysis and encryption tasks; The task scheduling module is used to schedule tasks according to computing density.

2. The system according to claim 1, characterized in that The main core module uses a static priority scheduling algorithm to allocate tasks to corresponding modules according to the characteristics of the tasks.

3. The system according to claim 1, characterized in that The general slave core uses a pipeline architecture to process logic and matrix operations; the dedicated slave core is used to perform fast Fourier transform signal analysis and advanced encryption standard encryption tasks.

4. The system according to claim 1, characterized in that The task scheduling module uses a dynamic scheduling algorithm based on the computing density of the tasks to allocate high computing load tasks to the dedicated slave cores and allocate low computing load tasks to the general slave cores.

5. The system according to claim 1, characterized in that The system also includes a reconfigurable computing unit; The reconfigurable computing unit is used to load hardware configuration.

6. The system according to claim 1, characterized in that The system also includes a computing unit; The computing unit is used to perform calculations and data processing and execute computing tasks.

7. The system according to claim 1, characterized in that The system also includes an on-chip storage module and an off-chip storage module; The on-chip storage module includes a first cache submodule and a second cache submodule; the first cache submodule is used for high-speed access to instructions and small data; the second cache submodule is used for caching large-scale data; The off-chip storage module is used to store data and system boot programs.

8. The system according to claim 1, characterized in that The system also includes a data management module; The data management module is used to perform data sharing, exchange, synchronization and transmission.

9. A method for improving the computing throughput of a distribution network monitoring control chip, which is implemented by a system for improving the computing throughput of a distribution network monitoring control chip according to any one of claims 1 to 8, characterized in that: The method comprises the following steps: Improve the computing throughput of the distribution network monitoring control chip through the main core module, slave core module, and task scheduling module; Allocate computing tasks; Execute control logic and operations; perform signal analysis and encryption tasks; Schedule tasks according to computing density.

10. The method according to claim 9, characterized in that The method further comprises the following steps: Through dynamic voltage and frequency adjustment technology, the working state of the computing unit is adjusted to balance performance and energy consumption; Use semaphore mechanism to manage data status; Use exclusive lock mechanism to modify data in shared memory.

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