Direct reading method of electric power remote memory

Abstract

The invention discloses a direct reading method for an electric power remote memory, which comprises the following steps of: optimizing a data structure, dynamically adjusting a memory reading strategy, and realizing redundant link configuration and automatic switching, fine-grained lock concurrency control, data encryption, access control and comprehensive test and strategy adjustment. The method effectively improves the efficiency, safety, stability and reliability of memory reading, and comprises the following steps: improving the reading speed by using an efficient data structure, monitoring the network condition and dynamically adjusting a reading strategy, configuring a redundant link to cope with a link fault, and adopting a fine-grained lock to prevent data competition. According to the method, encryption and access control are carried out on reading operation to ensure data security, unit testing, integration testing and pressure testing are carried out to optimize a memory reading strategy, the performance of remote memory reading operation can be remarkably improved, the maintenance cost of an information system is reduced, and stable operation of the information system in a high-concurrency environment is guaranteed.

Description

Technical Field

[0001] The invention relates to the field of information technology, and in particular to a method for directly reading an electric power remote memory. Background Art

[0002] The direct read method of power remote memory generally refers to a technology that allows remote devices or systems to directly access and read memory data in the power information system without going through a local processor or control unit. It usually requires the following key steps and components to complete:

[0003] Remote memory access interface, which allows remote devices to connect to memory devices in the power information system through the network, requires a network adapter or a dedicated communication module; memory mapping, memory mapping technology maps physical memory addresses to network-accessible address space, allowing remote devices to access remote memory like local memory; data transmission protocol, in order to achieve direct reading of remote memory, a set of data transmission protocols is required to manage the sending, receiving, error detection and correction of data packets; security authentication, in order to protect memory data from unauthorized access, a security authentication mechanism will be implemented, such as encryption and authentication protocols.

[0004] The Chinese patent publication number: CN113608686B discloses a method and a related device for directly accessing a remote memory. The main technical principle of the invention is a method and a related device for directly accessing a remote memory. The method reduces the number of memory state exchanges by creating a sliding window, improves the transmission efficiency of unilateral operations, and increases the usability of the RDMA network. When writing data, the target memory block is determined according to the data to be written and the available space of the sliding window, and after the data to be written is written to the target memory block, the available space of the sliding window is reduced. When reading data, a read request is sent to the server, and the target memory block is determined according to the target read data specified in the read request and the available space of the sliding window, and the target read data is copied to the target memory block. In addition, the patent also includes a method in which the sliding window is a circular linked list, and a method for determining the target memory block by rounding up the ratio of the data to be written to the unit length of the memory block in the memory pool.

[0005] The above prior art has the following disadvantages:

[0006] Although sliding windows can reduce the number of times memory states are exchanged, their management and maintenance may be relatively complex, especially in high-concurrency environments, where window creation, adjustment, and destruction may introduce additional overhead; although the RDMA (remote direct memory access) network provides an efficient transmission method, it is very sensitive to network latency. If the network condition is poor, even if the sliding window technology is used, access efficiency may decrease; using a circular linked list to implement a sliding window may not be as efficient as other data structures in some cases, especially in scenarios where frequent insertion and deletion operations are required; in a multi-threaded or multi-process environment, concurrent access to the sliding window requires precise control, otherwise it may cause data contention or inconsistency problems; direct access to remote memory may introduce security risks, and if adequate security measures are not taken, it may be accessed or attacked by unauthorized remote access.

[0007] The present invention proposes a solution to the above-mentioned shortcomings:

[0008] Optimize sliding window management and improve data structures. Use more efficient data structures, such as skip lists or balanced trees (red-black trees), to manage sliding windows and reduce overhead during frequent insertion and deletion operations.

[0009] Dynamic window adjustment: Implement an intelligent dynamic adjustment mechanism for sliding windows, automatically adjust the window size according to the actual network conditions and access patterns to optimize performance; automatically switch to an alternate network path or take other compensatory measures when it detects that the network delay or packet loss rate exceeds the threshold;

[0010] Redundant links use multiple network links to improve network stability and reliability through load balancing and failover strategies;

[0011] The lock mechanism is optimized by using a fine-grained lock concurrency control (OCC) mechanism to reduce lock competition and improve concurrent access efficiency;

[0012] Strengthened security authentication adopts more advanced encryption algorithms and security protocols, such as TLS1.3, as well as implements stricter access control policies. Summary of the invention

[0013] In order to solve the above-mentioned technical problems, the present invention provides a method for directly reading a power remote memory.

[0014] The technical solution of the present invention is achieved in this way:

[0015] S1. Data structure optimization and memory read preparation. Optimize the data structure using jump tables or red-black trees, design memory read interfaces and protocols, quickly respond to read requests, and implement memory prefetching mechanisms.

[0016] S2. Monitor network conditions, including latency, bandwidth, and packet loss rate, evaluate the impact on memory read performance, and dynamically adjust memory read policies based on network conditions, including adjusting the pre-fetch window size or priority, implementing a priority queue for memory reads, and ensuring that critical data can be read first.

[0017] S3, redundant link configuration and memory reading, implement link failure detection and automatic switching mechanism during memory reading, and test the recovery capability of redundant links when memory reading fails;

[0018] S4, concurrency control mechanism optimization and memory read security, use fine-grained lock concurrency control, implement memory read lock mechanism, and prevent data competition caused by concurrent access;

[0019] S5. Encrypt memory read operations to protect data security during transmission and implement access control to ensure that only authorized users can perform memory read operations.

[0020] S6. Perform unit testing of memory reads to verify the accuracy and efficiency of read operations. Perform integration testing of the entire system workflow, including memory reads. Perform stress testing to evaluate the system's performance bottlenecks under high-concurrency memory reads and adjust the memory read strategy based on the test results.

[0021] Furthermore, the data structure in step S1 uses a skip list or a red-black tree to achieve a fast response to a read request:

[0022] In data structure optimization, we choose the efficient data structure Skip List. Skip List can provide logarithmic time complexity in insertion, deletion and search operations, and its implementation is relatively simple. It has a multi-layer index structure, and each layer of index stores data at intervals, so that the search can quickly skip a large number of nodes. At the same time, the red-black tree is a self-balancing binary search tree, which ensures that the worst-case time complexity of search, insertion and deletion is O(log n). The tree is kept balanced through color and rotation operations. The skip list is used to determine the index level and the size of the data block stored in each layer of index. The structure of the skip list node contains a pointer to the next level. The structure of the red-black tree contains color, key value, pointers to left and right child nodes, and parent node pointer.

[0023] The memory read interface and the memory read interface in the protocol include the following methods:

[0024] read(address): read data according to the given memory address;

[0025] prefetch(address): prefetch the data of the specified address into the cache;

[0026] getResponse(): Get the response of the read request;

[0027] The protocols in the memory read interface and protocol include the following:

[0028] TCP / IP-based protocols:

[0029] Request format: includes operation type (read / prefetch), memory address, and data size;

[0030] Response format: includes status code, read data or error information;

[0031] The memory prefetch mechanism enables fast response to read requests. When a read request is received, it immediately checks whether there is data in the cache;

[0032] If the cache hits, the data is returned directly;

[0033] If there is no hit, a memory read operation is triggered;

[0034] Memory prefetching, analyzing read patterns, predicting data to be accessed, and loading it into cache in advance;

[0035] Prefetching based on historical access patterns or prefetching based on access locality, specific steps:

[0036] Initialization: Initialize the jump table or red-black data structure, initialize the cache and prefetch queue;

[0037] Processing read requests: When a read request is received, first search in the buffer. If the data is not in the buffer, use a jump table or red-black tree to find the memory address and read the data;

[0038] Prefetch data: Based on the current read request and access pattern, predict the next read request, add the predicted data address to the prefetch queue, and pre-read it to the cache when the system is idle;

[0039] Optimization and adjustment: Adjust the prefetch strategy and cache size according to the actual operation situation, monitor the changes in data access patterns, and dynamically adjust the prefetch algorithm.

[0040] Furthermore, in the step S2, the network status is monitored and the memory read strategy is dynamically adjusted according to the network status:

[0041] First, monitor the network situation. Latency monitoring uses ping operations or dedicated network diagnostic tools to measure network latency. Bandwidth monitoring calculates the current bandwidth by sending data packets of a specific size and measuring the transmission time. Packet loss monitoring determines the packet loss rate by sending a series of data packets and calculating the proportion of packets that do not receive a response.

[0042] Secondly, dynamically adjust the memory read strategy and prefetch window size:

[0043] If the network bandwidth is high and the latency is low, increase the prefetch window size to load more data in advance;

[0044] If the network condition is poor, reduce the prefetch window size to reduce the waiting time caused by too much prefetched data;

[0045] Adjust prefetch priority:

[0046] Dynamically adjust the priority of pre-fetched data according to network conditions, including giving priority to pre-fetching non-urgent data when the network condition is good, and giving priority to pre-fetching critical data when the network condition is poor;

[0047] Next, implement the priority queue for memory reading and define the priority queue:

[0048] Define priorities based on the importance of the data, including business-critical data with the highest priority, and prioritize data based on the urgency and access frequency of the data;

[0049] Queue Operations:

[0050] When a read request is received, it is inserted into the priority queue according to the data type and priority of the request. The read operation prioritizes the requests in the priority queue.

[0051] Next, ensure that key data is read first and identify key data:

[0052] Identify critical data, including real-time control instructions and emergency fault information, which will be given the highest priority in the priority queue;

[0053] Priority reading mechanism:

[0054] Prioritize key data requests in the priority queue. If the key data is not in the buffer, trigger the memory read operation immediately and reduce the waiting time.

[0055] The specific process of the above content is as follows:

[0056] Initialize monitoring tools, including ping tools, broadband test tools, and packet loss rate monitoring tools;

[0057] Periodic monitoring: regularly perform ping operations, record latency data, regularly perform broadband tests, record broadband data, regularly monitor packet loss rates, and record packet loss data;

[0058] Dynamically adjust the strategy. If the network delay increases or the bandwidth decreases, reduce the pre-fetch window size. If the packet loss rate increases, lower the pre-fetch priority and focus on reading key data.

[0059] Implement priority queues to ensure that critical data requests are processed first;

[0060] The above steps ensure that based on the optimization of step S1, step S2 can dynamically adjust the memory read strategy according to the real-time network status.

[0061] Furthermore, after completing S1 (data structure optimization and memory read preparation) and S2 (monitoring network status and dynamically adjusting memory read strategy), the S3 step will focus on implementing redundant link configuration and memory read, and ensure automatic switching and recovery in the event of a link failure. The following is a detailed process for implementing the S3 step:

[0062] Redundant link configuration, determine the number and configuration of redundant links, ensure that each key memory read path has at least one backup link, link allocation is to assign the main link and redundant link to different memory read tasks for load balancing and fast switching in case of failure; link fault detection, real-time monitoring of the status of all links, including link connectivity, bandwidth, latency and packet loss rate indicators; the fault detection algorithm uses a heartbeat mechanism, link status monitoring or BFD (Bidirectional Forwarding Detection); the fault trigger in the automatic switching mechanism is to immediately trigger the switching mechanism when the main link failure is detected, and the switching process is to switch to the redundant link, reinitialize the memory read operation, and update the network configuration and routing table; the simulated fault in testing the recovery capability of the redundant link is: simulating the main link failure in the test environment, including by physically disconnecting or configuring the link to be down, where the recovery test is used to test whether the system can automatically switch to the redundant link and continue the memory read operation, and record the switching time and data recovery;

[0063] The detailed steps of the above content are:

[0064] Configure redundant links: Configure at least one redundant link for each memory read path to ensure that the redundant link is physically separated from the main link to avoid common mode failures;

[0065] Realize link monitoring: collect link status information in real time;

[0066] Fault detection: The fault detection algorithm sets the fault threshold;

[0067] Implement automatic switching: automatically execute when a link failure is detected, and configure network devices to support fast link switching;

[0068] Test the switching mechanism: simulate link failures in a non-production environment to verify the effectiveness of the automatic switching mechanism, and record the switching time, data loss, and system recovery time;

[0069] Evaluate recovery capability: Analyze test results and evaluate the recovery capability of redundant links when memory read fails. Adjust fault detection thresholds and switching processes based on test results to optimize recovery mechanisms.

[0070] Through the above steps, step S3 can ensure that when the main link fails, the system can quickly switch to the redundant link and restore normal memory read operations, thereby improving the reliability and stability of the system.

[0071] Furthermore, after completing steps S1 (data structure optimization and memory read preparation), S2 (monitoring network status and dynamically adjusting memory read strategy) and S3 (redundant link configuration and memory read, and implementing link fault detection and automatic switching mechanism), step S4 will focus on concurrent control mechanism optimization and memory read security. The following is the detailed process of step S4:

[0072] Fine-grained locks are used to analyze the characteristics of memory read operations and determine the lock granularity, which is used to reduce lock contention and improve the efficiency of concurrent access. Lock implementation: Fine-grained use of read-write locks or optimistic locks.

[0073] Lock mechanism for memory read: The lock strategy is used to determine the lock acquisition and release strategy, including acquiring the lock before the memory read operation and releasing the lock after the operation is completed; Lock allocation: Allocate lock resources according to different memory read tasks to ensure that key operations can obtain locks first;

[0074] Preventing data competition: Data competition detection is used to implement data competition detection mechanisms and monitor potential conflicts in concurrent access; Conflict resolution: When data competition is detected, strategies are adopted to resolve the conflict, including rollback operations or retry mechanisms;

[0075] Testing the concurrency control mechanism: Concurrency testing is used to simulate high-concurrency access scenarios in the test environment and verify the effectiveness of the fine-grained locking mechanism; performance evaluation is used to evaluate the impact of the concurrency control mechanism on memory read performance;

[0076] The detailed steps of the above content are:

[0077] Identify critical regions in memory read operations and design fine-grained locks for these regions;

[0078] Write code to implement fine-grained locks and ensure that the lock acquisition and release logic is correct;

[0079] Develop clear lock acquisition and release strategies to avoid deadlock and resource starvation;

[0080] Perform concurrent memory read operations in a simulated environment to test whether the locking mechanism is effective;

[0081] Adjust the lock strategy based on the test results, optimize the concurrency control mechanism, and identify and resolve performance bottlenecks;

[0082] Through the above steps, step S4 can ensure that during concurrent access to memory, data contention is effectively prevented through a fine-grained lock mechanism while maintaining the security and efficiency of memory read operations.

[0083] Furthermore, after completing steps S1 (data structure optimization and memory read preparation), S2 (monitoring network status and dynamically adjusting memory read strategy), S3 (redundant link configuration and memory read, and implementing link fault detection and automatic switching mechanism) and S4 (concurrency control mechanism optimization and memory read security), step S5 will focus on data encryption and access control of memory read operations to ensure data security during transmission and that only authorized users can perform memory read operations. The following is a detailed process:

[0084] Memory read operation encryption: Encryption strategy formulation is used to determine the encryption algorithm used for memory read operations, such as AES (Advanced Encryption Standard) or RSA; encryption strategy formulation includes key management and encryption mode (CBC, GCM); encryption implementation: data is encrypted before memory read operations and kept encrypted during data transmission to ensure data security during transmission in the link;

[0085] Access control implementation: Authentication is used to implement user authentication mechanisms, including the use of passwords, certificates, or biometrics; Permission management is used to establish a permission management system, define user roles and permission levels, and ensure that only users with corresponding permissions can perform memory read operations; Access control lists (ACLs) are used to create and maintain access control lists, which record in detail which users or roles have access to which memory resources;

[0086] Integration of encryption and access control is used to integrate encryption mechanism and access control into the memory reading process to ensure that the access control logic is correctly executed during data encryption and transmission;

[0087] Security testing in testing and verification is used to perform security testing on encryption and access control mechanisms, including security performance testing of encryption algorithms and effectiveness of access control;

[0088] Compliance checks are used to verify that encryption and access control mechanisms comply with relevant security standards and regulatory requirements;

[0089] The detailed steps of the above content are:

[0090] Develop encryption strategies, select encryption algorithms and key generation and management solutions;

[0091] Implement encryption and realize data encryption and decryption functions in the memory reading interface;

[0092] Authentication mechanism, develop user authentication module and integrate it into the system;

[0093] Permission management, create user roles and permission models, and implement permission verification logic;

[0094] Integrated access control, adding access control checks to the memory reading process to ensure that only authorized users can perform operations;

[0095] Test encryption and access control through unit testing, integration testing, and stress testing of encryption and access control;

[0096] Optimize and adjust: adjust encryption algorithms and access control policies based on test results to ensure system security and ease of use;

[0097] Through the above steps, step S5 can ensure the data security of the memory read operation during the transmission process, and protect the memory resources from unauthorized access through the access control mechanism.

[0098] Furthermore, after completing steps S1 (data structure optimization and memory read preparation), S2 (monitoring network status and dynamically adjusting memory read strategy), S3 (redundant link configuration and memory read, and implementing link fault detection and automatic switching mechanism), S4 (concurrency control mechanism optimization and memory read security) and S5 (memory read operation encryption and access control), step S6 will focus on unit testing, integration testing and stress testing of memory read operations to verify the accuracy and efficiency of the operation and evaluate the performance bottleneck of the system under high concurrency. The following is the detailed process:

[0099] In the test and performance evaluation of memory read operations, unit testing is used to exhaustively test cases for memory reader operations, covering all read paths and boundary conditions; test execution, executes unit tests, verifies the accuracy and efficiency of each memory read operation, and records test results including pass, fail, and exceptions; defect repair is used to analyze failed cases, locate the problem, and repair it, re-execute the test, and ensure that all cases pass;

[0100] Workflow testing in integration testing is used to integrate test cases, covering the entire memory reading process from data structure optimization, network monitoring, link configuration, concurrency control to encryption and access control; test environment construction is used to build a test environment that simulates the real operating environment to ensure the effectiveness of integration testing; test execution is used to perform integration testing to verify whether the workflow of the entire system proceeds as expected, record test results, and analyze whether the interaction between system components is correct;

[0101] The stress test scenario in the stress test is used to simulate high-concurrency memory read operations; performance monitoring is used to monitor the system's performance indicators during the test, including response time, throughput, and resource utilization; bottleneck analysis is used to analyze the test results and identify the system's performance bottlenecks under high concurrency conditions;

[0102] In the test result analysis and strategy adjustment, result analysis is used to analyze the results of unit testing, integration testing and stress testing to find out the problems in the system; strategy adjustment is used to adjust the memory read strategy according to the test results, including optimizing data structure, improving concurrency control mechanism, adjusting encryption and access control process; iterative testing is used to re-execute related tests after adjusting the strategy to ensure the effectiveness of the improvement measures.

[0103] Beneficial Effects

[0104] The present invention effectively solves the shortcomings of the prior art by the following technical means and achieves the following

[0105] Beneficial effects:

[0106] Improving memory reading efficiency By adopting efficient data structures such as skip lists or red-black trees, the indexing and access speed of memory reading are optimized, thereby significantly improving the efficiency of memory reading.

[0107] Enhanced system stability Through intelligent and dynamic adjustment of the sliding window size and redundant link configuration, it can automatically adjust according to network conditions, effectively deal with network delays and failures, and enhance the stability and reliability of the system.

[0108] Reduce maintenance complexity Through the improved sliding window management mechanism, the complexity of window creation, adjustment and destruction in a high-concurrency environment is reduced, and the difficulty of system maintenance is reduced.

[0109] Improve security by strengthening the security authentication mechanism, adopting TLS1.3 encryption algorithm and strict access control policy, effectively preventing unauthorized access and data leakage, and improving the security of information systems.

[0110] Optimized concurrency control reduces lock contention and improves the efficiency of concurrent access by introducing fine-grained locks and optimistic concurrency control mechanisms, while preventing data contention and inconsistency issues.

[0111] Ensure data transmission security By encrypting memory read operations, the security of data during transmission is protected, ensuring the integrity and confidentiality of data.

[0112] Precise access control further protects system resources by implementing refined access control to ensure that only authorized users can perform memory read operations.

[0113] The comprehensive evaluation of system performance fully verifies the accuracy and efficiency of memory read operations through unit testing, integration testing, and stress testing, and identifies the performance bottlenecks of the system under high concurrency conditions, providing a basis for policy adjustments.

[0114] Continuous system optimization adjusts the memory read strategy according to the test results, ensures the effectiveness of improvement measures through iterative testing, and achieves continuous optimization and upgrading of the system.

[0115] In summary, the present invention not only improves the performance and security of the power remote memory direct reading method, but also simplifies the information system maintenance and improves the overall reliability and user experience of the information system.

[0116] Working principle:

[0117] First, in step S1, by optimizing the data structure, using a jump table or red-black tree, designing the memory read interface and protocol, quickly responding to read requests, and implementing a memory prefetch mechanism, so that when a read request is received, the system can immediately check whether there is data in the cache. If the cache hits, the data is directly returned; if there is no hit, the memory read operation is triggered, and the next read request is predicted based on the read mode, and the predicted data address is added to the prefetch queue and loaded into the cache in advance;

[0118] Secondly, in step S2, the network status, including latency, bandwidth, and packet loss rate, is monitored to evaluate the impact on memory read performance and dynamically adjust the memory read strategy. According to the network status, the pre-fetch window size and priority are adjusted to implement the priority queue for memory reads and ensure that critical data can be read first. This step ensures that when the network status changes, the information system can adaptively adjust the strategy to maintain the optimal read performance;

[0119] Next, in step S3, redundant link configuration and memory reading are implemented, including link failure detection and automatic switching mechanism. By configuring redundant links, the link status is monitored in real time, and when a primary link failure is detected, the switching mechanism is immediately triggered to switch to the redundant link and reinitialize the memory reading operation, thereby ensuring that the information system can recover quickly when a link fails, thereby improving the reliability and stability of the information system.

[0120] Then, in step S4, the concurrency control mechanism and memory read security are optimized, and fine-grained lock concurrency control is used to implement the lock mechanism for memory reads to prevent data contention caused by concurrent access. This step ensures data consistency and security during concurrent memory access by identifying key areas in memory read operations and designing fine-grained locks for these areas.

[0121] In addition, in step S5, the memory read operation is encrypted to protect the security of data during transmission, and access control is implemented to ensure that only authorized users can perform memory read operations. By formulating encryption strategies, implementing encryption, and integrating access control into the memory read process, data security and the effectiveness of the system's access control are ensured;

[0122] Finally, in step S6, unit testing, integration testing, and stress testing of memory reads are performed to verify the accuracy and efficiency of read operations, evaluate the performance bottleneck of the system under high-concurrency memory reads, and adjust the memory read strategy based on the test results. This step ensures the optimization of system performance and strategy through comprehensive testing and evaluation.

[0123] In summary, the present invention realizes direct reading of power remote memory through a series of interconnected steps, while ensuring the efficiency, safety, stability and reliability of the reading. BRIEF DESCRIPTION OF THE DRAWINGS

[0124] Figure 1 It is a structural block diagram of a method for directly reading a power remote memory in an embodiment of the present invention;

[0125] Figure 2 The present invention is a flowchart of a method for directly reading a power remote memory according to an embodiment of the present invention. DETAILED DESCRIPTION

[0126] In order to make the objects and advantages of the present invention more clearly understood, the present invention is further described below in conjunction with embodiments; it should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0127] The preferred implementation methods of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these implementation methods are only used to explain the technical principles of the present invention and are not intended to limit the protection scope of the present invention.

[0128] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0129] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0130] See also Figure 1-Figure 2 As shown, a method for directly reading a power remote memory includes:

[0131] S1. Data structure optimization and memory read preparation. Optimize the data structure using jump tables or red-black trees, design memory read interfaces and protocols, quickly respond to read requests, and implement memory prefetching mechanisms.

[0132] S2. Monitor network conditions, including latency, bandwidth, and packet loss rate, evaluate the impact on memory read performance, and dynamically adjust memory read policies based on network conditions, including adjusting the pre-fetch window size or priority, implementing a priority queue for memory reads, and ensuring that critical data can be read first.

[0133] S3, redundant link configuration and memory reading, implement link failure detection and automatic switching mechanism during memory reading, and test the recovery capability of redundant links when memory reading fails;

[0134] S4, concurrency control mechanism optimization and memory read security, use fine-grained lock concurrency control, implement memory read lock mechanism, and prevent data competition caused by concurrent access;

[0135] S5. Encrypt memory read operations to protect data security during transmission and implement access control to ensure that only authorized users can perform memory read operations.

[0136] S6. Perform unit testing of memory reads to verify the accuracy and efficiency of read operations. Perform integration testing of the entire system workflow, including memory reads. Perform stress testing to evaluate the system's performance bottlenecks under high-concurrency memory reads and adjust the memory read strategy based on the test results.

[0137] Furthermore, the data structure in step S1 uses a skip list or a red-black tree to achieve a fast response to a read request:

[0138] In data structure optimization, we choose the efficient data structure Skip List. Skip List can provide logarithmic time complexity in insertion, deletion and search operations, and its implementation is relatively simple. It has a multi-layer index structure, and each layer of index stores data at intervals, so that the search can quickly skip a large number of nodes. At the same time, the red-black tree is a self-balancing binary search tree, which ensures that the worst-case time complexity of search, insertion and deletion is O(log n). The tree is balanced through color and rotation operations. The skip list is used to determine the index level and the size of the data block stored in each layer of index. The structure of the skip list node contains a pointer to the next level. The structure of the red-black tree contains color, key value, pointers to left and right child nodes, and a parent node pointer.

[0139] Specifically, a skip table or a red-black tree is used to quickly respond to read requests:

[0140] 1. Choose the data structure

[0141] Skip List: Determine the index level: The preset data volume is n, and the index level k is determined by log 2 (n) to estimate;

[0142] The size of the data block stored in each index layer: the interval of the i-th index layer is 2^(ki), that is, the interval of the 0th layer (the bottom layer) is 1, the interval of the 1st layer is 2, and so on;

[0143] Skip list node structure: contains data values ​​and pointer arrays pointing to the next level nodes;

[0144] Red-Black Tree: Node structure: contains color (red or black), key value, pointers to left and right child nodes, and parent node pointer;

[0145] 2. Memory read interface and protocol implementation

[0146] Interface methods:

[0147] read(address): reads data according to the address, the time complexity is O(log n);

[0148] prefetch(address): prefetch data to cache, the time complexity is O(log n);

[0149] getResponse(): Get the response, the time complexity is O(1);

[0150] Agreement Contents:

[0151] The request and response formats are encapsulated according to the TCP / IP protocol stack;

[0152] 3. Memory prefetching mechanism implementation

[0153] Initialization: Initialize the jump table or red-black tree, as well as the cache and prefetch queue;

[0154] Processing read request: Check cache: time complexity is O(1);

[0155] If the cache misses, use a skip table or red-black tree to find the data: the time complexity is O(log n);

[0156] Prefetch data: Analyze the read mode: presuppose the principle of access locality, that is, data accessed continuously may also be continuous in physical address;

[0157] Prefetch strategy: Based on historical access patterns, predict the location of the next data block and add it to the prefetch queue;

[0158] Optimization and adjustment: Adjust the cache size: adjust according to the hit rate, the preset cache size is m, the hit rate is p, then the expected cache size is m'=m*p;

[0159] Adjust prefetch algorithm: dynamically adjust prefetch strategy according to changes in data access patterns;

[0160] Computational Verification Process

[0161] The preset data volume is 1024 nodes, and the index level of the skip list is calculated:

[0162] Index level k = log 2 (1024) = 10;

[0163] If you choose 4-level index, the top-level index interval is 2^(4-4)=1, the second-level index interval is 2^(4-3)=2, and so on;

[0164] Cache hit ratio calculation:

[0165] The preset cache size is 128, the total number of read requests is 1000, and the number of hits is 800;

[0166] Hit rate p = 800 / 1000 = 0.8;

[0167] Adjust the cache size according to the hit rate: m = 128 * 0.8 = 102.4, rounded up to 103;

[0168] Through the above steps, it is ensured that the system can respond to read requests quickly, and the overall performance is improved through the prefetch mechanism.

[0169] Furthermore, in the step S2, the network status is monitored and the memory read strategy is dynamically adjusted according to the network status:

[0170] First, monitor the network situation. Latency monitoring uses ping operations or dedicated network diagnostic tools to measure network latency. Bandwidth monitoring calculates the current bandwidth by sending data packets of a specific size and measuring the transmission time. Packet loss monitoring determines the packet loss rate by sending a series of data packets and calculating the proportion of packets that do not receive a response.

[0171] Secondly, dynamically adjust the memory read strategy and prefetch window size:

[0172] If the network bandwidth is high and the latency is low, increase the prefetch window size to load more data in advance;

[0173] If the network condition is poor, reduce the prefetch window size to reduce the waiting time caused by too much prefetched data;

[0174] Adjust prefetch priority:

[0175] Dynamically adjust the priority of pre-fetched data according to network conditions, including giving priority to pre-fetching non-urgent data when the network condition is good, and giving priority to pre-fetching critical data when the network condition is poor;

[0176] Next, implement the priority queue for memory reading and define the priority queue:

[0177] Define priorities based on the importance of the data, including business-critical data with the highest priority, and prioritize data based on the urgency and access frequency of the data;

[0178] Queue Operations:

[0179] When a read request is received, it is inserted into the priority queue according to the data type and priority of the request. The read operation prioritizes the requests in the priority queue.

[0180] Next, ensure that key data is read first and identify key data:

[0181] Identify critical data, including real-time control instructions and emergency fault information, which will be given the highest priority in the priority queue;

[0182] Priority reading mechanism:

[0183] Prioritize critical data requests in the priority queue. If the critical data is not in the buffer, trigger the memory read operation immediately and possibly reduce the waiting time.

[0184] Specifically, the memory read strategy is dynamically adjusted according to the network status:

[0185] 1. Monitor network status

[0186] Initialize monitoring tools: Initialize ping tool, broadband test tool and packet loss rate monitoring tool;

[0187] Periodic monitoring:

[0188] Delay monitoring: Use the ping operation, for example: ping -c 4 <destination address>, and record the average delay time;

[0189] Broadband monitoring: Send a data packet of a specific size (such as 100MB) and measure the transmission time to calculate the bandwidth: bandwidth = data packet size / transmission time;

[0190] Packet loss rate monitoring: Send a series of data packets (such as 100) and calculate the proportion of packets that did not receive a response;

[0191] 2. Dynamically adjust memory read strategy

[0192] Adjust the prefetch window size:

[0193] The current pre-fetch window size is preset to W and adjusted according to the network conditions:

[0194] If the bandwidth is high > 100Mbps and the latency is low < 10ms, increase the prefetch window: W = W*1.5;

[0195] If the network condition is not good, reduce the prefetch window: W = W / 2;

[0196] Adjust prefetch priority:

[0197] Adjust the priority of prefetching data according to network conditions:

[0198] When the network condition is good, prefetching non-urgent data is prioritized;

[0199] When the network condition is poor, priority is given to pre-fetching critical data;

[0200] 3. Implementing a priority queue for memory reading

[0201] Define priority queues: Define priorities based on the importance of data, such as business-critical data has the highest priority;

[0202] Queue operation: When a read request is received, it is inserted into the priority queue according to the data type and priority of the request;

[0203] Ensure that critical data is read first:

[0204] Identify critical data and give it the highest priority;

[0205] Prioritize critical data requests in the priority queue;

[0206] Computational Verification Process

[0207] Initialize the monitoring tool:

[0208] The default setting is to use the ping command for latency monitoring, iperf for broadband testing, and a custom script for packet loss rate monitoring.

[0209] Periodic monitoring:

[0210] The average latency returned by the default ping operation is 30ms;

[0211] The broadband test results show that the transmission time of a 100MB data packet is 1 second, so the bandwidth is 100MB / s = 800Mbps;

[0212] Packet loss rate monitoring shows that if 5 out of 100 packets sent do not receive a response, the packet loss rate is 5%;

[0213] Dynamic adjustment strategy:

[0214] The current pre-fetch window size is preset to 100KB. According to the above monitoring results:

[0215] Due to high bandwidth and low latency, increase the prefetch window: W = 100KB*1.5 = 150KB;

[0216] If the packet loss rate rises to 10%, reduce the prefetch window: W = 150KB / 2 = 75KB;

[0217] Through the above steps, step S2 can ensure that the memory read strategy is dynamically adjusted according to the real-time network status based on the optimization of step S1, thereby improving the flexibility and efficiency of the system.

[0218] Furthermore, after completing S1 (data structure optimization and memory read preparation) and S2 (monitoring network status and dynamically adjusting memory read strategy), the S3 step will focus on implementing redundant link configuration and memory read, and ensure automatic switching and recovery in the event of a link failure. The following is a detailed process for implementing the S3 step:

[0219] Redundant link configuration, determine the number and configuration of redundant links, ensure that each key memory read path has at least one backup link, link allocation is to assign the main link and redundant link to different memory read tasks for load balancing and fast switching in case of failure; link fault detection, real-time monitoring of the status of all links, including link connectivity, bandwidth, latency and packet loss rate indicators; the fault detection algorithm uses a heartbeat mechanism, link status monitoring or BFD (Bidirectional Forwarding Detection); the fault trigger in the automatic switching mechanism is to immediately trigger the switching mechanism when a main link failure is detected, and the switching process is to switch to the redundant link, reinitialize the memory read operation, and update the network configuration and routing table; the simulated fault in testing the recovery capability of the redundant link is: simulating the main link failure in the test environment, including by physically disconnecting or configuring the link to be down, where the recovery test is used to test whether the system can automatically switch to the redundant link and continue the memory read operation, and record the switching time and data recovery.

[0220] Specifically, redundant link configuration and memory readout ensure automatic switching and recovery in the event of a link failure:

[0221] 1. Configure redundant links

[0222] Determine the number of redundant links: The system is assumed to have N key memory read paths, and at least one redundant link is configured for each path, that is, the total number of redundant links is N;

[0223] Link allocation: Assign the main link and redundant link to different memory reading tasks to ensure load balancing; if N=4, configure 4 main links and 4 redundant links;

[0224] 2. Implement link monitoring

[0225] Collect link status information in real time: Use SNMP, NetFlow or the system's own monitoring tools to collect link status information;

[0226] 3. Fault Detection

[0227] Set failure thresholds: set the delay threshold to 50ms and the packet loss rate threshold to 5%;

[0228] 4. Realize automatic switching

[0229] Configure network devices: Configure network devices to support fast link switching, using VRRP (Virtual Router Redundancy Protocol);

[0230] 5. Test the switching mechanism

[0231] Simulate link failure: Simulate the main link failure in a non-production environment, including unplugging the network cable or configuring the link to be down;

[0232] Record test data: record switching time, data loss and system recovery time;

[0233] 6. Assess recovery capabilities

[0234] Analyze the test results: The preset test results show that the time from the occurrence of the fault to the completion of the switch is T seconds, and the amount of data loss is D bytes;

[0235] Adjust fault detection thresholds and switching processes: If T exceeds the preset maximum acceptable switching time, or D exceeds the acceptable amount of data loss, adjust the thresholds and processes;

[0236] Computational Verification Process

[0237] Redundant link configuration: If the preset critical path N=4, then 4 redundant links are configured;

[0238] Link monitoring: The preset monitoring tool shows that the current latency of the main link 1 is 45ms and the packet loss rate is 2%;

[0239] Fault detection: If the delay exceeds 50ms or the packet loss rate exceeds 5%, fault detection is triggered;

[0240] Automatic switching: If the main link 1 fails, the system will switch to the redundant link 1 within 0.5 seconds;

[0241] Test the switching mechanism:

[0242] Simulate the failure of the main link 1, record the switching time T = 0.5 seconds, and the data loss D = 0 bytes (under ideal conditions);

[0243] Evaluate recovery capability: If T = 0.5 seconds is within the acceptable range and D = 0, the recovery capability is considered to meet the requirements. Otherwise, it is necessary to adjust the fault detection threshold or optimize the switching process.

[0244] Through the above steps, step S3 can ensure that when the main link fails, the system can quickly switch to the redundant link and restore normal memory read operations, thereby improving the reliability and stability of the system.

[0245] Furthermore, in the step S4, after completing the steps S1 (data structure optimization and memory read preparation), S2 (monitoring network status and dynamically adjusting memory read strategy) and S3 (redundant link configuration and memory read, and implementing link fault detection and automatic switching mechanism), the step S4 will focus on the optimization of the concurrency control mechanism and the memory read security. The following is the detailed process of the step S4:

[0246] Fine-grained locks are used to analyze the characteristics of memory read operations and determine the lock granularity, which is used to reduce lock contention and improve the efficiency of concurrent access. Lock implementation: Fine-grained use of read-write locks or optimistic locks.

[0247] Lock mechanism for memory read: The lock strategy is used to determine the lock acquisition and release strategy, including acquiring the lock before the memory read operation and releasing the lock after the operation is completed; Lock allocation: Allocate lock resources according to different memory read tasks to ensure that key operations can obtain locks first;

[0248] Preventing data competition: Data competition detection is used to implement data competition detection mechanisms and monitor potential conflicts in concurrent access; Conflict resolution: When data competition is detected, strategies are adopted to resolve the conflict, including rollback operations or retry mechanisms;

[0249] Testing the concurrency control mechanism: Concurrency testing is used to simulate high-concurrency access scenarios in the test environment and verify the effectiveness of the fine-grained locking mechanism; performance evaluation is used to evaluate the impact of the concurrency control mechanism on memory read performance.

[0250] Specifically, concurrency control mechanism optimization and memory read security:

[0251] 1. Determine the lock granularity

[0252] Analyze memory read operation characteristics: Identify key areas in memory read operations, including specific data structures or memory address ranges;

[0253] Fine-grained lock: There are R preset key areas, and independent locks are designed for each area;

[0254] 2. Implement fine-grained locking

[0255] Choose the lock type: Use a read-write lock to allow multiple read operations to proceed simultaneously, but write operations are exclusive,

[0256] Or use optimistic locking to check the version number when the data is updated;

[0257] Write the lock code:

[0258] Acquire a read lock before the read operation and release the read lock after the read operation is completed;

[0259] Acquire the write lock before the write operation and release the write lock after the write operation is completed;

[0260] 3. Develop a locking strategy

[0261] Lock acquisition and release strategy: ensure that the lock is acquired before the memory read operation and released after the operation is completed to avoid deadlock, and adopt a hierarchical or sequential lock acquisition strategy;

[0262] 4. Prevent data races

[0263] Data race detection: Implement monitoring mechanisms, including using atomic operations or lock states to detect potential conflicts;

[0264] Conflict resolution: When data contention is detected, a rollback operation or retry mechanism is used;

[0265] 5. Test concurrency control mechanism

[0266] Concurrency testing: Perform concurrent memory read operations in a simulated environment, including starting 100 threads to read different areas simultaneously;

[0267] Performance evaluation: record the total time T of concurrent operations and the number of successfully completed operations N;

[0268] 6. Adjust the lock strategy

[0269] Analyze the test results: The preset test results show that 95 out of 100 concurrent operations were successful, with a total time of 5 seconds;

[0270] Optimize the concurrency control mechanism: if the success rate is lower than expected or the total time is too long, adjust the lock strategy;

[0271] If a lock is found to be a bottleneck, further subdivide the lock granularity;

[0272] Computational Verification Process

[0273] Lock granularity determination: If the preset critical area R=10, then 10 fine-grained locks are designed;

[0274] Concurrency test: among the preset 100 concurrent operations, each operation takes an average of 0.05 seconds, and the total time T = 5 seconds;

[0275] Performance evaluation: success rate = number of successful operations / total number of operations = 95 / 100 = 95%;

[0276] Average operation time = total time / number of successful operations = 5 seconds / 95 ≈ 0.0526 seconds;

[0277] Adjust the lock strategy: If the average operation time is too long, consider reducing the lock granularity or optimizing the lock acquisition and release logic;

[0278] Through the above steps, step S4 can ensure that during concurrent access to memory, data contention is effectively prevented through a fine-grained lock mechanism while maintaining the security and efficiency of memory read operations.

[0279] Furthermore, after completing steps S1 (data structure optimization and memory read preparation), S2 (monitoring network status and dynamically adjusting memory read strategy), S3 (redundant link configuration and memory read, and implementing link fault detection and automatic switching mechanism) and S4 (concurrency control mechanism optimization and memory read security), step S5 will focus on data encryption and access control of memory read operations to ensure data security during transmission and that only authorized users can perform memory read operations. The following is a detailed process:

[0280] Memory read operation encryption: Encryption strategy formulation is used to determine the encryption algorithm used for memory read operations, such as AES (Advanced Encryption Standard) or RSA; encryption strategy formulation includes key management and encryption mode (CBC, GCM); encryption implementation: data is encrypted before memory read operations and kept encrypted during data transmission to ensure data security during transmission in the link;

[0281] Access control implementation: Authentication is used to implement user authentication mechanisms, including the use of passwords, certificates, or biometrics; Permission management is used to establish a permission management system, define user roles and permission levels, and ensure that only users with corresponding permissions can perform memory read operations; Access control lists (ACLs) are used to create and maintain access control lists, which record in detail which users or roles have access to which memory resources;

[0282] Integration of encryption and access control is used to integrate encryption mechanism and access control into the memory reading process to ensure that the access control logic is correctly executed during data encryption and transmission;

[0283] Security testing in testing and verification is used to perform security testing on encryption and access control mechanisms, including security performance testing of encryption algorithms and effectiveness of access control;

[0284] Compliance checks are used to verify that encryption and access control mechanisms comply with relevant security standards and regulatory requirements.

[0285] Specifically, data encryption and access control for memory read operations ensure data security during transmission and that only authorized users can perform memory read operations:

[0286] Preset Data

[0287] Original data: "First mission" (text information);

[0288] AES-256 bit encryption key: "12345678901234567890123456789012" (32-byte key);

[0289] Initialization vector (IV): "123456789012" (12 bytes);

[0290] Computational Verification Process

[0291] Calculate the hash value of the original data, and use the SHA-256 hash algorithm to hash the original data; the preset calculated hash value is: "Hash1"

[0292] Encrypt the original data using the AES-256 bit encryption algorithm and GCM mode, as well as the preset key and IV.

[0293] The default encrypted data is: "EncryptedData"

[0294] Decrypting encrypted data

[0295] Decrypt "EncryptedData" using the same key and IV;

[0296] The default decrypted data is restored as: "DecryptedData"

[0297] Calculate the hash value of the decrypted data

[0298] Hash "DecryptedData" using the SHA-256 hash algorithm;

[0299] The default calculated hash value is: "Hash2"

[0300] Comparing hash values

[0301] Compare "Hash1" to "Hash2";

[0302] If "Hash1" == "Hash2", the encryption and decryption process maintains the integrity of the data and the verification is successful;

[0303] If "Hash1" != "Hash2", it means that an error occurred during the encryption or decryption process and further inspection is required;

[0304] Example verification results

[0305] The default value of "Hash1" is:

[0306] "a591a6d40bf420404a011733cfb7b190d62c65bf0bcda32b57b277d9ad9f146e"

[0307] The default "Hash2" is also:

[0308] "a591a6d40bf420404a011733cfb7b190d62c65bf0bcda32b57b277d9ad9f146e"

[0309] Since "Hash1" is the same as "Hash2", it is confirmed that the encryption and decryption process is correct and the data has not been tampered with in the process.

[0310] Furthermore, after completing steps S1 (data structure optimization and memory read preparation), S2 (monitoring network status and dynamically adjusting memory read strategy), S3 (redundant link configuration and memory read, and implementing link fault detection and automatic switching mechanism), S4 (concurrency control mechanism optimization and memory read security) and S5 (memory read operation encryption and access control), step S6 will focus on unit testing, integration testing and stress testing of memory read operations to verify the accuracy and efficiency of the operation and evaluate the performance bottleneck of the system under high concurrency. The following is the detailed process:

[0311] In the test and performance evaluation of memory read operations, unit testing is used to exhaustively test cases for memory reader operations, covering all read paths and boundary conditions; test execution, executes unit tests, verifies the accuracy and efficiency of each memory read operation, and records test results including pass, fail, and exceptions; defect repair is used to analyze failed cases, locate the problem, and repair it, re-execute the test, and ensure that all cases pass;

[0312] Workflow testing in integration testing is used to integrate test cases, covering the entire memory reading process from data structure optimization, network monitoring, link configuration, concurrency control to encryption and access control; test environment construction is used to build a test environment that simulates the real operating environment to ensure the effectiveness of integration testing; test execution is used to perform integration testing to verify whether the workflow of the entire system proceeds as expected, record test results, and analyze whether the interaction between system components is correct;

[0313] The stress test scenario in the stress test is used to simulate high-concurrency memory read operations; performance monitoring is used to monitor the system's performance indicators during the test, including response time, throughput, and resource utilization; bottleneck analysis is used to analyze the test results and identify the system's performance bottlenecks under high concurrency conditions;

[0314] In the test result analysis and strategy adjustment, result analysis is used to analyze the results of unit testing, integration testing and stress testing to find out the problems in the system; strategy adjustment is used to adjust the memory read strategy according to the test results, including optimizing data structure, improving concurrency control mechanism, adjusting encryption and access control process; iterative testing is used to re-execute related tests after adjusting the strategy to ensure the effectiveness of the improvement measures.

[0315] Specifically, memory read operations undergo unit testing, integration testing, and stress testing to verify the accuracy and efficiency of the operations:

[0316] Test case writing, writing test cases, including normal conditions, boundary conditions and abnormal conditions;

[0317] Test execution and computational verification;

[0318] Execute test cases and record the response time and results of each operation;

[0319] Assume that a memory read operation is expected to be completed within an average time T_avg, with a standard deviation of σ;

[0320] The actual operation completion time is T_actual;

[0321] Calculate the difference between the actual time and the average time: ΔT = T_actual-T_avg;

[0322] Verification: If |ΔT|≤σ, the operation time is within the acceptable range; otherwise, it is marked as a potential performance issue;

[0323] Bug fixes and retesting

[0324] Analyze and fix the use cases marked as failed;

[0325] Re-execute the test to verify the repair effect;

[0326] Integration testing verifies process workflow testing

[0327] Test scenarios covering the entire memory read process;

[0328] Test environment construction and execution

[0329] Build a simulation environment and perform integration testing;

[0330] Record response time and success rate at each stage;

[0331] Calculation verification

[0332] The expected average response time of the entire process is preset as T_avg, and the standard deviation is σ;

[0333] The average response time to actually complete the entire process is T_actual_avg;

[0334] Calculate the difference between the actual and expected average response time: ΔT_avg = T_actual_avg - T_avg;

[0335] Verification: If |ΔT_avg|≤σ, the process response time meets expectations; otherwise, analyze the problems in the specific stages;

[0336] Stress Testing Validation Process

[0337] Simulate high-concurrency access scenarios, including different read-write ratios and access modes;

[0338] Performance Monitoring and Data Collection

[0339] During the test, collect system response time, throughput, error rate and resource utilization data; calculate and verify

[0340] The expected system throughput is assumed to be X times / second, with a standard deviation of σ;

[0341] The average throughput in the actual test is X_actual times / second;

[0342] Calculate the throughput difference: ΔX = X_actual - X;

[0343] Verification: If |ΔX|≤σ, the system throughput meets expectations; otherwise, the throughput bottleneck is identified;

[0344] Perform a similar analysis on the response time, calculate the average response time T_rsp and standard deviation σ_rsp of operations per second, and verify whether it meets expectations;

[0345] Through the computational verification process, the S6 step can more accurately evaluate system performance, identify potential problems, and provide data support for system optimization.

[0346] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

[0347] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and rules of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for directly reading electric power remote memory, characterized in that: S1. Data structure optimization and memory read preparation, optimize data structure using jump table or red-black tree; S2. Monitor network conditions, including latency, bandwidth, and packet loss rate, evaluate the impact on memory read performance, and dynamically adjust memory read strategies based on network conditions, including adjusting prefetch window size or priority. S3, redundant link configuration and memory reading, implement link failure detection and automatic switching mechanism during memory reading, and test the recovery capability of redundant links when memory reading fails; S4, concurrency control mechanism optimization and memory read security, use fine-grained lock concurrency control to prevent data competition caused by concurrent access; S5. Encrypt the memory read operation, and control access so that only authorized users can perform the memory read operation. S6. Perform unit testing of memory reads to verify the accuracy and efficiency of read operations. Perform integration testing of the entire system workflow, including memory reads. Perform stress testing to evaluate the system's performance bottlenecks under high-concurrency memory reads and adjust the memory read strategy based on the test results.

2. The method for directly reading a power remote memory according to claim 1, characterized in that: In the step S1, a skip list or a red-black tree is used to achieve a fast response to a read request, and a data structure is selected, the skip list: determining the index level: the preset data volume is n, and the index level k is estimated by log2(n); the size of the data block stored in each index level: the index interval of the i-th level is 2^(ki), that is, the interval of the 0th level is 1, the interval of the 1st level is 2, and so on; the skip list node structure includes data values ​​and a pointer array pointing to the next level node; Red-Black Tree: Node structure: contains the color red or black, key value, pointers to left and right child nodes, and parent node pointer; Interface methods: read(address): reads data according to the address, the time complexity is O(log n); prefetch(address): prefetch data to cache, the time complexity is O(log n); getResponse(): Get the response, the time complexity is O(1); Protocol content: The request and response formats are encapsulated according to the TCP / IP protocol stack; Initialization: Initialize the jump table or red-black tree, as well as the cache and prefetch queue; Processing read request: Check cache: time complexity is O(1); If the cache misses, use a skip table or red-black tree to find the data: the time complexity is O(log n); Adjust the cache size: adjust according to the hit rate. The preset cache size is m, the hit rate is p, and the expected cache size is m'=m*p.

3. The method for directly reading a power remote memory according to claim 1, characterized in that: In the step S2, the network status is monitored, and the memory read strategy and pre-fetch window size are adjusted dynamically according to the network status: The current pre-fetch window size is preset to W and adjusted according to the network conditions: If the bandwidth is high > 100Mbps and the latency is low < 10ms, increase the prefetch window: W = W*1.5; If the network condition is not good, reduce the prefetch window: W = W / 2; Adjust prefetch priority: Adjust the priority of prefetching data according to network conditions: When the network condition is good, prefetching non-urgent data is prioritized; When the network condition is poor, priority is given to pre-fetching critical data.

4. The method for directly reading electric power remote memory according to claim 1, characterized in that: The redundant link configuration in step S3: if the critical path N=4, 4 redundant links are configured; Link monitoring: The preset monitoring tool shows that the current latency of the main link 1 is 45ms and the packet loss rate is 2%; Fault detection: If the delay exceeds 50ms or the packet loss rate exceeds 5%, fault detection is triggered; Automatic switching: If the main link 1 fails, it will switch to the redundant link 1 within 0.5 seconds; Test the switching mechanism: Simulate the failure of the main link 1, record the switching time T = 0.5 seconds, and the data loss D = 0 bytes; Evaluate the recovery capability: If T = 0.5 seconds and D = 0, the recovery capability is considered to meet the requirements.

5. The method for directly reading electric power remote memory according to claim 1, characterized in that: The implementation of the lock in step S4: Use read-write locks or optimistic locks at a fine-grained level and write the lock code: Acquire a read lock before the read operation and release the read lock after the read operation is completed; Acquire the write lock before the write operation and release the write lock after the write operation is completed; Performance evaluation: success rate = number of successful operations / total number of operations; Average operation time = total time / number of successful operations.

6. The method for directly reading electric power remote memory according to claim 1, characterized in that: The encryption strategy of step S5 is formulated to determine whether the encryption algorithm of the memory read operation uses AES or RSA; an encryption strategy is formulated, including key management, encryption mode CBC, GCM.

7. The method for directly reading electric power remote memory according to claim 1, characterized in that: The step S6 presets the expected system throughput as X times / second and the standard deviation as σ; The average throughput in the actual test is X_actual times / second; Calculate the throughput difference: ΔX = X_actual - X; Verification: If |ΔX|≤σ, the system throughput meets expectations; otherwise, the throughput bottleneck is identified; Perform a similar analysis on the response time and calculate the average response time T_rsp and standard deviation σ_rsp of operations per second to verify whether it meets expectations.

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