SSD dynamic ECC code rate management method and device, computer equipment and storage medium

Abstract

The invention provides an SSD dynamic ECC code rate management method and device, computer equipment and a storage medium, and the method comprises the following steps: dividing an NAND storage region of an SSD to obtain an SLC region and a non-SLC region; according to the characteristics of the SLC region and the non-SLC region, determining corresponding code rate values, and constructing a code rate management table; when a data write-in request is received, the code rate management table is utilized to encode write-in data to obtain encoded data, and the encoded data is written into a corresponding area; and when a data read-out request is received, decoding read-out data by using the code rate management table to obtain decoded data, and returning the decoded data to a requester. The technical problems that the effective bandwidth in the SLC area is low and the performance peak value of the whole disk cannot be achieved due to the fact that a fixed ECC code rate is adopted in a traditional SSD are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state drive read design, and more specifically to an SSD dynamic ECC code rate management method, device, computer equipment and storage medium. Background Art

[0002] Solid-state drives (SSDs) are high-performance storage devices that have been widely used in various fields. Their storage medium, NAND flash memory, is prone to bit flipping, so error correction codes (ECC) are required for coding protection.

[0003] In traditional SSDs, the ECC code rate is usually fixed throughout the life cycle. As NAND technology develops, the demand for ECC protection continues to increase, resulting in an increase in the spare space used to store ECC Parity data and a decrease in the code rate. For example, for every 4KB of data, 500 bytes or more of spare space may be required to store ECC Parity data. A lower code rate will reduce the effective bandwidth when the NAND bus transmits data.

[0004] In actual applications, the interface rate of SSDs is constantly increasing, and the performance requirements are getting higher and higher. However, the existing fixed bit rate management method limits the further improvement of SSD performance. Especially in the SLC area with higher reliability, due to the use of the same fixed low bit rate as other areas, the effective bandwidth is low, and the performance advantages of the SLC area cannot be fully utilized, which in turn affects the achievement of the peak performance of the entire disk. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects of the prior art and provide an SSD dynamic ECC code rate management method, device, computer equipment and storage medium, which aims to solve the technical problem that the traditional SSD uses a fixed ECC code rate, resulting in low effective bandwidth in the SLC area and the inability to achieve the peak performance of the entire disk.

[0006] To achieve the above object, the present invention adopts the following technical solutions:

[0007] A SSD dynamic ECC code rate management method includes the following steps:

[0008] Divide the NAND storage area of ​​the SSD into an SLC area and a non-SLC area;

[0009] According to the characteristics of the SLC area and the non-SLC area, the corresponding bit rate values ​​are determined and a bit rate management table is constructed;

[0010] When a data write request is received, the write data is encoded using the bit rate management table to obtain encoded data, and the encoded data is written into the corresponding area;

[0011] When a data read request is received, the read data is decoded using the code rate management table to obtain decoded data, and the decoded data is returned to the requesting party.

[0012] In one embodiment, the step of determining the corresponding bit rate values ​​according to the characteristics of the SLC area and the non-SLC area and constructing the bit rate management table includes:

[0013] Design a bit rate management table with super block number as index;

[0014] Initializing the bit rate management table, setting the bit rate value corresponding to the SLC area to the first ECC bit rate, and setting the bit rate value corresponding to the non-SLC area to the second ECC bit rate;

[0015] Storing the initialized bit rate management table in a storage area of ​​NAND;

[0016] The SSD is powered on and the bit rate management table is loaded from the storage area to the memory.

[0017] In one embodiment, when a data write request is received, the step of encoding the write data using the bit rate management table to obtain encoded data, and writing the encoded data into the corresponding area includes:

[0018] When receiving a data write request, parsing the target area corresponding to the write data, and determining the super block number to which the target area belongs;

[0019] According to the super block number, query the corresponding ECC code rate in the code rate management table in the memory;

[0020] Encoding the written data according to the ECC code rate to obtain encoded data;

[0021] The encoded data is transmitted to the storage area through a data transmission channel and written into the corresponding super block.

[0022] In one embodiment, when a data read request is received, the steps of decoding the read data using the bit rate management table to obtain decoded data, and returning the decoded data to the requesting party include:

[0023] When a data read request is received, parsing the target area corresponding to the read data, and determining the super block number to which the target area belongs;

[0024] According to the super block number, query the corresponding ECC code rate in the code rate management table in the memory;

[0025] Performing a decoding operation on the read data according to the ECC code rate to obtain decoded data;

[0026] The decoded data is returned to the data requester.

[0027] In one embodiment, the step before returning the decoded data to the data requester further includes:

[0028] Determining whether the decoded data comes from the SLC area;

[0029] If so, monitoring whether the number of error bits in the super block data of the SLC area is higher than a threshold;

[0030] If not, the decoded data is returned to the data requester.

[0031] In one embodiment, the step of monitoring whether the number of error bits in the super block data of the SLC area is higher than a threshold comprises:

[0032] Reading data of the super block of the SLC area;

[0033] Determine, by a judgment rule, whether the number of error bits in the super block of the SLC area is close to an upper limit of the error correction capability corresponding to the first ECC code rate;

[0034] If so, determining that the super block data is at risk;

[0035] If not, the decoded data is returned to the data requester.

[0036] In one embodiment, the steps after determining that the super block data is at risk include:

[0037] Switching the ECC code rate of the super block data from the first ECC code rate to the second ECC code rate;

[0038] Modify the bit rate information corresponding to the super block in the bit rate management table, and record the modified bit rate information as the second ECC bit rate;

[0039] The decoded data is returned to the data requester.

[0040] A SSD dynamic ECC code rate management device, the device comprising:

[0041] A region division module, used for dividing the NAND storage area of ​​the SSD into an SLC area and a non-SLC area;

[0042] A code rate management table construction module, used to construct a code rate management table, wherein the code rate management table uses the super block number as an index;

[0043] A code rate management table storage and loading module, used for storing the initialized code rate management table in a NAND storage area and loading the code rate management table from the storage area to a memory;

[0044] A data writing management module, used for encoding the writing data according to the bit rate management table and writing the writing data into the corresponding area;

[0045] The data readout management module is used to decode the readout data according to the code rate management table and return the decoded data to the data requester.

[0046] A computer device comprises a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the above method when executing the computer program.

[0047] A computer-readable storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the above method can be implemented.

[0048] The beneficial effects of the present invention compared with the prior art are as follows: the present invention divides the NAND storage area of ​​the SSD, constructs and manages the code rate management table, realizes the encoding writing and reading of the ECC code rate dynamically adjusted according to the characteristics of different areas, ensures the performance of the SLC area and the reliability of the non-SLC area, and can switch the code rate in time when there is a risk of data in the SLC area, thereby improving the overall performance, reliability and data security of the SSD.

[0049] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic diagram of a SSD dynamic ECC code rate management method provided by an embodiment of the present invention Figure 1 ;

[0051] Figure 2 A schematic diagram of a SSD dynamic ECC code rate management method provided by an embodiment of the present invention Figure 2 ;

[0052] Figure 3 A schematic diagram of a SSD dynamic ECC code rate management method provided by an embodiment of the present invention Figure 3 ;

[0053] Figure 4A schematic diagram of a SSD dynamic ECC code rate management method provided by an embodiment of the present invention Figure 4 ;

[0054] Figure 5 A schematic diagram of a SSD dynamic ECC code rate management method provided by an embodiment of the present invention Figure 5 ;

[0055] Figure 6 A schematic diagram of a SSD dynamic ECC code rate management method provided by an embodiment of the present invention Figure 6 ;

[0056] Figure 7 A schematic diagram of a SSD dynamic ECC code rate management method provided by an embodiment of the present invention Figure 7 ;

[0057] Figure 8 A schematic block diagram of an SSD dynamic ECC code rate management device provided by an embodiment of the present invention;

[0058] Fig. 9 A schematic block diagram of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0060] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0061] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0062] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0063] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0064] See also Figure 1 As shown, an embodiment of the present invention discloses a method for dynamic ECC code rate management of SSD, comprising the following steps:

[0065] S110, dividing the NAND storage area of ​​the SSD into an SLC area and a non-SLC area;

[0066] Specifically, the NAND storage area of ​​the SSD is divided into SLC (Single-Level Cell) area and non-SLC area according to the different ways in which the storage unit stores data. Common non-SLC areas include TLC (Triple-Level Cell), QLC (Quad-Level Cell), etc. It can be understood that each storage unit in the SLC area only stores 1 bit of data, with a higher read and write speed and a lower error probability, so the read and write performance and reliability are relatively high. Each storage unit in the non-SLC area stores multiple bits of data, such as TLC stores 3 bits and QLC stores 4 bits, with higher storage density, but relatively slower read and write performance and a relatively higher error probability. Through regional division, differentiated management and processing can be performed based on the characteristics of different areas, providing a basis for subsequent bit rate allocation and data processing.

[0067] S120, determining the corresponding bit rate values ​​according to the characteristics of the SLC area and the non-SLC area, and constructing a bit rate management table;

[0068] Specifically, based on the high performance and relatively low error probability characteristics of the SLC area, a higher code rate value (such as the first ECC code rate) is determined for it to ensure that higher bandwidth and performance can be achieved when writing and reading data in this area. In view of the high storage density but relatively low reliability of the non-SLC area, a lower code rate value (such as the second ECC code rate) is determined for it to ensure data reliability through stronger error correction capabilities. A code rate management table is constructed based on the determined code rate value, and the table entry records the storage area type (SLC or non-SLC) and the corresponding code rate value corresponding to each super block. By determining the code rate values ​​of different areas and reasonably constructing the code rate management table, the appropriate code rate can be selected for encoding and decoding according to the regional characteristics during the data reading and writing process, achieving a balanced optimization of performance and reliability.

[0069] S130, when receiving a data write request, encoding the write data using the bit rate management table to obtain encoded data, and writing the encoded data into a corresponding area;

[0070] Specifically, when the SSD receives a data write request, it encodes and writes the data according to the bit rate of different areas, ensuring high-performance data writing in the SLC area and enhancing data reliability through low-bit rate encoding in the non-SLC area, ensuring that the data can be accurately stored in the corresponding area.

[0071] S140. When a data read request is received, the read data is decoded using the code rate management table to obtain decoded data, and the decoded data is returned to the requesting party.

[0072] Specifically, when the SSD receives a data read request, it can accurately restore the original data by performing decoding operations according to the bit rate at the time of writing, ensuring the integrity and correctness of the data. At the same time, decoding according to the bit rate of different areas can also give full play to the high performance advantages of the SLC area and improve the efficiency of data reading while ensuring data reliability.

[0073] See also Figure 2 As shown, in one embodiment, the step of determining the corresponding bit rate values ​​according to the characteristics of the SLC area and the non-SLC area and constructing the bit rate management table includes:

[0074] S121, design a bit rate management table, using the super block number as an index;

[0075] Specifically, a table dedicated to managing the ECC code rate is designed, namely the code rate management table. The table uses the super block number as the only index, which means that the corresponding code rate information can be quickly and accurately found in the table through the super block number, which is convenient for quickly querying and obtaining the required code rate during data reading and writing, and improving the efficiency of data processing.

[0076] It is understandable that the super block number is a unique number used to identify each super block in the NAND storage area in the SSD. The super block is a logical concept in the SSD storage structure, usually composed of multiple physical blocks, and is used to provide concurrent write performance for newly written data. Each super block has a specific number, through which the relevant information of the super block can be quickly located and managed in related data structures such as the code rate management table, such as the storage area type (SLC or non-SLC), the corresponding ECC code rate, etc., so that during the data reading and writing process, the SSD can accurately obtain and apply the corresponding management strategy according to the super block number, and realize efficient management and data processing of different super blocks.

[0077] S122, initializing the bit rate management table, setting the bit rate value corresponding to the SLC area to a first ECC bit rate, and setting the bit rate value corresponding to the non-SLC area to a second ECC bit rate;

[0078] Specifically, the code rate management table is set when the SSD is shipped or initialized. According to the different characteristics of the SLC area and the non-SLC area, a higher code rate value is set for the SLC area, called the first ECC code rate, to ensure its high performance and low error rate; a lower code rate value is set for the non-SLC area, called the second ECC code rate, to enhance its data reliability. By initializing the code rate management table and pre-setting appropriate code rate values ​​for different areas, the corresponding code rate can be automatically applied according to the regional characteristics during data storage and reading, achieving an optimal balance between performance and reliability.

[0079] S123, storing the initialized bit rate management table in a storage area of ​​NAND;

[0080] Specifically, the initialized bit rate management table is saved in the NAND storage area of ​​the SSD to store data stably and long-term, ensuring that the information in the bit rate management table will not be lost even after the SSD is powered off or restarted, and can be reloaded and used the next time it is powered on, ensuring the continuity and stability of bit rate management.

[0081] S124, the SSD is powered on, and the bit rate management table is loaded from the storage area to the memory.

[0082] Specifically, when the SSD is powered on, the system reads the previously saved rate management table from the NAND storage area and loads the rate management table into the memory so that the rate information can be quickly accessed and used in subsequent data read and write operations, reducing the time overhead of frequently accessing the NAND to read the rate information during data processing, improving the speed and efficiency of data reading and writing, while also ensuring the real-time and accuracy of rate management.

[0083] See also Figure 3 As shown, in one embodiment, when a data write request is received, the step of encoding the write data using the bit rate management table to obtain encoded data, and writing the encoded data into the corresponding area includes:

[0084] S131, when receiving a data write request, parsing the target area corresponding to the write data, and determining the super block number to which the target area belongs;

[0085] Specifically, when the SSD receives a data write request from a host or other device, the system first needs to determine the specific location of the SSD to which the data is to be written, that is, the target area. By parsing the relevant information of the write data, such as address information, etc., the corresponding target area is determined. According to the storage structure and management method of the SSD, the super block number to which the target area belongs is further determined. It can be understood that accurately parsing the target area and determining the super block number is the basis for subsequent correct encoding and writing operations, ensuring that the data can be written to the specified super block and realizing orderly storage of data.

[0086] S132, querying the corresponding ECC code rate in the code rate management table in the memory according to the super block number;

[0087] Specifically, when the SSD is powered on, the code rate management table has been loaded into the memory. At this time, according to the super block number determined above, the corresponding ECC code rate can be quickly found in the code rate management table in the memory, so that the ECC code rate corresponding to the target super block can be obtained in time, avoiding the time delay caused by frequent access to the NAND storage area and improving the efficiency of data writing.

[0088] S133, encoding the write data according to the ECC code rate to obtain encoded data;

[0089] Specifically, the queried ECC code rate is used to encode the data to be written. The encoding process will add appropriate check information to the original data according to the selected ECC code rate rule to generate encoded data. For example, if it is high-rate encoding, relatively less check information may be added to ensure higher bandwidth and performance; if it is low-rate encoding, more check information will be added to enhance the error correction capability and reliability of the data. Encoding is performed according to the characteristics of different areas and the corresponding code rates, so that data can be written with higher performance in the SLC area and with stronger reliability in the non-SLC area, thereby optimizing data storage.

[0090] S134, transmitting the encoded data to the storage area through a data transmission channel, and writing the encoded data into a corresponding super block.

[0091] Specifically, the encoded data after encoding processing is transmitted to the NAND storage area through the data transmission channel inside the SSD, such as the system bus 501. According to the super block number determined previously, the encoded data is accurately written into the corresponding super block, thereby completing the final writing operation of the data, ensuring the integrity and recoverability of the data, and also achieving the purpose of dynamic management and storage according to the code rate of different areas.

[0092] See also Figure 4As shown, in one embodiment, when a data read request is received, the read data is decoded using the bit rate management table to obtain decoded data, and the steps of returning the decoded data to the requesting party include:

[0093] S141, when receiving a data read request, parsing a target area corresponding to the read data, and determining a super block number to which the target area belongs;

[0094] Specifically, when the SSD receives a data read request, the system will analyze the relevant information in the request to determine the target area where the data to be read is located. By analyzing the target area, the super block number to which it belongs is further clarified, which provides a key basis for subsequent accurate acquisition of the corresponding bit rate and data reading operations, ensuring that data can be read from the correct super block.

[0095] S142, querying the corresponding ECC code rate in the code rate management table in the memory according to the super block number;

[0096] Specifically, since the bit rate management table has been loaded into the memory when the SSD is powered on, the corresponding ECC bit rate is quickly searched in the bit rate management table in the memory according to the super block number determined above, thereby avoiding the time consumption of reading the bit rate information from the storage medium and improving the efficiency of data reading.

[0097] S143, performing a decoding operation on the read data according to the ECC code rate to obtain decoded data;

[0098] Specifically, the data read from the NAND is decoded according to the decoding rules corresponding to the queried ECC code rate. The decoding process uses the check information added during encoding to correct possible data errors and restore the original correct data, that is, the decoded data, thereby ensuring that the read data is accurately restored and the integrity and reliability of the data are guaranteed. At the same time, decoding according to the code rates of different regions can also better adapt to the data characteristics of different regions.

[0099] S144. Return the decoded data to the data requester.

[0100] Specifically, the correct data obtained after decoding is returned to the device or program that originally initiated the data reading request through the corresponding interface or channel, thus completing the entire data reading process, allowing the requesting party to obtain the required accurate data and achieve effective data reading and transmission.

[0101] See also Figure 5 As shown, in one embodiment, the step before returning the decoded data to the data requester also includes:

[0102] S211, determining whether the decoded data comes from the SLC area;

[0103] Specifically, before returning the decoded data to the data requester, the system first needs to determine whether the data comes from the SLC area by querying the relevant storage area identifier or other information related to the data source, thereby providing a basis for subsequent different processing strategies based on the data source, and being able to perform special management and monitoring based on the characteristics of the SLC area.

[0104] S212: If yes, monitor whether the number of error bits in the super block data of the SLC area is higher than a threshold;

[0105] Specifically, if it is determined that the decoded data comes from the SLC area, the system will further monitor the number of error bits in the super block data of the SLC area through a specific algorithm or mechanism, and compare it with a preset threshold to promptly discover possible risks in the SLC area data so as to take appropriate measures to ensure data reliability.

[0106] S213: If not, return the decoded data to the data requester.

[0107] Specifically, if the decoded data does not come from the SLC area, or comes from the SLC area but the number of error bits is not higher than the threshold, it means that the data is in a normal state, and the decoded data is directly returned to the data requester, thereby ensuring that the data can be returned to the requester quickly and efficiently when the data is normal, without affecting the normal reading and use of the data.

[0108] See also Figure 6 As shown, in one embodiment, the step of monitoring whether the number of error bits in the super block data of the SLC area is higher than a threshold comprises:

[0109] S2121, reading data of the super block in the SLC area;

[0110] S2122, judging by a judgment rule whether the number of error bits in the super block of the SLC area is close to an upper limit of the error correction capability corresponding to the first ECC code rate;

[0111] Specifically, the system reads data from the super block in the SLC area and uses a specific judgment rule to analyze the number of error bits therein. The judgment rule is set based on the upper limit of the error correction capability corresponding to the first ECC code rate to determine whether the number of error bits is close to the upper limit, thereby accurately evaluating the error situation of the super block data in the SLC area and providing an accurate basis for subsequent risk determination.

[0112] S2123: If yes, determine that the super block data has a risk;

[0113] Specifically, when it is determined that the number of error bits is close to the upper limit of the error correction capability of the first ECC code rate, it indicates that the data of the current super block has a high risk and the data may not be correctly restored. Timely discovery of potential data risks provides trigger conditions for taking corresponding protection measures.

[0114] S2124: If not, return the decoded data to the data requester.

[0115] Specifically, if the number of error bits is not close to the upper limit of the error correction capability of the first ECC code rate, that is, the data is in a relatively safe state, then the decoded data is directly returned to the data requester. In the case of low data risk, it is ensured that the data can be returned to the requester quickly and normally without affecting the data reading and use process.

[0116] See also Figure 7 As shown, in one embodiment, the steps after determining that the super block data has a risk include:

[0117] S311, switching the ECC code rate of the super block data from the first ECC code rate to the second ECC code rate;

[0118] Specifically, when it is determined that the super block data has a risk, in order to enhance the reliability of the super block data, the ECC code rate used is switched from the original first ECC code rate (high code rate) to the second ECC code rate (low code rate). It can be understood that a low code rate means more verification information and can provide a stronger error correction capability. By switching the code rate, the probability of further data errors can be effectively reduced, the reliability of the data can be improved, and the security of the data can be ensured.

[0119] S312, modifying the bit rate information corresponding to the super block in the bit rate management table, and recording the modified bit rate information as the second ECC bit rate;

[0120] Specifically, the code rate information corresponding to the super block in the code rate management table is updated, and the originally recorded first ECC code rate is modified to the second ECC code rate to reflect the code rate currently actually used by the super block, thereby ensuring the accuracy and consistency of the code rate management table, so that subsequent data read and write operations can be correctly processed according to the latest code rate information.

[0121] S313: Return the decoded data to the data requesting party.

[0122] Specifically, after completing the bit rate switching and updating the bit rate management table, the decoded data is returned to the data requester to ensure that the data requester can obtain the required data in a timely manner. At the same time, in the process of returning data, the data risk processing and bit rate management update are completed, ensuring the integrity and reliability of the entire data processing process.

[0123] Compared with the prior art, the SSD dynamic ECC code rate management method provided by this solution has the following advantages:

[0124] Beneficial effects:

[0125] (1) High code rate writing is used in the SLC area to ensure the effective bandwidth and peak performance, giving full play to the high performance advantages of the SLC area, enabling the SSD to respond more quickly when processing large amounts of data, thereby improving the operating efficiency of the overall system.

[0126] (2) The non-SLC area uses low bit rate writing to ensure data reliability through stronger error correction capabilities and reduce the risk of data errors. The data errors in the SLC area are monitored. When the number of error bits approaches the upper limit of the high bit rate error correction capability, it switches to low bit rate writing in time, further ensuring data reliability and preventing possible data loss or damage in advance.

[0127] (3) The ECC code rate is dynamically adjusted according to the characteristics of different areas, adapting to the needs of different storage areas within the SSD, improving the versatility and practicality of the SSD, and enabling it to perform well in various application scenarios.

[0128] (4) By reasonably allocating the bit rate, the effective bandwidth waste caused by using a fixed low bit rate throughout the entire SSD life cycle is avoided. While ensuring data reliability, resource utilization is optimized and the cost-effectiveness of the SSD is improved.

[0129] Figure 8 is a schematic block diagram of an SSD dynamic ECC code rate management device provided by an embodiment of the present application. Figure 8 As shown, corresponding to the above SSD dynamic ECC code rate management method, the present application also provides an SSD dynamic ECC code rate management device 400. The SSD dynamic ECC code rate management device 400 includes a unit for executing the above SSD dynamic ECC code rate management method, and the device can be configured in a desktop computer, tablet computer, laptop computer, etc.

[0130] Specifically, see Figure 8 As shown, the SSD dynamic ECC code rate management device 400 includes:

[0131] The area division module 410 is used to divide the NAND storage area of ​​the SSD into SLC areas and non-SLC areas, laying the foundation for subsequent differentiated bit rate management according to the characteristics of different areas, so that the device can optimize the processing according to the characteristics of different areas.

[0132] The code rate management table construction module 420 is used to construct a code rate management table. The code rate management table uses the super block number as an index, provides an effective code rate management mechanism, can quickly and accurately allocate and obtain corresponding code rates for different super blocks, and realize flexible control of data reading and writing.

[0133] The code rate management table storage and loading module 430 is used to store the initialized code rate management table in the NAND storage area and load the code rate management table from the storage area to the memory, ensuring the availability of the code rate management table in different states, being able to restore the code rate information after power failure, and being able to quickly access it during operation, reducing the delay in the data reading and writing process

[0134] The data write management module 440 is used to encode the write data according to the code rate management table and write it into the corresponding area, thereby realizing dynamic encoding and writing according to the characteristics of different areas, optimizing the writing performance of the SLC area while ensuring data reliability, and improving the overall writing efficiency of the SSD.

[0135] The data reading management module 450 is used to decode the read data according to the bit rate management table and return it to the data requester, ensuring that the read data can be accurately restored. At the same time, decoding is performed according to the bit rates of different regions, thereby improving the efficiency and reliability of data reading and meeting the user's needs for data reading.

[0136] Furthermore, the SSD dynamic ECC code rate management device 400 in this embodiment should also include a high code rate data risk management module 460. When a super block is read, if it is written using a high code rate and the number of error bits in its data is close to a threshold (user-defined, generally selected to be less than the upper limit of the error correction capability corresponding to the high code rate), when the super block is subsequently erased and the data is rewritten, it is switched to low code rate writing to ensure reliability, and the corresponding table entry information of the super block code rate table is also modified (the corresponding code rate is changed from high code rate to low code rate). By monitoring and managing the risks of high code rate data, potential data risks can be discovered in time, and corresponding measures can be taken to prevent them. When the data risk is high, the code rate is reduced to enhance the error correction capability, ensure the reliability of the data, and avoid data loss or damage caused by too many data errors. At the same time, the update of the super block code rate table also ensures that subsequent data processing can be carried out according to the new code rate, thereby improving the stability and reliability of the entire SSD storage system.

[0137] It should be noted that technicians in the relevant field can clearly understand that the specific implementation process of the above-mentioned SSD dynamic ECC code rate management device and each unit can refer to the corresponding description in the aforementioned method embodiment, and for the convenience and brevity of description, it will not be repeated here.

[0138] The above-mentioned SSD dynamic ECC code rate management device 400 can be implemented in the form of a computer program, and the computer program can be run on the computer device as shown in the figure.

[0139] See also Fig. 9 , Fig. 9 5 is a schematic block diagram of a computer device provided in an embodiment of the present application. The computer device 500 may be a terminal or a server, wherein the terminal may be an electronic device with communication functions such as a smart phone, a tablet computer, a laptop computer, a desktop computer, a personal digital assistant, and a wearable device. The server may be an independent server or a server cluster composed of multiple servers.

[0140] See also Fig. 9 As shown, the computer device 500 includes a processor 520 , a memory, and a network interface 550 connected via a system bus 510 , wherein the memory may include a non-volatile storage medium 530 and an internal memory 540 .

[0141] The non-volatile storage medium 530 can store an operating system 531 and a computer program 532. The computer program 532 includes program instructions, and when the program instructions are executed, the processor 520 can execute a SSD dynamic ECC code rate management method.

[0142] The processor 520 is used to provide computing and control capabilities to support the operation of the entire computer device 500 .

[0143] The internal memory 540 provides an environment for the operation of the computer program 532 in the non-volatile storage medium 530. When the computer program 532 is executed by the processor 520, the processor 520 can execute a SSD dynamic ECC code rate management method.

[0144] The network interface 550 is used to communicate with other devices over the network. Fig. 9 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present application, and does not constitute a limitation on the computer device 500 to which the solution of the present application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0145] It should be understood that in the embodiment of the present application, the processor 520 may be a central processing unit (CPU), and the processor 320 may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. Among them, the general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0146] It can be understood by those skilled in the art that all or part of the processes in the method for implementing the above embodiment can be completed by instructing the relevant hardware through a computer program. The computer program includes program instructions, and the computer program can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiment of the above method.

[0147] Therefore, the present application also provides a storage medium. The storage medium may be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions. When the program instructions are executed by a processor, the processor executes the following steps:

[0148] S110, dividing the NAND storage area of ​​the SSD into an SLC area and a non-SLC area;

[0149] S120, determining the corresponding bit rate values ​​according to the characteristics of the SLC area and the non-SLC area, and constructing a bit rate management table;

[0150] S130, when receiving a data write request, encoding the write data using the bit rate management table to obtain encoded data, and writing the encoded data into a corresponding area;

[0151] S140. When a data read request is received, the read data is decoded using the code rate management table to obtain decoded data, and the decoded data is returned to the requesting party.

[0152] The storage medium may be any computer-readable storage medium that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a magnetic disk, or an optical disk.

[0153] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0154] The non-Company software tools or components appearing in the embodiments of this application are merely examples and do not represent actual use.

[0155] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of each unit is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0156] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs. The units in the device of the embodiment of the present application can be combined, divided and deleted according to actual needs. In addition, the functional units in the various embodiments of the present application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0157] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for a computer device (which can be a personal computer, terminal, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present application.

[0158] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A SSD dynamic ECC code rate management method, characterized in that: The following steps are involved: Divide the NAND storage area of ​​the SSD into an SLC area and a non-SLC area; According to the characteristics of the SLC area and the non-SLC area, the corresponding bit rate values ​​are determined and a bit rate management table is constructed; When a data write request is received, the write data is encoded using the bit rate management table to obtain encoded data, and the encoded data is written into the corresponding area; When a data read request is received, the read data is decoded using the code rate management table to obtain decoded data, and the decoded data is returned to the requesting party.

2. The SSD dynamic ECC code rate management method according to claim 1, characterized in that: The step of determining the corresponding bit rate values ​​according to the characteristics of the SLC area and the non-SLC area and constructing the bit rate management table comprises: Design a bit rate management table with super block number as index; Initializing the bit rate management table, setting the bit rate value corresponding to the SLC area to the first ECC bit rate, and setting the bit rate value corresponding to the non-SLC area to the second ECC bit rate; Storing the initialized bit rate management table in a storage area of ​​NAND; The SSD is powered on and the bit rate management table is loaded from the storage area to the memory.

3. The SSD dynamic ECC code rate management method according to claim 2, characterized in that: When a data write request is received, the step of encoding the write data using the bit rate management table to obtain encoded data, and writing the encoded data into the corresponding area comprises: When receiving a data write request, parsing the target area corresponding to the write data, and determining the super block number to which the target area belongs; According to the super block number, query the corresponding ECC code rate in the code rate management table in the memory; Encoding the written data according to the ECC code rate to obtain encoded data; The encoded data is transmitted to the storage area through a data transmission channel and written into the corresponding super block.

4. The SSD dynamic ECC code rate management method according to claim 3, characterized in that: When a data read request is received, the steps of decoding the read data using the code rate management table to obtain decoded data, and returning the decoded data to the requesting party include: When a data read request is received, parsing the target area corresponding to the read data, and determining the super block number to which the target area belongs; According to the super block number, query the corresponding ECC code rate in the code rate management table in the memory; Performing a decoding operation on the read data according to the ECC code rate to obtain decoded data; The decoded data is returned to the data requester.

5. The SSD dynamic ECC code rate management method according to any one of claim 4, characterized in that: The step before returning the decoded data to the data requester also includes: Determining whether the decoded data comes from the SLC area; If so, monitoring whether the number of error bits in the super block data of the SLC area is higher than a threshold; If not, the decoded data is returned to the data requester.

6. The SSD dynamic ECC code rate management method according to claim 5, characterized in that: The step of monitoring whether the number of error bits in the super block data of the SLC area is higher than a threshold comprises: Reading data of the super block of the SLC area; Determine, by a judgment rule, whether the number of error bits in the super block of the SLC area is close to an upper limit of the error correction capability corresponding to the first ECC code rate; If so, determining that the super block data is at risk; If not, the decoded data is returned to the data requester.

7. The SSD dynamic ECC code rate management method according to claim 6, characterized in that: The steps after determining that the super block data has a risk include: Switching the ECC code rate of the super block data from the first ECC code rate to the second ECC code rate; Modify the bit rate information corresponding to the super block in the bit rate management table, and record the modified bit rate information as the second ECC bit rate; The decoded data is returned to the data requester.

8. A SSD dynamic ECC code rate management device, characterized in that: The device comprises: A region division module, used for dividing the NAND storage area of ​​the SSD into an SLC area and a non-SLC area; A code rate management table construction module, used to construct a code rate management table, wherein the code rate management table uses the super block number as an index; A code rate management table storage and loading module, used for storing the initialized code rate management table in a NAND storage area and loading the code rate management table from the storage area to a memory; A data writing management module, used for encoding the writing data according to the bit rate management table and writing the writing data into the corresponding area; The data readout management module is used to decode the readout data according to the code rate management table and return the decoded data to the data requester.

9. A computer device, characterized in that: The computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, wherein the computer program includes program instructions, and when the program instructions are executed by a processor, the method according to any one of claims 1 to 7 can be implemented.

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