Test apparatus and method for field programmable gate array systems

Abstract

The present application relates to field programmable gate array system technical field, disclose a kind of field programmable gate array system testing device and method, testing device includes built-in self-test state machine and multiple built-in self-test circuits, built-in self-test circuit is configured on corresponding function module;Built-in self-test state machine is used to receive bit stream data;Built-in self-test state machine is also used to determine first test route based on bit stream data, for controlling built-in self-test circuit generates test excitation signal;Built-in self-test state machine is also used to control built-in self-test circuit and corresponding test excitation signal is sent to the function module to be measured;Built-in self-test state machine is also used to receive at least one test result output by the function module to be measured, for determining whether corresponding function module to be measured is normal based on test result.The present application can only be tested to the function module required by the specific application needed to be completed by field programmable gate array system, to reduce test time.

Description

Technical Field

[0001] This invention relates to the field of field-programmable gate array (FPGA) systems, and more specifically to a testing device and method for FPGA systems. Background Technology

[0002] A Field Programmable Gate Array (FPGA) is a programmable integrated circuit chip that allows for flexible modification of its internal logic functions and circuit connections through programming to adapt to different application requirements. FPGAs are widely used in communications, automotive electronics, industrial control, aerospace, and data centers. During the production and configuration of FPGA systems, testing is necessary to ensure the reliability and stability of the functional modules within the FPGA system.

[0003] Currently, the testing method for FPGA systems generally involves configuring the FPGA system and generating bitstream data using hardware description language code. This bitstream data is then transmitted to the FPGA system, and automated test equipment programs and tests all components according to the bitstream data transmission sequence to determine if each component is functioning correctly. If the FPGA system is large, this process can lead to long testing times and high costs for all its logic resources. Summary of the Invention

[0004] In view of this, the present invention provides a test apparatus and method for field programmable gate array (FPGA) systems to solve the problems of long test time and high test cost of FPGA systems.

[0005] In a first aspect, the present invention provides a test apparatus for a field-programmable gate array (FPGA) system. The test apparatus includes a built-in self-test (WPT) state machine and multiple built-in self-test circuits. The FPGA system includes multiple functional modules, with each functional module corresponding to one of the multiple built-in self-test circuits. The built-in self-test circuits are configured on the corresponding functional modules. The WPT state machine is used to receive bitstream data, which indicates at least one functional module required by a target application and the connection relationship between the at least one functional module. The WPT state machine is also used to determine a first test path based on the bitstream data and to control the built-in self-test circuits to generate test excitation signals. The first test path indicates the test sequence of at least one functional module under test, which is a functional module required by the target application. The WPT state machine is also used to control the built-in self-test circuits to send test excitation signals to the corresponding functional module under test based on the first test path. The WPT state machine is also used to receive test results from at least one functional module under test collected by the built-in self-test circuits and to determine whether the corresponding functional module under test is functioning correctly based on the test results.

[0006] The FPGA system testing apparatus provided in this embodiment, through the cooperation of a built-in self-test state machine and a built-in self-test circuit, can test only the functional modules required for specific applications of the FPGA system, thereby reducing testing time and saving testing costs. Furthermore, the cooperation between the built-in self-test state machine and the built-in self-test circuit also allows for dynamic adjustment of the test mode, enabling testing of the corresponding functional modules of the FPGA system under different application scenarios to ensure their proper functioning, thus improving testing flexibility.

[0007] In one optional implementation, the built-in self-test state machine is also used to re-determine the second test route based on bitstream data when the functional module under test is abnormal, so as to update the first test route. The second test route is used to represent the test order of the normal functional module under test and the first functional module, and the first functional module is a functional module of the same type as the abnormal functional module under test.

[0008] In this embodiment, when the functional module under test is abnormal, the built-in self-test state machine can reselect the test route to skip the abnormal functional module and replace the faulty functional module with a functional module with the same function (the first functional module), thereby improving the yield of the FPGA system.

[0009] In one alternative implementation, the functional module includes a wiring switch box, which has a built-in self-test state machine that adjusts the first test route to the second test route via the wiring switch box.

[0010] In one alternative implementation, the test excitation signal is used to trigger the corresponding functional module under test to perform fixed-point multiplication processing.

[0011] In one optional implementation, a built-in self-test state machine is used to determine that the corresponding functional module under test is normal if the test result is the same as the preset result.

[0012] In one alternative implementation, the built-in self-test state machine is also used to determine the clock signal generated by the internal oscillator as a reference clock.

[0013] In this embodiment, the internal oscillator of the FPGA system itself is used as a reference clock and BIST flag, which simplifies the test setup and saves costs.

[0014] In one alternative implementation, the plurality of functional modules include at least one of a digital signal processor, a programmable logic group, and a memory.

[0015] Secondly, the present invention provides a testing method for a field-programmable gate array (FPGA) system. The testing method is applied to a built-in self-test state machine in a testing device according to the first aspect or any corresponding embodiment described above. The testing method includes: receiving bitstream data, the bitstream data indicating at least one functional module required by a target application and the connection relationship of at least one functional module; determining a first test route based on the bitstream data, the first test route indicating the test sequence of at least one functional module under test, the functional module under test being a functional module required by the target application; controlling a built-in self-test circuit to generate test stimulus signals; based on the first test route, controlling the built-in self-test circuit to send test stimulus signals to the corresponding functional module under test; receiving test results collected by the built-in self-test circuit from at least one functional module under test; and determining whether the corresponding functional module under test is functioning correctly based on the test results.

[0016] The FPGA system testing method provided in this embodiment, after receiving bitstream data, determines a first test path based on the bitstream data and controls the built-in self-test circuit to generate test stimulus signals. Then, based on the first test path, it controls the built-in self-test circuit to send test stimulus signals to the corresponding functional module under test. After receiving the test results output by at least one functional module under test collected by the built-in self-test circuit, it determines whether the corresponding functional module under test is normal based on the test results. This method can test only the functional modules required for the specific application that the FPGA system needs to complete, thereby reducing testing time and saving testing costs.

[0017] In an optional implementation, the testing method further includes: when the functional module under test is abnormal, re-determining a second test route based on bitstream data to update the first test route, wherein the second test route is used to represent the test order of the normal functional module under test and the first functional module, and the first functional module is a functional module of the same type as the abnormal functional module under test.

[0018] In one optional implementation, determining whether the corresponding functional module under test is normal based on the test results includes: if the test results are the same as the preset results, determining that the corresponding functional module under test is normal. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments or related technologies of the present invention, the drawings used in the description of the specific embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1This is a schematic diagram of a test apparatus for an FPGA system according to an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of the first test route according to an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of the second test route according to an embodiment of the present invention;

[0023] Figure 4 This is a flowchart illustrating a testing method for an FPGA system according to an embodiment of the present invention;

[0024] Figure 5 This is a flowchart illustrating another testing method for an FPGA system according to an embodiment of the present invention.

[0025] Reference numerals: 100, Field Programmable Gate Array (FPGA); 110, Intellectual Property Core; 120, Block Random Access Memory (BRAM); 130, Programmable Logic Block (PLC); 140, Wired Switch Box; 150, Digital Signal Processor (DSP); 160, Input / Output Module (I / O); 210, Built-in Self-Test State Machine (WST); 220, Built-in Self-Test Circuit. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] After receiving the bitstream data, the automated test equipment for FPGA systems transmits the bitstream data to the FPGA system. The bitstream flows in a preset order, programming and testing all components of the FPGA system. Although this testing method has high coverage, because it tests every compiled bit, it can lead to long testing times and high costs if the FPGA system is large.

[0028] In view of this, the present invention provides a test device for a field-programmable gate array (FPGA) system. By building a self-test state machine, it can test only the functional modules required for specific applications that the FPGA system needs to complete, thereby reducing test time and saving test costs.

[0029] The structure of the test device for the Field Programmable Gate Array (FPGA) system provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0030] like Figure 1As shown, the test apparatus for the FPGA system includes a Build-in Self-Test (BIST) state machine (FSM) 210 and multiple BIST circuits 220. Specifically, the Field Programmable Gate Array (FPGA) system 100 includes multiple functional modules, and each functional module corresponds one-to-one with a multiple BIST circuit 220, with the BIST circuits 220 configured on the corresponding functional modules.

[0031] For example, the functional module can be a digital signal processor (DSP), a configurable logic cell (CLC), a memory (Mem), or a switch box (SWH), etc.

[0032] in, Figure 1 Taking multiple functional modules including an Intellectual Property (IP) core 110, a Block Random-Access Memory (BRAM) 120, a Configurable Logic Block (CLB) 130, a Switch Box (SWH) 140, a Digital Signal Processor (DSP) 150, and an Input / Output (IO) module 160 as an example, but not limited to these.

[0033] Specifically, IP core 110 is a pre-designed, reusable functional module; for example, IP core 110 can be a processor core, a communication protocol core, etc. Block random access memory 120 is a large-capacity storage module that can be used to store data, program code, etc. Programmable logic blocks 130 can be programmed to implement various logic functions, such as combinational logic (AND, OR, NOT, etc.) and sequential logic (flip-flops, counters, etc.). The interconnect switch box 140 can flexibly change the connection relationships between various functional modules according to the configuration information in the bitstream data to achieve different circuit functions. The digital signal processor 150 is used to process data signals, such as filtering and transformation. The input / output module 160 is the interface for data interaction between the FPGA system and external devices; through the I / O module 160, the FPGA system can receive external data and send processed data to external devices.

[0034] It should be understood that the FPGA system 100 can be internally divided into multiple regions, each of which can include multiple functional modules, and independent testing and configuration can be performed within each region. Figure 1This example uses two regions (Region_1 and Region_2), but is not limited to this.

[0035] Specifically, the BIST FSM 210 is used to receive bitstream data, determine a first test path based on the bitstream data, and control the BIST circuit 220 to generate test stimulus signals. The BIST FSM 210 is also used to control the BIST circuit 220 to send test stimulus signals to the function under test (DUT) module based on the first test path, and to control the BIST circuit 220 to collect test results output by at least one DUT module, and receive the test results. The BIST FSM 210 is also used to determine whether the corresponding DUT module is functioning correctly based on the test results.

[0036] The bitstream data is used to indicate at least one functional module required by the target application and the connection relationship of at least one functional module. Specifically, the bitstream data can be generated by FPGA programming tools and can contain configuration information of multiple functional modules, enabling the FPGA system to implement the corresponding functions (i.e., the target application) according to the design requirements. When the bitstream data is loaded into the FPGA system, it determines the internal logic functions and connection relationships of the FPGA system.

[0037] The first test route represents the test sequence for at least one functional module to be tested. The functional module to be tested is the functional module required by the target application. For example, if implementing the target application requires… Figure 1 This involves all functional modules in Region_1 and Region_2. At this point, the functional module to be tested can be any functional module in Region_1 and Region_2. The first test path can be... Figure 2 The path is indicated by the dashed line.

[0038] Specifically, FPGAs have a wide variety of applications, each corresponding to different bitstream data. These different bitstream data cause the functional modules within the FPGA system to exhibit different functions and connections. The BIST FSM210 can dynamically adjust the test path based on the bitstream data of the different applications currently being loaded.

[0039] Test stimulus signals are used to instruct the module under test (DUT) to perform specific operations in order to verify whether the DUT functions correctly. For example, test stimulus signals can be used to trigger the corresponding DUT (such as a DSP) to perform fixed-point multiplication. Test stimulus signals can be high-level or low-level signals. The built-in self-test state machine 210 can control the built-in self-test circuit 220 to generate test stimulus signals according to a predefined test strategy and the characteristics of the DUT. After generating the test stimulus signals, the built-in self-test state machine 210 sequentially controls the BIST circuit 220 to transmit the test stimulus signals to the corresponding DUTs according to the order set in the first test path.

[0040] For example, a Register Transfer Level (RTL) design netlist can be input into a software synthesizer. The software synthesizer performs logic synthesis operations based on the RTL design netlist to obtain bitstream data. The RTL design netlist can be written by the designer using a hardware description language (such as Verilog or VHDL). The RTL design netlist mainly includes registers, combinational logic units (such as logic circuits composed of AND gates, OR gates, NOT gates, etc.), and the connections between various modules.

[0041] Specifically, the software synthesizer can transform the relatively abstract register-transfer level logic into a concrete gate-level circuit representation composed of various basic logic elements based on the logic description in the RTL design netlist and some pre-set constraints (such as clock frequency requirements, resource usage limits, etc.). After a series of back-end processing, it generates bitstream data that can be loaded into the FPGA system.

[0042] When testing the functional modules of the FPGA system using the test apparatus provided in this embodiment, after receiving the bitstream data, the BIST FSM 210 first enters an initialization state. In this state, the BIST FSM 210 initializes some registers, counters, and other resources related to the BIST circuit 220, such as clearing counters and setting initial test mode flags, to prepare for subsequent formal testing. Simultaneously, it can also reset the functional modules under test (such as CLBs, DSPs, or BRAMs) within the FPGA system to ensure that the functional modules are in a known initial state, facilitating accurate judgment of test results later.

[0043] Then, BIST FSM 210 enters the test stimulus generation state. In this state, BIST FSM 210 can determine the first test route based on bitstream data, and control BIST circuit 220 to generate corresponding test stimulus signals according to the predefined test strategy and the functions of each function module under test. Based on the first test route, BIST circuit 220 is controlled to send test stimulus signals to the corresponding function module under test.

[0044] After the test stimulus signals are sent sequentially to the corresponding function under test modules, the BIST FSM 210 enters the test execution state. In this state, each function under test module receives the test stimulus signals and begins to perform the corresponding operations. The BIST FSM 210 waits for each function under test module to output the test results.

[0045] After each function module under test performs its corresponding operation, the BIST FSM 210 enters the result detection state. In this state, the BIST FSM 210 controls the BIST circuit 220 to collect the test results output by each function module under test. After receiving the test results, the BIST FSM 210 determines whether the corresponding function module under test is normal based on the test results.

[0046] The FPGA system testing apparatus provided in this embodiment, through the cooperation of the BIST FSM 210 and the BIST circuit 220, can test only the functional modules required for specific applications of the FPGA system, thereby reducing testing time and saving testing costs. Furthermore, the cooperation between the BIST FSM 210 and the BIST circuit 220 allows for dynamic adjustment of the testing mode, enabling testing of the FPGA system's functional modules under different application scenarios to ensure their proper functioning, thus improving testing flexibility.

[0047] In one example, BIST FSM 210 is used to determine if the corresponding functional module under test is normal if the test result is the same as the preset result. That is, if the test result is the same as the preset result, the corresponding functional module under test is normal; if the test result is different from the preset result, the corresponding functional module under test is abnormal.

[0048] When an anomaly occurs in the module under test, the BIST FSM 210 can enter a fault handling state. In this state, the BIST FSM 210 can store information such as the location of the faulty module and the fault type (e.g., logical function error, timing error, or other types) in a specific register. It can also issue a fault warning signal to inform the designer that there is an anomaly in the module under test.

[0049] Furthermore, in some implementations, the BIST FSM 210 is also used to re-determine a second test path based on bitstream data when the functional module under test (DUT) malfunctions. The second test path represents the test order of the normal DUT and the first functional module, where the first functional module is a functional module of the same type as the malfunctioning DUT. That is, when the DUT malfunctions, the BIST FSM 210 can reselect a test path to skip the malfunctioning functional module and replace the faulty functional module with a functional module of the same function (the first functional module), thereby improving the yield of the FPGA system.

[0050] For example, the functional module includes a wired switch box (SWH), through which the BIST FSM 210 adjusts the first test path to a second test path. In other words, when the functional module under test malfunctions, the SWH can be reprogrammed to change the first test path to the second test path, thus bypassing the malfunctioning functional module.

[0051] In some embodiments, the second test route may also be a first test route that bypasses the abnormal functional module, for example, if it is determined that... Figure 1 An anomaly exists in the BRAM on Region_2. In this case, the second test route can be as follows: Figure 3 The path is indicated by the dashed line.

[0052] In some optional implementations, the built-in self-test state machine 210 is also used to determine the clock signal generated by the internal oscillator (OSC) as the reference clock (Closk, CLK). Alternatively, the internal oscillator can be output as a BIST flag, which is used to characterize the state of the BIST FSM 210, such as initialization state, test stimulus generation state, test execution state, result checking state, or fault handling state.

[0053] In this embodiment, the internal oscillator of the FPGA system itself is used as a reference clock and BIST flag, which simplifies the test setup and saves costs.

[0054] In this embodiment, a testing method for an FPGA system is also provided, which can be used in the aforementioned built-in self-test state machine 210. Figure 4 This is a flowchart illustrating a testing method for an FPGA system according to an embodiment of the present invention, as shown below. Figure 4 As shown, the method includes the following steps:

[0055] Step S401: Receive bitstream data.

[0056] The bitstream data is used to indicate at least one functional module required by the target application and the connection relationship of at least one functional module.

[0057] Specifically, bitstream data can be generated by FPGA programming tools and can contain configuration information for multiple functional modules, enabling the FPGA system to implement the corresponding functions (i.e., the target application) according to design requirements.

[0058] Step S402: Determine the first test route based on the bitstream data.

[0059] The first test route is used to represent the test sequence of at least one functional module to be tested, which is the functional module required by the target application.

[0060] For example, the first test route can be Figure 2 The path is indicated by the dashed line.

[0061] Step S403: Control the built-in self-test circuit to generate a test excitation signal.

[0062] Specifically, the test stimulus signal is used to instruct the functional module under test to perform a specific operation in order to verify whether the function of the functional module under test is normal. For example, the test stimulus signal can be used to trigger the corresponding functional module under test (such as DSP) to perform fixed-point multiplication.

[0063] Step S404: Based on the first test route, control the built-in self-test circuit to send test excitation signals to the corresponding functional module under test.

[0064] Step S405: Receive the test results output by at least one functional module under test collected by the built-in self-test circuit.

[0065] Step S406: Determine whether the corresponding functional module under test is normal based on the test results.

[0066] For example, if the test result is the same as the preset result, the corresponding functional module under test is determined to be normal; if the test result is different from the preset result, the corresponding functional module under test is determined to be abnormal.

[0067] In some alternative implementations, the normality of the corresponding functional module under test can also be determined by whether a test result is detected. Specifically, if the built-in self-test circuit does not collect a test result, the functional module under test corresponding to the built-in self-test circuit is abnormal; if the built-in self-test circuit collects a test result, the functional module under test corresponding to the built-in self-test circuit is normal.

[0068] The FPGA system testing method provided in this embodiment, after receiving bitstream data, determines a first test path based on the bitstream data and controls the built-in self-test circuit to generate test stimulus signals. Then, based on the first test path, it controls the built-in self-test circuit to send test stimulus signals to the corresponding functional module under test. After receiving the test results output by at least one functional module under test collected by the built-in self-test circuit, it determines whether the corresponding functional module under test is normal based on the test results. This method can test only the functional modules required for the specific application that the FPGA system needs to complete, thereby reducing testing time and saving testing costs.

[0069] Optionally, when the functional module under test is abnormal, the built-in self-test state machine 210 re-determines the second test route based on the bit stream data to update the first test route. The second test route is used to represent the test order of the normal functional module under test and the first functional module. The first functional module is a functional module of the same type as the abnormal functional module under test.

[0070] Specifically, such as Figure 5 As shown, after executing steps S401 to S406, if there is an anomaly in the functional module under test, the built-in self-test state machine 210 executes step S501. The built-in self-test state machine 210 re-determines the second test route based on the bitstream data to update the first test route (the second test route is the new first test route). Then it returns to step S403 until there are no anomalies in all functional modules under test. When there are no anomalies in the functional modules under test, step S502 is executed to end the test.

[0071] In this embodiment, the built-in self-test state machine 210 is presented in the form of a functional unit, which refers to an application-specific integrated circuit (ASIC), a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above functions.

[0072] For example, the built-in self-test state machine may include one or more processors, memory, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other using different buses and may be mounted on a common motherboard or otherwise installed as needed. The processor can process instructions that execute within the computer device, including instructions stored in or on memory to display graphical information of a GUI on an external input / output device (such as a display device coupled to the interface).

[0073] In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory units, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system).

[0074] The processor can be a central processing unit, a network processor, or a combination thereof. The processor may further include hardware chips. These hardware chips can be application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof. The programmable logic devices can be complex programmable logic devices (CLPs), field-programmable gate arrays (FPGAs), general-purpose array logic (GDAs), or any combination thereof.

[0075] The memory stores instructions executable by at least one processor to cause the at least one processor to perform the method shown in the above embodiments.

[0076] The memory may include a stored program area and a stored data area, wherein the stored program area may store the operating system and application programs required for at least one function; the stored data area may store data created based on the use of the computer device, etc. Furthermore, the memory may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory may optionally include memory remotely located relative to the processor, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0077] The memory may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory may also include a combination of the above types of memory.

[0078] The built-in self-test state machine also includes a communication interface for the built-in self-test state machine to communicate with other devices or communication networks.

[0079] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0080] In the description of this specification, the references to terms such as "this embodiment," "an embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0081] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0082] Although embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations all fall within the scope defined by the present invention.

Claims

1. A test apparatus for a field programmable gate array system, characterized by, The test device comprises a built-in self-test state machine and a plurality of built-in self-test circuits, the field programmable gate array system comprises a plurality of functional modules, the field programmable gate array system is suitable for a plurality of application scenarios, different applications correspond to different bit stream data, the plurality of functional modules and the plurality of built-in self-test circuits are one-to-one corresponding, and the built-in self-test circuit is arranged on the corresponding functional module; The built-in self-test state machine is configured to receive bit stream data, and the bit stream data is used to indicate at least one functional module required by a target application and a connection relationship of the at least one functional module; The built-in self-test state machine is further configured to determine a first test route based on the bit stream data, and to control the built-in self-test circuit to generate a test excitation signal, the first test route is used to indicate a test sequence of at least one functional module to be tested, the functional module to be tested is the functional module required by the target application, the test excitation signal is used to instruct the functional module to be tested to execute a specific operation, so as to verify whether the function of the functional module to be tested is normal, and the built-in self-test state machine dynamically adjusts the test route according to the bit stream data of different applications currently loaded; The built-in self-test state machine is further configured to control the built-in self-test circuit to send the test excitation signal to the corresponding functional module to be tested based on the first test route; The built-in self-test state machine is further configured to receive a test result output by at least one functional module to be tested collected by the built-in self-test circuit, and to determine whether the corresponding functional module to be tested is normal based on the test result; The built-in self-test state machine is further configured to determine a second test route based on the bit stream data again to update the first test route when the functional module to be tested is abnormal, the second test route is used to indicate a test sequence of the normal functional module to be tested and a first functional module, the first functional module is a functional module of the same type as the abnormal functional module to be tested, and the functional module comprises a wire switch box, and the built-in self-test state machine adjusts the first test route to the second test route through the wire switch box.

2. The test device of claim 1, wherein, The test excitation signal is used to trigger the corresponding functional module to be tested to perform fixed-point multiplication processing.

3. The test device of claim 1, wherein, The built-in self-test state machine is configured to determine that the corresponding functional module to be tested is normal when the test result is the same as a preset result.

4. The test device of claim 1, wherein, The built-in self-test state machine is further configured to determine a clock signal generated by an internal oscillator as a reference clock.

5. The test device of claim 1, wherein, The plurality of functional modules comprise at least one of a digital signal processor, a programmable logic group and a memory.

6. A method of testing a field programmable gate array system, characterized by, The test method is applied to the built-in self-test state machine in the test device of any one of claims 1 to 5, and the test method comprises: receiving bit stream data, and the bit stream data is used to indicate at least one functional module required by a target application and a connection relationship of the at least one functional module; determining a first test route based on the bitstream data, the first test route being used to represent a test sequence of at least one functional module to be tested, the functional module to be tested being required by the target application; controlling a built-in self-test circuit to generate a test excitation signal; controlling the built-in self-test circuit to send the test excitation signal to the corresponding functional module to be tested based on the first test route; receiving a test result output by the at least one functional module to be tested collected by the built-in self-test circuit; determining whether the corresponding functional module to be tested is normal based on the test result.

7. The test method of claim 6, wherein, The test method further comprises: when the functional module to be tested is abnormal, determining a second test route based on the bitstream data again to update the first test route, the second test route being used to represent a test sequence of the normal functional module to be tested and a first functional module, the first functional module being a functional module of the same type as the abnormal functional module to be tested.

8. The test method of claim 6, wherein, The determining whether the corresponding functional module to be tested is normal based on the test result comprises: in a case where the test result is the same as a preset result, determining that the corresponding functional module to be tested is normal.

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