Delay processing method, monitoring system, computing device and computer readable storage medium

Abstract

The embodiment of the invention provides a delay processing method, a monitoring system, computing equipment and a computer readable storage medium, the delay processing method is applied to the monitoring system, and the monitoring system is used for monitoring and processing delay of a multi-architecture processor; the method comprises the following steps: under the condition that the architecture type of a processor is a first architecture, obtaining instruction delay of a memory access instruction in a first architecture processor, and determining the memory access delay of the first architecture processor based on total delay, emission delay and address translation delay in the instruction delay; under the condition that the architecture type of the processor is a second architecture, memory access delay of a second architecture processor is obtained, and the second architecture is an architecture except the first architecture in the multiple architectures; and for any architecture processor, calling a preset delay processing task based on the memory access delay of the processor. According to the invention, high-accuracy and high-efficiency cross-architecture compatible delay processing is realized.

Description

Technical Field

[0001] The embodiments of this specification relate to the technical field of distributed operation and maintenance, and in particular to a delay processing method, a monitoring system, a computing device, and a computer-readable storage medium. Background Art

[0002] With the rapid development of distributed computing and cloud computing technologies, large-scale server systems are becoming more and more widely used in various industries, such as high-performance computing, big data processing, and machine learning.

[0003] At present, in the process of monitoring processors on large-scale server systems, especially in key areas such as e-commerce and Elastic Compute Service (ECS), real-time and efficient determination of memory access delays not only helps to promptly discover performance bottlenecks, but also can dynamically call delay processing tasks according to memory access pressure conditions, ensuring the stable operation of large-scale server systems.

[0004] However, in response to different scenario requirements, servers equipped with multi-architecture processors can adapt to a variety of application scenarios. As a result, the complexity of upper-layer applications monitoring underlying performance is also increasing. In monitoring systems used to monitor and process delays of multi-architecture processors, how to achieve high-accuracy and high-efficiency delay processing while ensuring cross-architecture compatibility is an urgent problem to be solved. Summary of the invention

[0005] In view of this, the embodiments of this specification provide a highly accurate and efficient delay processing method with cross-architecture compatibility. One or more embodiments of this specification also relate to a monitoring system, a computing device, a computer-readable storage medium and a computer program product to solve the technical defects existing in the prior art.

[0006] According to a first aspect of an embodiment of this specification, a delay processing method is provided, which is applied to a monitoring system, wherein the monitoring system is used to monitor and process the delay of a multi-architecture processor; the method comprises:

[0007] When the architecture type of the processor is a first architecture, obtaining an instruction delay of a memory access instruction in the first architecture processor, and determining a memory access delay of the first architecture processor based on a total delay, an issue delay, and an address translation delay in the instruction delay;

[0008] When the architecture type of the processor is a second architecture, obtaining a memory access latency of a processor of the second architecture, wherein the second architecture is an architecture other than the first architecture in the multiple architectures;

[0009] For any architecture processor, based on the processor's memory access latency, a preset delay processing task is called.

[0010] According to a second aspect of an embodiment of this specification, there is provided a monitoring system for monitoring and processing latency of a multi-architecture processor, the monitoring system comprising a collection component and a data processing platform;

[0011] A collection component is used to obtain the instruction delay of the memory access instruction in the processor of the first architecture when the architecture type of the processor is the first architecture, and determine the memory access delay of the processor of the first architecture based on the total delay, the emission delay and the address translation delay in the instruction delay; when the architecture type of the processor is the second architecture, obtain the memory access delay of the processor of the second architecture, wherein the second architecture is an architecture other than the first architecture in the multiple architectures;

[0012] The data processing platform is used to call preset delay processing tasks based on the memory access delay of the processor for any architecture processor.

[0013] According to a third aspect of an embodiment of this specification, a computing device is provided, including:

[0014] Memory and processor;

[0015] The memory is used to store computer programs / instructions, and the processor is used to execute the computer programs / instructions. When the computer programs / instructions are executed by the processor, the steps of the delay processing method are implemented.

[0016] According to a fourth aspect of the embodiments of this specification, a computer-readable storage medium is provided, which stores a computer program / instruction, and the computer program / instruction implements the steps of the above-mentioned delay processing method when executed by a processor.

[0017] According to a fifth aspect of the embodiments of this specification, a computer program product is provided, including a computer program / instruction, which implements the steps of the above-mentioned delay processing method when executed by a processor.

[0018] In one embodiment of the present specification, based on different processor architecture types, corresponding methods are used to obtain the memory access delay of the processor, thereby achieving cross-architecture compatibility in the monitoring system and improving the flexibility and practicality of the monitoring system. On a first architecture processor, the memory access delay is determined based on the total delay, transmission delay and address translation delay, and the memory access delay is determined with high accuracy, avoiding unnecessary data collection and parsing operations, improving delay processing efficiency, and for any architecture processor, based on the processor's memory access delay, the preset delay processing task is dynamically called to ensure stable operation and high performance of multi-architecture processors. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a flow chart of a time-delay processing method;

[0020] Figure 2 is a flow chart of a delay processing method provided by an embodiment of this specification;

[0021] Figure 3 is a schematic diagram of memory access delay of a delay processing method provided by an embodiment of this specification;

[0022] Figure 4 It is a flowchart of a delay processing method provided by an embodiment of this specification;

[0023] Figure 5 It is a flowchart of an ARM architecture processor in a delay processing method provided in an embodiment of this specification;

[0024] Figure 6 This is a processing flow chart of a delay processing method applied to an e-commerce scenario provided by an embodiment of this specification;

[0025] Figure 7 It is a structural schematic diagram of a monitoring system provided by an embodiment of this specification;

[0026] Figure 8 It is a structural block diagram of a computing device provided by an embodiment of this specification. DETAILED DESCRIPTION

[0027] Many specific details are described in the following description to facilitate a full understanding of this specification. However, this specification can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of this specification, so this specification is not limited to the specific implementation disclosed below.

[0028] The terms used in one or more embodiments of this specification are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of this specification. The singular forms of "a", "said" and "the" used in one or more embodiments of this specification and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in one or more embodiments of this specification refers to and includes any or all possible combinations of one or more associated listed items.

[0029] It should be understood that although the terms first, second, etc. may be used to describe various information in one or more embodiments of this specification, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of this specification, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0030] In addition, it should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in one or more embodiments of this specification are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0031] First, the terms involved in one or more embodiments of this specification are explained.

[0032] Dynamic Random Access Memory (DRAM): A common type of computer storage medium, mainly used for main memory. It stores data bits through capacitors, each capacitor represents a bit (0 or 1). Because capacitors gradually discharge, they need to be refreshed regularly to maintain data integrity. Compared with static random access memory (SRAM), DRAM is cheaper, but has slower access speeds.

[0033] Static Random Access Memory (SRAM): A type of computer storage medium that does not require regular refresh, mainly used for cache. It uses a group of transistors (usually six) to store one bit of data, so it is more stable and has faster access speed than dynamic random access memory (DRAM). However, due to its high manufacturing cost, it is usually used in situations with high speed requirements such as cache.

[0034] Synchronous Dynamic Random Access Memory (SDRAM) is a dynamic random access memory (DRAM) with a synchronous interface. Usually DRAM has an asynchronous interface so that it can respond to changes in control inputs at any time. SDRAM has a synchronous interface and waits for a clock signal before responding to control inputs, so that it can be synchronized with the computer's system bus. The clock is used to drive a finite state machine to pipeline the incoming instructions. This allows SDRAM to have a more complex operating mode compared to asynchronous DRAM, which does not have a synchronous interface.

[0035] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is an SDRAM with a double data rate. Its data transmission speed is twice the system clock frequency. Due to the increased speed, its transmission performance is better than traditional SDRAM.

[0036] Memory: A hardware component in a computer that temporarily stores data.

[0037] Cache: A high-speed memory located between the processor and main memory, used to store copies of frequently accessed data to reduce the number and time of accessing the main memory. Cache usually has a very fast access speed, which can significantly improve the overall performance of the system and reduce the time the processor waits for data. Common three-level caches include L1 cache, L2 cache, and L3 cache.

[0038] Access instruction: A machine instruction used in a computer program to load (LOAD) data from memory or a register.

[0039] Memory access instruction: A machine instruction used in a computer program to load (LOAD) data from memory.

[0040] Memory Access Latency: The total time interval from when the processor (CPU) issues a memory access instruction to when data is received from the dynamic random access memory (DRAM) or when the write operation is confirmed to be completed. Memory access latency includes the entire process of the processor issuing an instruction, the instruction being received by the memory controller, the dynamic random access memory processing the instruction, and the data being returned or the write being confirmed.

[0041] Statistical Profiling Extension (SPE): The Statistical Profiling Extension is optional in ARMv8.2 and is only supported in the AArch64 execution state. Sampling criteria are set based on instructions or micro-operations, and then samples are taken at certain cycles. Each sample collects contextual information associated with the sample to form a profile record, and only one record is compiled at any time. When sampling continuously on a system running a large workload for a long time, analyzing samples of large working sets can provide deep insights into software execution and its associated performance.

[0042] Performance Monitoring Unit (PMU): In modern processor architectures, a performance monitoring unit is a hardware component that monitors and collects processor performance data. The performance monitoring unit can be used to track various types of performance events, such as cache hits and misses, branch prediction successes and failures, execution cycles, instructions, interrupts, etc.

[0043] Processor pipeline (CPU pipeline): A technology widely used in modern microprocessors that allows multiple instructions to be executed in an overlapping manner to improve processor efficiency and throughput. This approach borrows the concept of industrial production lines and breaks down the execution process of instructions into a series of consecutive steps, each of which is handled by a different processor component. Each component can process different stages of different instructions at the same time, so that at any given moment, multiple instructions are being processed but are in different stages of execution. A typical processor pipeline includes the following basic stages: instruction fetch (IF), decode (ID), execute (EX), memory access (MA), and write back (WB).

[0044] Micro Operation: The basic, low-level operation performed by a computer processor when executing instructions. These operations usually involve direct control of hardware components such as registers, arithmetic logic units (ALUs), and control units, such as data transfer, arithmetic operations, logical operations, and conditional tests. Micro operations are the basis of machine instructions, and the function of each machine instruction is realized through a series of micro operation sequences. In computer architecture, especially in the design of microprogram control, the concept of micro operations is particularly important, which helps designers break down complex instruction sets into manageable small steps, thereby simplifying the design and implementation process of the processor.

[0045] Instruction Set Architecture (ISA): Instruction set architecture refers to the part of computer architecture related to programming, which defines the machine language instruction format and addressing mode.

[0046] Reduced Instruction Set Computing (RISC): A processor architecture design concept that emphasizes the use of a smaller number of simple instructions to build a processor in order to improve the execution efficiency and speed of the processor.

[0047] Reduced Instruction Set Processor (RISC Processor): A processor designed based on the RISC concept, characterized by a shorter instruction pipeline, a fixed instruction format and a simple addressing mode, which can achieve high-speed processing.

[0048] Complex Instruction Set Computing (CISC): A processor architecture design concept that emphasizes the use of a larger number of complex instructions to build processors in order to improve the functionality and flexibility of the processor.

[0049] Complex Instruction Set Processor (CISC Processor): A processor designed based on the CISC concept, characterized by a large number of complex instructions, each of which can complete multiple operations.

[0050] ARM architecture: A processor architecture based on the principle of Reduced Instruction Set Computing (RISC), widely used in mobile devices, embedded systems, servers and other fields. The ARM architecture is known for its low power consumption, high performance and flexibility.

[0051] x86 architecture: A complex instruction set computing (CISC) processor architecture widely used in personal computers and servers. The x86 architecture is characterized by strong compatibility and supports a wide software ecosystem.

[0052] x86-64 architecture: A 64-bit version of the x86 instruction set architecture. x86-64 extends the traditional 32-bit x86 architecture to support a larger memory address space and more registers, thereby improving performance and efficiency.

[0053] RISC-V (5th generation): An open standard instruction set architecture based on reduced instruction set computing (RISC) principles.

[0054] MIPS (Microprocessor without Interlocked Pipeline Stages): A reduced instruction set (RISC) processor architecture originally developed by a research team at Stanford University and later commercialized. The characteristics of the MIPS architecture include fixed-length instruction format, extensive use of registers, and a simple and regular instruction set. The MIPS architecture is widely used in embedded systems.

[0055] PowerPC: A reduced instruction set computing (RISC) microprocessor architecture used primarily in personal computers, game consoles, and embedded systems. The PowerPC design emphasizes high performance and low power consumption.

[0056] Kernel state: A processor operating mode in an operating system in which the executed code has full access to system resources such as memory, files, and devices. Programs running in kernel state can interact directly with hardware, execute privileged instructions, and perform core operations such as memory management and process scheduling. Because kernel state has high permissions, any errors in this mode may cause system instability or even crash. Therefore, only the core parts of the operating system and explicitly trusted drivers usually run in kernel state.

[0057] User mode: Another processor operating mode in the operating system, as opposed to kernel mode. In this mode, applications run and are restricted by the operating system and cannot directly access hardware or execute certain privileged instructions. User-mode programs can only access hardware resources indirectly by requesting the kernel to perform specific operations through system calls. This method improves the security and stability of the system because even if errors occur in user-mode programs, they will not directly affect other parts of the system. Most applications run in user mode.

[0058] Dynamic Shared Object (DSO): A code or data module that can be loaded into memory at runtime and shared by multiple programs. In Unix-like systems (such as Linux), dynamic shared objects usually exist in the form of shared libraries with a file extension of .so (for example, libexample.so). These libraries can be loaded when the program starts, or dynamically loaded as needed while the program is running. In performance analysis tools (such as perf), dynamic shared object information is used to identify and parse function call stacks to help developers understand which functions are performance bottlenecks. Dynamic shared objects contain symbolic information for functions and variables, which is very useful for mapping performance data to specific source code lines. With dynamic shared objects, developers can more accurately locate and optimize performance problems in the code.

[0059] perf tool: an open source performance analysis tool, mainly used in Linux systems. It provides a variety of performance analysis functions, including CPU usage, memory usage, cache hit rate, I / O operations, etc., to help developers and system administrators diagnose and optimize system performance.

[0060] Currently, the perf tool can be used in both x86 and ARM architectures. On servers with x86 architecture processors, the performance monitoring unit of the Double Data Rate Core (DDRC) can be used to collect data and obtain statistics related to memory access latency, and then further calculate and obtain the average memory access latency. In some ARM architecture processors that support statistical analysis extensions, the existing perf tool processing flow is as follows: Figure 1 As shown, Figure 1 A schematic diagram of a delay processing method is shown:

[0061] Collect statistical analysis extended data through the perfrecord command;

[0062] Traverse all available performance monitoring unit devices and statistical analysis extension devices;

[0063] Parse the configuration parameters entered by the user;

[0064] Parse and record function symbol information;

[0065] Start sampling other information;

[0066] Start extended sampling for statistical analysis;

[0067] The sampling data is written into the perf.data file;

[0068] Collect statistical analysis extended data through the perfrecord command;

[0069] Analyze and calculate the collected statistical analysis extended data and visualize the output;

[0070] Call the script to process the output;

[0071] instruction latency to fetch access instructions;

[0072] Calculate the average memory access latency during the sampling phase.

[0073] like Figure 1 The delay processing method shown in the figure, the perf tool obtains the average delay through statistical analysis extension on the ARM architecture, but has the following shortcomings:

[0074] 1. The perf tool not only needs to traverse all available performance monitoring unit devices and statistical analysis extension devices, and then find available statistical analysis extension devices, but also needs to parse the configuration parameters entered by the user, such as sampling frequency, filter conditions, sampling type, etc. It will also parse and record function symbol information, etc. In addition, during the sampling process, it is necessary not only to start statistical analysis extension sampling, but also to start other information sampling. Finally, all sampling data collected by the hardware will be written into the perf.data file. This process consumes a large CPU utilization and generates a large amount of intermediate data.

[0075] 2. The perf tool writes all collected sampling data into the perf.data file, and does not support directly obtaining the memory access delay from the stored file. It is necessary to parse the perf.data file using a large amount of collected information to determine the memory access delay. Therefore, the perf tool cannot determine the memory access delay in real time.

[0076] In summary, the sampling and parsing methods provided by the existing perf tools cannot achieve high-accuracy and high-efficiency delay processing while ensuring cross-architecture compatibility.

[0077] In response to the above problems, this specification provides a delay processing method. This specification also involves a monitoring system, a computing device, a computer-readable storage medium and a computer program product, which are described in detail one by one in the following embodiments.

[0078] See also Figure 2 , Figure 2 A flowchart of a delay processing method provided by an embodiment of the present specification is shown. The method is applied to a monitoring system, and the monitoring system is used to monitor and process the delay of a multi-architecture processor; the method includes the following specific steps:

[0079] Step 202: When the architecture type of the processor is a first architecture, obtain the instruction delay of the memory access instruction in the first architecture processor, and determine the memory access delay of the first architecture processor based on the total delay, the issuance delay and the address translation delay in the instruction delay.

[0080] The monitoring system is a system for monitoring the performance status of a multi-architecture processor, and in the embodiment of this specification, is used to monitor and process the delay of the multi-architecture processor in real time and accurately.

[0081] Multi-architecture processors are processors that use different instruction set architectures, including but not limited to x86, x86-64, ARM, RISC-V, MIPS, PowerPC and other instruction set architectures. Multi-architecture processors can be deployed on server systems and are suitable for a variety of application scenarios. For example, a distributed system is a cluster system composed of multiple server nodes interconnected through a network. Multiple server nodes collaborate to complete tasks. Multi-architecture processors are deployed on the server nodes of the distributed system.

[0082] The architecture type of the processor is the instruction set architecture type of the processor, including but not limited to at least one of the following: x86, x86-64, ARM, RISC-V, MIPS, PowerPC, etc.

[0083] The first architecture is an architecture type that cannot directly obtain processor-level memory access latency data. This is usually because the hardware under this architecture does not support direct collection of coarse-grained data at the processor level, or because the operating system and virtualization layer restrict access to low-level hardware, and cannot collect coarse-grained data at the processor level. Therefore, for the first architecture, an indirect method is needed to calculate memory access latency.

[0084] The first architecture processor is a processor of an architecture type for which processor-level memory access latency data cannot be directly obtained, including but not limited to at least one of the following: x86 architecture processor, x86-64 architecture processor, ARM architecture processor, RISC-V architecture processor, MIPS architecture processor, PowerPC architecture processor, etc. For example, in a hybrid cloud environment, the server includes x86 and ARM architecture processors, and the memory access latency of the ARM architecture processor cannot be directly obtained, then the ARM architecture processor is the first architecture processor.

[0085] The memory access instruction is a machine instruction in the processor for loading data from the memory. For example, the first architecture processor is an ARM processor, and the ARM memory access instruction is: LDR r1, [r0], which loads the data at the memory address r0 into the register r1.

[0086] The instruction delay of a memory access instruction is the duration of multiple stages of the processor executing the memory access instruction, from the time the processor issues the memory access instruction to the time the data is loaded into the register or the write operation is confirmed to be completed. Accordingly, the instruction delay includes the total delay, the transmission delay, and the address translation delay. The instruction delay of the memory access instruction can be collected from the performance monitoring unit device, or parsed from the statistical analysis extended data collected by the statistical analysis extension device, which is not limited here. For example, the statistical analysis extended data collected by the statistical analysis extension device is shown in Table 1:

[0087]

[0088] Table 1

[0089] The above is a collection of statistical analysis extended data. The first column is the address, the second column is the byte content stored in the address, and the third column is the context information for interpreting the second column.

[0090] PC 0x41f62c el0 ns=1 is the address of the program counter "0x41f62c", "el0" is "ExceptionLevel 0", that is, the user level (User Mode), which is the lowest privilege level in the ARM exception level system and is usually used to execute user space applications. "ns=1" indicates that the current execution state is non-secure state. This state identifier is used to distinguish between secure and non-secure states. "ns=1" indicates that it is currently executing in non-secure state. PAD (padding) is the padding identifier. LD GP-REG indicates that the instruction type is a memory access instruction of a general register. "EVRETIRED L1D-ACCESS L1D-REFILL TLB-ACCESS LLC-ACCESS LLC-REFILL" indicates that this is a retired instruction, which has passed L1D cache miss, LLC cache miss, and TLB hit. Then its data source is 14, which means that the data comes from DRAM. Only when all caches miss will the main memory be accessed. "LAT601ISSUE" indicates that the launch delay is 601 cycles, and "LAT "894TOT" indicates that the total delay is 894 cycles, "VA0xff77449d01a0" indicates that the virtual memory address of the data accessed by the memory access instruction is "0xff77449d01a0", "LAT6XLAT" indicates that the address translation delay is 6 cycles, "DATA-SOURCE 14" indicates that the data source is the DRAM with identifier 14, and "END" indicates the end of the statistical analysis extended data. For the second statistical analysis extended data, refer to the first statistical analysis extended data.

[0091] The total latency is the time from when the processor issues a micro-operation to when the operation is completed, which is the latency at the micro-operation level in the instruction. See "LAT 894TOT" and "LAT 1067TOT" in Table 1 above.

[0092] The issue delay is the time from when the micro-operation is decoded and ready for execution to when it is actually sent to the execution unit, which is the delay at the micro-operation level in the instruction. See "LAT 601ISSUE" and "LAT481 ISSUE" in Table 1 above.

[0093] The address translation delay is the time it takes for the virtual address of the micro-operation data to be sent to the memory management unit (MMU) and translated into a physical address by the MMU, which is the delay at the micro-operation level in the instruction. See "LAT 6XLAT" in Table 1 above.

[0094] The memory access latency of the first architecture processor is the duration of the data access phase in the memory access instruction executed by the first architecture processor, which is a processor-level latency. The data access phase is the phase from when the first architecture processor issues a memory access instruction to the memory, to when data is received from the dynamic random access memory (DRAM) or the write operation is confirmed to be completed. This phase covers the entire process of the processor issuing a memory access instruction to the memory, the memory access instruction being received by the memory controller, the dynamic random access memory processing the memory access instruction, and the data being returned or the write being confirmed. The memory access latency of the first architecture processor is used to measure the memory access performance of the first architecture processor, that is, the speed and efficiency of the processor accessing the memory. A lower memory access latency means that the first architecture processor reads data from the memory faster, and a higher memory access latency means that the first architecture processor reads data from the memory slower, and a preset delay processing task needs to be called to complete monitoring and processing.

[0095] When the architecture type of the processor is a first architecture, an instruction delay of a memory access instruction in the first architecture processor is obtained. An optional method is: when the architecture type of the processor is the first architecture, an instruction delay of a memory access instruction collected by a collection device in the first architecture processor is obtained, wherein the collection device includes but is not limited to a statistical analysis extension device and a performance monitoring unit device.

[0096] Based on the total delay, the emission delay and the address translation delay, the memory access delay of the processor of the first architecture is determined. An optional method is: based on the total delay, the emission delay and the address translation delay, the memory access delay of the memory access instruction in the processor of the first architecture is determined. Based on the memory access delay of the memory access instruction in the processor of the first architecture, the memory access delay of the processor of the first architecture is determined. Wherein, based on the total delay, the emission delay and the address translation delay, the memory access delay of the memory access instruction is determined. An optional method is: the total delay is subtracted from the emission delay and the address translation delay to obtain the memory access delay of the memory access instruction. Among them, based on the memory access delay of the memory access instructions in the first architecture processor, the memory access delay of the first architecture processor is determined. One optional method is: counting the memory access delay of the memory access instructions in the first architecture processor to determine the average memory access delay of the first architecture processor. Another optional method is: counting the memory access delay of the memory access instructions in the first architecture processor to determine the peak memory access delay of the first architecture processor. Another optional method is: counting the memory access delay of the memory access instructions in the first architecture processor to determine the variance or standard deviation of the memory access delay of the first architecture processor, which is not limited here.

[0097] For memory access instructions, since the total delay covers multiple sub-stages such as the emission stage, instruction translation stage, and execution stage, in the execution stage, the duration is mainly used for the data memory access stage and other stages, such as the write back / update cache stage, and the duration of these other stages is negligible compared to the main data memory access stage, the memory access delay of the memory access instruction can be more accurately determined by subtracting the emission delay and address translation delay from the total delay. Figure 3 As shown, Figure 3 A schematic diagram showing memory access delay of a delay processing method provided by an embodiment of this specification is shown:

[0098] The micro-operation of memory access instruction includes the emission stage, execution stage and memory access stage. There is an address translation stage in the execution stage. The entire micro-operation generates a total delay, the emission stage generates an emission delay, the address translation stage generates an address translation delay, and the remaining delay is mainly the memory access delay in the memory access stage. The memory access delay can be determined more accurately through formula 1:

[0099] Memory access delay = total delay - transmission delay - address translation delay Formula 1

[0100] Exemplarily, a distributed system includes multiple server nodes, and processors of a specific architecture type are deployed on any server node, including x86 architecture processors and ARM architecture processors. A monitoring system monitors the distributed system and processes the delay of a distributed system of multi-architecture processors. In the monitoring system, for a processor of an ARM architecture type in the distributed system, the statistical analysis extension data collected by the statistical analysis extension device in the ARM architecture processor within 10 seconds is obtained, including the instruction delay of 200 memory access instructions, wherein the instruction delay of a memory access instruction includes: total delay: 894 clock cycles. Emission delay: 661 clock cycles. Address translation delay: 6 clock cycles. Formula 1 is used to calculate the memory access delay of 200 memory access instructions in the ARM architecture processor, wherein the memory access delay of one memory access instruction is: 894 clock cycles-661 clock cycles-6 clock cycles=227 clock cycles. Based on the memory access delay of 200 memory access instructions, the memory access delay of the ARM architecture processor is determined to be: 204 clock cycles.

[0101] When the architecture type of the processor is the first architecture, the instruction delay of the memory access instruction in the first architecture processor is obtained, and the memory access delay of the first architecture processor is determined based on the total delay, the transmission delay and the address translation delay. The memory access delay is determined with high accuracy, unnecessary data collection and analysis operations are avoided, and the delay processing efficiency is improved.

[0102] Step 204: when the architecture type of the processor is a second architecture, obtain a memory access latency of the second architecture processor, wherein the second architecture is an architecture other than the first architecture in the multiple architectures.

[0103] The second architecture is an architecture type that can directly obtain processor-level memory access latency data, and the second architecture is an architecture outside the first architecture in the multi-architecture. This is usually because the hardware under this architecture supports directly collecting coarse-grained data at the processor level, or because the operating system and virtualization layer do not restrict low-level hardware access, and coarse-grained data at the processor level can be collected. The second architecture does not have the limitations of the first architecture mentioned above, allowing higher transparency and lower levels of access rights. The required latency data can be directly read through the performance monitoring unit (PMU) or other built-in performance monitoring tools without the need for additional data parsing steps.

[0104] The second architecture processor is a processor of an architecture type that can directly obtain processor-level memory access latency data, including but not limited to at least one of the following: x86 architecture processor, x86-64 architecture processor, ARM architecture processor, RISC-V architecture processor, MIPS architecture processor, PowerPC architecture processor, etc. For example, in a hybrid cloud environment, the server includes x86 and ARM architecture processors, and the memory access latency of the ARM architecture processor cannot be directly obtained, then the x86 architecture processor is the second architecture processor.

[0105] The memory access latency of the second architecture processor is the duration of the data access phase in the memory access instruction executed by the second architecture processor, which is a processor-level latency. The data access phase is the phase from when the second architecture processor issues a memory access instruction to the memory, to when data is received from the dynamic random access memory (DRAM) or the write operation is confirmed to be completed. This phase covers the entire process of the processor issuing a memory access instruction to the memory, the memory access instruction being received by the memory controller, the dynamic random access memory processing the memory access instruction, and the data being returned or the write being confirmed. The memory access latency of the second architecture processor is used to measure the memory access performance of the second architecture processor, that is, the speed and efficiency of the processor accessing the memory. A lower memory access latency means that the second architecture processor reads data from the memory faster, and a higher memory access latency means that the second architecture processor reads data from the memory slower, and a preset delay processing task needs to be called to complete monitoring and processing.

[0106] It should be noted that the first architecture is an architecture in which the processor-level memory access latency cannot be directly obtained in a multi-architecture processor. This is due to the limitations of the hardware design or operating system, such as the lack of necessary PMU support or the existence of a strict access control mechanism; the second architecture is an architecture in which the processor-level memory access latency can be directly obtained in a multi-architecture processor, and there are no similar hardware or operating system-level limitations. The two are not limited to specific architectures, but are determined by factors such as the internal characteristics of the multi-architecture processor, operating system support, and whether there are appropriate performance monitoring interfaces. By distinguishing between the two architectures and adopting different monitoring strategies for different architectures, the monitoring system can effectively adapt to various processor platforms and have cross-architecture compatibility.

[0107] When the architecture type of the processor is the second architecture, a memory access delay of the second architecture processor is obtained. An optional method is: when the architecture type of the processor is the second architecture, the memory access delay of the second architecture processor collected by a collection device in the second architecture processor is obtained, wherein the collection device includes but is not limited to a statistical analysis extension device and a performance monitoring unit device.

[0108] Exemplarily, in the monitoring system, for a certain x86 architecture type processor in the distributed system, the memory access delay of the x86 architecture processor is directly acquired from the performance monitoring unit: 280 clock cycles.

[0109] By distinguishing between the two architectures and obtaining the processor's memory access latency in a targeted manner, the system can effectively adapt to various processor platforms and have cross-architecture compatibility.

[0110] Step 206: For any architecture processor, based on the memory access delay of the processor, call a preset delay processing task.

[0111] The memory access latency of the processor is the duration of the data access phase in the processor's execution of a memory access instruction. The data access phase is the phase from when the processor issues a memory access instruction to the memory, to when data is received from the dynamic random access memory (DRAM) or the write operation is confirmed to be completed. This phase covers the entire process of the processor issuing a memory access instruction to the memory, the memory access instruction being received by the memory controller, the dynamic random access memory processing the memory access instruction, and the data being returned or the write being confirmed. The memory access latency of the processor is used to measure the memory access performance of the processor, that is, the speed and efficiency of the processor accessing the memory. A lower memory access latency means that the processor reads data from the memory faster, and a higher memory access latency means that the processor reads data from the memory slower, and the preset delay processing task needs to be called to complete monitoring and processing.

[0112] The preset delay processing tasks are pre-set operation and maintenance strategy tasks, which are used to take corresponding optimization or mitigation measures for different levels of memory access delays to improve or maintain the performance of multi-architecture processors. The preset delay processing tasks include but are not limited to: configuration adjustment tasks, load balancing tasks, cache optimization tasks, hardware acceleration tasks, capacity expansion tasks, visual monitoring tasks, alarm management tasks, log recording and analysis tasks, etc.

[0113] For example, for the ARM architecture processor, based on the memory access delay (204 clock cycles) of the ARM processor, the visualization monitoring task and the alarm management task are called. For a certain x86 architecture processor, based on the memory access delay (280 clock cycles) of the x86 architecture processor, the visualization monitoring task and the alarm management task are called.

[0114] In the embodiments of the present specification, based on different processor architecture types, corresponding methods are used to obtain the memory access delay of the processor, thereby achieving cross-architecture compatibility in the monitoring system and improving the flexibility and practicality of the monitoring system. On a processor of a first architecture, the memory access delay is determined based on the total delay, transmission delay and address translation delay, and the memory access delay is determined with high accuracy, thereby avoiding unnecessary data collection and parsing operations and improving delay processing efficiency. Moreover, for any architecture processor, based on the memory access delay of the processor, the preset delay processing task is dynamically called, thereby ensuring the stable operation and high performance of the multi-architecture processor.

[0115] In an optional embodiment of the present specification, the memory access delay of the processor of the first architecture is an average memory access delay; in step 202, the memory access delay of the processor of the first architecture is determined based on the total delay, the issuance delay and the address translation delay in the instruction delay, including the following specific steps:

[0116] Determine a memory access delay of a memory access instruction in a processor of the first architecture based on a total delay, an issue delay, and an address translation delay in the instruction delay;

[0117] Count the memory access delays of memory access instructions in the first architecture processor to obtain an average memory access delay of the first architecture processor.

[0118] The average memory access latency is the average duration of the data access phase in each memory access instruction of the first architecture processor, which is the processor-level latency. The average memory access latency of the first architecture processor is used to measure the memory access performance of the first architecture processor, that is, the speed and efficiency of the processor accessing the memory. A lower average memory access latency means that the first architecture processor reads data from the memory faster, and a higher average memory access latency means that the first architecture processor reads data from the memory slower, and needs to call the preset delay processing task to complete monitoring and processing.

[0119] Based on the total delay, emission delay and address translation delay in the instruction delay, the memory access delay of the memory access instruction in the first architecture processor is determined. One optional method is: subtract the emission delay and address translation delay from the total delay to obtain the memory access delay of the memory access instruction in the first architecture processor. Another optional method is: using a machine learning algorithm to predict the memory access delay of the memory access instruction in the first architecture processor based on the total delay, emission delay and address translation delay in the instruction delay. Another optional method is: using a statistical modeling algorithm to determine the memory access delay of the memory access instruction in the first architecture processor based on the total delay, emission delay and address translation delay in the instruction delay. This is not limited here.

[0120] Exemplarily, the memory access delay of 200 memory access instructions in the ARM architecture processor is calculated using Formula 1, where the memory access delay of one memory access instruction is: 894 clock cycles - 661 clock cycles - 6 clock cycles = 227 clock cycles. The memory access delays of the 200 memory access instructions are counted to determine that the average memory access delay of the ARM architecture processor is: 204 clock cycles.

[0121] In the embodiments of the present specification, the memory access delay of the memory access instruction in the first architecture processor is first determined based on the total delay, the transmission delay and the address translation delay, and then the memory access delay of each memory access instruction in the first architecture processor is counted to obtain the average memory access delay of the first architecture processor, thereby improving the accuracy of the determined memory access delay.

[0122] In an optional embodiment of the present specification, before determining the memory access delay of the processor of the first architecture based on the total delay, the issue delay and the address translation delay in the instruction delay in step 202, the following specific steps are also included:

[0123] Delaying the writing of the memory access instruction in the first architecture processor into a pre-set kernel state buffer;

[0124] Correspondingly, in step 202, based on the total delay, the issue delay and the address translation delay in the instruction delay, the memory access delay of the processor of the first architecture is determined, including the following specific steps:

[0125] When the current size of the kernel-mode buffer reaches a preset threshold, the instruction delay of the memory access instruction in the first architecture processor is taken out, and the memory access delay of the first architecture processor is determined in the user mode based on the total delay, the emission delay and the address translation delay in the instruction delay.

[0126] The kernel state buffer is a memory area allocated in the kernel state of the operating system, which is used to temporarily store the instruction delay of the memory access instruction in the first architecture processor. The kernel state buffer allows the operating system to efficiently process a large amount of data without frequently switching context information. Since the operations in the kernel state have higher permissions, they can directly access hardware resources and perform tasks with higher performance requirements. Therefore, using the kernel state buffer to temporarily store the instruction delay of the memory access instruction in the first architecture processor can reduce the delay and overhead in the data transmission process. A kernel state buffer is set to temporarily store various collected indicator data. Whenever the instruction delay of a new memory access instruction is recorded, it will be placed in this buffer first, and will not be taken out for processing until a certain condition is met. In the embodiment of this specification, the current size of the kernel state buffer reaches a preset threshold.

[0127] The current size of the kernel buffer is the amount of data currently written to the kernel buffer. The current size of the kernel buffer is a dynamically changing value that changes dynamically as data is continuously written and retrieved. For example, a kernel buffer is used to store memory access instruction delay data, and its total capacity is 1024 bytes. If 512 bytes of data have been written, the current size is 512 bytes.

[0128] The preset threshold is a preset data size threshold used to trigger the fetching of the written data in the kernel mode buffer area. The preset threshold can be a fixed value, such as 800 bytes, or a ratio, such as 50%.

[0129] Exemplarily, the instruction delays of 200 memory access instructions in an ARM architecture processor are written into a pre-set kernel state buffer, the kernel state buffer size is 1600 bytes, and the current size of the kernel state buffer is 800 bytes, which reaches half of the kernel state buffer size. The instruction delays of 300 memory access instructions stored therein are taken out, and formula 1 is used in user state to calculate the memory access delays of the 200 memory access instructions in the ARM architecture processor.

[0130] In the embodiments of the present specification, by setting a kernel-mode buffer to control the temporary storage and processing timing of instruction delays, memory access delays can be output at a certain frequency, reducing context information switching, improving delay processing efficiency, reducing latency, and enhancing the stability of multi-architecture processors.

[0131] Generally, the instruction delay directly collected from the first architecture processor is the instruction delay of the access instruction, and it is necessary to further screen out the instruction delay of the memory access instruction on this basis.

[0132] In an optional embodiment of the present specification, in step 202, when the architecture type of the processor is the first architecture, obtaining the instruction delay of the memory access instruction in the processor of the first architecture includes the following specific steps:

[0133] When the architecture type of the processor is a first architecture, obtaining an instruction delay of an access instruction in the processor of the first architecture;

[0134] Based on the data source of the access instruction, the instruction delay of the memory access instruction in the first architecture processor is obtained by screening from the instruction delay of the access instruction in the first architecture processor.

[0135] The data source of the access instruction is the actual storage location of the data when the access instruction is executed, which can be different levels of cache (such as L1, L2, L3 cache), main memory (such as dynamic random access memory DRAM), or other storage media. For example, if the data of the access instruction comes from the L1 cache, the latency of this instruction will be very low because it does not need to access the main memory. "EV RETIRED L1D-ACCESS L1D-REFILL TLB-ACCESS LLC-ACCESS LLC-REFILL" in Table 1 indicates that the access instruction did not hit the first-level cache. For another example, if the data of the access instruction comes from the dynamic random access memory (DRAM), the latency of this instruction will be high because it needs to read data from the main memory through the memory controller. "DATA-SOURCE 14" in Table 1 indicates that the data source is the DRAM with identifier 14, which means that the data of the access instruction is read from the main memory.

[0136] Based on the data source of the access instruction, the instruction delay of the memory access instruction in the first architecture processor is screened from the instruction delay of the access instruction in the first architecture processor. An optional method is: from the instruction delay of the access instruction in the first architecture processor, the instruction delay of the access instruction whose data source is the dynamic random access memory is screened and obtained as the instruction delay of the memory access instruction in the first architecture processor. Another optional method is: from the instruction delay of the access instruction in the first architecture processor, the instruction delay whose data source is not the cache is screened and obtained as the instruction delay of the memory access instruction in the first architecture processor. This is not limited here.

[0137] For example, in the monitoring system, for the ARM architecture type of a processor in the distributed system, the statistical analysis extension data collected by the statistical analysis extension device in the ARM architecture processor within 10 seconds is obtained, including the instruction delay of 500 access instructions. From the instruction delay of the 500 access instructions, 200 access instructions are screened and obtained from the instruction delay of the dynamic random access memory as the instruction delay of the memory access instruction in the ARM architecture processor, and the other 300 access data are discarded.

[0138] In the embodiments of the present specification, based on the data source of the access instructions, the instruction delay of the memory access instruction is screened out from the instruction delay of the access instruction, thereby achieving accurate monitoring of the actual memory access performance. It can not only parse and process key memory access delay data in real time, but also reduce unnecessary data copying and processing overhead, thereby improving the efficiency and accuracy of the monitoring system and ensuring the efficient operation of multi-architecture processors.

[0139] In an optional embodiment of the present specification, step 206 includes the following specific steps:

[0140] For any architecture processor, based on the processor's memory access latency, call the visualization monitoring task.

[0141] Visual monitoring tasks are tasks that display the performance status of software and hardware resources on multi-architecture processors in the form of visual interfaces or visual charts, so that users can intuitively understand and analyze the performance status of multi-architecture processors. This type of task usually includes the display of real-time data, trend analysis of historical data, and highlighting of abnormal situations. For example, when continuous sampling is performed on a multi-architecture processor that runs a large workload for a long time, analyzing samples of large working sets can provide in-depth understanding of software execution and its related performance, and provide a statistical view of the performance characteristics of executing memory access instructions. Developers and operation and maintenance personnel can use the statistical view to optimize the code to obtain better performance status.

[0142] For example, for ARM architecture processors, based on the memory access latency of the ARM architecture processor, the visualization monitoring task is called to generate a visualized dynamic chart, which is updated at a certain period. For x86 architecture processors, based on the memory access latency of the x86 architecture processor, the visualization monitoring task is called to generate a visualized dynamic chart, which is updated at a certain period. Developers and operation and maintenance personnel can use the above dynamic charts to optimize the code to obtain better performance status.

[0143] In the embodiments of this specification, by calling the visualization monitoring task, the memory access delay of any architecture processor is displayed in real time in a visualized form, providing an intuitive performance status view, which not only helps developers and operation and maintenance personnel to quickly identify performance bottlenecks and abnormal situations, but also supports trend analysis of historical data to facilitate long-term performance optimization. Dynamically updated charts ensure the timeliness of information and can respond to changes in multi-architecture processors in a timely manner, thereby improving the overall performance and stability of multi-architecture processors, simplifying the process of interpreting complex data, and improving the efficiency of monitoring and optimization work.

[0144] In an optional embodiment of the present specification, step 206 includes the following specific steps:

[0145] For any architecture processor, when the processor's memory access latency exceeds a preset threshold, the alarm management task is called.

[0146] Alarm management tasks are a series of notifications and measures that are automatically triggered when the memory access latency exceeds the preset threshold. These tasks are designed to promptly alert the operation and maintenance personnel or system administrators to potential problems and take appropriate measures to prevent the performance degradation or failure of multi-architecture processors. For example, email notification: When the memory access latency exceeds the preset threshold, an email with detailed information is automatically sent to the operation and maintenance team to inform the current latency and possible impact. SMS alarm: When the memory access latency exceeds the preset threshold, an SMS with detailed information is automatically sent to the operation and maintenance team to inform the current latency and possible impact. Logging: When the memory access latency exceeds the preset threshold, detailed alarm information is recorded in the log file, including timestamp, affected processor, specific latency value, etc., to facilitate subsequent analysis and auditing. Automatic response: When the memory access latency exceeds the preset threshold, predefined scripts or commands are automatically executed, such as restarting related services, adjusting memory allocation policies, increasing cache size, expanding capacity, etc., to restore the performance of multi-architecture processors as soon as possible.

[0147] For example, for ARM architecture processors, when the memory access latency (204 clock cycles) of the ARM architecture processor exceeds the preset memory access latency threshold (200 clock cycles), an email containing detailed information is automatically sent to the operation and maintenance team. For x86 architecture processors, when the memory access latency (280 clock cycles) of the x86 architecture processor exceeds the preset memory access latency threshold (200 clock cycles), an email containing detailed information is automatically sent to the operation and maintenance team. The operation and maintenance team dispatches memory resources from the resource pool to expand the memory capacity of the server node where the processor is located.

[0148] In the embodiments of the present specification, by calling the alarm management task, when the memory access delay of the processor exceeds the preset threshold, a series of notifications and response measures are automatically triggered, which can not only promptly remind attention to potential performance problems, but also automatically execute predefined scripts or commands to restore the performance of the multi-architecture processor. This mechanism ensures the stability and efficient operation of the multi-architecture processor, reduces the risk of service interruption due to performance degradation, and improves the reliability and response speed of the multi-architecture processor.

[0149] In an optional embodiment of the present specification, obtaining the instruction delay of the memory access instruction in the processor of the first architecture in step 202 includes the following specific steps:

[0150] According to a preset cycle, an instruction delay of a memory access instruction in a processor of the first architecture is obtained.

[0151] The preset period is a preset time interval for obtaining the instruction delay of memory access instructions. The preset period can be fixed or adjusted according to actual needs. The preset period ensures that the monitoring system can regularly obtain the instruction delay of memory access instructions, thereby providing continuous and consistent performance monitoring. The preset period automates the data collection and processing process, reduces the need for manual intervention, and improves the reliability and efficiency of multi-architecture processors.

[0152] According to a preset cycle, the instruction delay of the memory access instruction in the first architecture processor is obtained. An optional method is: according to a preset cycle, the instruction delay of the memory access instruction collected by the collection device in the first architecture processor is obtained, and according to the preset cycle, the instruction delay of the memory access instruction is uploaded to the log platform. Accordingly, step 204 includes the following specific steps: according to the preset cycle, the instruction delay of the memory access instruction is obtained from the log platform, and the memory access delay of the first architecture processor is determined based on the total delay, the transmission delay and the address translation delay.

[0153] For example, the preset cycle is set to once every 20 seconds. Every 20 seconds, the collection component will obtain the memory access delay of the memory access instructions collected within 5 seconds from the ARM architecture processor, obtain the average memory access delay of the ARM architecture processor, and upload these data to the log platform. The data processing platform can obtain the latest average memory access delay from the log platform at a cycle of once every 20 seconds. If the memory access delay exceeds the preset threshold, the monitoring system will automatically trigger the alarm management task and send an email or SMS to notify the operation and maintenance team.

[0154] In the embodiments of this specification, the delay data of memory access instructions is collected and processed regularly according to a preset cycle, so as to realize continuous and consistent monitoring of the performance of multi-architecture processors. This periodic operation ensures the real-time and accuracy of the data and improves the reliability and efficiency of the system.

[0155] In an optional embodiment of the present specification, the first architecture is an ARM architecture, and a statistical analysis extension device is deployed on the ARM architecture processor; in step 202, when the architecture type of the processor is the first architecture, obtaining the instruction delay of the memory access instruction in the first architecture processor includes the following specific steps:

[0156] When the architecture type of the processor is ARM architecture, the instruction delay of the memory access instruction in the ARM architecture processor collected by the statistical analysis extension device is obtained.

[0157] ARM architecture processor is a processor based on ARM instruction set architecture. ARM architecture has low power consumption, high performance and flexibility, and is widely used in mobile devices, embedded systems, servers and other fields.

[0158] The statistical analysis extension device is a hardware device used to collect statistical analysis extension data during the execution of the processor. It collects statistical analysis extension data based on binary, including but not limited to instruction delay, cache miss results, instruction type, data source, access mode, etc.

[0159] For statistical analysis extension, only the instruction delay of memory access instructions is collected, without collecting information such as timestamps, context information identifiers and physical addresses, thereby reducing data processing overhead.

[0160] When the architecture type of the processor is ARM architecture, the instruction delay of memory access instructions in the ARM architecture processor collected by the statistical analysis extension device is obtained. An optional method is: when the architecture type of the processor is ARM architecture, the statistical analysis extension data collected by the statistical analysis extension device is obtained, wherein the statistical analysis extension data includes the instruction delay of memory access instructions in the ARM architecture processor. Except for the statistical analysis extension data, the rest of the information is not collected. The corresponding statistical analysis extension device is directly searched, without traversing all available performance monitoring unit devices and statistical analysis extension devices, and then finding the available statistical analysis extension device. Because function hot spot analysis is not involved, there is no need to parse and record dynamic shared objects and other information. The configuration parameters can be directly converted into system call configuration values ​​without the need to use the command line parameter parsing process. Compared with the perf tool, the startup overhead of the statistical analysis extension device collection is greatly reduced.

[0161] An optional method is to collect the instruction delay of memory access instructions in ARM architecture processors by the statistical analysis extension device, based on preset filtering conditions. The preset filtering conditions include but are not limited to: instruction type, cache miss results, data source, access mode, etc. Another optional method is to collect the instruction delay of memory access instructions in ARM architecture processors by the statistical analysis extension device based on a time window. Another optional method is to collect the instruction delay of memory access instructions in ARM architecture processors by the statistical analysis extension device based on event triggering, wherein when a specific event occurs (such as CPU utilization exceeds a threshold, system response time slows down, etc.), the data collection process is started, which is not limited here.

[0162] Exemplarily, in the monitoring system, for the ARM architecture type of a processor in the distributed system, the statistical analysis extended data collected by the statistical analysis extension device in the ARM architecture processor within 10 seconds based on preset filtering conditions is obtained, as shown in Table 1, including the instruction delay of 200 memory access instructions.

[0163] In the embodiments of the present specification, when the architecture type of the processor is ARM architecture, the instruction delay of the memory access instruction in the ARM architecture processor collected by the statistical analysis extension device is directly obtained, thereby achieving efficient and accurate data collection, avoiding unnecessary data collection and processing, reducing startup overhead, and simplifying the configuration process. This not only improves the efficiency and accuracy of data collection, but also ensures real-time and effective use of resources, helps to quickly identify and resolve performance bottlenecks, and improves the overall stability and response speed of the distributed system.

[0164] In an optional embodiment of the present specification, the instruction delay of the memory access instruction in the ARM architecture processor is collected by a statistical analysis extension device based on the instruction type and cache miss result.

[0165] The instruction type is the type of machine instruction executed by the processor, which is used to complete specific operations, such as data loading, storage, movement, etc. For example, load (LOAD), store (STORE), move (MOVE), etc.

[0166] The cache miss result is the result of the statistical analysis extension device recording the miss of the memory access instruction in the different levels of cache when the processor executes the memory access instruction. A miss means that the data needs to be obtained from a higher level cache or main memory.

[0167] Based on the instruction type collection, an optional method is: collecting the instruction delay of the memory access instruction whose instruction type is the load type (LOAD).

[0168] Based on the cache miss result collection, one optional method is: based on the multi-level cache miss result collection, another optional method is: collect the first-level cache miss results and the total delay collection, and another optional method is: collect the first-level cache miss results, the second-level cache miss results and the total delay collection, which is not limited here.

[0169] Exemplarily, with the instruction type being load type (LOAD) and the cache miss result being all three-level cache misses as preset filtering conditions, the statistical analysis extension device collects statistical analysis extension data, as shown in Table 1, including instruction delays of 200 memory access instructions.

[0170] In the embodiments of the present specification, based on the preset filtering conditions of instruction type and cache miss results, the statistical analysis expansion device can accurately collect the instruction delay of memory access instructions in the ARM architecture processor, which not only improves the pertinence and accuracy of data collection, but also reduces unnecessary data processing overhead.

[0171] Since the statistical analysis expansion device can currently only filter out the first-level cache miss results, it can determine whether all three-level caches miss based on the first-level cache miss results and the total delay, and then load data from the memory. However, it does not limit the function of not being able to collect the second-level cache miss results and the third-level cache miss results in the future, and can directly collect the instruction delay of memory access instructions that miss multiple levels of cache.

[0172] In an optional embodiment of the present specification, the cache miss result is determined according to the first-level cache miss result and the total delay.

[0173] The first-level cache miss result is the result of the statistical analysis extension device recording the miss of the memory access instruction in the first-level cache when the processor executes the memory access instruction. A miss means that the data needs to be obtained from a higher-level cache or main memory.

[0174] Based on the collection of the first-level cache miss result, an optional method is: collecting when the first-level cache miss result is a miss.

[0175] Based on the total delay acquisition, an optional method is: acquisition when the total delay exceeds a preset threshold, wherein the preset threshold is set according to the performance of the processor.

[0176] Exemplarily, with the instruction type being load type (LOAD), the L1 cache miss result being miss (L1cache miss), and the total delay exceeding the preset threshold (250 clock cycles) as preset filtering conditions, the statistical analysis extension device collects statistical analysis extension data, as shown in Table 1, including the instruction delays of 200 memory access instructions. After the above preset filtering conditions, on an ARM architecture processor with a 50% machine water level, the data volume can be reduced from 15G to about 20M after collecting for 10s.

[0177] In the embodiments of the present specification, based on preset filtering conditions of instruction type, first-level cache miss results and total delay, the statistical analysis expansion device can accurately collect the instruction delay of memory access instructions in the ARM architecture processor, which not only further improves the pertinence and accuracy of data collection, but also further reduces unnecessary data processing overhead.

[0178] Since current processors often use a multi-core structure, if the memory access instruction in each processor core is delayed, it will cause. Considering that in actual scenarios, the latency of multiple processor cores in the same processor accessing memory in a short period of time is basically the same, any processor core can be selected to represent the overall memory access latency.

[0179] In an optional embodiment of the present specification, the instruction delay of the memory access instruction in the ARM architecture processor is collected by the statistical analysis extension device from any processor core in the ARM architecture processor.

[0180] A processor core is an independent computing unit in a processor that can execute instructions and process data. Each processor core can execute program code independently, and multiple cores can work in parallel to improve the overall performance of the system.

[0181] For example, in a 128-core ARM architecture processor system, in order to reduce the complexity and overhead of data collection, one of every 8 cores can be selected as a representative: cores No. 1, 9, 17, ..., 121 (a total of 16 cores) are selected to perform instruction delay collection of memory access instructions. This ensures that the collected data is representative while reducing the workload of data processing.

[0182] In the embodiments of this specification, the memory access latency of some processor cores can be determined to represent the overall memory access latency, which greatly reduces the amount of data processing and reduces overhead, and is suitable for scenarios with large amounts of data.

[0183] Considering that the latency of accessing memory is relatively stable in actual scenarios, the instruction latency of memory access instructions within a time window can be collected to determine the overall memory access latency.

[0184] In an optional embodiment of the present specification, the instruction delay of the memory access instruction in the ARM architecture processor is collected by the statistical analysis extension device according to a preset time window.

[0185] The preset time window is a pre-set time interval for collecting instruction delays of memory access instructions in ARM architecture processors. The preset time window ensures that the data collected within a certain period of time is representative and can reflect the overall performance of the system within that period of time. By setting an appropriate time window, the overhead of data collection and processing can be reduced while ensuring data accuracy. The preset time window can be adjusted according to actual needs to adapt to different application scenarios and performance monitoring needs.

[0186] Exemplarily, a 5-second time window is used to represent the memory access delay within 20 seconds, and the instruction delay of the memory access instruction of the ARM architecture processor within 5 seconds is collected.

[0187] In the embodiments of the present specification, the statistical analysis expansion device collects instruction delays of memory access instructions according to a preset time window, thereby reducing the frequency and overhead of data collection while ensuring data accuracy.

[0188] In an optional embodiment of the present specification, the second architecture is an x86 architecture, and a performance monitoring unit device is deployed on the x86 architecture processor; step 204 includes the following specific steps:

[0189] When the architecture type of the processor is the x86 architecture, the memory access delay of the x86 architecture processor collected by the performance monitoring unit device is obtained.

[0190] The x86 architecture processor is a processor based on the x86 instruction set architecture. The x86 architecture has the characteristics of strong compatibility and is widely used in personal computers, servers and other fields.

[0191] The performance monitoring unit device is a hardware device used to collect and analyze various performance indicators during the execution of the processor. It monitors the performance status of the processor in real time based on binary collection performance indicators. The performance monitoring unit device includes multiple performance counters configured to record specific types of events, such as the number of executions, cache hits / misses, branch prediction errors, etc. The specific events that the performance monitoring unit device needs to monitor can be selected programmatically, and the corresponding counters can be configured to record the number of occurrences of these events. Compared with the statistical analysis extension devices in ARM architecture processors, the performance monitoring unit devices for x86 architecture processors are currently more mature and can directly collect the memory access delay of x86 architecture processors.

[0192] For example, in the monitoring system, for the performance detection unit device of the x86 architecture processor, the method of obtaining the average memory access latency through the performance detection unit has been integrated into the kernel perf tool. The average memory access latency can be directly obtained by collecting the llc_demand_data_read_miss_to_pmem_latency indicator through the perf tool.

[0193] In the embodiments of the present specification, when the architecture type of the processor is the x86 architecture, the memory access delay of the x86 architecture processor is collected by using a performance monitoring unit device, thereby achieving efficient and accurate performance monitoring. Not only can detailed performance data be obtained in real time, but also the overhead of data collection and processing is reduced, cross-architecture compatibility of the monitoring system is achieved, and the flexibility and practicality of the monitoring system are improved.

[0194] With respect to the above-mentioned embodiments, Figure 4 A schematic diagram of a delay processing method provided by an embodiment of this specification is shown. Figure 4 As shown:

[0195] Initialize the collection environment. Install the binary based on statistical analysis to expand the device collection instruction delay on the server with ARM architecture processor, and install the binary based on performance monitoring unit device collection memory access delay on the server with other architecture processors.

[0196] The xperf acquisition component periodically obtains the corresponding binary instruction delay according to the architecture, determines the memory access delay of the memory access instruction in the ARM architecture processor based on the total delay, emission delay and address translation delay, determines the memory access delay of the memory access instruction in the ARM architecture processor, counts the memory access delay of each memory access instruction in the ARM architecture processor, obtains the average memory access delay of the ARM architecture processor, and counts the memory access delay of each memory access instruction in other architecture processors to obtain the average memory access delay of other architecture processors;

[0197] The xperf collection component periodically uploads the average memory access latency to the log platform;

[0198] The data processing platform used for data processing / data calculation periodically reads the average memory access delay of other architecture processors and ARM architecture processors from the log platform, and calls the visualization monitoring task and alarm management task for any architecture processor based on the processor's memory access delay.

[0199] Figure 4The delay processing method shown is a memory access delay detection solution that is compatible with ARM and x86 architectures. The solution has cross-architecture compatibility and can make intelligent adjustments based on the characteristics of x86 and ARM architectures to ensure the accuracy of memory access delay detection and the timeliness of alarms. This cross-architecture compatibility greatly improves the flexibility and practicality of the monitoring system.

[0200] In addition, the statistical analysis extension function based on the ARM architecture can set filtering conditions based on instructions or micro-operations and perform sampling in a certain time window. Each sample will collect context information related to the sample to form a statistical analysis extension data record. At any time, only one statistical analysis extension data record is compiled. In response to the memory access latency of the ARM architecture, a solution based on statistical analysis extension is further designed on this basis, such as Figure 5 As shown, Figure 5 A schematic diagram of a process flow of an ARM architecture processor in a delay processing method provided in one embodiment of this specification is shown:

[0201] Start the statistical analysis extended collection command;

[0202] Directly determine the corresponding statistical analysis expansion equipment;

[0203] Configure the statistical analysis extension device to collect only the information of LOAD (access instruction), L1 cache miss (miss L1 cache) and Latency>250 (total latency>250 cycles) of the 16 processor cores within the preset time window, and do not collect timestamps, context identifiers (context id) and physical addresses;

[0204] Output data on demand and extract instruction latency for access instructions whose data source is dynamic random access memory (DRAM);

[0205] Calculate and output memory access latency.

[0206] like Figure 5 The delay processing method for the ARM architecture shown is to use the statistical analysis extension mechanism to implement memory access delay detection, and reduce the amount of data collected by the statistical analysis extension by setting hardware-specific filtering conditions for the statistical analysis extension; directly specify the statistical analysis extension device and configuration parameters to avoid unnecessary data collection and dynamic shared object parsing records, and reduce the processor overhead of starting the statistical analysis extension; reduce the number of processors and time for collection to reduce processor and memory overhead; calculate the memory access delay by directly processing the instruction delay of the load instruction from the dynamic random access memory, without copying data, and obtain the memory access delay in real time, which can achieve a system processor overhead of less than 1%, and the memory occupied by each core can be controlled at around 1M, which is particularly suitable for online scenarios with large data volumes and high real-time requirements.

[0207] The following combination Figure 6 , taking the application of the delay processing method provided in this specification in the e-commerce scenario as an example, the delay processing method is further explained. Figure 6 A processing flow chart of a delay processing method applied to an e-commerce scenario provided by an embodiment of the present specification is shown, which is applied to a monitoring system, and the monitoring system is used to monitor and process the delay of an e-commerce platform distributed system of a multi-architecture processor; the method includes the following specific steps:

[0208] Step 602: Obtain the instruction delay of access instructions in the ARM architecture processor collected by the statistical analysis extension device, and write the instruction delay of access instructions in the ARM architecture processor into a pre-set kernel state buffer, wherein the instruction delay of the access instruction is collected by the statistical analysis extension device from any processor core in the ARM architecture processor based on the instruction type, the first-level cache miss result and the total delay, and the instruction delay includes the total delay, the transmission delay and the address translation delay.

[0209] Step 604: When the current size of the kernel state buffer reaches a preset threshold, the instruction delay of the access instruction in the ARM architecture processor is taken out, and in the user state, based on the data source of the access instruction, the instruction delay of the memory access instruction in the ARM architecture processor is screened and obtained, and the transmission delay and the address translation delay are subtracted from the total delay to obtain the memory access delay of the memory access instruction in the ARM architecture processor, and the memory access delay of each memory access instruction in the ARM architecture processor is counted to obtain the average memory access delay of the ARM architecture processor.

[0210] Step 606: Obtain the average memory access latency of the x86 architecture processor collected by the performance monitoring unit device.

[0211] Step 608: Upload the average memory access latency of any architecture processor to the log platform.

[0212] Step 610: According to a preset period, the average memory access latency of a processor of any architecture is obtained from the log platform, and based on the average memory access latency of the processor, a visualization monitoring task is called.

[0213] Step 612: When the average memory access latency of the processor exceeds a preset threshold, call an alarm management task.

[0214] The embodiments of this specification provide an innovative solution that is not only compatible with x86 and ARM architectures, but can also be intelligently adjusted according to the characteristics of different architectures to ensure the accuracy of memory access delays and the timeliness of alarms. Secondly, in response to the functional deficiencies of ARM memory access delays, a memory access delay processing solution at the instruction level based on the statistical analysis extension mechanism of the ARM architecture is designed. By accurately measuring the execution delays of each stage of the pipeline of the sampled instructions and calculating the current average memory access delay, a solid data foundation is provided for real-time detection. Not only can it monitor and accurately measure memory access delays in real time, but it can also maintain a low monitoring system overhead. It is suitable for online environments with large amounts of data and high real-time performance in e-commerce scenarios, and provides an efficient and reliable solution for performance monitoring of distributed systems of e-commerce platforms.

[0215] Corresponding to the above method embodiment, this specification also provides a monitoring system embodiment, Figure 7 FIG. 1 is a schematic diagram showing the structure of a monitoring system provided by an embodiment of the present specification. Figure 7 As shown, the monitoring system 700 is used to monitor and process the delay of a distributed system of multi-architecture processors, and the monitoring system 700 includes a collection component 702 and a data processing platform 704;

[0216] The acquisition component 702 is used to obtain the instruction delay of the memory access instruction in the processor of the first architecture when the architecture type of the processor is the first architecture, and determine the memory access delay of the processor of the first architecture based on the total delay, the emission delay and the address translation delay in the instruction delay; when the architecture type of the processor is the second architecture, obtain the memory access delay of the processor of the second architecture, wherein the second architecture is an architecture other than the first architecture in the multiple architectures;

[0217] The data processing platform 704 is used to call a preset delay processing task based on the memory access delay of the processor for any architecture processor.

[0218] In the embodiments of the present specification, the acquisition component adopts a corresponding method to obtain the memory access delay of the processor based on different processor architecture types, thereby achieving cross-architecture compatibility in the monitoring system and improving the flexibility and practicality of the monitoring system. On a processor of a first architecture, the memory access delay is determined based on the total delay, transmission delay and address translation delay, and the memory access delay is determined with high accuracy, thereby avoiding unnecessary data collection and analysis operations and improving delay processing efficiency. In addition, the data processing platform dynamically calls the preset delay processing task based on the memory access delay of the processor for any architecture processor, thereby ensuring the stable operation and high performance of multi-architecture processors.

[0219] In an optional embodiment of the present specification, the monitoring system 700 further includes a log platform;

[0220] The collection component 702 is further used to upload the memory access delay of the processor of the first architecture and the memory access delay of the processor of the second architecture to the log platform;

[0221] The data processing platform 704 is further used to obtain the memory access delay of the processor of the first architecture and the memory access delay of the processor of the second architecture from the log platform.

[0222] In the embodiments of this specification, the memory access delay of the processor of the first architecture is determined on the first architecture by utilizing the characteristic that the paths of the collection component and the log platform are independent of the processor architecture. This not only allows the data path between the collection component and the distributed system to be reused, but also allows the delay processing and delay processing task functions to be reused, further enhancing the scalability and maintainability of the monitoring system.

[0223] In an optional embodiment of the present specification, the memory access delay of the first architecture processor is an average memory access delay; the acquisition component 702 determines the memory access delay of the memory access instruction in the first architecture processor based on the total delay, the transmission delay and the address translation delay in the instruction delay; and counts the memory access delay of the memory access instruction in the first architecture processor to obtain the average memory access delay of the first architecture processor.

[0224] In an optional embodiment of the present specification, the acquisition component 702 is also used to write the instruction delay of the memory access instruction in the first architecture processor into a preset kernel state buffer; when the current size of the kernel state buffer reaches a preset threshold, the instruction delay of the memory access instruction in the first architecture processor is taken out, and the memory access delay of the first architecture processor is determined in the user state based on the total delay, the transmission delay and the address translation delay in the instruction delay.

[0225] In an optional embodiment of the present specification, the acquisition component 702 is specifically used to obtain the instruction delay of access instructions in the first architecture processor when the architecture type of the processor is the first architecture; based on the data source of the access instruction, the instruction delay of the access instruction in the first architecture processor is screened and obtained from the instruction delay of the access instruction in the first architecture processor.

[0226] In an optional embodiment of the present specification, the data processing platform 704 is specifically used to call a visualization monitoring task based on the memory access latency of a processor of any architecture.

[0227] In an optional embodiment of the present specification, the data processing platform 704 is specifically configured to call an alarm management task for any architecture processor when the memory access latency of the processor exceeds a preset threshold.

[0228] In an optional embodiment of the present specification, the acquisition component 702 is specifically used to obtain the instruction delay of the memory access instruction in the first architecture processor according to a preset cycle.

[0229] In an optional embodiment of the present specification, the first architecture is an ARM architecture, and a statistical analysis extension device is deployed on the ARM architecture processor; the collection component 702 is specifically used to obtain the instruction delay of the memory access instruction in the ARM architecture processor collected by the statistical analysis extension device when the architecture type of the processor is an ARM architecture.

[0230] In an optional embodiment of the present specification, the instruction delay of the memory access instruction in the ARM architecture processor is collected by a statistical analysis extension device based on the instruction type and cache miss result.

[0231] In an optional embodiment of the present specification, the cache miss result is determined according to the first-level cache miss result and the total delay.

[0232] In an optional embodiment of the present specification, the instruction delay of the memory access instruction in the ARM architecture processor is collected by the statistical analysis extension device from any processor core in the ARM architecture processor.

[0233] In an optional embodiment of the present specification, the instruction delay of the memory access instruction in the ARM architecture processor is collected by the statistical analysis extension device according to a preset time window.

[0234] In an optional embodiment of the present specification, the second architecture is an x86 architecture, and a performance monitoring unit device is deployed on the x86 architecture processor; the collection component 702 is specifically used to obtain the memory access delay of the x86 architecture processor collected by the performance monitoring unit device when the architecture type of the processor is the x86 architecture.

[0235] The above is a schematic scheme of a monitoring system of this embodiment. It should be noted that the technical scheme of the monitoring system and the technical scheme of the delay processing method described above are of the same concept, and the details not described in detail in the technical scheme of the monitoring system can be referred to the description of the technical scheme of the delay processing method described above.

[0236] Figure 8 The structure block diagram of a computing device provided by an embodiment of the present specification is shown. The components of the computing device 800 include but are not limited to a memory 810 and a processor 820. The processor 820 is connected to the memory 810 via a bus 830, and the database 850 is used to store data.

[0237] The computing device 800 also includes an access device 840, which enables the computing device 800 to communicate via one or more networks 860. Examples of these networks include a public switched telephone network (PSTN), a local area network (LAN), a wide area network (WAN), a personal area network (PAN), or a combination of communication networks such as the Internet. The access device 840 may include one or more of any type of network interface (e.g., a network interface card (NIC)) of wired or wireless, such as an IEEE 802.11 wireless local area network (WLAN) wireless interface, a Worldwide Interoperability for Microwave Access (Wi-MAX) interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth interface, and a Near Field Communication (NFC).

[0238] In one embodiment of the present specification, the above components of the computing device 800 and Figure 8 Other components not shown in the figure may also be connected to each other, for example, via a bus. It should be understood that Figure 8 The computing device structure block diagram shown is only for the purpose of illustration, and is not intended to limit the scope of this specification. Those skilled in the art can add or replace other components as needed.

[0239] The computing device 800 may be any type of stationary or mobile computing device, including a mobile computer or mobile computing device (e.g., a tablet computer, a personal digital assistant, a laptop computer, a notebook computer, a netbook, etc.), a mobile phone (e.g., a smart phone), a wearable computing device (e.g., a smart watch, smart glasses, etc.), or other types of mobile devices, or a stationary computing device such as a desktop computer or a personal computer (PC). The computing device 800 may also be a mobile or stationary server.

[0240] The processor 820 is used to execute the following computer program / instruction, which implements the steps of the above-mentioned delay processing method when executed by the processor.

[0241] The above is a schematic scheme of a computing device of this embodiment. It should be noted that the technical scheme of the computing device and the technical scheme of the delay processing method described above are of the same concept, and the details not described in detail in the technical scheme of the computing device can be referred to the description of the technical scheme of the delay processing method described above.

[0242] An embodiment of the present specification further provides a computer-readable storage medium storing a computer program / instruction, which implements the steps of the above-mentioned delay processing method when executed by a processor.

[0243] The above is a schematic scheme of a computer-readable storage medium of this embodiment. It should be noted that the technical scheme of the storage medium and the technical scheme of the delay processing method described above are of the same concept, and the details not described in detail in the technical scheme of the storage medium can be referred to the description of the technical scheme of the delay processing method described above.

[0244] An embodiment of the present specification further provides a computer program product, including a computer program / instruction, which implements the steps of the above-mentioned delay processing method when executed by a processor.

[0245] The above is a schematic scheme of a computer program product of this embodiment. It should be noted that the technical scheme of the computer program product and the technical scheme of the delay processing method described above are of the same concept, and the details not described in detail in the technical scheme of the computer program product can be found in the description of the technical scheme of the delay processing method described above.

[0246] The above is a description of a specific embodiment of the specification. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0247] The computer instructions include computer program codes, which may be in source code form, object code form, executable files or some intermediate forms, etc. The computer readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the contents contained in the computer readable medium may be appropriately increased or decreased according to the requirements of patent practice. For example, in some regions, according to patent practice, computer readable media do not include electric carrier signals and telecommunication signals.

[0248] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the embodiments of this specification are not limited by the order of the actions described, because according to the embodiments of this specification, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the embodiments of this specification.

[0249] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0250] The preferred embodiments of this specification disclosed above are only used to help explain this specification. The optional embodiments do not describe all the details in detail, nor do they limit the invention to only the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of the embodiments of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the embodiments of this specification, so that technicians in the relevant technical field can well understand and use this specification. This specification is only limited by the claims and their full scope and equivalents.

Claims

1. A delay processing method, applied to a monitoring system, wherein the monitoring system is used to monitor and process the delay of a multi-architecture processor; the method comprises: When the architecture type of the processor is a first architecture, obtaining an instruction delay of a memory access instruction in the first architecture processor, and determining a memory access delay of the first architecture processor based on a total delay, an issue delay, and an address translation delay in the instruction delay; When the architecture type of the processor is a second architecture, obtaining a memory access latency of a processor of the second architecture, wherein the second architecture is an architecture other than the first architecture in the multiple architectures; For any architecture processor, based on the processor's memory access latency, a preset delay processing task is called.

2. According to the method of claim 1, the memory access delay of the processor is an average memory access delay; The determining the memory access delay of the processor of the first architecture based on the total delay, the issuance delay and the address translation delay in the instruction delay comprises: Determine a memory access delay of a memory access instruction in the processor of the first architecture based on a total delay, an issue delay, and an address translation delay in the instruction delay; Count the memory access delays of memory access instructions in the first architecture processor to obtain an average memory access delay of the first architecture processor.

3. The method according to claim 1, before determining the memory access latency of the processor of the first architecture based on the total latency, the issue latency and the address translation latency in the instruction latency, further comprising: Delaying writing the memory access instruction in the first architecture processor into a preset kernel state buffer; The determining the memory access delay of the processor of the first architecture based on the total delay, the issuance delay and the address translation delay in the instruction delay comprises: When the current size of the kernel-mode buffer reaches a preset threshold, the instruction delay of the memory access instruction in the first architecture processor is taken out, and the memory access delay of the first architecture processor is determined in the user mode based on the total delay, the emission delay and the address translation delay in the instruction delay.

4. The method according to claim 1, wherein when the architecture type of the processor is a first architecture, obtaining the instruction latency of a memory access instruction in a processor of the first architecture comprises: When the architecture type of the processor is a first architecture, obtaining an instruction delay of an access instruction in the processor of the first architecture; Based on the data source of the access instruction, the instruction delay of the memory access instruction in the first architecture processor is obtained by screening from the instruction delay of the access instruction in the first architecture processor.

5. The method according to claim 1, wherein for any architecture processor, based on the memory access delay of the processor, calling a preset delay processing task comprises: For any architecture processor, based on the processor's memory access latency, call the visualization monitoring task.

6. The method according to claim 1, wherein for any architecture processor, based on the memory access delay of the processor, calling a preset delay processing task comprises: For any architecture processor, when the memory access latency of the processor exceeds a preset threshold, an alarm management task is called.

7. The method according to claim 1, wherein obtaining the instruction latency of the memory access instruction in the processor of the first architecture comprises: According to a preset cycle, an instruction delay of a memory access instruction in a processor of the first architecture is obtained.

8. The method according to any one of claims 1 to 7, wherein the first architecture is an ARM architecture, and a statistical analysis extension device is deployed on the ARM architecture processor; The step of obtaining the instruction delay of a memory access instruction in a processor of the first architecture when the architecture type of the processor is the first architecture includes: When the architecture type of the processor is ARM architecture, the instruction delay of the memory access instruction in the ARM architecture processor collected by the statistical analysis extension device is obtained.

9. According to the method of claim 8, the instruction delay of the memory access instruction in the ARM architecture processor is collected by the statistical analysis extension device based on the instruction type and the cache miss result. 10 . The method according to claim 9 , wherein the cache miss result is determined according to the first-level cache miss result and the total delay.

11. According to the method of claim 8, the instruction delay of the memory access instruction in the ARM architecture processor is collected by the statistical analysis extension device from any processor core in the ARM architecture processor.

12. The method according to claim 8, wherein the instruction delay of the memory access instruction in the ARM architecture processor is collected by the statistical analysis extension device according to a preset time window.

13. The method according to any one of claims 1 to 7, wherein the second architecture is an x86 architecture, and a performance monitoring unit device is deployed on the x86 architecture processor; The step of obtaining the memory access latency of the processor of the second architecture when the architecture type of the processor is the second architecture further includes: When the architecture type of the processor is an x86 architecture, a memory access delay of the x86 architecture processor collected by the performance monitoring unit device is obtained.

14. A monitoring system, the monitoring system is used to monitor and process the delay of a multi-architecture processor, the monitoring system includes a collection component and a data processing platform; The acquisition component is used to obtain the instruction delay of the memory access instruction in the processor of the first architecture when the architecture type of the processor is the first architecture, and determine the memory access delay of the processor of the first architecture based on the total delay, the emission delay and the address translation delay in the instruction delay, and obtain the memory access delay of the processor of the second architecture when the architecture type of the processor is the second architecture, wherein, The second architecture is an architecture other than the first architecture in the multiple architectures; The data processing platform is used to call a preset delay processing task based on the memory access delay of the processor for any architecture processor.

15. The system according to claim 14, wherein the monitoring system further comprises a logging platform; The collection component is further used to upload the memory access delay of the first architecture processor and the memory access delay of the second architecture processor to the log platform; The data processing platform is further used to obtain the memory access delay of the first architecture processor and the memory access delay of the second architecture processor from the log platform.

16. A computing device comprising: Memory and processor; The memory is used to store computer programs / instructions, and the processor is used to execute the computer programs / instructions. When the computer program / instructions are executed by the processor, the steps of the method described in any one of claims 1 to 13 are implemented.

17. A computer-readable storage medium storing a computer program / instruction, wherein the computer program / instruction, when executed by a processor, implements the steps of the method according to any one of claims 1 to 13.

18. A computer program product, comprising a computer program / instruction, which, when executed by a processor, implements the steps of the method according to any one of claims 1 to 13.

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