Server mainboard, server, bandwidth acquisition method, product, equipment and medium

Abstract

The invention discloses a server mainboard, a server, a bandwidth acquisition method, a product, equipment and a medium, and relates to the technical field of server interface control, the server mainboard comprises a bandwidth allocation identification component arranged for a bus equipment slot, the bandwidth allocation identification component can identify the bandwidth allocation condition of the corresponding bus equipment slot, and the bandwidth allocation condition of the corresponding bus equipment slot is determined by the bandwidth allocation identification component. The bandwidth resources are automatically identified and allocated on the basis of the bandwidth allocation identification component without occupying any resource of GPIO (General Purpose Input / Output), so that the technical problems that a GPIO identification circuit needs to be designed to make a bandwidth allocation table and the allocation efficiency is low are solved, and the purposes of not occupying GPIO resources, saving GPIO and improving the bandwidth allocation efficiency are achieved. And the distribution efficiency is improved.

Description

Technical Field

[0001] The present application relates to the technical field of server interface control, and in particular to a server mainboard, a server, a bandwidth acquisition method, a product, a device and a medium. Background Art

[0002] In the server field, with the rapid development of hardware technology, the data transmission speed and bandwidth requirements between CPU (Central Processing Unit) and PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) devices continue to rise.

[0003] The PICe interface on the server motherboard generally uses PCIe x8 slots and PCIe x16 slots, which is convenient for plugging in different types of expansion cards later. Even if the gold finger on the expansion card is x2 or x4, it can also be plugged into the PCIe x8 slot or PCIex16 slot. In the related art, the method used by PCIe to automatically identify and allocate bandwidth can be based on the GPIO (General Purpose Input Output) chip to dynamically configure the bandwidth, but it needs to occupy GPIO resources and needs to add a bandwidth allocation table in the detection of non-matching procedures, and the bandwidth allocation efficiency is low. Summary of the invention

[0004] The present application provides a server motherboard, a server, a bandwidth acquisition method, a product, a device and a medium, so as to at least solve the problem in the related art that a GPIO identification circuit needs to be designed to make a bandwidth allocation table, and the allocation efficiency is low.

[0005] The present application provides a server mainboard, comprising: a bus device slot configured on the server mainboard; The server motherboard also includes a bandwidth allocation identification component set for the bus device slot, and the bandwidth allocation identification component is connected to the processor; the bandwidth allocation identification component is configured to identify the bandwidth allocation status of the bus device slot and provide query for the processor.

[0006] The present application also provides a server, comprising: any one of the above-mentioned server mainboards.

[0007] The present application also provides a bandwidth acquisition method, which is implemented based on any of the above-mentioned server motherboards; the method includes: Performing polling addressing on the bandwidth allocation identification component configured in the bus device slot; Based on the bandwidth allocation identification component response, the bandwidth allocation status of the corresponding bus device slot is obtained.

[0008] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned bandwidth acquisition methods when executing the computer program.

[0009] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned bandwidth acquisition methods are implemented.

[0010] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned bandwidth acquisition methods when executed by a processor.

[0011] Through the present application, since a bandwidth allocation identification component is set for a bus device slot, the bandwidth allocation identification component can identify the bandwidth allocation status of the corresponding bus device slot and can be queried by the processor, thereby realizing automatic identification and allocation of bandwidth resources based on the bandwidth allocation identification component, without occupying any GPIO resources, solving the technical problem of needing to design a GPIO identification circuit to make a bandwidth allocation table and low allocation efficiency, and achieving the technical effect of not occupying GPIO resources, saving the use of GPIO, and improving allocation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0013] Figure 1 A schematic diagram of the structure of a server motherboard provided in an embodiment of the present application; Figure 2 A schematic diagram of the structure of a programmable device provided in an embodiment of the present application; Figure 3 A schematic diagram of an addressing process of a programmable device provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a server provided in an embodiment of the present application; Figure 5 A schematic diagram of a flow chart of a bandwidth acquisition method provided in an embodiment of the present application; Figure 6 A flowchart of another bandwidth acquisition method provided in an embodiment of the present application; Figure 7 A schematic diagram of the structure of a bandwidth acquisition device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0015] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0016] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0017] In conjunction with the specific application environment architecture or the specific hardware architecture on which the execution of the bandwidth acquisition method depends, the specific application environment architecture or the specific hardware architecture is described herein.

[0018] The bandwidth acquisition method provided in the embodiment of the present application is essentially a bandwidth automatic addressing acquisition method for a server CPU bus device slot (e.g., a PCIe slot) based on a bandwidth allocation identification component (e.g., a programmable device, specifically, an FPGA (Field Programmable Gate Array)), wherein a bandwidth allocation identification component (e.g., a programmable device, specifically, an FPGA chip) is set for each bus device slot (including a standard PCIe slot on a server mainboard, and also including a standard PCIe slot on an adapter card connected to the server mainboard), and the bandwidth allocation identification component can identify the bandwidth allocation status of the corresponding bus device slot and can be queried by the processor, thereby the processor can realize automatic identification and allocation of bandwidth resources based on the bandwidth allocation identification component, wherein no GPIO resources need to be occupied, thereby saving the use of GPIO and improving the bandwidth allocation efficiency.

[0019] The following first explains the technical contents related to FPGA and PCIe.

[0020] FPGA is a chip that can re-edit its internal structure to achieve the purpose of use. FPGA emerged as a semi-custom circuit in the field of application-specific integrated circuits. It not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of gate circuits of the original programmable devices. FPGA has higher integration, stronger logic functions and greater flexibility.

[0021] FPGA is widely used in many fields, such as communications, electronics, video signal processing, aerospace, etc., and has launched many powerful products with the advantages of low cost, low power consumption and high performance.

[0022] In recent years, with the rise of 5G, autonomous driving, AI and big data technologies, FPGA has ushered in new development opportunities.

[0023] FPGA has advantages in processing efficiency and flexibility in the field of AI. In the future, it will usher in new growth with the development of A1 technology. It includes many categories, such as robots, speech recognition, image recognition, natural language processing and expert systems. The market potential of FPGA cannot be underestimated.

[0024] At the same time, how to improve the programmability of FPGA has always been the focus of industry research. Programmability here refers to both the flexibility of hardware and the ease of use at the software level. Therefore, the architecture of FPGA is also constantly being renovated and upgraded.

[0025] The technical solution provided by the embodiments of the present application is based on the application design of FPGA, so that the FPGA chip can identify the bandwidth allocation status of the bus device slot (such as the PCIe slot), thereby facilitating the processor to automatically address and obtain and allocate bandwidth, thereby reducing the occupancy of GPIO and improving the efficiency of bandwidth allocation.

[0026] PCIe has made fundamental changes in bus structure, which are mainly reflected in two aspects: first, it changes from parallel bus to serial bus; second, it adopts point-to-point interconnection. The bus connecting the devices under the bridge in the original parallel bus structure is changed into a link. A link can contain one or more channels. Each channel consists of two pairs of differential signal lines to form a dual-simplex serial transmission channel. There are no dedicated data, address, control and clock lines. Various transactions on the bus are organized into information packets for transmission. Another feature of PCIe that breaks through the traditional bus is the point-to-point interconnection method. Each device is connected by an independent link and has exclusive bandwidth. This is an effective solution to improve the transmission rate.

[0027] The PCIe bus structure treats a link as a bus, thus maintaining compatibility with the traditional PCI bus in terms of address space, configuration mechanism and software. One PCIe device occupies one bus (link), so there are many bridges and buses in a PCIe-based computer. Traditional PCI devices can also run on the PCIe platform. Through the PCIe to PCI (or PCI-X) bridge, the PCI (or PCI-X) bus can be brought out, and traditional PCI devices can be integrated into the PCI Express structure by hanging on such a bus. In related technologies, the CPU and motherboard can increase support for PCIe4.0; or, PCIe 5.0 can be provided and fully backward compatible with 4.0 and 3.0 devices; or, up to 16 CPU PCIe 5.0 channels and up to 4 CPU PCIe 4 channels can be provided; or, up to 20 CPU PCIe 4.0 channels can be provided.

[0028] PCIe (Peripheral Component Interconnect Express) is a high-speed serial computer expansion card standard, mainly used to connect the CPU and various expansion cards, such as graphics cards, sound cards, and network adapters. The bandwidth of PCIe is closely related to its version and the number of lanes.

[0029] Here are the details of the different versions of PCIe and their bandwidth: PCIe 1.0: The online bit transfer rate is 2.5Gb / s, using 8 / 10 encoding, so the bandwidth of PCIe 1.0x1 is 250MB / s.

[0030] PCIe 2.0: The online bit transfer rate is doubled to 5Gb / s, using 8 / 10 encoding, so the bandwidth of PCIe 2.0x 1 is 500MB / s.

[0031] PCIe 3.0: The online bit transfer rate is 8Gb / s, using 128 / 130 encoding, so the bandwidth of PCIe 3.0x 1 is 1GB / s.

[0032] PCIe 4.0: The online bit transfer rate is increased to 16GT / s.

[0033] PCIe 5.0: The online bit transfer rate can reach up to 32GT / s.

[0034] In addition, the bandwidth of PCIe is also related to the number of its lanes. For example, the theoretical maximum bandwidth of the PCIe x1 slot is 1GB / s, which is suitable for devices with low data transmission requirements; the theoretical maximum bandwidth of the PCIe x4 slot is 4GB / s, which is suitable for devices with medium bandwidth requirements; the theoretical maximum bandwidth of the PCIe x8 slot is 8GB / s, which is suitable for devices with higher data transmission speed requirements; the PCIe x16 slot has the highest theoretical maximum bandwidth of 16GB / s, which is widely used to connect high-performance graphics cards.

[0035] The PICe interface on the server motherboard generally uses PCIe x8 slots and PCIe x16 slots to facilitate the later insertion of different types of expansion cards. Even if the gold finger on the expansion card is x2 or x4, it can also be plugged into the PCIe x8 slot or PCIex16 slot. However, in the related art, the bandwidth directly provided by the CPU to the PCIe x8 slot and PCIe x16 slot is the maximum bandwidth, resulting in the inability to effectively identify the expansion card with a small number of channels (Lane) when inserted. The CPU also allocates the maximum bandwidth, resulting in a waste of PCIe resources and a loss of CPU function. For example, two PCIE X8 devices are inserted into two PCIE X16 slots, but it is impossible to support two X8 devices in one X16 slot; PCIe cannot automatically identify and allocate bandwidth.

[0036] In response to this, the related art proposes a method for PCIe to automatically identify and allocate bandwidth. There are two specific methods that can be used: one is to use the PCA9555 GPIO expansion chip instead of GPIO to dynamically configure the bandwidth; the other is to use the resistance control current or voltage detection method on the physical detection circuit board to determine the required bandwidth. However, both of the above methods require the addition of a bandwidth allocation table in the detection non-matching program, expansion chip detection or physical resistance detection. After obtaining the change data, it is necessary to match the numerical value with the corresponding number of channels (Lane) with the bandwidth allocation table set in advance, and then the CPU analyzes the corresponding bandwidth for allocation. In the early stage, it is necessary to count the data of different expansion cards to simulate the table building. The types and models of corresponding expansion cards are fixed. After the expansion card data that is not in the table is plugged in, there is an identification error. The table needs to be matched when used, and the overall identification and allocation of bandwidth is inefficient. In addition, the bandwidth can also be allocated by the high and low pin levels on the PCIe device side, but there is also the situation that the allocation is not detailed and accurate.

[0037] At the same time, due to the large number of server models and many customer customization requirements, the diversity of server CPU PCIe port connection forms is very complex. The connections between CPU PCIe ports and devices and riser cards (Riser cards) on different motherboards are not the same. The PCIe port allocation inside the riser card itself is also diverse. Each model and each customized shipping configuration BIOS (Basic Input Output System) needs to be developed and adapted separately according to the motherboard PCIe port topology and the PCIe port topology of several riser cards matched with the motherboard. As a result, the development of server firmware for a specific configuration is very cumbersome and affects the efficiency of customized development and mass production of server products.

[0038] In response to at least one of the above technical problems, an embodiment of the present application provides a server CPU PCIe slot bandwidth automatic addressing acquisition solution based on FPGA chip application design, wherein the FPGA chip sets the pin level for the PCIe slot bandwidth to be used as a bandwidth allocation identification component that can identify the slot bandwidth allocation situation. The bandwidth allocation identification component can identify the bandwidth allocation situation of the bus device slot, and the bandwidth allocation identification component is connected to the processor, which can be used by the processor to obtain the bandwidth allocation situation based on automatic addressing, and then perform bandwidth allocation. There is no need for GPIO participation, no GPIO resources are occupied, no table lookup comparison is required, and the bandwidth allocation efficiency is improved.

[0039] In some embodiments, the bus device slot can be a standard PCIe slot configured in the server, specifically a standard PCIe slot on the server motherboard, or a standard PCIe slot on a riser card connected to the server motherboard, so as to adapt to various PCIe port topologies, simplify the server firmware development process, facilitate server product customization, and improve mass production efficiency.

[0040] For example, Figure 1 A schematic diagram of the structure of a server motherboard provided in an embodiment of the present application. Figure 1 The server motherboard 10 may include: a bus device slot 11 configured for the server motherboard 10; the server motherboard 10 also includes a bandwidth allocation identification component 12 set for the bus device slot 11, and the bandwidth allocation identification component 12 is connected to the processor 100; the bandwidth allocation identification component 12 is configured to identify the bandwidth allocation status of the bus device slot 11 and provide it for query by the processor 100.

[0041] The bus device slot 11 configured on the server mainboard 10 is used to connect the bus device and the processor 100. Exemplarily, the bus device slot may be a standard PCIe slot of a server, which may be a standard PCIe slot on a server mainboard or a standard PCIe slot on an adapter card, and the bus device may include expansion cards such as a graphics card, a network card, and a sound card, which are not limited here.

[0042] Among them, the bandwidth allocation identification component 12 configured for the bus device slot 11 can identify the bandwidth allocation of the bus device slot 11 and provide the processor 100 with addressing and querying, so that the processor 100 can automatically obtain the bandwidth allocation of the corresponding bus device slot 11 by polling and addressing the bandwidth allocation identification component 12, and then perform bandwidth allocation. Exemplarily, the bandwidth allocation identification component 12 can be implemented based on hardware design, which will be described in detail later.

[0043] Exemplarily, from the perspective of spatial layout, the bandwidth allocation identification component 12 can be placed next to the bus device slot 11; or, the bandwidth allocation identification component 12 can be placed in other free space on the server motherboard 10 or the adapter card, which is not limited here.

[0044] In the embodiment of the present application, the bandwidth allocation identification component 12 is set for the bus device slot 11, and can be set one-to-one with the bus device slot 11. Exemplarily, the number of the bus device slots 11 is equal to the number of the bandwidth allocation identification components 12, and each bandwidth allocation identification component 12 is configured to represent the bandwidth allocation of a corresponding bus device slot 11.

[0045] It should be noted that Figure 1 It is only exemplarily shown that the number of bus device slots 11 is 3, and the number of corresponding bandwidth allocation identification components 12 is 3, and the bandwidth allocation identification components 12 correspond to the bus device slots 11 one by one, but it does not constitute a limitation on the server motherboard 10 provided in the embodiment of the present application. In other implementations, the number of bus device slots 11 configured on the server motherboard 10 can also be 1, 2, 4 or other numbers, and the number of bandwidth allocation identification components 12 corresponds to 1, 2, 4 or other numbers, which is not limited here.

[0046] In the server motherboard 10 provided in the embodiment of the present application, a bandwidth allocation identification component 12 is set for the bus device slot 11. The bandwidth allocation identification component 12 can identify the bandwidth allocation status of the corresponding bus device slot 11 and can be queried by the processor 100, thereby realizing automatic identification and allocation of bandwidth resources based on the bandwidth allocation identification component 12, without occupying any GPIO resources, saving the use of GPIO, and without the need for table lookup matching, thereby improving the bandwidth allocation efficiency.

[0047] In some embodiments, the bandwidth allocation identification component 12 includes a programmable device; the programmable device identifies the bandwidth allocation status of the corresponding bus device slot 11 based on high and low level settings.

[0048] Among them, the internal structure of the programmable device can be re-edited to flexibly adapt to different bus device slots 11 and identify the bandwidth allocation of the corresponding bus device slots 11. Specifically, for bus device slots 11 with different bandwidth allocations, based on the internal structure editing of the programmable device, such as high and low level settings, different bandwidth allocations can be flexibly identified. When the high and low level settings are different, the identified bandwidth allocations are different.

[0049] In the server motherboard provided by the embodiment of the present application, by setting a bandwidth allocation identification component 12 for the bus device slot 11, the bandwidth allocation identification component 12 can identify the bandwidth allocation status of the corresponding bus device slot 11 and can be queried by the processor 100, thereby realizing automatic identification and allocation of bandwidth resources based on the bandwidth allocation identification component 12, wherein no GPIO resources need to be occupied, saving the use of GPIO, and no table lookup matching is required, thereby improving the bandwidth allocation efficiency; at the same time, by setting the broadband allocation identification component 12 as a programmable device, based on setting the high and low levels of different pins of the programmable device, the bandwidth allocation status of the bus device slot 11 is identified, the implementation method is simple and flexible, easy to adapt to a variety of different bus port topologies, improve the accuracy and efficiency of bandwidth allocation, and simplify the server firmware development process, facilitate the customized development of server products, and improve mass production efficiency.

[0050] Exemplarily, the programmable device may include an FPGA chip. In the embodiment of the present application, an FPGA chip is placed next to each standard PCIe slot of the server (which may be a standard PCIe slot on the motherboard or a standard PCIe slot on the riser card), and the FPGA chip pins are set to high and low levels based on the bandwidth allocation of the standard PCIe slot, so as to identify the bandwidth allocation of the standard PCIe slot based on the FPGA chip, so as to facilitate the processor to poll and address the FPGA chips configured in all standard PCIe slots, so as to automatically obtain the bandwidth allocation of each standard PCIe slot, and perform bandwidth allocation, so as to achieve efficient and accurate automatic bandwidth allocation.

[0051] In some embodiments, continue to refer to Figure 1 The bandwidth allocation identification component 12, such as a programmable device, is connected to the processor 100 based on a system management bus (SMBUS IIC bus).

[0052] Among them, the system management bus is a two-wire, synchronous, serial bus that can be used to connect various monitoring chips on the server motherboard 10, such as the programmable device used as the bandwidth allocation identification component 12 in the embodiment of the present application, such as a FPGA chip.

[0053] Exemplarily, an FPGA chip is placed next to each standard PCIe slot of the server (which can be a standard PCIe slot on the server motherboard or a standard PCIe slot on an adapter card). The FPGA chip is connected to the processor 100 through the system management bus so that the processor 100 can monitor the bandwidth allocation of the PCIe slot, realize automatic addressing and acquisition of the bandwidth allocation, and then realize bandwidth allocation.

[0054] In some embodiments, the programmable device at least includes a signal interface, and the signal interface is configured to connect to a system management bus so that the programmable device can communicate with the processor based on the signal interface.

[0055] The number of signal interfaces included in the programmable device is set based on the wiring harness of the system management bus. When the system management bus is a two-wire bus, the number of signal interfaces of the programmable device is correspondingly two, so as to connect to the system management bus and realize communication.

[0056] Specifically, the system management bus may include a clock signal line and a data signal line, and correspondingly, the signal interface of the programmable device may include a clock signal interface and a data signal interface.

[0057] In some embodiments, Figure 2 This is a schematic diagram of the structure of a programmable device provided in an embodiment of the present application, wherein the programmable device is an FPGA chip U1 as an example to illustrate the structure of the programmable device. Figure 2 In the FPGA chip U1 used as a programmable device, the signal interface includes a clock signal interface SCK and a data signal interface SDA; the clock signal interface SCK is configured to connect to the clock signal line SMBUS_SCK of the system management bus, synchronize the clock signal, and facilitate synchronous data transmission; the data signal interface SDA is configured to connect to the data signal line SMBUS_SDA of the system management bus, and transmit the data signal; the data signal is the actual data of the bandwidth allocation of the associated bus device slot 11, which will be described in detail later.

[0058] Among them, the signal interface of the FPGA chip U1 can be connected to the GPIO interface of the processor through the IIC bus of the clock signal line SMBUS_SCK and the IIC bus of the data signal line SMBUS_SDA.

[0059] Therefore, by setting the signal interface of the programmable device including a clock signal interface and a data signal interface, the clock signal line of the system management bus is connected based on the clock signal interface, and the data signal line of the system management bus is connected based on the data signal interface, clock signal synchronization and data signal transmission are realized, thereby realizing communication between the programmable device and the processor based on the system management bus, facilitating the processor to query the programmable device to obtain the bandwidth allocation of the bus device slot 11 associated with the data signal, thereby realizing automatic query and acquisition of bandwidth, and then realizing bandwidth allocation. In other implementations, when the processor and the programmable device communicate based on other types of buses, the programmable device can also be set with a corresponding communication interface to realize connection with the processor based on the bus, which is not limited here.

[0060] In some embodiments, continue to refer to Figure 2 Taking the FPGA chip U1 as a programmable device as an example, the programmable device may also include a signal acquisition interface, which is configured to identify a signal output port, ie, a sub-port, corresponding to the bus device slot 11 based on high and low level settings.

[0061] For example, Figure 2 The signal acquisition interface is shown as SubGH, SubEF, SubCD and SubAB, which correspond to pin 12, pin 11, pin 10 and pin 9 of FPGA chip U1 respectively. Based on pulling up or pulling down pins 12, pin 11, pin 10 and pin 9, or connecting power or grounding, the high and low level settings of the corresponding signal acquisition interface can be realized. Specifically, when the pin is pulled up or connected to the power supply, the level of the corresponding signal acquisition interface is a high level; when the pin is pulled down or grounded, the level of the corresponding signal acquisition interface is a low level, thereby realizing the high and low level settings of different signal acquisition interfaces. Among them, when the signal output ports of the bus device slot 11 are different, the high and low level settings of the signal acquisition interface are different, thereby realizing the identification of the signal output port of the bus device slot 11.

[0062] In the server motherboard provided by the embodiment of the present application, based on the high and low level settings of the signal acquisition interface of the programmable device, it is possible to identify different signal output ports of the bus device slot 11, and the firmware setting method is simple, flexible and versatile.

[0063] In some embodiments, the number of the signal acquisition interface is at least one; different signal acquisition interfaces are configured to identify different signal output ports.

[0064] Specifically, the number of signal acquisition interfaces in the programmable device can be set based on the number of signal output ports of the bus device slot 11. For example, the number of signal acquisition interfaces in the programmable device is equal to the number of signal output ports of the bus device slot 11, and they are set in a one-to-one matching manner. Based on this, when the signal acquisition interface in the programmable device is set to a high level, the corresponding signal output port of the bus device slot 11 is used; when the signal acquisition interface in the programmable device is set to a low level, the corresponding signal output port of the bus device slot 11 is not used, thereby flexibly identifying different signal output ports of the bus device slot 11 based on the high and low level settings of the signal acquisition interface in the programmable device.

[0065] Understandably, Figure 2 The number of signal acquisition interfaces is shown as 4, namely SubGH, SubEF, SubCD and SubAB, but it does not constitute a limitation on the server motherboard provided in the embodiment of the present application. In other embodiments, the number of signal acquisition interfaces can also be 1, 2, 3, 5 or other numbers, which can be set based on the number of signal output ports of the bus device slot, which is not limited here.

[0066] In some embodiments, continue to refer to Figure 2 Taking the FPGA chip U1 used as a programmable device as an example, the programmable device also includes a first type of identification pin and a second type of identification pin; the first type of identification pin is configured to identify the processor associated with the corresponding bus device slot 11; the second type of identification pin is configured to identify the processor port associated with the corresponding bus device slot 11.

[0067] For example, Figure 2 The first type of identification pins are shown as CPU0, CPU1, CPU2 and CPU3, which correspond to pin 1, pin 2, pin 3 and pin 4 of the FPGA chip U1 respectively; the second type of identification pins are shown as PE0, PE1, PE2 and PE3, which correspond to pin 5, pin 6, pin 7 and pin 8 of the FPGA chip U1 respectively.

[0068] The first type of identification pin can identify the processor associated with the bus device slot 11, and CPU0, CPU1, CPU2 and CPU3 correspond to different processors. The second type of identification pin can identify the processor port associated with the bus device slot 11, and PE0, PE1, PE2 and PE3 correspond to different processor ports. Figure 2As shown, by connecting the first type identification pin or the second type identification pin to the power supply VCC, the corresponding pin can be set to a high level; by connecting the first type identification pin or the second type identification pin to the ground GND, the corresponding pin can be set to a low level. When the associated processors are different, the high and low level settings of the corresponding first type identification pins are different; when the processor ports are different, the high and low level settings of the corresponding second type identification pins are different. Therefore, by setting the high and low levels of the first type identification pins and the second type identification pins, the associated processors and processor ports can be flexibly identified, and the firmware setting method is simple, flexible, and versatile.

[0069] In some embodiments, the number of first-class identification pins is at least one; different first-class identification pins are configured to identify different processors; and / or, the number of second-class identification pins is at least one; different second-class identification pins are configured to identify different processor ports.

[0070] Specifically, the number of first-class identification pins in a programmable device can be set based on the number of associated processors. For example, the number of first-class identification pins in a programmable device can be equal to the number of associated processors, and the first-class identification pins and the associated processors are set in a one-to-one matching manner. Based on this, the first-class identification pin can be set to a high level to identify the corresponding associated processor.

[0071] Similarly, the number of second-class identification pins in a programmable device can be set based on the number of processor ports. For example, the number of second-class identification pins in a programmable device can be equal to the number of processor ports, and the second-class identification pins and processor ports are set in a one-to-one correspondence. Based on this, the second-class identification pin can be set to a high level to identify the corresponding processor port.

[0072] Understandably, Figure 2 It is only exemplarily shown that the number of the first-class identification pins and the number of the second-class identification pins are both 4, but it does not constitute a limitation on the server motherboard provided in the embodiment of the present application. In other embodiments, the number of the first-class identification pins can also be 1, 2, 3, 5 or other numbers, which can be set based on the number of associated processors; the number of the second-class identification pins can also be 1, 2, 3, 5 or other numbers, which can be set based on the number of processor ports; the number of the first-class identification pins and the number of the second-class identification pins can be equal or different, which is not limited here.

[0073] In some embodiments, the bus device slot 11 at least includes the bus device slot 11 on the server mainboard 10 ; and the bandwidth allocation identification component 12 is at least disposed on the server mainboard 10 .

[0074] Specifically, the bandwidth allocation identification component 12 and the corresponding bus device slot 11 are both located on the same server mainboard 10, so as to facilitate corresponding matching settings.

[0075] In some embodiments, the bus device slot 11 also includes a bus device slot 11 on an adapter card connected to the server mainboard 10; the bandwidth allocation identification component 12 is also disposed on the adapter card.

[0076] Among them, the riser card is a server expansion card, which is mainly used to provide additional expansion slots in the limited space of the server chassis to install more hardware devices, such as network adapters, hard disk controllers, etc. The riser card can be installed on the bus device slot of the server motherboard, such as the standard PCIe slot, to transfer the expansion slot on the server motherboard to a position more suitable for the server chassis, thereby making full use of the internal space of the server and enhancing the scalability and flexibility of the server.

[0077] In the embodiment of the present application, by setting a bandwidth allocation identification component 12 for the bus device slot 11, the bandwidth allocation identification component 12 can identify the bandwidth allocation of the corresponding bus device slot 11 and can be queried by the processor 100, thereby realizing automatic identification and allocation of bandwidth resources based on the bandwidth allocation identification component 12, wherein no GPIO resources need to be occupied, saving the use of GPIO, and no table lookup matching is required, thereby improving the bandwidth allocation efficiency; at the same time, by setting the broadband allocation identification component 12 as a programmable device, based on setting the high and low levels of different pins of the programmable device, the bandwidth allocation of the bus device slot 11 is identified, the implementation method is simple and flexible, easy to adapt to a variety of different bus port topologies, improve the accuracy and efficiency of bandwidth allocation, and simplify the server firmware development process, facilitate the customized development of server products, and improve mass production efficiency; at the same time, for the bus device slot on the adapter card connected to the server motherboard, the configured bandwidth allocation identification component 12 is also set on the corresponding adapter card, so that the bandwidth allocation identification component 12 and the corresponding bus device slot 11 are both located on the same adapter card, which is convenient for corresponding matching settings.

[0078] In some embodiments, the bandwidth allocation identification component 12 is implemented based on an FPGA chip. When designing a bus device slot of a server mainboard, the FPGA chip is set in the hardware circuit of the server mainboard or the adapter card connected thereto, and the signal acquisition interface in the FPGA chip and the levels of the first type identification pin and the second type identification pin are set according to the sub-port of the PCIe port of the processor to which the slot belongs, so as to identify the bandwidth allocation of the bus device slot.

[0079] The FPGA chip can transmit address bytes to the processor via the system management bus.

[0080] Exemplarily, the meaning of the addressing bytes is shown in Table 1 and Table 2 below.

[0081] Table 1 FPGA chip addressing byte address table

[0082] In Table 1, address offset represents an offset, which is a relative address value used to indicate the position offset relative to a base address. The data / addressing byte corresponding to the address offset is byte0.

[0083] Table 2 Meaning of addressing bytes

[0084] Table 2 explains the meanings of different bits in the addressing byte. In the addressing byte byte0, bits 0 to 1 are used to identify the subport, including subport AB, subport CD, subport EF and subport GH; bits 2 to 3 are used to identify the processor port, including 4 ports, namely PE0, PE1, PE2 and PE3; bits 4 to 5 are used to identify the associated processor, including 4 processors, namely CPU0, CPU1, CPU2 and CPU3.

[0085] Among them, the FPGA chip defines the actual meaning of the high and low level signals input to each pin based on the signal acquisition interface, the first type of representation pins and the second type of identification pins, as shown in Table 3 below.

[0086] Table 3 The actual meaning of each pin input high and low level signal defined by the FPGA chip pin

[0087] Table 3 shows the communication protocol between the FPGA chip configured with the internally defined PCIe slot and the root node (RootPort) of the BIOS, which defines the information represented by the bytes of the root node transmitted to the BIOS when the PCIe slot is powered on. This information includes: which subport of which port (i.e., PE port) of which processor the PCIe slot is connected to.

[0088] Through the above Table 3 and the following Table 4, addressing is performed to query whether the addressed FPGA chip will return the confirmation character ack, and based on the slot address (i.e., subport address) of the returned confirmation character ack, the bandwidth form of each PCIe slot root node allocated by the processor can be obtained according to the following Table 5, that is, automatic addressing to obtain the bandwidth allocation situation.

[0089] Table 4 FPGA chip addressing byte definition table

[0090] Table 4 shows the encoding meaning of the addressing byte. Among them, the addressing byte byte0 can be an 8-bit binary code, and the bit in the table represents the bit, a total of 0 to 7 bits; illustratively, bit 7 to 6 represents the 6th to 7th bit in the 8-bit binary code, and the others are similar and will not be repeated. Among them, bits 6 to 7 can be reserved, bits 4 to 5 are determined by the input level of the first type of identification pin, used to identify which processor it belongs to, that is, one of CPU0 to CPU3; bits 2 to 3 are determined by the input level of the second type of identification pin, used to identify which processor port it belongs to, that is, one of PE0 to PE3; bits 0 to 1 are determined by the input level of the signal acquisition interface, indicating which subport of the PE port it belongs to, that is, one of AB, CD, EF, and GH.

[0091] Table 5 Corresponding table of the bandwidth form allocated by the processor to each PCIe root node

[0092] In some embodiments, the FPGA chip can read the values ​​of the first-category identification pins CPU0~CPU3, the second-category identification pins PE0~PE3, and the signal acquisition interface (i.e., sub-port) SubAB, SubCD, SubEF, and SubGH pins, and write them into internal registers; the FPGA chip receives a query from the system management bus of the processor (BIOS configured by the processor), and determines whether the queried address is the same as the address of the FPGA chip. If they are the same, it responds to the addressing byte byte0 of the root node of the BIOS through the system management bus. If they are not the same, it returns to the previous step to continue comparing the addresses.

[0093] refer to Figure 3 , which shows an addressing process of a programmable device, which may specifically include the following steps: S30, start.

[0094] S31. Read the value of the characteristic pin and write it into the internal register.

[0095] The characteristic pins may include the first type identification pins CPU0~CPU3, the second type identification pins PE0~PE3 and the signal acquisition interface (i.e. sub-port) SubAB, SubCD, SubEF and SubGH pins. Based on the value of the characteristic pins, the bandwidth allocation of the device bus slot is identified.

[0096] In this step, the FPGA chip writes the generated addressing byte byte0 into the internal register based on the value of its own characteristic pin.

[0097] S32. Receive a query from the system management bus of the processor.

[0098] In this step, the FPGA chip receives a query from the system management bus of the processor (based on the BIOS computer program configured by the processor, the processor performs the query action).

[0099] S33. Based on the fact that the queried address is the same as the address of the current FPGA, respond to the processor with an addressing byte through the system management bus.

[0100] This step may include: the FPGA chip determines whether the queried address is the same as the address of the current FPGA chip. If they are the same, it responds to the addressing byte byte0 to the root node of the BIOS through the system management bus. If they are not the same, it returns to the previous step to continue comparing the addresses.

[0101] In an embodiment of the present application, based on the FPGA chip setting, the processor used by the current PCIe slot, the PE port used by the processor, and the sub-port under the PE port can be uniformly encoded into an 8-bit addressing byte address, which is the addressing byte address of the FPGA chip in the system management bus.

[0102] Based on this, when the server is turned on, the processor polls and addresses all PCIe slot FPGA chips based on the computer program configured by the BIOS, and traverses whether the sub-port addresses of all PCIe root nodes of all processors are in use to determine the bandwidth allocation of each PCIe port, and uses the bandwidth of each PCIe root node of each processor to allocate, thereby realizing automatic acquisition and allocation of bandwidth.

[0103] In some embodiments, the BIOS computer program may be stored in a ROM (Read-Only Memory), and when the server is powered on, the processor extracts and executes the BIOS computer program stored in the ROM to achieve automatic addressing based on the FPGA chip to obtain the usage of the PCIe slot, thereby achieving automatic acquisition and allocation of the PCIe slot bandwidth allocation.

[0104] An embodiment of the present application also provides a server, including any of the above-mentioned server mainboards, having corresponding beneficial effects.

[0105] For example, Figure 4 A schematic diagram of the structure of a server provided in an embodiment of the present application. Figure 4The server 20 may also include a processor 100 and an input / output system chip 200, the input / output system chip may be a BIOS (BIOS is a computer program stored in a ROM), the bandwidth allocation identification component 12 and the input / output system chip 200 are both connected to the processor 100; the processor 100 runs the computer program built into the input / output system chip 200 to obtain the bandwidth allocation status of the bus device slot 11 associated with the bandwidth allocation identification component 12, and allocate bandwidth.

[0106] Exemplarily, the processor 100 may be connected to other devices, including the bandwidth allocation identification component 12 and the input / output system chip 200, through a PCH (Platform Controller Hub) chip; or may be connected through other chips or structural components, which are not limited here.

[0107] Figure 4 In the figure, the bus device slot 11 can be a PCIe slot, the bandwidth allocation identification component 12 can be a PFGA chip, each PCIe slot is correspondingly provided with an FPGA chip, the PCIe device is plugged into the gold finger of the PCIe slot, the signal port of the FPGA chip is connected to the PCH chip through the system management bus to connect to the processor 100, and the FPGA chip is installed on the board where the PCIe slot is located.

[0108] In the server provided in the embodiment of the present application, the input and output system chip 200 may have a built-in computer program and be provided for the processor 100 to run when the server is turned on; the processor 100 runs the computer program to poll and address the bandwidth allocation identification component 12, obtain the bandwidth allocation status of the corresponding bus device slot 11 identified by the bandwidth allocation identification component 12, and then perform bandwidth allocation to achieve automatic identification and allocation of bandwidth resources, without occupying any GPIO resources, saving the use of GPIO and improving the efficiency of bandwidth allocation.

[0109] In some embodiments, the server may further include an adapter card connected to the server mainboard; the bus device slot is arranged on the server mainboard and the adapter card, and the bandwidth allocation identification component is correspondingly arranged on the server mainboard and the adapter card.

[0110] Specifically, the bus device slot at least includes a bus device slot on a server mainboard; and the bandwidth allocation identification component is at least arranged on the server mainboard.

[0111] Specifically, the bandwidth allocation identification component and the corresponding bus device slot are both located on the same server mainboard, which facilitates corresponding matching settings.

[0112] In addition, the bus device slot also includes a bus device slot on an adapter card connected to the server mainboard; and the bandwidth allocation identification component is also arranged on the adapter card.

[0113] Among them, for the bus device slot on the adapter card connected to the server motherboard, the configured bandwidth allocation identification component is also set on the corresponding adapter card, so that the bandwidth allocation identification component and the corresponding bus device slot are both located on the same adapter card, which is convenient for corresponding matching settings.

[0114] In some embodiments, the bandwidth allocation identification component is implemented based on an FPGA chip. When designing a bus device slot of a server mainboard, the FPGA chip is set in the hardware circuit of the server mainboard or the adapter card connected thereto, and the signal acquisition interface in the FPGA chip and the levels of the first type identification pin and the second type identification pin are set according to the sub-port of the PCIe port of the processor to which the slot belongs, so as to flexibly identify the bandwidth allocation of the bus device slot.

[0115] The embodiment of the present application further provides a bandwidth acquisition method, which can be implemented based on any of the above-mentioned server mainboards and has corresponding beneficial effects.

[0116] For example, Figure 5 A schematic diagram of a bandwidth acquisition method provided in an embodiment of the present application. Figure 5 , the bandwidth acquisition method may include: S51. Perform polling addressing on the bandwidth allocation identification component configured in the bus device slot.

[0117] There may be at least one bandwidth allocation identification component configured for a bus device slot in the server, and the bandwidth allocation conditions of all bus device slots in the server are obtained by polling and addressing the bandwidth allocation identification component.

[0118] S52: Based on the bandwidth allocation identification component response, obtain the bandwidth allocation status of the corresponding bus device slot.

[0119] The bandwidth allocation identification component sends the bandwidth allocation status of the corresponding bus device slot to the processor in response to the query of the processor, so that the processor obtains the bandwidth allocation status of the corresponding bus device slot.

[0120] In the bandwidth acquisition method provided in the embodiment of the present application, the processor can automatically obtain the bandwidth allocation status of the corresponding bus device slot based on polling addressing of the bandwidth allocation identification component configured for the bus device slot, thereby realizing automatic bandwidth acquisition and allocation, without occupying any GPIO resources, saving the use of GPIO and improving the bandwidth allocation efficiency.

[0121] In some embodiments, the step of "obtaining bandwidth allocation of corresponding bus device slots" may specifically include: Obtaining addressing information fed back by a bandwidth allocation identification component; Based on the addressing information, the associated identification information is parsed, the identification information including the target processor, the target processor port, and the target signal output port of the bus device slot; Based on the identification information, the bandwidth allocation of the corresponding bus device slot is determined.

[0122] The addressing information may include addressing byte byte0. For the relevant description of addressing byte byte0, please refer to the previous text and will not be repeated here. By parsing the addressing information, identification information can be obtained, that is, which processor is used by the current bus device slot, which port of the processor is used, and which sub-port under the port is used, and then the bandwidth allocation is determined in combination with Table 5 in the previous text.

[0123] In the embodiment of the present application, the processor can determine the bandwidth allocation of the bus device slot based on the acquisition and analysis of the addressing information, with high efficiency and accuracy.

[0124] In some embodiments, the bandwidth allocation identification component is connected to the processor based on a system management bus.

[0125] Based on this, polling and addressing the bandwidth allocation identification component configured in the bus device slot may specifically include: Scan bus data transmitted by the system management bus; The addressing byte responded by the bandwidth allocation identification component is received until the scanning is completed; wherein the addressing byte is associated with the bandwidth allocation status of the bus device slot.

[0126] In an embodiment of the present application, the bandwidth allocation identification component is scanned based on the system management bus, and the corresponding addressing byte is received when the bandwidth allocation identification component responds, thereby completing the polling addressing of the bandwidth allocation identification component, obtaining the bandwidth allocation status of all corresponding bus device slots, realizing efficient acquisition of slot bandwidth, and facilitating accurate bandwidth allocation.

[0127] In some embodiments, Figure 6 A flowchart of another bandwidth acquisition method provided in an embodiment of the present application. Figure 6 , the bandwidth acquisition method may include the following steps: S60, start.

[0128] Specifically, the process starts to be executed when the server is turned on.

[0129] S61. Scan system management bus data.

[0130] Specifically, the processor or the BIOS connected thereto scans bus data of the system management bus.

[0131] Exemplarily, the BIOS performs polling addressing on all PCIe slot FPGA chips. Within the addressing address range, the subport occupies 2 bits, the PE port occupies 2 bits, the processor bit number occupies 2 bits, and the total number of bits is 6 bits, and the corresponding number is 2 to the power of 6, that is, 0 to 63.

[0132] S62. The FPGA connected based on the system management bus responds and receives the addressing byte.

[0133] Specifically, the BIOS determines whether the system management bus device, that is, the FPGA connected to the system management bus responds; if the FPGA responds, the BIOS receives the addressing byte byte0 of the FPGA chip, that is, the BIOS reads the FPGA chip and obtains the addressing byte byte0; if the FPGA does not respond, it returns to the previous step to continue scanning the system management bus data.

[0134] S63. According to the addressing bytes, the processor, port and sub-port are parsed and bandwidth is allocated until the scan is completed.

[0135] Specifically, the BIOS parses the addressing byte byte 0. Based on the read addressing byte byte 0, the BIOS parses the processor to which the current bus device slot / slot belongs, the port of the processor, the sub-port number under the port, and allocates bandwidth.

[0136] Furthermore, the BIOS determines whether the scanning of the system management bus is completed; if the scanning is completed, the process ends, that is, S64 is executed; otherwise, the process returns to continue scanning the system management bus data.

[0137] Among them, BIOS records the address data returned by all slot FPGA chips, translates the address data to port bandwidth with reference to Table 5 above, and allocates bandwidth.

[0138] S64, end.

[0139] After the BIOS uses the acquired bandwidth of each processor and each slot root node for allocation, the bandwidth allocation is completed and the boot process continues.

[0140] In the bandwidth acquisition method provided in the embodiment of the present application, when the server is powered on, the BIOS can poll and address all PCIe slot FPGA chips. During the power-on process, the BIOS traverses the subport addresses of all PCIe root nodes of all processors to determine whether they are used, so as to determine the bandwidth allocation of each PCIe port. The BIOS uses the bandwidth of each PCIe root node of each processor to allocate and continue the power-on process.

[0141] The embodiment of the present application can realize the automatic allocation of server CPU PCIe bandwidth resources, without the need to design a GPIO identification circuit to make a bandwidth allocation table, and without occupying GPIO resources; it has strong versatility and is applicable to any server computer system. It performs bandwidth allocation based on BIOS, proposes a universal server PCIe bandwidth adaptive allocation mechanism, forms a unified specification for server system design, and can arbitrarily apply PCIe port resources, which is convenient for self-configuration; there is no need to use complex and cumbersome GPIO level identification to design a bandwidth allocation table, and there is no need to manually transmit motherboard bandwidth design changes, that is, there is no need to develop a customized BIOS version for PCIe bandwidth allocation for each motherboard design; there is no need to participate in any GPIO resources of the motherboard PCH, which saves the use of GPIO, and realizes that the bandwidth of each PCIe slot can be automatically identified and dynamically allocated by the BIOS through system management bus addressing detection when the server is turned on, thereby realizing the standardization of bandwidth allocation design, and the server motherboard and riser card (Riser card) using this technical solution can be assembled and configured at will without the need to re-adapt the BIOS to the slot bandwidth.

[0142] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0143] The embodiment of the present application also provides a bandwidth acquisition device, referring to Figure 7 The bandwidth acquisition device may include: a polling addressing module 71, configured to perform polling addressing on the bandwidth allocation identification component configured in the bus device slot; a bandwidth identification module 72, configured to obtain the bandwidth allocation status of the corresponding bus device slot based on the response of the bandwidth allocation identification component.

[0144] In some embodiments, in the bandwidth acquisition device, the bandwidth identification module 72 is configured to obtain the bandwidth allocation status of the corresponding bus device slot, which may specifically include the bandwidth identification module 72 being configured to: obtain addressing information fed back by the bandwidth allocation identification component; based on the addressing information, parse out associated identification information, the identification information including the target processor, the target processor port and the target signal output port of the bus device slot; based on the identification information, determine the bandwidth allocation status of the corresponding bus device slot.

[0145] In some embodiments, the bandwidth allocation identification component is connected to the processor based on a system management bus.

[0146] Based on this, the polling addressing module 71 is specifically configured to: scan the bus data transmitted by the system management bus; receive the addressing byte responded by the bandwidth allocation identification component until the scanning is completed; wherein the addressing byte is associated with the bandwidth allocation status of the bus device slot.

[0147] In the embodiments of the present application, the description of the features in the embodiments corresponding to the bandwidth acquisition device can refer to the relevant description of the embodiments corresponding to the bandwidth acquisition method, which will not be repeated here.

[0148] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned bandwidth acquisition method embodiments.

[0149] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned bandwidth acquisition method embodiments when running.

[0150] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0151] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any of the above-mentioned bandwidth acquisition method embodiments are implemented.

[0152] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned bandwidth acquisition method embodiments are implemented.

[0153] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0154] The server motherboard, server, bandwidth acquisition method, product, device and medium provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A server motherboard, characterized in that: include: The bus device slot configured on the server motherboard; The server motherboard also includes a bandwidth allocation identification component set for the bus device slot, and the bandwidth allocation identification component is connected to the processor; the bandwidth allocation identification component is configured to identify the bandwidth allocation status of the bus device slot and provide query for the processor.

2. The server motherboard according to claim 1, characterized in that: The bandwidth allocation identification component includes a programmable device; The programmable device identifies bandwidth allocation status corresponding to the bus device slot based on high and low level settings.

3. The server motherboard according to claim 2, characterized in that: The programmable device is connected to the processor based on a system management bus.

4. The server motherboard according to claim 3, characterized in that: The programmable device at least includes a signal interface, and the signal interface is configured to connect to the system management bus.

5. The server motherboard according to claim 4, characterized in that: The programmable device further comprises a signal acquisition interface, wherein the signal acquisition interface is configured to identify a signal output port corresponding to the bus device slot based on high and low level settings.

6. The server motherboard according to claim 5, characterized in that: The number of the signal acquisition interface is at least one; Different signal acquisition interfaces are configured to identify different signal output ports.

7. The server motherboard according to claim 5, characterized in that: The programmable device also includes a first type identification pin and a second type identification pin; The first type of identification pin is configured to identify a processor associated with a corresponding bus device slot; The second type identification pin is configured to identify a processor port associated with a corresponding bus device slot.

8. The server motherboard according to claim 7, characterized in that: The number of the first type identification pins is at least one; Different first-type identification pins are configured to identify different processors; and / or, The number of the second type identification pins is at least one; Different of the second-type identification pins are configured to identify different of the processor ports.

9. The server motherboard according to claim 4, characterized in that: The signal interface includes a clock signal interface and a data signal interface; The clock signal interface is configured to connect to the clock signal line of the system management bus to synchronize the clock signal; The data signal interface is configured to connect to the data signal line of the system management bus to transmit data signals; the data signals are associated with the bandwidth allocation of the bus device slots.

10. The server motherboard according to claim 1, characterized in that: The bus device slot at least includes the bus device slot on the server mainboard; the bandwidth allocation identification component is at least arranged on the server mainboard.

11. The server motherboard according to claim 1, characterized in that: The bus device slot also includes a bus device slot on an adapter card connected to the server mainboard; the bandwidth allocation identification component is also arranged on the adapter card.

12. A server, characterized in that: Comprising a server mainboard as described in any one of claims 1-11.

13. The server according to claim 12, characterized in that: Also included is an adapter card, the adapter card being connected to the server mainboard; The bus device slot is arranged on the server mainboard and the adapter card, and the bandwidth allocation identification component is correspondingly arranged on the server mainboard and the adapter card.

14. The server according to claim 12, characterized in that: It also includes a processor and an input-output system chip, wherein the bandwidth allocation identification component and the input-output system chip are both connected to the processor; The processor runs a computer program built into the input / output system chip to obtain bandwidth allocation status of the bus device slot associated with the bandwidth allocation identification component and allocate bandwidth.

15. A bandwidth acquisition method, characterized in that: The method is implemented based on the server motherboard according to any one of claims 1 to 11; the method comprises: Performing polling addressing on the bandwidth allocation identification component configured in the bus device slot; Based on the bandwidth allocation identification component response, the bandwidth allocation status of the corresponding bus device slot is obtained.

16. The bandwidth acquisition method according to claim 15, characterized in that: The obtaining of bandwidth allocation status corresponding to the bus device slot includes: Acquire the addressing information fed back by the bandwidth allocation identification component; Based on the addressing information, parsing out associated identification information, the identification information including a target processor, a target processor port, and a target signal output port of a bus device slot; Based on the identification information, a bandwidth allocation status corresponding to the bus device slot is determined.

17. The bandwidth acquisition method according to claim 15, characterized in that: The bandwidth allocation identification component is connected to the processor based on a system management bus; The polling and addressing of the bandwidth allocation identification component configured for the bus device slot includes: Scanning bus data transmitted by the system management bus; The addressing byte responded by the bandwidth allocation identification component is received until the scanning is completed; wherein the addressing byte is associated with the bandwidth allocation status of the bus device slot.

18. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the bandwidth acquisition method according to any one of claims 15 to 17 are implemented.

19. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the bandwidth acquisition method according to any one of claims 15 to 17 when executing the computer program.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the bandwidth acquisition method according to any one of claims 15 to 17.

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