Method, device and equipment for managing line interruption and storage medium

Abstract

The invention provides a management line interruption method and device, equipment and a storage medium. The method comprises the steps that first input, second input and third input are obtained, the first input comprises a first table and a second table, the first table is a table to be mapped and filled, the second table comprises a first interrupt information set, and the second input comprises a second interrupt information set for a target multi-level in a register transfer level of the integrated circuit; the third input comprises configuration parameters; based on the first, second, and third inputs, an inspection result, a hierarchical line interrupt connection result, and at least one output of a third table including an interrupt mapping table obtained by updating the first table are automatically obtained. According to the method, the interrupt mapping table and the hierarchical front-end hardware description language connection code can be automatically generated, line interrupt and design files of each module can be checked, the energy and time cost of manual management are reduced, and the efficiency and quality of external line interrupt management of chip design are improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a method, apparatus, device, and storage medium for managing line interruption. Background Art

[0002] The interrupt system is an important part of the computer system. For example, it is used in real-time control, fault handling, and handshakes with peripheral communications, which require coordinating the system's response and processing of various internal and external events. This can improve the processor's multi-tasking capabilities and greatly improve the computer's efficiency.

[0003] In the field of chip design, various external interrupts are usually handled. According to the way of initiating the interrupt, external interrupts can be divided into two types: wire interrupt (WSI) and message interrupt (MSI). Wire interrupt refers to the interrupt driven directly by the signal line, and message interrupt refers to the interrupt driven by writing a specific address and data (message) operation.

[0004] Message interrupt type interrupts can more easily implement more and more flexible interrupts, but they require additional design to implement writing specific addresses and data, as well as standardized support for external devices. Line interrupts are the way more traditional external devices or modules implement interrupts. Although not flexible enough, they are simple enough to implement and widely supported by various traditional and new external devices or modules, and are still an important part of modern interrupt system implementation. Summary of the invention

[0005] At least one embodiment of the present disclosure provides a method for managing line interrupts, comprising: obtaining a first input, wherein the first input includes a first table and a second table, the first table being configured as a table to be mapped and filled, and the second table including a first interrupt information set; obtaining a second input, wherein the second input includes a second interrupt information set corresponding to a target multi-level in a register transfer level of an integrated circuit, the target multi-level including multiple levels from an upper level of a target line interrupt controller in the register transfer level to a top level of the register transfer level; obtaining a third input, wherein the third input includes configuration parameters corresponding to the first input and / or the second input; based on the first input, the second input, and the third input, automatically obtaining a check result, a hierarchical line interrupt connection result, and at least one output in a third table, wherein the check result includes a result of a consistency comparison based on the first interrupt information set and the second interrupt information set, the hierarchical line interrupt connection result includes a line interrupt connection code corresponding to the target multi-level, and the third table includes an interrupt mapping table obtained by updating the first table based on the second table.

[0006] At least one embodiment of the present disclosure provides a device for managing line interrupts, comprising: a first input acquisition module, configured to acquire a first input, wherein the first input includes a first table and a second table, the first table is configured as a table to be mapped and filled, and the second table includes a first interrupt information set; a second input acquisition module, configured to acquire a second input, wherein the second input includes a second interrupt information set corresponding to a target multi-level in a register transfer level of an integrated circuit, the target multi-level including multiple levels from a level above a target line interrupt controller in the register transfer level to a top level of the register transfer level; a third input acquisition module, configured to acquire a third input, wherein the third input includes a configuration parameter corresponding to the first input and / or the second input; an output acquisition module, configured to automatically acquire at least one output in a check result, a hierarchical line interrupt connection result, and a third table based on the first input, the second input, and the third input, wherein the check result includes a result of consistency comparison based on the first interrupt information set and the second interrupt information set, the hierarchical line interrupt connection result includes a line interrupt connection code corresponding to the target multi-level, and the third table includes an interrupt mapping table acquired by updating the first table based on the second table.

[0007] At least one embodiment of the present disclosure provides an electronic device, including: a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, the method for managing line interrupts as described in any one of the above items is implemented.

[0008] At least one embodiment of the present disclosure provides a computer-readable storage medium, wherein the storage medium stores a computer program, and when the computer program is executed by a processor, the method for managing line interrupts as in any of the above examples is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 is a flow chart of a method for managing line interruption proposed in some embodiments of the present disclosure;

[0011] Figure 2 is a schematic diagram of a principle of managing line interruption proposed in some embodiments of the present disclosure;

[0012] Figure 3 yes Figure 1 A flowchart of an execution process of step S1 of the method for managing line interruption;

[0013] Figure 4 is a schematic diagram of a management line interruption proposed in some embodiments of the present disclosure;

[0014] Figure 5 is a structural diagram of a hierarchical module of a register transfer level proposed in some embodiments of the present disclosure;

[0015] Figure 6 is a schematic diagram of parameter setting examples proposed in some embodiments of the present disclosure;

[0016] Figure 7 is a schematic diagram of an example of a format table file proposed in some embodiments of the present disclosure;

[0017] Figure 8 is a schematic diagram of an example of a file basic information page table proposed in some embodiments of the present disclosure;

[0018] Fig. 9 is a schematic diagram of an example of a first table proposed in some embodiments of the present disclosure;

[0019] Fig.10 is a schematic diagram of an example of a third table proposed in some embodiments of the present disclosure;

[0020] Fig.11 A block diagram of a device for managing line interruption provided in some embodiments of the present disclosure;

[0021] Fig.12 A schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meanings as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless the embodiments of the present disclosure explicitly define such meanings.

[0024] The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one", "an" or "the" and similar words do not indicate a quantity limitation, but indicate the existence of at least one. Similarly, words such as "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Flowcharts are used in the embodiments of the present disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the previous or subsequent steps are not necessarily carried out in order. On the contrary, various steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or more steps can be removed from these processes.

[0025] As the scale of designed chips becomes larger and larger, the number of external line interrupts also increases. For example, in large or advanced chip designs such as server SOC (System On Chip, i.e., system-level chip), there are often a lot of external line interrupt sources, and these external line interrupts may also be distributed in several different levels of digital implementation, and then converged to the external line interrupt manager (line interrupt manager can also be called line interrupt controller), and line interrupt refers to line interrupt signal. These external line interrupts need to be correctly integrated and connected in each level of SOC, and they must be able to clearly and efficiently provide information such as their sorting mapping on the input of the external line interrupt controller, so as to facilitate reference for subsequent corresponding simulation verification, post-silicon testing, programming guidance, and product specification writing.

[0026] The research disclosed in this paper found that the current management method for these external line interruptions is to manually organize the basic information of each part of the line interruption into a table, and then manually connect them step by step in the SOC design according to the table order. In this case, the sequence number of each level of connection and the interrupt sequence number of the final external line interrupt controller input may be inconsistent. This process also requires great labor and time costs, and the inconsistency of the connection relationship and the manual processing method are prone to errors, which require subsequent verification, discovery and iterative correction.

[0027] For example, at present, external line interrupt management is mainly carried out through manual mapping management, including interrupt mapping table and digitally implemented front-end hardware description language (Verilog Hardware Description Language) code connection (referred to as Verilog code connection), which requires a lot of manpower and time costs. In addition, during the project evolution process, the number, sorting and connection of external line interrupts are changed. In addition to the duplication of manpower and time consumption, there is also a high possibility of errors and a lack of effective inspection of line interrupt signals and corresponding SOC design files.

[0028] At least one embodiment of the present disclosure provides a method for managing line interrupts, the method comprising: obtaining a first input, wherein the first input comprises a first table and a second table, the first table being configured as a table to be mapped and filled, and the second table comprising a first interrupt information set; obtaining a second input, wherein the second input comprises a second interrupt information set corresponding to a target multi-level in a register transfer level of an integrated circuit, the target multi-level comprising a plurality of levels from an upper level of a target line interrupt controller in the register transfer level to a top level of the register transfer level; obtaining a third input, wherein the third input comprises configuration parameters corresponding to the first input and / or the second input; based on the first input, the second input and the third input, automatically obtaining an inspection result, a hierarchical line interrupt connection result, and at least one output in a third table, wherein the inspection result comprises a result of a consistency comparison based on the first interrupt information set and the second interrupt information set, the hierarchical line interrupt connection result comprises a line interrupt connection code corresponding to the target multi-level, and the third table comprises an interrupt mapping table obtained by updating the first table based on the second table.

[0029] The method for managing external line interrupts of the above-mentioned embodiment of the present disclosure can automatically generate an interrupt mapping table and a hierarchical Verilog connection code for system line interrupts, and can also check the line interrupt information of each module and the design file in which it is located, thereby greatly reducing the energy and time cost of manual management and improving the efficiency and quality of external line interrupt management in chip design.

[0030] Figure 1 The present invention is a flowchart of a method for managing line interruption proposed in some embodiments of the present disclosure.

[0031] For example, Figure 1 As shown, the method for managing line interruption at least includes steps S1 to S4.

[0032] Step S1: Obtain a first input, wherein the first input includes a first table and a second table, the first table is configured as a table to be mapped and filled, and the second table includes a first interruption information set.

[0033] Step S2, obtaining a second input, wherein the second input includes a second interrupt information set corresponding to a target multi-level in a register transfer level of the integrated circuit, and the target multi-level includes multiple levels from the previous level of the target line interrupt controller in the register transfer level to the top level of the register transfer level.

[0034] Step S3: Obtain a third input, wherein the third input includes configuration parameters corresponding to the first input and / or the second input.

[0035] Step S4, based on the first input, the second input and the third input, automatically obtain the inspection result, the hierarchical line interruption connection result, and at least one output in the third table, wherein the inspection result includes the result of consistency comparison based on the first interruption information set and the second interruption information set, the hierarchical line interruption connection result includes the line interruption connection code corresponding to the target multi-level, and the third table includes an interruption mapping table obtained by updating the first table based on the second table.

[0036] The above-mentioned embodiments of the present disclosure establish a set of work processes. By collecting line interrupt information, a consistency comparison check between the first interrupt information set and the second interrupt information set can be implemented, and a system-level line interrupt mapping table and / or corresponding digital Verilog connection code files of each level can be automatically generated, so that the line interrupt connections of each level and the final line interrupt connection sequence to the external line interrupt controller can be kept consistent, which greatly reduces the labor and time costs required for the work and improves the efficiency and quality of external line interrupt management in chip design.

[0037] In the embodiments of the present disclosure, "line interruption" refers to a line interruption signal, and "interruption information" or "line interruption information" refers to the information content of the corresponding line interruption signal, which are consistent. For example, they can refer to the attributes of each column of the corresponding line interruption signal in a table. The first interruption information set and the second interruption information set refer to the information content of all line interruption signals in the corresponding table.

[0038] For example, in some examples, the integrated circuit may be a large or advanced chip design such as a server SOC, and the embodiments of the present disclosure are not limited to this. As long as it is applicable to a chip with external line interruptions, it is acceptable and will not be exhaustively listed or elaborated herein.

[0039] For example, in some examples, in step S4, relative to the first interruption information set, the second interruption information set in the second input is a design file (for example, it may include one design file or multiple design files corresponding to relevant levels, which may depend on the actual situation), such as the set of three design files corresponding to the three-layer module described below.

[0040] For example, in some examples, in step S4, a consistency comparison is performed based on the first interruption information set and the second interruption information set, which may include the following processes or steps: a script program is used to perform a check according to corresponding rules (the first filling rule and / or the second processing rule described below), thereby obtaining a check result to ensure the consistency of the line interruption information in the second table and the design file.

[0041] For example, in some examples, the consistency comparison and inspection of the first interruption information set and the second interruption information set include but are not limited to the following situations: some content in the first interruption information set does not exist in the second interruption information set (for example, the signal name in the second table is not found in the design file), or, the second interruption information set contains some content that is not in the first interruption information set, or, the first interruption information set contains content that does not comply with the corresponding rules (such as the first filling rule and / or the second processing rule described below) (for example, a typo in the second table), or, the first interruption information set is consistent with the second interruption information set. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. It can be determined according to the actual situation, and will not be exhaustively listed and repeated here.

[0042] For example, in some examples, in step S4, the inconsistent content in the first interrupt information set and the second interrupt information set in the check result will be reported as an error (ERROR) or a warning (WARNING), so that the files of these check results are checked again. It should be noted that the embodiments of the present disclosure do not limit the display of the error report and the specific circumstances of the error report, which will not be repeated here.

[0043] For example, in some examples, the method for managing line interruption disclosed herein further includes: in response to the check result being a comparison inconsistency, iteratively correcting at least one of the first input, the second input, and the third input until the check result is a comparison inconsistency, for example, until no errors or warnings appear, that is, all errors and warnings are finally cleared, and the line interruption check is completed.

[0044] The embodiments of the present disclosure can detect some potential errors or aspects inconsistent with the design in the process of line interrupt integration earlier and more easily, thereby improving the quality and efficiency of chip design and line interrupt management.

[0045] For example, in some examples, in response to the check result being inconsistent, if it is found that the first input is wrong, the first input is iteratively corrected; if it is found that the second input is wrong, the second input is iteratively corrected (as described below). Figure 4Operation ① shown). In addition, when the check result is inconsistent, it is also possible that both the first input and the second input are wrong, and the probability of this happening is lower than the probability of one of them being wrong. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. As long as the situation that leads to the inconsistent check result is within the protection scope of the present disclosure, it will not be repeated here.

[0046] For example, in some examples, step S4 may include the following process or steps: based on the first input, the second input and the third input, automatically obtaining the at least one output through a script program.

[0047] Figure 2 It is a schematic diagram of the principle of managing line interruption proposed in some embodiments of the present disclosure.

[0048] For example, Figure 2 As shown, in step S4, based on the first input R1, the second input R2 and the third input R3, through the script program D1, the three outputs of the inspection result C1, the hierarchical line interruption connection result C2 and the third table (i.e., the interruption mapping table C3 after the mapping process is completed) can be automatically obtained.

[0049] The embodiment of the present disclosure realizes the recognition of the content of the second table and the comparison check with the design file through a script program, and can automatically generate a new interrupt mapping table and a hierarchical Verilog interrupt connection language code, so that the order of line interrupt connections at each level and the final line interrupt connection sequence to the external line interrupt controller can be kept consistent. In this way, not only the time and cost can be greatly reduced, but also the efficiency and quality of external line interrupt management can be greatly improved.

[0050] It should be noted that this is merely illustrative and is not a limitation of the embodiments of the present disclosure. For example, the output obtained in step S4 may also be merely an inspection result. For example, some serious errors during the inspection may cause the hierarchical line connection results to be interrupted and the third table may no longer be generated. The embodiments of the present disclosure are not limited to this and may be determined based on actual conditions, which will not be enumerated or elaborated here.

[0051] For example, in step S2, the upper level of the target line interrupt controller in the register transfer level refers to the upper level (eg, u_hier2 level shown below) of the target line interrupt controller itself (eg, target line interrupt controller u_aplic level shown below).

[0052] For example, in some examples, the line interrupt connection code corresponding to the target multi-level in the hierarchical line interrupt connection result refers to a line interrupt Verilog connection code file of the level generated corresponding to each layer design file in the second input (the RTL filelist file list described below), and these code files all conform to the order of the line interrupts in the interrupt mapping table.

[0053] For example, in some examples, the content of the page table in the third table is changed compared to the first table, as described below.

[0054] Figure 3 yes Figure 1 Flow chart of an execution process of step S1 of the method for managing line interruption.

[0055] Figure 4 This is a schematic diagram of a management line interruption proposed in some embodiments of the present disclosure.

[0056] For example, Figure 3-Figure 4 As shown, an example of step S1 includes at least step S11 and step S12.

[0057] Step S11: automatically obtain a format table file A1, wherein the format table file A1 includes a first table and at least one sample table.

[0058] Step S12: collect line interruption information based on the sample table of the format table file A1 to obtain a second table for obtaining the first input R1.

[0059] For example, Figure 3 and Figure 4 As shown, in step S11, the format table file is automatically obtained by the script program D2. For example, the format table file can be understood as an initial example standardized format interrupt table file, which is used at the beginning of a project or when there is no modifiable interrupt table file that meets the corresponding standard of the present disclosure, and can quickly cut into the method of the embodiment of the present disclosure to manage external line interrupts. For example, the steps of this format table file are generally only used once at the beginning. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0060] The embodiments of the present disclosure implement automatic generation of a format table file by executing corresponding script commands in a process environment, thereby implementing automatic processing of each step of the method of the present disclosure and rapid deployment of applications, thereby improving efficiency.

[0061] In the embodiments of the present disclosure, "table" (such as the first table, sample table, second table and file basic information page table in this article, etc.) refers to a table that is made into grids according to the required content items and filled with text or numbers and other materials for statistical viewing. For example, these tables can be tables in Excel format. Of course, this is merely exemplary. For example, it can also be other forms of tables, such as Word, Access, Numbers, etc. The embodiments of the present disclosure are not limited to this. As long as the table adopts a visual communication mode and can organize and collate data, it will not be exhaustive or elaborated here.

[0062] It should be noted that for the sake of conciseness and clarity of the description in this article, the following is a detailed description mainly taking an Excel table as an example, but the embodiments of the present disclosure do not limit the type or form of each table, which may be determined according to the actual situation and will not be repeated here.

[0063] For example, in some examples, in step S11, the format table file also includes a file basic information page table, and the file basic information page table includes first header information.

[0064] For example, in some examples, obtaining the first input further includes the following process or step: configuring the first table, the sample table, the second table, and the file basic information page table as page tables of the same table file.

[0065] For example, in some examples, in step S1, the first input R1 is a multi-page table file (such as the same table file mentioned above), for example, the format may be an xlsx table file. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0066] The embodiment of the present disclosure implements the first input through a multi-page table file, which is simple in method and manages line interruption information more conveniently and efficiently, thereby improving efficiency.

[0067] Figure 5 It is a composition diagram of the hierarchical modules of the register transfer level proposed in some embodiments of the present disclosure.

[0068] For example, in some examples, in step S2, obtaining the second input includes the following process or step S2a: based on the register transfer level (RTL) of the target line interrupt controller and the integrated circuit, and according to the list rule of listing the register transfer level file information line by line from the top layer from top to bottom on the register transfer level until the upper layer of the target line interrupt controller, obtaining the second input.

[0069] For example, in step S2a, the register transfer level of the integrated circuit represents the integrated circuit design described by the register transfer level, which can also be referred to as RTL file.

[0070] For example, in step S2a, the second input is: according to the digital design of the integrated circuit (such as SOC) of the actual project, a file list of RTL files of each level starting from the top module is recorded, for example, the file list can be called rtl.list (or RTL filelist). Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. The embodiments of the present disclosure do not limit the name of the file list, as long as the RTL files in the file list list the contents of the file list line by line from top to bottom according to their levels in the digital design and list them to the level where the target line interrupt controller that manages these line interrupts is instantiated (for example Figure 5 It should be noted that the target line interrupt controller level of some embodiments of the present disclosure may also be referred to as the target line interrupt controller instantiation level, and the target line interrupt controller level refers to the level above the target line interrupt controller level (or the target line interrupt controller instantiation level).

[0071] For example, Figure 5 As shown, the target line interrupt controller is instantiated as u_aplic, and Figure 5 In the example of register transfer level, the top module is top, the middle module u_hier1 and u_hier2, and the target line interrupt controller u_aplic. Figure 5 The hierarchical example shown is top.u_hier1.u_hier2.u_aplic, and the file list RTL filelist includes RTL design files of the three layers of modules top, u_hier1 and u_hier2. For example, each of the three layers of top, u_hier1 and u_hier2 has only one corresponding design file. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. The specific module hierarchy arrangement is determined according to the design project planning such as SOC. As long as the location of the target line interrupt controller is determined, it will not be exhaustively listed or repeated here.

[0072] In some embodiments of the present disclosure, "module" corresponds to "Module", which refers to a collection of certain functions implemented in digital design, such as PCIE module, DRAMC module or interrupt controller module, etc., or a module formed by integrating PCIE module, DRAMC module and interrupt controller module, and the module integrated with these three modules implements more functions. For example, the top layer mentioned above is a module that integrates all the functions required by chips such as SOC, and the top-level module will not be integrated by other design files. Therefore, each module refers to all the modules required in chips such as SOC, and adding a specific function definition before "module" means a digital design unit that specifically implements the function. Without adding a specific function definition, it broadly refers to a digital design unit that implements the functions required by a certain chip.

[0073] For example, in some examples, each module (such as the middle layer u_hier1) has one or more sub-modules that need to be interrupted, and each sub-module generates a corresponding line interruption. Therefore, the line interruption information of the level corresponding to each module includes the summary of the line interruption information of all the sub-modules under the module (such as the various interruption information summary signals described below).

[0074] For example, in some examples, in step S3, the configuration parameters include control parameters in the form of key-value pairs, and the control parameters include one or more of the following: the line interrupt controller module name (ARG_TARGET), the top-level module name (ARG_TOP), and the maximum number of external line interrupts required to be supported (ARG_WIRE_MAX).

[0075] The embodiments of the present disclosure can adapt to various types of system line interruption management of different projects through parameterized settings, can meet flexible needs, and have a wide range of applications.

[0076] Figure 6 It is a schematic diagram of parameter setting examples proposed in some embodiments of the present disclosure.

[0077] For example, Figure 6 As shown, the configuration parameters are parameter settings required for a script program (such as script program D1) during processing. For example, Figure 6 The line interrupt controller module name APLIC, the top-level module name demo_top and the maximum number of external line interrupts that the project needs to support are 155. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. It can be freely adjusted according to actual design conditions and will not be exhaustively listed or repeated here.

[0078] For example, in some examples, the SOC design target line interrupt controller can only support the connection of 155 line interrupts, but the number of interrupt requirements collected from all modules is 170, so the program will list all required interrupts (170) in the interrupt mapping table and check them against the maximum number of interrupts supported by the design (155). At this time, the result will report an error, so that it is found that the number of interrupts needs to be controlled or the design support capability needs to be modified. This is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0079] For example, in some examples, when the method for managing line interrupts of the present invention is directed to different target line interrupt controllers, the line interrupt controller module name in the configuration parameters is also matched with the corresponding target line interrupt controller, thereby being able to manage all line interrupts of each target line interrupt controller, making the application more convenient and easier to adapt for use in new projects.

[0080] For example, the script program of the embodiment of the present disclosure can be implemented by Python language, which is more flexible. However, the embodiment of the present disclosure is not limited to this, and the script program of the present disclosure can also be implemented by other programming languages, which will not be exhaustively listed and repeated here.

[0081] Figure 7 It is a schematic diagram of an example of a format table file proposed in some embodiments of the present disclosure.

[0082] For example, Figure 7 As shown, the format table file A1 includes a first table (such as page table 1) and at least one sample table. Figure 7 As shown, the format table file A1 also includes a file basic information page table (such as page table 0). Some embodiments of the present disclosure can manage all line interrupt information and the generated interrupt mapping table after mapping based on the format table file.

[0083] For example, Figure 7 As shown, the page table sequence number of the format table file A1 is set to start from 0 and be numbered in sequence, and the first row and first column sequence numbers in the page table are all marked starting from 1. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0084] For example, Figure 7 As shown, the page table name of page table 0 is Note, the page table name of page table 1 is APLIC_int_mapping, and page table 1 can also be called the interrupt mapping table before mapping filling. At least one sample table in the format table file A1 can be Figure 7The sample table in the format table file A1 can also be called the interrupt sub-table before filling in, so starting from page table 2, it is necessary to collect and fill in the line interrupt information of each module according to the rules or specifications (see below for details). Of course, this is only for example, and the format table file of the embodiment of the present disclosure is not limited to Figure 7 The example is composed of, and the page table name of the page table is not limited to Figure 7 The naming method of the examples is not limited in the embodiments of the present disclosure and will not be exhaustively listed or elaborated here.

[0085] For example, in some examples, the first header information of the file basic information page table includes at least one of the following information: version, description, date, and modifier information. This facilitates the management of line interrupts and is flexible and versatile. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0086] Figure 8 It is a schematic diagram of an example of a file basic information page table proposed in some embodiments of the present disclosure.

[0087] For example, Figure 8 As shown, the first header information of the file basic information page table (such as page table 0) includes: version (revision), description (description), date (date) and modifier information (modifier).

[0088] For example, Figure 8 The file basic information page table in the example is in the initial state, which is automatically generated by the script program D2. Subsequent filling and modification can be updated according to the actual project records. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. The first header information of the present disclosure can also be composed in other ways, which will not be repeated here. It should be noted that the page table name and / or the capitalization of the header information of the table in some embodiments of the present disclosure do not affect the protection scope of the present disclosure.

[0089] Fig. 9 is a schematic diagram of an example of a first table proposed in some embodiments of the present disclosure. Fig.10 is a schematic diagram of an example of a third table proposed in some embodiments of the present disclosure, Fig.10 is Fig. 9 The result obtained by mapping and filling the table based on is described below for details.

[0090] For example, in some examples, the first table to be mapped and filled includes third header information, and the third header information includes at least one of the following naming identification information: line index, signal name, module name, target, description, trigger mode, suspend state, and configuration register address. The format and content of the first table can be automatically generated by the script program D2. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0091] For example, Fig. 9 As shown, the third header information of the first table to be mapped and filled (such as page table 1) includes: wire index (Wire Index), signal name (SignalName), module name (Module Name), target (Targets), description (Description), trigger mode (Source Mode), pending state (Pending Bit) and configuration register address (Aplic cfg Register (offset)). Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. For example, Fig. 9 The first table to be mapped and filled (ie, the interrupt mapping table before mapping and filling) is shown to be blank except for the third table header information.

[0092] For example, Figure 7 As shown, the header information of the sample table (such as page table 2) includes signal name (Signal Name), port width (PortWidth), module name (Module Name), description (Description), trigger mode (Source Mode), target (Targets) and pending status (Pending Bit). Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. For example, in some examples, the sample table is different from the first table sample table, and other places except the corresponding header information are not completely blank (that is, in addition to the corresponding header information, some content is recorded), such as Figure 7 As shown, this can be freely adjusted according to actual conditions and will not be elaborated here.

[0093] For example, in some examples, the line index represents the serial number of the line interrupt index, which is the identification serial number of all valid line interrupts after processing; the trigger mode includes whether the line interrupt is triggered by the rising edge or the falling edge, whether the high level is valid or the low level is valid, and whether it is enabled, etc.; the target represents the corresponding target line interrupt controller; the signal name represents the name of the line interrupt information; the module name represents the name of each module; the description represents the content of the line interrupt information; the suspension state represents the state of the suspension register, for example, it represents a state with a request but has not been processed; the configuration register address represents the address and offset bit of the corresponding configuration register in the interrupt controller, etc.; the port width represents the width of the port (such as the port for the signal connection between each two modules). For example, the register information such as the suspension state and the configuration register address is determined according to the SOC address allocation and is associated with the SOC design. Since this is not the focus of the embodiments of the present disclosure, it will not be repeated here. It should be noted that the various contents and their interpretations in the above header information are only exemplary and are not limited to the embodiments of the present disclosure.

[0094] For example, in some examples, in step S12, line interruption information is collected based on the sample table of the format table file A1 to obtain a second table, including the following process or step S12a: based on the sample table of the format table file A1 and filling in the sample table according to the first filling rule, to obtain the second table. For example, the second header information of the second table is the same as the header information of the sample table.

[0095] For example, in some examples, the second table includes second header information, and the second header information includes at least one of the following naming identification information: signal name, port width, module name, description, trigger mode, target, and suspend state. For example, the second header information of the second table may also include a clock domain (Clk Domain), or the clock domain column may be empty. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0096] For example, the headers (such as the first header information, the second header information, and the third header information) of some embodiments of the present disclosure can be manually adjusted to be highlighted for easy viewing without affecting the execution of the process of the method for managing line interruptions. For example, the headers of some embodiments of the present disclosure are named for identification, and the embodiments of the present disclosure support adding or inserting new column information as needed without affecting the execution of the process of the method of the present disclosure.

[0097] For example, in some examples, in step S12a, filling in the sample table can be done manually to collect the line interruption information of each module or part on the SOC system according to the example format, and to improve the sample table to obtain the second table (not shown). Thus, the second table is a standardized interruption table file collected from each module or part. For example, the table where the line interruption corresponding to each module is located is a page table in the first input (multi-page table file). Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0098] For example, in some examples, such as Fig.10 As shown, the third table is the interrupt mapping table after mapping processing. Fig.10 is Fig. 9 Based on the above, the content of the second table after the line interruption information collection is completed is at least partially mapped to the result obtained in the first table.

[0099] For example, in some examples, the first filling rule for filling in the sample table (i.e., the interruption sub-table before starting to fill in) to obtain the second table (i.e., the interruption sub-table after completing the filling in) includes at least one of the following:

[0100] (1) A complete line interruption information should fill in all the information of the interruption sub-table, and the columns of description, trigger mode, clock domain, and suspend status in the header information (i.e., the second header information) of the interruption sub-table can be empty.

[0101] (2) If the target column ("Targets" column) in the second header information of the interrupt subtable has multiple interrupt target destinations (e.g., APLIC, MSCP), each target is separated by a punctuation mark (e.g., a semicolon), the target column is case insensitive, and the parameter specifies the name that the script program matches during processing, thereby naming the target module according to the project or actual situation. The target destination indicates the target line interrupt controller, for example, the target destination refers to the instantiation of the target line interrupt controller.

[0102] (3) The content of the first valid interrupt in the column where the module name is located (the "Module Name" column) in the second header information of the interrupt subtable is not empty (for example, although the script can automatically process it as the top-level module specified by the parameter, some embodiments may choose not to use it in this way), and the column where the module name is located in the second header information of the interrupt subtable supports filling in different module names (for example, the premise is that these modules are consistent with the number of instantiations implicitly represented in the page table name); for another example, for this column, the script program will automatically use the module name filled in last time to process the subsequent empty content (that is, at least the module name of the first valid interrupt is not empty) (from the perspective of easy viewing, it is not preferred to leave it blank).

[0103] (4) The column where the port width is located ("PortWidth" column) in the second header information of the interrupt subtable supports multi-bit width interrupt signals. For example, a number greater than 1 can be filled in, or the default 1-bit signal can be left blank.

[0104] (5) For the column where the signal name is located in the second header information of the interrupt subtable (the "SignalName" column): this column supports grammatically correct signal names, and also supports blank, slash " / " and case-insensitive NA or N / A to indicate skipping the row in the table; or, the case-insensitive Reserved is used for interrupt signal mapping placeholders; or, if the interrupt signal name has been determined but a placeholder needs to be mapped at a certain stage instead of an actual code connection, the prefix Reserved_ can be used.<signal_name> The interrupt signal mapping is performed in this way.

[0105] In some embodiments of the present disclosure, the interrupt signal mapping placeholder means: perform the interrupt placeholder operation according to the expected number of interrupt signals, let this line interrupt occupy a line interrupt sequence number first, without actually connecting the signal, so that in the digital design and development stage, the line interrupt that has been determined but not yet implemented is occupied first, which is convenient for the entire project stage to determine or maintain the consistency and stability of the index number of each line interrupt earlier, and reduce or reduce the difficulty or modification of subsequent verification and other processing. Since this is not the focus of the description of the embodiments of the present disclosure, it will not be repeated here.

[0106] The first filling rule of the embodiment of the present disclosure includes the design of table content skipping and interrupt mapping placeholder in the column where the signal name is located, which can greatly improve the flexibility of filling in the interrupt sub-table and the stability of subsequent processing. In addition, the table content skips the row, that is, the row is directly skipped after the specified content is matched, so that the interrupt can be quickly deleted without changing the number of rows in the original page table, etc. Flexible applications.

[0107] It should be noted that the above-mentioned first filling rule is merely exemplary and is not a limitation of the embodiments of the present disclosure. As long as it meets the project requirements, it will not be exhaustively listed or elaborated here.

[0108] For example, in some examples, when the check result is inconsistent, if it is necessary to iteratively correct the first input (such as Figure 4 The operation ①) shown in the figure also requires correction according to the first filling rule mentioned above, that is, the embodiment of the present disclosure can fill in the sample table or correct the second table according to the first filling rule mentioned above, which will not be repeated here. For example, the first input in step S1 can be the uncorrected initial first input, or it can be the first input obtained after correcting the second table after checking the inspection results. The embodiment of the present disclosure does not limit this, and it can be determined according to the actual situation, which will not be repeated here.

[0109] For example, in some examples, in step S4, based on the first input, the second input and the third input, the inspection results, the hierarchical line interruption connection results, and at least one output in the third table are automatically obtained, including the following process or step S4a: updating the first table based on the second table to obtain the third table.

[0110] For example, in some examples, in step S4a, the first table and the third table are page tables at the same location, but the content of the third table is changed compared to the first table, that is, the content is filled in other places in the first table except the table header to obtain the third table.

[0111] Some embodiments of the present disclosure update the first table based on the second table and according to the second processing rule (see below for details) to obtain a third table, for example Fig.10 The third table in is an interrupt mapping table generated by mapping the two interrupt sub-tables. Therefore, the third table of the embodiment of the present disclosure not only includes the interrupt information in the interrupt sub-table, but also includes the information obtained from the design such as the suspend state and the configuration register address and the hierarchical instantiation.

[0112] In some examples, the second processing rules include the following basic rules for processing the second table and basic rules for processing the interrupt mapping table.

[0113] For example, in some examples, the basic rules for processing the second table include at least one of the following:

[0114] (1) Determine the target column ("Targets" column) in the second header information of the second table. If there is no target line interrupt controller module name information (such as "APLIC" information, where the parameter specifies that the system line interrupt controller module name is APLIC, which is consistent with the first filling rule of the sample table), skip it.

[0115] (2) Determine the column where the signal name is located in the header information of the second table (the "Signal Name" column). If it is invalid, skip it (for example, Figure 7 spaces, slashes " / ", and various NA or N / A cases).

[0116] (3) Determine whether the column where the module name is located in the second header information of the second table (the "Module Name" column) can be found in the second input RTL file; if the first valid content row of the page table is empty, the top-level module name (the top-level module name specified by the configuration parameters) is used by default; if the non-first valid row in the page table is empty, the last valid module name is used by default (here it is preferred to follow the first filling rule and leave it blank).

[0117] (4) Determine the column where the port width is located in the second header information of the second table (the "PortWidth" column). If it is empty or 1, directly process it as a 1-bit signal. If it is greater than 1, call a function to complete the port signal expansion.

[0118] (5) Determine whether the column where the description is located (the "Description" column) in the second header information of the second table is empty, and adjust the content written into the interrupt mapping table according to the determination result.

[0119] (6) Determine whether the port in the column where the signal name is located in the second header information of the second table (see below) can be found on the instance. If it is a top-level module, determine whether the interrupt is defined at the top level. If it does not meet the rules, an error is reported. At the same time, based on the port connection of the RTL design file, automatically determine the interrupt signal name written into the interrupt mapping table and the generated hierarchical code. If the port is not connected in the design, the default port name and connection name are used consistently. If the port has a connected signal, the signal name connected in the design is used.

[0120] For example, in some examples, the basic rules for processing the interrupt mapping table include at least one of the following:

[0121] (1) The script D1 clears or initializes the contents of all interrupt mapping tables line by line according to the third header information; wherein the contents of the configuration register address and suspend status columns in the third header information are initialized, and the contents of other header information columns in the third header information are cleared.

[0122] (2) Script program D1 processes the second tables one by one starting from sequence number 2 (this is only exemplary), checks each second table row by row according to the basic rules for processing the second table, and maps the qualified line interruption information row by row into the interruption mapping table.

[0123] (3) In the interrupt mapping table, the content of the line index in the third header information is automatically generated according to the serial number; the four columns of signal name, target, description and trigger mode in the third header information are the corresponding information extracted from the second table or the default description added by the script program; in addition, the three columns of module name, configuration register address and suspend status in the third header information are the instantiation name and hierarchy information extracted by the script program from the RTL design file, or the function of the script program is calculated according to the base address assigned by the SOC and the design rules according to the line index number of the line interrupt, the base address is a fixed parameter of the function, and the line index number and the design rules determine the offset.

[0124] The embodiments of the present disclosure can realize the function of automatically generating an interrupt mapping table for a system external line interrupt manager, and can also ensure that there is only one copy of the table file for managing these external line interrupt information to avoid redundancy and confusion. At the same time, the file containing the output interrupt mapping table can also continue to be used as input for rechecking and automatically generating management line interrupts after subsequent line interrupt changes.

[0125] It should be noted that the above-mentioned second processing rule is merely exemplary and is not a limitation of the embodiments of the present disclosure. As long as the normal line interruption information that complies with the corresponding rules can be written into the interruption mapping table (for example, if it does not comply with the corresponding processing rules, an error is reported), the embodiments of the present disclosure do not limit or elaborate on this.

[0126] For example, in Figure 7 In the example, the page table name of the interrupt sub-table may not be a module name, for example, the page table name may also be a collection name composed of related modules, and the embodiments of the present disclosure are not limited to this. Figure 7 As shown, the page table name of page table 3 is demo_ss4x3x4, and the last "x4" in the page table name of page table 3 indicates that the module in the page table is instantiated in 4 copies. The embodiment of the present disclosure supports automatic expansion of interrupt information of multiple instantiated modules through the page table name suffix "x[Num]", thereby reducing table redundancy.

[0127] For example, for instantiation, a module can instantiate multiple instances. For example, the PCIE module instantiates four copies of PCIE_1, PCIE_2, PCIE3, and PCIE4 on the SOC, each of which is independent but has the same function; assuming that the PCIE module has 2 line interrupts, then the four instantiations require 8 line interrupts to be sent to the line interrupt controller, and the port name of each instantiation is actually the same. For this situation where a module instantiates multiple instances, you only need to add the number of instances to the interrupt subtable name according to the format, and the program can automatically expand the page table four times to perform interrupt mapping processing.

[0128] For example, in some examples, step S4 may include the following processes or steps: obtaining a single-layer interrupt information summary signal of the line interrupt information corresponding to each level in the target multi-level based on the second interrupt information set, and, in sequence from the top layer to the bottom at the register transfer level, modularly transmitting the single-layer interrupt information summary signal corresponding to each current level in the target multi-level to the next level connected to the current level until all the single-layer interrupt information summary signals of the target multi-level are gathered to the target line interrupt controller to obtain the hierarchical line interrupt connection result.

[0129] In some embodiments of the present disclosure, "modular transmission" means that each current level first collects all the line interruption information corresponding to the current level and transmits the collected line interruption information as a whole to the next level. In some examples, all the line interruption information of the current level can be modularly sent to the next level by opening a port on the next level. For example, all the line interruption information of the u_hier1 layer can be sent to the u_hier2 layer by opening a port on the u_hier2 layer.

[0130] In some embodiments of the present disclosure, a single-layer interruption information summary signal refers to a summary result of all line interruption information corresponding to each level. For example, a single-layer interruption information summary signal refers to a file obtained by sorting and connecting line interruptions in the corresponding levels (i.e., completing a hierarchical connection). The single-layer interruption information summary signal can be a bus-type signal, which can realize signal transmission by opening ports on the level.

[0131] For example, in some examples, opening a port at the module level may be achieved manually. Of course, this is merely exemplary and is not a limitation of the embodiments of the present disclosure.

[0132] For example, in some examples, the above-mentioned hierarchical structure is configured to be non-repeated aggregation, which means that each current level only aggregates the line interruption information within the current level, and no longer repeatedly aggregates the line interruption information that has been aggregated by the previous level. For example, after the u_hier2 layer obtains the second-level interruption information summary signal that has been aggregated by the u_hier1 layer through the port, the u_hier2 layer only needs to aggregate all the line interruption information of the u_hier2 layer itself to obtain the third-level interruption information summary signal, but does not need to aggregate the first-level interruption information summary signal again. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure.

[0133] For example, in Figure 5 In the example, an embodiment of the present disclosure aggregates all line interrupt information of the three layers, namely the top layer, the u_hier1 layer and the u_hier2 layer, to the interrupt controller u_aplic, and each of the three layers, namely the top layer, the u_hier1 layer and the u_hier2 layer, has an RTL design file, thereby obtaining the hierarchical line interrupt connection code in the output result.

[0134] For example, in some examples, the embodiments of the present disclosure may collect all the line interruption information corresponding to the top layer to obtain a first-layer interruption information summary signal, and send the first-layer interruption information summary signal to the u_hier1 layer as a whole by opening a port on the u_hier1 layer, and then collect all the line interruption information corresponding to the u_hier1 layer to obtain a second-layer interruption information summary signal, and send both the first-layer interruption information summary signal and the second-layer interruption information summary signal to the u_hier2 layer by opening a port on the u_hier2 layer, and then collect all the line interruption information corresponding to the u_hier2 layer to obtain a third-layer interruption information summary signal, and send the first-layer interruption information summary signal, the second-layer interruption information summary signal, and the third-layer interruption information summary signal to the interrupt controller u_aplic by opening a port on the interrupt controller u_aplic. Of course, this is merely exemplary and is not a limitation of the embodiments of the present disclosure.

[0135] For example, in some examples, the first layer interruption information summary signal, the second layer interruption information summary signal and the third layer interruption information summary signal correspond one by one to the RTL design files of the three layers of modules top, u_hier1 and u_hier2 mentioned above.

[0136] For example, each of the first-layer interruption information summary signal, the second-layer interruption information summary signal, and the third-layer interruption information summary signal refers to a file obtained by sorting and connecting line interruptions in the respective corresponding layers, thereby obtaining the final hierarchical line interruption connection code corresponding to the target multi-level. For example, each of the first-layer interruption information summary signal, the second-layer interruption information summary signal, and the third-layer interruption information summary signal can be a bus-type signal, and these bus-type signals are configured to be modularly transmitted to the next level connected to the current level until all the bus-type signals reach the target line interrupt controller, thereby obtaining the final hierarchical line interruption connection result corresponding to the target multi-level.

[0137] The embodiments of the present disclosure can automatically generate a corresponding RTL file list and Verilog connection codes for line interrupts at each level with a corresponding number of levels through modular transmission of line interrupt information. The code files all conform to the order of line interrupts in the interrupt mapping table, so that port unification can be achieved, information management is facilitated, and design integration is very convenient, saving time and effort.

[0138] In some examples, the method for managing line interruption of any of the above embodiments may be used to maintain all line interruption information of a target line interruption controller.

[0139] The script program implemented by the above-mentioned embodiment of the present disclosure can quickly provide a table file for applying the method according to the defined specifications and rules, check the consistency between the filled-in line interruption information and the design, and the parameterized setting can adapt to various types of system line interruption management in different projects. It can flexibly support the information expansion of adding interrupt sub-tables through naming matching rather than fixed row and column matching, and can automatically analyze and check the hierarchy and signal connection information of the interruption signal, and has the characteristics of rich functions and flexible versatility.

[0140] For example, in some examples, for the method of managing line interruptions of the present disclosure, in response to N target line interruption controllers, the method of managing line interruptions is configured to execute N times accordingly according to the N target line interruption controllers, where N is an integer greater than or equal to 2.

[0141] The method for managing line interruption in the embodiment of the present disclosure has strong scalability, strong versatility and a wide range of applications.

[0142] For example, in some examples, the embodiments of the present disclosure also implement multiple management line interruption methods by adjusting inputs (e.g., adjusting at least one of the first input, the second input, and the third input), such as the line interruption controller module name in the configuration parameters can be adjusted for different target line interruption controllers as described above. Of course, this is only exemplary and is not a limitation of the embodiments of the present disclosure. This can be freely adjusted according to actual needs, and will not be exhaustively listed or repeated here.

[0143] Fig.11 A block diagram of a device for managing line interruption provided in some embodiments of the present disclosure.

[0144] For example, Fig.11 As shown, the apparatus 100 for managing line interruption provided by at least one embodiment of the present disclosure includes a first input acquisition module 110 , a second input acquisition module 120 , a third input acquisition module 130 and an output acquisition module 140 .

[0145] The first input acquisition module 110 is configured to acquire a first input, wherein the first input includes a first table and a second table, the first table is configured as a table to be mapped and filled, and the second table includes a first interruption information set.

[0146] The second input acquisition module 120 is configured to obtain a second input, wherein the second input includes a second interrupt information set corresponding to a target multi-level in a register transfer level of the integrated circuit, and the target multi-level includes multiple levels from the previous level of the target line interrupt controller in the register transfer level to the top level of the register transfer level.

[0147] The third input acquisition module 130 is configured to acquire a third input, wherein the third input includes configuration parameters corresponding to the first input and / or the second input.

[0148] The output acquisition module 140 is configured to automatically acquire at least one output among the inspection results, the hierarchical line interruption connection results, and the third table based on the first input, the second input, and the third input, wherein the inspection results include the results of consistency comparison based on the first interruption information set and the second interruption information set, the hierarchical line interruption connection results include the line interruption connection codes corresponding to the target multi-level, and the third table includes the interruption mapping table obtained by updating the first table based on the second table.

[0149] It should be noted that in the embodiments of the present disclosure, the device for managing line interruption may include more or fewer modules, and the connection relationship between the modules is not limited and can be determined according to actual needs. The specific configuration of each module is not limited. For the specific implementation and technical effects of the device for managing line interruption, reference can be made to the relevant contents of the method for managing line interruption provided in the above embodiments of the present disclosure, which will not be repeated here.

[0150] Each module in the above embodiment can be configured as software, hardware, firmware or any combination of the above items to perform specific functions. For example, these modules can correspond to a dedicated integrated circuit, can also correspond to pure software code, and can also correspond to a module combining software and hardware.

[0151] It should be noted that although the device for managing line interruptions is divided into modules for respectively executing corresponding processing when describing the device for managing line interruptions, those skilled in the art are aware that the processing performed by each module can also be performed without any specific module division in the device for managing line interruptions or without clear boundaries between the modules.

[0152] Fig.12 A structural diagram of an electronic device provided for at least one embodiment of the present disclosure, the electronic device 200 includes a processor 210 and a memory 220, wherein a computer program is stored on the memory 220, and when the computer program is executed by the processor 210, a method for managing line interruptions of at least some embodiments of the present disclosure is implemented.

[0153] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as laptop computers, tablet computers, etc. and fixed terminals such as desktop computers, etc. Fig.12 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0154] For example, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. When the computer program is executed by a processor, the method for managing line interrupts of an embodiment of the present disclosure is executed.

[0155] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In an embodiment of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device. In an embodiment of the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0156] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0157] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 200 can refer to the above description of the method for managing line interruption, which will not be repeated here.

[0158] Based on one or more embodiments of the present disclosure, a method for managing line interrupts is provided, comprising: obtaining a first input, wherein the first input includes a first table and a second table, the first table being configured as a table to be mapped and filled, and the second table including a first interrupt information set; obtaining a second input, wherein the second input includes a second interrupt information set corresponding to a target multi-level in a register transfer level of an integrated circuit, the target multi-level including multiple levels from an upper level of a target line interrupt controller in the register transfer level to a top level of the register transfer level; obtaining a third input, wherein the third input includes configuration parameters corresponding to the first input and / or the second input; based on the first input, the second input, and the third input, automatically obtaining an inspection result, a hierarchical line interrupt connection result, and at least one output in a third table, wherein the inspection result includes a result of a consistency comparison based on the first interrupt information set and the second interrupt information set, the hierarchical line interrupt connection result includes a line interrupt connection code corresponding to the target multi-level, and the third table includes an interrupt mapping table obtained by updating the first table based on the second table.

[0159] For example, in a method for managing line interruptions provided by at least one embodiment of the present disclosure, obtaining a first input includes: automatically obtaining a format table file, wherein the format table file includes a first table and at least one sample table; collecting line interruption information based on the sample table of the format table file, and obtaining a second table to obtain the first input.

[0160] For example, in a method for managing line interrupts provided by at least one embodiment of the present disclosure, the format table file also includes a file basic information page table, the file basic information page table includes first header information, and the first header information includes at least one of the following information: version, description, date and modifier information.

[0161] For example, in a method for managing line interrupts provided by at least one embodiment of the present disclosure, obtaining a first input further includes: configuring the first table, at least one sample table, and a file basic information page table as page tables of the same table file.

[0162] For example, in a method for managing line interrupts provided by at least one embodiment of the present disclosure, the second table includes second header information, and the second header information includes at least one of the following naming identification information: signal name, port width, module name, description, trigger mode, target and suspend status.

[0163] For example, in a method for managing line interrupts provided by at least one embodiment of the present disclosure, the first table includes third table header information, and the third table header information includes at least one of the following naming identification information: line index, signal name, module name, target, description, trigger mode, suspend status and configuration register address.

[0164] For example, in a method for managing line interrupts provided by at least one embodiment of the present disclosure, obtaining a second input includes: based on a target line interrupt controller and a register transfer level of an integrated circuit, and according to a list rule of listing register transfer level file information row by row from the top layer to the bottom on the register transfer level until the upper layer of the target line interrupt controller, obtaining the second input.

[0165] For example, in a method for managing line interrupts provided in at least one embodiment of the present disclosure, the configuration parameters include control parameters in the form of key-value pairs, and the control parameters include one or more of the following: the line interrupt controller module name, the top-level module name, and the maximum number of external line interrupts required to be supported.

[0166] For example, in a method for managing line interruptions provided in at least one embodiment of the present disclosure, based on a first input, a second input, and a third input, inspection results, hierarchical line interruption connection results, and at least one output in a third table are automatically obtained, including: based on the first input, the second input, and the third input, at least one output is automatically obtained through a script program.

[0167] For example, in a method for managing line interruptions provided in at least one embodiment of the present disclosure, based on a first input, a second input, and a third input, inspection results, hierarchical line interruption connection results, and at least one output in a third table are automatically obtained, including: updating the first table based on the second table to obtain the third table.

[0168] For example, in a method for managing line interrupts provided in at least one embodiment of the present disclosure, based on a first input, a second input, and a third input, an inspection result, a hierarchical line interrupt connection result, and at least one output in a third table are automatically obtained, including: obtaining a single-layer interrupt information summary signal of the line interrupt information corresponding to each level in the target multi-level based on the second interrupt information set, and, in accordance with the top layer from top to bottom at the register transfer level, modularly transmitting the single-layer interrupt information summary signal corresponding to each current level in the target multi-level to the next level connected to the current level, until all the single-layer interrupt information summary signals of the target multi-level are gathered to the target line interrupt controller to obtain the hierarchical line interrupt connection result.

[0169] For example, at least one embodiment of the present disclosure provides a method for managing line interruptions, further comprising: in response to a check result indicating that the comparison is inconsistent, iteratively correcting at least one of the first input, the second input, and the third input until the check result indicates that the comparison is consistent.

[0170] For example, in a method for managing line interruptions provided in at least one embodiment of the present disclosure, in response to the number of target line interruption controllers being N, the method for managing line interruptions is configured to execute N times accordingly according to the N target line interruption controllers, where N is an integer greater than or equal to 2.

[0171] Based on one or more embodiments of the present disclosure, there is also provided an apparatus for managing line interrupts, comprising: a first input acquisition module, configured to acquire a first input, wherein the first input includes a first table and a second table, the first table is configured as a table to be mapped and filled, and the second table includes a first interrupt information set; a second input acquisition module, configured to acquire a second input, wherein the second input includes a second interrupt information set corresponding to a target multi-level in a register transfer level of an integrated circuit, the target multi-level including multiple levels from an upper level of a target line interrupt controller in the register transfer level to a top level of the register transfer level; a third input acquisition module, configured to acquire a third input, wherein the third input includes configuration parameters corresponding to the first input and / or the second input; an output acquisition module, configured to automatically acquire at least one output in a third table, based on the first input, the second input, and the third input, wherein the inspection result includes a result of consistency comparison based on the first interrupt information set and the second interrupt information set, the hierarchical line interrupt connection result includes a line interrupt connection code corresponding to the target multi-level, and the third table includes an interrupt mapping table acquired by updating the first table based on the second table.

[0172] Based on one or more embodiments of the present disclosure, an electronic device is provided, including: a processor and a memory, wherein a computer program is stored in the memory, and when the computer program is executed by the processor, any of the above methods for managing line interrupts is implemented.

[0173] Based on one or more embodiments of the present disclosure, a computer-readable storage medium is provided, wherein a computer program is stored in the storage medium, and when the computer program is executed by a processor, any of the above methods for managing line interrupts is implemented.

[0174] There are a few points to note:

[0175] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to the general design.

[0176] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0177] The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A method for managing line interruption, comprising: Obtaining a first input, wherein the first input includes a first table and a second table, the first table is configured as a table to be mapped and filled, and the second table includes a first interruption information set; Obtaining a second input, wherein the second input includes a second interrupt information set corresponding to a target multi-level in a register transfer level of the integrated circuit, the target multi-level including a plurality of levels from a level above a target line interrupt controller in the register transfer level to a top level of the register transfer level; Obtaining a third input, wherein the third input includes configuration parameters corresponding to the first input and / or the second input; Based on the first input, the second input and the third input, the inspection result, the hierarchical line interruption connection result and at least one output in the third table are automatically obtained, wherein the inspection result includes the result of consistency comparison based on the first interruption information set and the second interruption information set, the hierarchical line interruption connection result includes the line interruption connection code corresponding to the target multi-level, and the third table includes an interruption mapping table obtained by updating the first table based on the second table.

2. The method for managing line interruptions of claim 1, wherein: The obtaining of the first input comprises: automatically obtaining a format table file, wherein the format table file includes the first table and at least one sample table; Line interruption information is collected based on the sample table of the format table file to obtain the second table for obtaining the first input.

3. The method for managing line interruptions of claim 2, wherein: The format table file also includes a file basic information page table, The file basic information page table includes first header information, and the first header information includes at least one of the following information: version, description, date and modifier information.

4. The method for managing line interruptions of claim 3, wherein: The obtaining of the first input further includes: The first table, the at least one sample table and the file basic information page table are configured as page tables of the same table file.

5. The method for managing line interruption according to any one of claims 1 to 5, wherein: The second table includes second table header information, and the second table header information includes at least one of the following naming identification information: signal name, port width, module name, description, trigger mode, target and suspension status.

6. The method for managing line interruptions of claim 1, wherein: The first table includes third header information, and the third header information includes at least one of the following naming identification information: line index, signal name, module name, target, description, trigger mode, suspension status and configuration register address.

7. The method for managing line interruptions of claim 1, wherein: The obtaining of the second input comprises: The second input is obtained based on the target line interrupt controller and the register transfer level of the integrated circuit and in accordance with a listing rule of listing register transfer level file information row by row from the top layer to the upper layer of the target line interrupt controller on the register transfer level.

8. The method for managing line interruptions of claim 1, wherein: The configuration parameters include control parameters in the form of key-value pairs, and the control parameters include one or more of the following: a line interrupt controller module name, a top-level module name, and a maximum number of external line interrupts required to be supported.

9. The method for managing line interruptions of claim 1, wherein: The method of automatically obtaining at least one output in a third table, a check result, a hierarchical line interruption connection result, and the third table based on the first input, the second input, and the third input, comprises: Based on the first input, the second input and the third input, the at least one output is automatically obtained through a script program.

10. The method for managing line interruptions of claim 1, wherein: The method of automatically obtaining at least one output in a third table, a check result, a hierarchical line interruption connection result, and the third table based on the first input, the second input, and the third input, comprises: The first table is updated based on the second table to obtain the third table.

11. The method for managing line interruptions of claim 1, wherein: The method of automatically obtaining at least one output in a third table, a check result, a hierarchical line interruption connection result, and the third table based on the first input, the second input, and the third input, comprises: A single-layer interruption information summary signal of line interruption information corresponding to each layer in the target multi-layer is obtained based on the second interruption information set, and According to the register transfer level, from the top layer to the bottom, the single-layer interrupt information summary signal corresponding to each current layer in the target multi-layer is sequentially transmitted modularly to the next layer connected to the current layer, until all the single-layer interrupt information summary signals of the target multi-layer are gathered to the target line interrupt controller to obtain the hierarchical line interrupt connection result.

12. The method for managing line interruptions of claim 1, further comprising: In response to the checking result being that the comparison is inconsistent, at least one of the first input, the second input, and the third input is iteratively corrected until the checking result is that the comparison is consistent.

13. The method for managing line interruptions of claim 1, wherein: In response to the number of the target line interrupt controllers being N, the method for managing line interrupts is configured to be executed N times correspondingly according to the N target line interrupt controllers, wherein N is an integer greater than or equal to 2.

14. A device for managing line interruption, comprising: A first input acquisition module, configured to acquire a first input, wherein the first input includes a first table and a second table, the first table is configured as a table to be mapped and filled, and the second table includes a first interruption information set; A second input acquisition module is configured to acquire a second input, wherein the second input includes a second interrupt information set corresponding to a target multi-level in a register transfer level of the integrated circuit, the target multi-level including a plurality of levels from an upper level of a target line interrupt controller in the register transfer level to a top level of the register transfer level; a third input acquisition module, configured to acquire a third input, wherein the third input includes configuration parameters corresponding to the first input and / or the second input; An output acquisition module is configured to automatically acquire at least one output among an inspection result, a hierarchical line interruption connection result, and a third table based on the first input, the second input, and the third input, wherein the inspection result includes a result of a consistency comparison based on the first interruption information set and the second interruption information set, the hierarchical line interruption connection result includes a line interruption connection code corresponding to the target multi-level, and the third table includes an interruption mapping table obtained by updating the first table based on the second table.

15. An electronic device, comprising: processor and memory, Wherein, a computer program is stored in the memory, and when the computer program is executed by the processor, the method according to any one of claims 1 to 13 is implemented.

16. A computer-readable storage medium, wherein: The storage medium stores a computer program, and when the computer program is executed by the processor, the method according to any one of claims 1 to 13 is implemented.

Images