AHB bus bridge with ECC bus function and control method thereof

Abstract

The invention discloses an AHB bus bridge with an ECC bus function and a control method thereof, and the AHB bus bridge comprises an AHB bus module which is used for generating a data operation instruction, obtaining the data operation instruction, determining the type of the data operation instruction, and transmitting transmission data corresponding to the data operation instruction according to the type of the data operation instruction; the error correction and detection module is used for generating corresponding 8-bit ECC (Error Correction Code) data or performing ECC verification on transmission data according to the type of the data operation instruction; and the transmission conversion module is used for converting the data operation instruction into a read command of a corresponding SRAM interface protocol according to the type of the data operation instruction or combining the transmission data and the 8bit ECC data corresponding to the transmission data and then converting the transmission data and the 8bit ECC data into corresponding SRAM interface protocol data. According to the AHB bus bridge with the ECC bus function and the control method of the AHB bus bridge, by optimizing matching between the ECC bit width and the data bit width, waste of the area of a memory is reduced; and the use efficiency of the memory is improved while the data correctness is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of digital electronic technology, and in particular to an AHB bus bridge with an ECC bus function and a control method thereof. Background Art

[0002] In digital system design, bus bridges are used to connect buses with different protocols so that the master and slave devices on different buses can communicate. The AHB bus protocol launched by ARM is widely used in high-performance systems and supports data read and write operations of different widths. In order to ensure the correctness of data during transmission and storage, it is usually necessary to integrate ECC function in the bus bridge. However, traditional ECC implementation methods may lead to waste of memory (such as SRAM) area because the ECC bit width does not match the data bit width. Summary of the invention

[0003] In order to solve the technical problems existing in the background technology, the present invention proposes an AHB bus bridge with ECC bus function and a control method thereof.

[0004] The AHB bus bridge with ECC bus function proposed by the present invention comprises: AHB bus module, used for generating data operation instructions, obtaining data operation instructions, determining the type of data operation instructions, and transmitting the transmission data corresponding to the data operation instructions according to the type of data operation instructions; data operation instructions include Word 32bit write data action, byte 8bit / halfword 16bit write data action, and read data action; transmission data includes Word 32bit write data, byte 8bit / halfword 16bit write data, and read data; The error correction and detection module is used to generate corresponding 8-bit ECC data or perform ECC check on the transmitted data according to the type of data operation instruction; A transmission conversion module, used to convert the data operation instruction into a corresponding SRAM interface protocol read command according to the type of the data operation instruction or to merge the transmission data and the 8-bit ECC data corresponding to the transmission data and convert them into corresponding SRAM interface protocol data; The output module is used to obtain the Mbist control state and write the SRAM interface protocol data into the data storage module based on the Mbist control state. The Mbist control state includes control enable and control disable. The data storage module is used to store the written transmission data and read out the written transmission data according to the read command of the SRAM interface protocol.

[0005] Preferably, the transmitting of the transmission data corresponding to the data operation instruction according to the type of the data operation instruction specifically includes: When the data operation instruction is specifically a Word 32bit write data action, the transmission path is specifically to transmit the data operation instruction and the transmission data to the error correction and detection module; When the data operation instruction is specifically a byte 8bit / halfword 16bit write data action, the transmission path is specifically to transmit the data operation instruction and the transmission data to the error correction and detection module; When the data operation instruction is specifically a data read operation, the transmission path is specifically to transmit the data operation instruction to the transmission conversion module.

[0006] Preferably, the error correction and error detection module specifically includes: The ENC unit is used for generating corresponding 8-bit ECC data when the received data operation instruction is specifically a Word 32-bit write data action, and combining the Word 32-bit write data with the 8-bit ECC data and transmitting them to the transmission conversion module; The DEC unit is used for receiving the read data transmitted by the data storage module when the data operation instruction is specifically a read data action, and performing ECC check on the transmitted data. When an error occurs in the ECC check, an ECC error flag is generated; when the ECC check data is correct, the correct read data is returned to the AHB bus module; The FSM unit is used for, when the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data action, performing a read operation on the data storage module to obtain a group of 32-bit data, performing data replacement on the group of 32-bit data according to a position of the byte 8-bit write data or a position of the halfword 16-bit write data to generate corresponding first-type 32-bit data, and transmitting the first-type 32-bit data to the ENC unit; The ENC unit is further used to generate corresponding 8-bit ECC data according to the first type 32-bit data, and combine the first type 32-bit data and the corresponding 8-bit ECC data and transmit them to the transmission conversion module.

[0007] Preferably, the transmission conversion module specifically includes: An instruction conversion unit, used for converting the data operation instruction into a read command of a corresponding SRAM interface protocol when the data operation instruction is specifically a data read action; A data conversion unit, used for converting the combined transmission data and the 8-bit ECC data corresponding to the transmission data into corresponding SRAM interface protocol data when the data operation instruction is specifically a Word 32-bit write data action; The data conversion unit is also used to convert the merged first type data and the 8-bit ECC data corresponding to the first type data into corresponding SRAM interface protocol data when the data operation instruction is specifically a byte 8-bit / halfword 16-bit data write action.

[0008] Preferably, the step of writing the SRAM interface protocol data into the data storage module based on the Mbist control state specifically includes: When the Mbist control state is specifically control enabled, the SRAM interface protocol data is written into the data storage module after being tested for correctness by the SRAM DFT; When the Mbist control state is specifically control disabled, the SRAM interface protocol data is directly written into the data storage module.

[0009] The present invention provides a control method for an AHB bus bridge with an ECC bus function, which is applied to any of the above-mentioned AHB bus bridges with an ECC bus function. The control method comprises the following steps: S1. Obtain a data operation instruction, determine the type of the data operation instruction, and transmit the transmission data corresponding to the data operation instruction according to the type of the data operation instruction. The data operation instruction includes a Word 32-bit write data action, a byte8-bit / halfword 16-bit write data action, and a read data action; S2. Generate corresponding 8-bit ECC data or perform ECC check on the transmitted data according to the type of data operation instruction; S3, converting the data operation instruction into a corresponding SRAM interface protocol read command according to the type of the data operation instruction or converting the result of merging the transmission data and the 8-bit ECC data corresponding to the transmission data into corresponding SRAM interface protocol data; S4. Obtain the Mbist control state, and write the SRAM interface protocol data into the data storage module based on the Mbist control state. The Mbist control state includes control enable and control disable.

[0010] Preferably, when the data operation instruction is specifically a Word 32bit write data action, step S2 specifically includes: Generate 8-bit ECC data corresponding to the Word 32-bit write data, and merge the Word 32-bit write data with the corresponding 8-bit ECC data; When the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data action, step S2 specifically includes: performing a read operation on the data storage module to obtain a group of 32-bit data, performing data replacement on the group of 32-bit data according to the position of the byte 8-bit write data or the position of the halfword 16-bit write data to generate corresponding first-type 32-bit data, generating corresponding 8-bit ECC data according to the first-type 32-bit data, and merging the first-type 32-bit data with the corresponding 8-bit ECC data; When the data operation instruction is specifically a data read action, step S2 specifically includes: performing ECC check on the transmitted data, and when an ECC check error occurs, generating an ECC error flag; when the ECC check data is correct, executing step S3.

[0011] Preferably, when the data operation instruction is specifically a Word 32bit write data action, step S3 specifically includes: The result of merging Word 32-bit write data and corresponding 8-bit ECC data is converted into corresponding SRAM interface protocol data; When the data operation instruction is specifically a byte 8bit / halfword 16bit write data action, step S3 specifically includes: converting the result of combining the first type 32bit data and the corresponding 8bitECC data into corresponding SRAM interface protocol data; When the data operation instruction is specifically a data read action, step S3 specifically includes: converting the data read action into a corresponding read command of the SRAM interface protocol.

[0012] Preferably, when the data operation instruction is specifically a Word 32bit write data action or a byte 8bit / halfword 16bit write data action, step S4 specifically includes: When the Mbist control state is specifically control enabled, the SRAM interface protocol data is written into the data storage module after being tested for correctness by the SRAM DFT; When the Mbist control state is specifically control disabled, the SRAM interface protocol data is directly written into the data storage module.

[0013] In the present invention, the proposed AHB bus bridge with ECC bus function and its control method obtain data operation instructions, determine the type of data operation instructions, and transmit the transmission data corresponding to the data operation instructions according to the type of data operation instructions, the data operation instructions include Word 32bit write data action, byte 8bit / halfword 16bit write data action, and read data action; according to the type of data operation instructions, generate corresponding 8bitECC data or perform ECC check on the transmission data; according to the type of data operation instructions, convert the data operation instructions into the corresponding SRAM interface protocol read command or convert the result after the transmission data and the 8bitECC data corresponding to the transmission data are merged into the corresponding SRAM interface protocol data; obtain the Mbist control state, and write the SRAM interface protocol data into the data storage module based on the Mbist control state, the Mbist control state includes control enable and control disable. By optimizing the matching of ECC bit width and data bit width, the waste of memory area is reduced, the correctness of data is guaranteed, and the use efficiency of memory is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 A schematic diagram of the system architecture of the AHB bus bridge with ECC bus function proposed by the present invention; Figure 2 The figure is a schematic diagram of the working process structure of the AHB bus bridge control method with ECC bus function proposed by the present invention. DETAILED DESCRIPTION

[0015] Reference Figure 1 and Figure 2 The AHB bus bridge with ECC bus function proposed by the present invention comprises: The AHB bus module is used to generate data operation instructions, obtain data operation instructions, determine the type of data operation instructions, and transmit the transmission data corresponding to the data operation instructions according to the type of data operation instructions; the data operation instructions include Word 32bit write data actions, byte 8bit / halfword 16bit write data actions, and read data actions; the transmission data includes Word 32bit write data, byte 8bit / halfword 16bit write data, and read data.

[0016] In this embodiment, the transmission data corresponding to the data operation instruction is transmitted according to the type of the data operation instruction, specifically including: When the data operation instruction is specifically a Word 32bit write data action, the transmission path is specifically to transmit the data operation instruction and the transmission data to the error correction and detection module; When the data operation instruction is specifically a byte 8bit / halfword 16bit write data action, the transmission path is specifically to transmit the data operation instruction and the transmission data to the error correction and detection module; When the data operation instruction is specifically a data read operation, the transmission path is specifically to transmit the data operation instruction to the transmission conversion module.

[0017] The error correction module is used to generate corresponding 8-bit ECC data or perform ECC check on the transmitted data according to the type of data operation instruction. ECC (Error Checking and Correcting) means error checking and correction.

[0018] In this embodiment, the error correction and error detection module specifically includes: The ENC unit is used to generate corresponding 8-bit ECC data when the received data operation instruction is specifically a Word 32-bit write data action, and combine the Word 32-bit write data with the 8-bit ECC data and transmit them to the transmission conversion module. The ENC unit represents an encoding unit.

[0019] The DEC unit is used to receive the read data transmitted by the data storage module when the data operation instruction is specifically a read data action, and perform ECC check on the transmitted data. When an error occurs in the ECC check, an ECC error flag is generated; when the ECC check data is correct, the correct read data is returned to the AHB bus module. The DEC unit represents a decoding unit.

[0020] The FSM unit is used for performing a read operation on the data storage module to obtain a group of 32-bit data when the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data action, performing data replacement on the group of 32-bit data according to the position of the byte 8-bit write data or the position of the halfword 16-bit write data to generate corresponding first-type 32-bit data, and transmitting the first-type 32-bit data to the ENC unit. The FSM unit represents a finite state machine unit.

[0021] The ENC unit is further used to generate corresponding 8-bit ECC data according to the first type 32-bit data, and combine the first type 32-bit data and the corresponding 8-bit ECC data and transmit them to the transmission conversion module.

[0022] The transmission conversion module is used to convert the data operation instruction into the corresponding SRAM interface protocol read command according to the type of the data operation instruction or to merge the transmission data and the 8-bit ECC data corresponding to the transmission data and convert them into the corresponding SRAM interface protocol data.

[0023] In this embodiment, the transmission conversion module specifically includes: The instruction conversion unit is used to convert the data operation instruction into a corresponding read command of the SRAM interface protocol when the data operation instruction is specifically a data read action.

[0024] The data conversion unit is used to convert the combined transmission data and the 8-bit ECC data corresponding to the transmission data into corresponding SRAM interface protocol data when the data operation instruction is specifically a Word 32-bit write data action.

[0025] The data conversion unit is also used to convert the merged first type data and the 8-bit ECC data corresponding to the first type data into corresponding SRAM interface protocol data when the data operation instruction is specifically a byte 8-bit / halfword 16-bit data write action.

[0026] The output module is used to obtain the Mbist control state and write the SRAM interface protocol data into the data storage module based on the Mbist control state. The Mbist control state includes control enable and control disable.

[0027] In this embodiment, the SRAM interface protocol data is written into the data storage module based on the Mbist control state, specifically including: when the Mbist control state is specifically control enabled, the SRAM interface protocol data is written into the data storage module after the SRAM DFT correctness test. When the Mbist control state is specifically control disabled, the SRAM interface protocol data is directly written into the data storage module.

[0028] In this embodiment, the SRAM DFT correctness test is performed through the Mbist (Memory Bulk-in Self-Test) control module. In addition to the DFT machine test, the module also supports the user to perform correctness test on the SRAM using software. The module enables data transmission that cannot complete normal functions. The module is only used to test whether there are defects in the SRAM production process alone.

[0029] The data storage module is used to store the written transmission data and read out the written transmission data according to the read command of the SRAM interface protocol.

[0030] The data writing process is as follows: 1) If a Word 32bit data write action occurs on the AHB bus, the data will first enter the ENC unit to generate 8bit ECC data. The Word 32bit and 8bit ECC results are merged together and transmitted to the conversion module, which converts the AHB interface protocol data into SRAM interface protocol data. If the Mbist control module is not enabled, the data is directly output to the inside of the data storage module through the transmission conversion module. At this time, the SRAM is written through the AHB interface and the ECC action is added. If the Mbist control module is enabled, the data of the data storage module comes from the Mbist control module, and the data can be a random number, all 0, or all 1. The bus bridge we designed also supports SRAM Mbist test passing.

[0031] 2) If a byte 8bit / halfword 16bit write operation occurs on the AHB bus, the SRAM needs to be read first, and the 32-bit data is read out. The byte 8bit position (4 byte positions in the 32-bit data) or halfword 16bit (2 halfword positions in the 32-bit data) to be written is replaced to generate new 32-bit data, and the new 32-bit data is used to generate a new 8-bit ECC result. The subsequent writing process is the same as the 32-bit writing process.

[0032] The data read process is as follows: If a data read action occurs on the AHB bus, the AHB bus read command, read address and other information will be converted into a read command of the SRAM interface protocol through the transmission conversion module. At this time, the SRAM will reply with 40-bit data (32-bit valid data + 8-bit ECC data). The 40-bit data is ECC-checked by the DEC unit. If an error occurs, an ECC Error flag will be generated. Otherwise, the data is correct and the correct read data will be returned to the AHB bus.

[0033] In this embodiment, the AHB bus bridge needs to read first and then write when performing Byte / halfword write operation, which takes 3 cycles, 1 cycle more than the normal byte write operation (2 cycles). If it is a Memory write Byte / halfword operation, it takes 4 cycles, 2 cycles more than the normal byte write operation (2 cycles). This saves the Memory area and has the ECC function to ensure the correctness of the data.

[0034] Reference Figure 1 and Figure 2The present invention proposes a control method for an AHB bus bridge with an ECC bus function, which is applied to any of the above-mentioned AHB bus bridges with an ECC bus function, and the control method comprises the following steps: S1. Obtain data operation instructions, determine the type of data operation instructions, and transmit the transmission data corresponding to the data operation instructions according to the type of data operation instructions. The data operation instructions include Word 32bit write data action, byte8bit / halfword 16bit write data action, and read data action.

[0035] S2. Generate corresponding 8-bit ECC data or perform ECC check on the transmitted data according to the type of data operation instruction.

[0036] In this embodiment, when the data operation instruction is specifically a Word 32bit write data action, step S2 specifically includes: Generate 8-bit ECC data corresponding to the Word 32-bit write data, and merge the Word 32-bit write data with the corresponding 8-bit ECC data; When the data operation instruction is specifically a byte 8bit / halfword 16bit write data action, step S2 specifically includes: performing a read operation on the data storage module to obtain a group of 32-bit data, performing data replacement on the group of 32-bit data according to the position of the byte 8bit write data or the position of the halfword 16bit write data to generate corresponding first type 32-bit data, generating corresponding 8-bitECC data according to the first type 32-bit data, and merging the first type 32-bit data with the corresponding 8-bitECC data.

[0037] When the data operation instruction is specifically a data read action, step S2 specifically includes: performing ECC check on the transmitted data, and when an ECC check error occurs, generating an ECC error flag; when the ECC check data is correct, executing step S3.

[0038] S3. Convert the data operation instruction into a corresponding SRAM interface protocol read command according to the type of the data operation instruction or convert the result of combining the transmission data and the 8-bit ECC data corresponding to the transmission data into corresponding SRAM interface protocol data.

[0039] In this embodiment, when the data operation instruction is specifically a Word 32bit write data action, step S3 specifically includes: The result of merging Word 32-bit write data and corresponding 8-bit ECC data is converted into corresponding SRAM interface protocol data; When the data operation instruction is specifically a byte 8bit / halfword 16bit write data action, step S3 specifically includes: converting the result of combining the first type 32bit data and the corresponding 8bitECC data into corresponding SRAM interface protocol data; When the data operation instruction is specifically a data read action, step S3 specifically includes: converting the data read action into a corresponding read command of the SRAM interface protocol.

[0040] S4. Obtain the Mbist control state, and write the SRAM interface protocol data into the data storage module based on the Mbist control state. The Mbist control state includes control enable and control disable.

[0041] In this embodiment, when the data operation instruction is specifically a Word 32bit write data action or a byte 8bit / halfword 16bit write data action, step S4 specifically includes: when the Mbist control state is specifically control enabled, the SRAM interface protocol data is written into the data storage module after passing the SRAM DFT correctness test; when the Mbist control state is specifically control disabled, the SRAM interface protocol data is directly written into the data storage module.

[0042] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. AHB bus bridge with ECC bus function, characterized in that: include: AHB bus module, used for generating data operation instructions, obtaining data operation instructions, determining the type of data operation instructions, and transmitting the transmission data corresponding to the data operation instructions according to the type of data operation instructions; data operation instructions include Word 32bit write data action, byte 8bit / halfword 16bit write data action, and read data action; transmission data includes Word 32bit write data, byte 8bit / halfword 16bit write data, and read data; The error correction and detection module is used to generate corresponding 8-bit ECC data or perform ECC check on the transmitted data according to the type of data operation instruction; A transmission conversion module, used to convert the data operation instruction into a corresponding SRAM interface protocol read command according to the type of the data operation instruction or to merge the transmission data and the 8-bit ECC data corresponding to the transmission data and convert them into corresponding SRAM interface protocol data; The output module is used to obtain the Mbist control state and write the SRAM interface protocol data into the data storage module based on the Mbist control state. The Mbist control state includes control enable and control disable. The data storage module is used to store the written transmission data and read out the written transmission data according to the read command of the SRAM interface protocol.

2. The AHB bus bridge with ECC bus function according to claim 1, characterized in that: The transmitting of the transmission data corresponding to the data operation instruction according to the type of the data operation instruction specifically includes: When the data operation instruction is specifically a Word 32bit write data action, the transmission path is specifically to transmit the data operation instruction and the transmission data to the error correction and detection module; When the data operation instruction is specifically a byte 8bit / halfword 16bit write data action, the transmission path is specifically to transmit the data operation instruction and the transmission data to the error correction and detection module; When the data operation instruction is specifically a data read operation, the transmission path is specifically to transmit the data operation instruction to the transmission conversion module.

3. The AHB bus bridge with ECC bus function according to claim 1, characterized in that: The error correction and detection module specifically includes: The ENC unit is used for generating corresponding 8-bit ECC data when the received data operation instruction is specifically a Word 32-bit write data action, and combining the Word 32-bit write data with the 8-bit ECC data and transmitting them to the transmission conversion module; The DEC unit is used to receive the read data transmitted by the data storage module when the data operation instruction is specifically a read data action, and perform ECC check on the transmitted data. When an error occurs in the ECC check, an ECC error flag is generated; when the ECC check data is correct, the correct read data is returned to the AHB bus module; The FSM unit is used for, when the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data action, performing a read operation on the data storage module to obtain a group of 32-bit data, performing data replacement on the group of 32-bit data according to a position of the byte 8-bit write data or a position of the halfword 16-bit write data to generate corresponding first-type 32-bit data, and transmitting the first-type 32-bit data to the ENC unit; The ENC unit is further used to generate corresponding 8-bit ECC data according to the first type 32-bit data, and combine the first type 32-bit data and the corresponding 8-bit ECC data and transmit them to the transmission conversion module.

4. The AHB bus bridge with ECC bus function according to claim 3, characterized in that: The transmission conversion module specifically includes: An instruction conversion unit, used for converting the data operation instruction into a read command of a corresponding SRAM interface protocol when the data operation instruction is specifically a data read action; A data conversion unit, used for converting the combined transmission data and the 8-bit ECC data corresponding to the transmission data into corresponding SRAM interface protocol data when the data operation instruction is specifically a Word 32-bit write data action; The data conversion unit is also used to convert the merged first type data and the 8-bit ECC data corresponding to the first type data into corresponding SRAM interface protocol data when the data operation instruction is specifically a byte 8-bit / halfword 16-bit data write action.

5. The AHB bus bridge with ECC bus function according to claim 1, characterized in that: The step of writing the SRAM interface protocol data into the data storage module based on the Mbist control state specifically includes: When the Mbist control state is specifically control enabled, the SRAM interface protocol data is written into the data storage module after being tested for correctness by the SRAM DFT; When the Mbist control state is specifically control disabled, the SRAM interface protocol data is directly written into the data storage module.

6. AHB bus bridge control method with ECC bus function, characterized in that: The control method is applied to the AHB bus bridge with ECC bus function as claimed in any one of claims 1 to 5, and the control method comprises the following steps: S1. Obtain a data operation instruction, determine the type of the data operation instruction, and transmit the transmission data corresponding to the data operation instruction according to the type of the data operation instruction. The data operation instruction includes a word 32-bit write data action, a byte 8-bit / halfword 16-bit write data action, and a read data action; S2. Generate corresponding 8-bit ECC data or perform ECC check on the transmitted data according to the type of data operation instruction; S3, converting the data operation instruction into a corresponding SRAM interface protocol read command according to the type of the data operation instruction or converting the result of merging the transmission data and the 8-bit ECC data corresponding to the transmission data into corresponding SRAM interface protocol data; S4. Obtain the Mbist control state, and write the SRAM interface protocol data into the data storage module based on the Mbist control state. The Mbist control state includes control enable and control disable.

7. The AHB bus bridge control method with ECC bus function according to claim 6, characterized in that: When the data operation instruction is specifically a Word 32bit write data action, step S2 specifically includes: Generate 8-bit ECC data corresponding to the Word 32-bit write data, and merge the Word 32-bit write data with the corresponding 8-bit ECC data; When the data operation instruction is specifically a byte 8-bit / halfword 16-bit write data action, step S2 specifically includes: performing a read operation on the data storage module to obtain a group of 32-bit data, performing data replacement on the group of 32-bit data according to the position of the byte 8-bit write data or the position of the halfword 16-bit write data to generate corresponding first-type 32-bit data, generating corresponding 8-bit ECC data according to the first-type 32-bit data, and merging the first-type 32-bit data with the corresponding 8-bit ECC data; When the data operation instruction is specifically a data read action, step S2 specifically includes: performing ECC check on the transmitted data, and when an ECC check error occurs, generating an ECC error flag; when the ECC check data is correct, executing step S3.

8. The AHB bus bridge control method with ECC bus function according to claim 7, characterized in that: When the data operation instruction is specifically a Word 32bit write data action, step S3 specifically includes: The result of merging Word 32-bit write data and corresponding 8-bit ECC data is converted into corresponding SRAM interface protocol data; When the data operation instruction is specifically a byte 8bit / halfword 16bit write data action, step S3 specifically includes: converting the result of combining the first type 32bit data and the corresponding 8bitECC data into corresponding SRAM interface protocol data; When the data operation instruction is specifically a data read action, step S3 specifically includes: converting the data read action into a corresponding read command of the SRAM interface protocol.

9. The AHB bus bridge control method with ECC bus function according to claim 8, characterized in that: When the data operation instruction is specifically a Word 32-bit write data action or a byte 8-bit / halfword 16-bit write data action, step S4 specifically includes: When the Mbist control state is specifically control enabled, the SRAM interface protocol data is written into the data storage module after being tested for correctness by the SRAM DFT; When the Mbist control state is specifically control disabled, the SRAM interface protocol data is directly written into the data storage module.

Images