Storage device including high bandwidth memory, CXL storage device, system-in-package, and system-on-chip

Abstract

A compute fast link (CXL) storage device may include a high bandwidth memory (HBM) including a CXL base die and a plurality of core dies sequentially stacked on the CXL base die. The CXL base die may include an HBM interface intellectual property (IP) core configured to translate data transmission and reception between the plurality of core dies and a dynamic random access memory (DRAM) in accordance with a CXL specification, and the HBM interface IP core corresponds to a non-Joint Electronic Equipment Engineering Committee (JEDEC) standard.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0131175 filed in the Korean Intellectual Property Office on September 27, 2023, and Korean Patent Application No. 10-2024-0033323 filed in the Korean Intellectual Property Office on March 8, 2024, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] Apparatuses, methods, and systems consistent with example embodiments of the present application relate to storage devices, compute express link (CXL) storage devices, system-level packages, and systems-on-chips, and more particularly, to storage devices, CXL storage devices, system-level packages, and systems-on-chips including high bandwidth memory (HBM). Background Art

[0003] A device configured to process data can perform various operations by accessing a memory. For example, the device can process data read from the memory and write the processed data to the memory. Depending on the performance and functionality required by the system, various devices that communicate with each other through links that provide high bandwidth and low latency may be included in the system. The memory included in the system may be shared and accessed by two or more devices. Therefore, the performance of the system may depend not only on the operating speed of each device, but also on the communication efficiency between the devices and the time it takes to access the memory. Summary of the invention

[0004] One or more embodiments of the present disclosure provide a storage system, a storage device, and a method of operating the storage system and the storage device for reducing latency.

[0005] According to one aspect of the present disclosure, a compute express link (CXL) storage device may include: a high bandwidth memory (HBM), including a CXL base die and a plurality of core dies sequentially stacked on the CXL base die, wherein the CXL base die may include: an HBM interface intellectual property (IP) core configured to convert data transmission and reception between the plurality of core dies and a dynamic random access memory (DRAM) according to a CXL specification, and the HBM interface IP core corresponds to a non-Joint Electron Device Engineering Council (JEDEC) standard.

[0006] According to another aspect of the present disclosure, a system-in-package (SiP) may include: an application-specific integrated circuit (ASIC) die; a compute express link (CXL) base die connected to a high bandwidth memory (HBM) including a plurality of core dies through through silicon vias (TSVs); and an interposer connecting the ASIC die to the CXL base die, wherein the CXL base die includes an HBM interface intellectual property (IP) core to convert data transmission and reception between the plurality of core dies and a dynamic random access memory (DRAM) in accordance with a CXL specification, and the HBM interface IP core corresponds to a non-Joint Electron Device Engineering Council (JEDEC) standard.

[0007] According to another aspect of the present disclosure, a storage device may include: a high bandwidth memory (HBM), including a base die and a plurality of core dies stacked sequentially on the base die, wherein the base die includes: an HBM interface intellectual property (IP) core, configured to convert data transmission and reception between the plurality of core dies and a dynamic random access memory (DRAM) according to a peripheral component interconnect express (PCIe) interface, a universal chiplet interconnect express (UCIe) interface, and a die-to-die (D2D) interface, and the HBM interface IP core corresponds to a non-Joint Electron Device Engineering Council (JEDEC) standard. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Embodiments of the present inventive concept will be more clearly understood from the following detailed description in conjunction with the accompanying drawings, in which:

[0009] Figure 1A A main storage device according to a comparative example is shown;

[0010] Figure 1B A system on chip (SoC) according to a comparative example is shown;

[0011] Figure 2 is a block diagram illustrating a system according to one or more embodiments;

[0012] Figure 3 A Compute Express Link (CXL) storage device according to a comparative example is shown;

[0013] Figure 4 A CXL storage device according to one or more embodiments is shown;

[0014] Figure 5 A semiconductor device according to one or more embodiments is shown;

[0015] Fig. 6A and Figure 6B shows a CXL-based die according to one or more embodiments;

[0016] Fig. 7AA primary storage device according to one or more embodiments is shown;

[0017] Figure 7B A primary storage device according to one or more embodiments is shown;

[0018] Figure 8 A SoC according to one or more embodiments is shown;

[0019] Fig.9A , Fig. 9B and Fig. 9C shows a semiconductor device layout according to one or more embodiments;

[0020] Fig.10 is a block diagram illustrating an electronic device including a die-to-die (D2D) interface according to an embodiment; and

[0021] Fig.11 is a block diagram illustrating a data center including a CXL storage device according to one or more embodiments. DETAILED DESCRIPTION

[0022] Hereinafter, embodiments are described in detail with reference to the accompanying drawings.

[0023] Figure 1A A main storage device 101 according to a comparative example is shown.

[0024] refer to Figure 1A , the main memory device 101 may include a high bandwidth memory (HBM) 110 , a first low power double data rate physical layer interface (LPDDR PHY) 120 , a second LPDDR PHY 130 , a memory controller 140 , a bus 150 , a communication interface controller 160 , and a communication interface block 170 .

[0025] HBM 110 may include a stacked plurality of memory dies to which data is written or read in parallel through a plurality of channels. In some embodiments, HBM may include a plurality of dynamic random access memory (DRAM) dies and may be referred to as HBM DRAM.

[0026] The first LPDDR PHY 120 may include a plurality of input / output (I / O) circuits to access the HBM 110. For example, the first LPDDR PHY 120 may include one or more ports for communicating with the HBM 110. The first LPDDR PHY 120 may include a physical layer or an electrical layer and a logical layer provided for signals, frequencies, timings, driving, detailed operating parameters, and functions to facilitate communication between the HBM 110 and the memory controller 140. For example, the first LPDDR PHY 120 may include a hard macro (HM) block 121 configured to receive a signal from the HBM 110 and electrically convert the signal, and a soft macro (SM) block 123 configured to convert the output of the HM block 121 into a format suitable for the second LPDDR PHY 130. The first LPDDR PHY 120 may perform memory interface operations, such as selecting rows and columns corresponding to memory cells, writing data to the memory cells, and reading the written data. The first LPDDR PHY 120 may support the Joint Electron Device Engineering Council (JEDEC) standard.

[0027] The second LPDDR PHY 130 may include a plurality of I / O circuits to interface with the communication interface block 170. For example, the second LPDDR PHY 130 may include a physical layer or an electrical layer and a logical layer provided for signals, frequencies, timings, driving, detailed operating parameters, and functions required for communication based on the communication interface block 170. For example, the second LPDDR PHY 130 may include an HM block 131 configured to receive a signal from the first LPDDR PHY 120 and electrically convert the signal, and an SM block 133 configured to convert an output of the HM block 131 so that the converted output is transmitted to the memory controller 140. The second LPDDR PHY 130 may support the JEDEC standard.

[0028] The memory controller 140 may control the overall operation of the main memory device 101. For example, the memory controller 140 may receive the output of the second LPDDR PHY 130 and provide read data to the communication interface block 170 via the bus 150, or receive the output of the communication interface block 170 via the bus 150 and provide written data to the HBM 110 via the second LPDDR PHY 130 and the first LPDDR PHY 120.

[0029] The communication interface block 170 may provide communication interfaces, such as a die-to-die (D2D) interface, a peripheral component interconnect express (PCIe) interface, and a universal chiplet interconnect express (UCIe) interface. The communication interface controller 160 may control the communication interfaces (e.g., D2D, PCIe, and UCIe interfaces) to manage communications between different components within the system.

[0030] The main memory device 101 as described above in the comparative example may perform communication protocol and / or interface conversion according to the JEDEC standard twice. For example, the main memory device 101 may perform one communication protocol and / or interface conversion in the first LPDDR PHY 120 to access the HBM 110, and perform one more communication protocol and / or interface conversion in the second LPDDR PHY 130 to align with multiple communication protocols. However, because the communication protocol and / or interface conversion needs to be performed twice, the storage delay of the HBM 110 may increase.

[0031] Figure 1B A system on chip (SoC) according to a comparative example is shown.

[0032] refer to Figure 1B , a system on chip (SoC) 102 may include an HBM 112 including a plurality of core dies, a first LPDDR PHY 120 , a second LPDDR PHY 130 , an HBM controller 142 , a bus 152 , and a central processing unit (CPU) 162 .

[0033] HBM 112 may include a stacked plurality of memory dies to which data is written or read in parallel through a plurality of channels. In some embodiments, HBM may include a plurality of DRAM dies and may be referred to as HBM DRAM.

[0034] The first LPDDR PHY 120 may include a plurality of I / O circuits to access the HBM 112. For example, the first LPDDR PHY 120 may include one or more ports for communicating with the HBM 112. The first LPDDR PHY 120 may include a physical layer or an electrical layer and a logical layer provided for signals, frequencies, timings, driving, detailed operating parameters, and functions to facilitate communication between the HBM 112 and the HBM controller 142. For example, the first LPDDR PHY 120 may include an HM block 121 configured to receive a signal from the HBM 112 and electrically convert the signal, and an SM block 123 configured to convert the output of the HM block 121 into a format suitable for the second LPDDR PHY 130. The first LPDDR PHY 120 may perform memory interface operations, such as selecting rows and columns corresponding to memory cells, writing data to memory cells, and reading written data. The first LPDDR PHY 120 may support the JEDEC standard.

[0035] The second LPDDR PHY 130 may include a plurality of I / O circuits to interface with the HBM controller 142. For example, the second LPDDR PHY 130 may include a physical layer or an electrical layer and a logical layer provided for signals, frequencies, timings, drivers, detailed operating parameters, and functions required for communication based on the HBM controller 142. For example, the second LPDDR PHY 130 may include an HM block 131 configured to receive a signal from the first LPDDR PHY 120 and electrically convert the signal, and an SM block 133 configured to convert an output of the HM block 131 so that the converted output is transmitted to the HBM controller 142. The second LPDDR PHY 130 may support the JEDEC standard.

[0036] The HBM controller 142 may perform protocol conversion for communication with the main memory. For example, the HBM controller 142 may be based on a double data rate (DDR) PHY interface (DFI) protocol. The HBM controller 142 may convert the DFI protocol to an advanced microcontroller bus architecture (AMBA) protocol supported by the bus 152 and the CPU 162. The CPU 162 may perform various calculations using data received from the HBM controller 142 via the bus 152.

[0037] The above-mentioned SoC 102 according to the comparative example may perform communication protocol and / or interface conversion according to the JEDEC standard twice. For example, the SoC 102 may perform a communication protocol and / or interface conversion once in the first LPDDR PHY 120 to access the HBM 112, and perform a communication protocol and / or interface conversion again in the second LPDDR PHY 130 to align with multiple communication protocols. However, because the communication protocol and / or interface conversion needs to be performed twice, the storage delay of the HBM 112 may increase.

[0038] Figure 2 is a block diagram illustrating a system 200 according to one or more embodiments.

[0039] refer to Figure 2 , the system 200 may be a computing system (or a component included in a computing system) including a device 210 and a host processor 220 that communicate with each other. For example, the system 200 may be included in a fixed computing system (e.g., a desktop computer, a server, or an information kiosk), or in a portable computing system (e.g., a laptop, a mobile phone, or a wearable device). In addition, in some embodiments, the system 200 may be included in a SoC or a system-in-package (SiP), in which the device 210 and the host processor 220 are implemented in one chip or package.

[0040] like Figure 2As shown, system 200 may include device 210, host processor 220, device memory 230, and host memory 240. According to various embodiments, system 200 may not include device memory 230. Figure 2 , device 210 and host processor 220 can communicate with each other via link 250, and send or receive messages / data to or from each other through link 250.

[0041] Although the embodiments are described based on the CXL specification reference link 250 supporting the Compute Express Link (CXL) protocol, the embodiments are not limited thereto, and the device 210 and the host processor 220 may communicate with each other based on a coherent interconnect technology (e.g., XBus protocol, NVLink protocol, Infinity Fabric protocol, Cache Coherent Interconnect for Accelerators (CCIX) protocol, and Coherent Accelerator Processor Interface (CAPI)).

[0042] In some embodiments, the link 250 may support multiple protocols and transmit messages and / or data based on multiple protocols. For example, the link 250 may support CXL protocols including non-coherent protocols (e.g., CXL.io), coherent protocols (e.g., CXL.cache), and memory access protocols (or memory protocols) (e.g., CXL.mem). In some embodiments, the link 250 may support protocols such as the Peripheral Component Interconnect (PCI) protocol, the PCIe protocol, the Universal Serial Bus (USB) protocol, and the Serial Advanced Technology Attachment (SATA) protocol. In this specification, the protocols supported by the link 250 may be referred to as interconnect protocols.

[0043] Device 210 may be an adapted component configured to meet a specific purpose of host processor 220. In some embodiments, in accordance with CXL Specification 2.0, device 210 may be configured to operate as an accelerator to provide support for the functionality outlined in the CXL Specification. For example, software executed on host processor 220 may offload at least a portion of a computing task and / or an I / O task to device 210. In some embodiments, device 210 may include at least one of a programmable component such as a graphics processing unit (GPU) and a neural processing unit (NPU), a component such as an intellectual property (IP) core configured to provide fixed functionality, and a reconfigurable component such as a field programmable gate array (FPGA). Figure 2 As shown, device 210 may include a physical layer 211 , a multi-protocol multiplexer 212 , an interface circuit 213 , and an accelerator circuit 214 , and communicate with a device memory 230 .

[0044] Accelerator circuitry 214 may perform useful functions provided by device 210 to host processor 220 and may be referred to as accelerator logic. Figure 2 As shown, when device memory 230 is included in system 200, accelerator circuit 214 can communicate with device memory 230 based on a protocol independent of link 250 (ie, a device-specific protocol). Figure 2 As shown, accelerator circuit 214 may communicate with host processor 220 via interface circuit 213 using a number of protocols.

[0045] The interface circuit 213 may determine one of a plurality of protocols based on messages and / or data for communication between the accelerator circuit 214 and the host processor 220. The interface circuit 213 may be connected to at least one protocol queue included in the multi-protocol multiplexer 212, and exchange messages and / or data with the host processor 220 via the at least one protocol queue. In some embodiments, the interface circuit 213 and the multi-protocol multiplexer 212 may be integrated into one component. In some embodiments, the multi-protocol multiplexer 212 may include a plurality of protocol queues corresponding to a plurality of protocols supported by the link 250, respectively. In addition, in some embodiments, the multi-protocol multiplexer 212 may arbitrate between communications based on different protocols and provide the selected communication to the physical layer 211. In some embodiments, the physical layer 211 may be connected to the physical layer 221 of the host processor 220 via a single interconnect, bus, trace, etc.

[0046] Host processor 220 may be a main processor (eg, a CPU) of system 200, and in some embodiments, host processor 220 may operate in accordance with the CXL specification. Figure 2 As shown, the host processor 220 may be connected to the host memory 240 and may include a physical layer 221 , a multi-protocol multiplexer 222 , an interface circuit 223 , a coherency / cache circuit 224 , a bus circuit 225 , at least one core 226 , and an I / O device 227 .

[0047] At least one core 226 may execute instructions and may be connected to coherence / cache circuitry 224. Coherence / cache circuitry 224 may include a cache hierarchy and may be referred to as coherence / cache logic. Figure 2As shown, the consistency / cache circuit 224 can communicate with at least one core 226 and the interface circuit 223. For example, the consistency / cache circuit 224 can implement communication based on two or more protocols including a consistency protocol and a memory access protocol. In some embodiments, the consistency / cache circuit 224 may include a direct memory access (DMA) circuit. The I / O device 227 may be used to communicate with the bus circuit 225. For example, the bus circuit 225 may be a PCIe logic, and the I / O device 227 may be a PCIe I / O device.

[0048] The interface circuit 223 may enable communication between components of the host processor 220 (e.g., the coherence / cache circuit 224 and the bus circuit 225) and the device 210. In some embodiments, the interface circuit 223 may enable communication of messages and / or data between components of the host processor 220 and the device 210 based on a plurality of protocols (e.g., a non-coherent protocol, a coherent protocol, and a memory protocol). For example, the interface circuit 223 may determine one of a plurality of protocols based on messages and / or data for communication between components of the host processor 220 and the device 210.

[0049] The multi-protocol multiplexer 222 may include at least one protocol queue. The interface circuit 223 may be connected to the at least one protocol queue and may exchange messages and / or data with the device 210 via the at least one protocol queue. In some embodiments, the interface circuit 223 and the multi-protocol multiplexer 222 may be integrated into one component. In some embodiments, the multi-protocol multiplexer 222 may include a plurality of protocol queues corresponding to a plurality of protocols supported by the link 250, respectively. In addition, in some embodiments, the multi-protocol multiplexer 222 may arbitrate between communications based on different protocols and provide the selected communications to the physical layer 221.

[0050] In some embodiments, the host processor 220 may execute hierarchical software including an operating system (OS) and / or applications executed on the OS, and access the host memory 240 and / or the device memory 230 based on virtual memory. The host processor 220 may be connected to the host memory 240 via a D2D interface, and the device 210 may also be connected to the device memory 230 via the D2D interface.

[0051] As described below with reference to the accompanying drawings, the D2D interface may support a CXL protocol or a UCIe protocol for communication between a first die and a second die. The first die may include a first interconnect interface that provides a first channel configured to communicate with the second die as a D2D interface. The second die may include a plurality of connected chiplet dies configured to communicate with the first die, wherein each of the plurality of connected chiplet dies may include a second interconnect interface that provides a second channel as a D2D interface. Each of the first interconnect interface and the second interconnect interface may include a logic circuit that indicates a correlation between the number of connected chiplet dies connected to the first channel and a connected signal pin among a plurality of signal pins of each connected chiplet die. According to one or more embodiments, based on a mapping table of the logic circuit, a large number of chiplet memories implemented by a relatively small number of connected signal pins (e.g., command / address (CA) pins and data (DQ) pins) may provide a high-capacity memory solution for the D2D interface. According to another embodiment, based on a mapping table of a logic circuit, a small number of chiplet memories implemented by a relatively large number of connected CA pins and connected DQ pins can provide a high-speed and high-performance solution for a D2D interface.

[0052] Figure 3 A CXL storage device 300 according to a comparative example is shown.

[0053] refer to Figure 3 , the CXL memory device 300 may include a DRAM 310 , a first LPDDR PHY 320 , a second LPDDR PHY 330 , a memory controller 340 , a bus 350 , and a CXL interface circuit 360 .

[0054] The first LPDDR PHY 320 may include a plurality of I / O circuits to access the DRAM 310, and, for example, the first LPDDR PHY 320 may include one or more ports for communicating with the DRAM 310. The first LPDDR PHY 320 may include a physical layer or an electrical layer and a logical layer provided for signals, frequencies, timings, driving, detailed operating parameters, and functions to facilitate communication between the DRAM 310 and the CXL interface circuit 360. For example, the first LPDDR PHY 320 may include an HM block 321 configured to receive a signal from the DRAM 310 and electrically convert the signal, and an SM block 323 configured to convert an output of the HM block 321 into a format suitable for the second LPDDR PHY 330. The first LPDDR PHY 320 may perform memory interface operations, such as selecting a row and a column corresponding to a memory cell, writing data to the memory cell, and reading the written data. The first LPDDR PHY 320 may support the JEDEC standard.

[0055] The second LPDDR PHY 330 may include a plurality of I / O circuits to interface or align with the CXL interface circuit 360, and, for example, the second LPDDR PHY 330 may include one or more ports for communicating based on the CXL protocol. The second LPDDR PHY 330 may include a physical layer or an electrical layer and a logical layer provided for signals, frequencies, timings, drivers, detailed operating parameters, and functions required for communication based on the CXL interface circuit 360. For example, the second LPDDR PHY 330 may include an HM block 331 configured to receive a signal from the first LPDDR PHY 320 and electrically convert the signal, and an SM block 333 configured to convert an output of the HM block 331 so that the converted output is transmitted to the memory controller 340. The second LPDDR PHY 330 may support the JEDEC standard.

[0056] The memory controller 340 may control the overall operation of the CXL memory device 300. For example, the memory controller 340 may receive the output of the second LPDDR PHY 330 and provide read data to the CXL interface circuit 360 via the bus 350, or receive the output of the CXL interface circuit 360 via the bus 350 and provide write data to the DRAM 310 via the second LPDDR PHY 330 and the first LPDDR PHY 320.

[0057] The CXL interface circuit 360 may include a CXL block 361 and a communication interface block 363. The communication interface block 363 may support a communication interface, such as a PCIe interface and a UCIe interface.

[0058] The CXL memory device 300 described above according to the comparative example may perform conversion according to the JEDEC standard twice. For example, the CXL memory device 300 may perform a communication protocol and / or interface conversion once in the first LPDDR PHY 320 to access the DRAM 310, and perform a communication protocol and / or interface conversion again in the second LPDDR PHY 330 to align with the CXL protocol. However, since the communication protocol and / or interface conversion needs to be performed twice, the CXL storage latency of the DRAM 310 may increase.

[0059] Figure 4 A CXL storage device 400 is shown in accordance with one or more embodiments.

[0060] refer to Figure 4 , the CXL memory device 400 may include an HBM 410 , an HBM interface IP core 420 , a memory controller 430 , a bus 440 , and a CXL interface circuit 450 .

[0061] The HBM interface IP core 420 may include a plurality of I / O circuits to access the HBM 410. For example, the HBM interface IP core 420 may include one or more ports for communicating with the HBM 410. The HBM interface IP core 420 may include a physical layer or an electrical layer and a logical layer provided for signals, frequencies, timings, drivers, detailed operating parameters, and functions to facilitate communication between the HBM 410 and the CXL interface circuit 450. For example, the HBM interface IP core 420 may directly convert the interface of the HBM core device to the DFI protocol, bypassing the need to convert to the JEDEC interface. The HBM interface IP core 420 may include a through silicon via (TSV) input and output (IO) block 421 configured to receive signals from or provide signals to the HBM 410, and an SM block 423 configured to convert the output of the TSV IO block 421 to a format suitable for the CXL interface circuit 450. The HBM interface IP core 420 may perform memory interface operations, such as selecting rows and columns corresponding to memory cells of the HBM 410, writing data to the memory cells, and reading the written data. Herein, the HBM interface IP core 420 may not support or comply with the JEDEC standard. Instead, the HBM interface IP core 420 may correspond to a non-JEDEC PHY.

[0062] The memory controller 430 may control the overall operation of the CXL memory device 400. For example, the memory controller 430 may receive the output of the HBM interface IP core 420 and provide read data to the CXL interface circuit 450 via the bus 440, or receive the output of the CXL interface circuit 450 via the bus 440 and provide write data to the HBM 410 via the HBM interface IP core 420.

[0063] The CXL interface circuit 450 may include a CXL block 451 and a communication interface block 453. The communication interface block 453 may support a communication interface, such as a PCIe interface and a UCIe interface.

[0064] The CXL memory device 400 described above according to one or more embodiments may perform communication protocol and / or interface conversion only once, thereby reducing the latency consumed in the communication protocol / interface conversion. For example, the CXL memory device 400 may perform communication protocol / interface conversion only once in the HBM interface IP core 420 to access the HBM 410, thereby aligning the input / output of the HBM 410 with the CXL protocol and reducing the latency of the CXL memory device 400 accordingly.

[0065] Figure 5 A semiconductor device 500 according to one or more embodiments is shown.

[0066] refer to Figure 5 , the semiconductor device 500 may be implemented as a SiP, a multi-chip package, a SoC, or as a stacked package including a plurality of packages.

[0067] The semiconductor device 500 may include a stacked semiconductor memory 510 , an application specific integrated circuit (ASIC) die 520 , and an interposer 530 . The stacked semiconductor memory 510 and the ASIC die 520 may be connected to the top of the interposer 530 .

[0068] The stacked semiconductor memory 510 may correspond to an HBM in which bandwidth is increased by stacking a plurality of memory chips (eg, a plurality of dies) and electrically connecting the plurality of memory chips to each other via TSVs. For example, the stacked semiconductor memory 510 may correspond to Figure 4 HBM 410.

[0069] The plurality of dies may include a CXL base die 511 and a plurality of core dies 513. Each of the plurality of core dies 513 may correspond to a DRAM slice die. For example, the plurality of core dies 513 may include 12 HBM DRAM slice dies HBM DRAM DIE 0 to HBM DRAM DIE 11.

[0070] The CXL-based die 511 may include Figure 4 For example, the HBM interface IP core 541 of the CXL base die 511 may correspond to Figure 4 The HBM interface IP core 420 for interfacing between the HBM 410 and the storage controller 430. The CXL base die 511 may include an HBM controller 543, which may correspond to Figure 4 The CXL base die 511 may include a CXL block 545, which may correspond to Figure 4 The CXL interface circuit 450 is provided.

[0071] ASIC die 520 may include a computing subsystem 521 and a CXL block 523. CXL block 523 of ASIC die 520 may perform the same functions as CXL block 545 of CXL base die 511. Computing subsystem 521 may perform various calculations. For example, computing subsystem 521 may include at least one of at least one CPU, at least one GPU, and at least one NPU. 9A to 9C Describe the specific implementation of the computing subsystem 521.

[0072] Fig. 6A and Figure 6B A CXL-based die 600 is shown according to one or more embodiments.

[0073] refer to Fig. 6A and Figure 6B , the CXL-based die 600 may correspond to Figure 5 The CXL-based die 511 .

[0074] According to one or more embodiments, the CXL base die 600 may include a PHY interface 610 , an HBM controller 620 , a low latency channel (LLC) 630 , a UCI port 640 , a boot module 650 , and a test module 660 .

[0075] The PHY interface 610 may correspond to Figure 5 The HBM interface IP core 541. For example, the PHY interface 610 may include four HBM (three-dimensional (3D) DRAM) PHY blocks. Each HBM PHY block may be allocated to three core dies.

[0076] The HBM controller 620 may correspond to Figure 5 The HBM controller 543 of the PHY interface 610 may include four control blocks (eg, four HBMC_4CH). The four control blocks may correspond to four HBM PHY blocks included in the PHY interface 610, respectively, and each control block may process four channels.

[0077] LLC 630 can correspond to Figure 4 The LLC 630 may include four LLC blocks. The LLC 630 may be connected to the HBM controller 620. For example, the four LLC blocks may be connected to four control blocks included in the HBM controller 620, respectively.

[0078] UCI port 640 may correspond to Figure 4 The communication interface block 453. Figure 6B , the UCI port 640 may include a port supporting a UCIe communication interface. For example, the UCI port 640 may include eight UCIe ports. Every two UCIe ports may correspond to one control block of the HBM controller 620. That is, one UCIe port may send and receive two channels.

[0079] Fig. 7A A primary storage device 701 is shown in accordance with one or more embodiments.

[0080] refer to Fig. 7A , the main storage device 701 may include an HBM 710 including multiple core dies, an HBM interface IP core 720, an interface conversion block 730, and a communication interface block 740. The HBM interface IP core 720 may directly convert the interface of the HBM core device into the DFI protocol and bypass (or skip) the conversion to the JEDEC interface.

[0081] The interface conversion block 730 may perform communication protocol conversion and / or communication interface conversion for communication of the main memory. For example, the HBM interface IP core 720 may be based on the DFI protocol. The interface conversion block 730 may convert the DFI protocol into an interface supporting the main memory (e.g., a PCIe interface, a UCIe interface, etc.).

[0082] The communication interface block 740 may support communication interfaces such as a PCIe interface and a UCIe interface, but is not limited thereto. According to various embodiments, the communication interface block 740 may support, for example, the following interfaces: an Industry Standard Architecture (ISA) interface, a SATA interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Universal Storage Bus (USB) Attached SCSI (UAS), an Internet SCSI (iSCSI), a Fibre Channel (FC) interface, and a FC over Ethernet (FCoE) interface.

[0083] Figure 7B A primary storage device 702 is shown in accordance with one or more embodiments.

[0084] refer to Figure 7B, the main storage device 702 may include an HBM 750 including multiple core dies, an HBM interface IP core 760 , an HBM controller 770 , a bus 775 , a D2D controller 780 , and a D2D communication interface block 790 .

[0085] The HBM interface IP core 760 can directly convert the interface of the core device included in the HBM 750 into the DFI protocol and bypass (or skip) the conversion to the JEDEC interface. The HBM interface IP core 760 can include a TSV IO block 761 configured to receive a signal from the HBM 750 or provide a signal to the HBM 750, and an SM block 763 configured to convert the output of the TSV IO block 761 into a format suitable for the D2D communication interface block 790.

[0086] The HBM controller 770 may perform protocol conversion for communication with the main memory. For example, the HBM interface IP core 760 may be based on the DFI protocol. The HBM controller 770 may convert the DFI protocol into the AMBA protocol supported by the bus 775 and the D2D controller 780.

[0087] The D2D communication interface block 790 may support a D2D communication interface, which may include at least one of a PCIe interface, a UCIe interface, an ISA interface, a SATA interface, a SCSI, a SAS, a UAS, an iSCSI, a FC interface, and a FCoE interface.

[0088] Figure 8 A SoC 800 is shown in accordance with one or more embodiments.

[0089] refer to Figure 8 , the SoC 800 may include an HBM 810 including a plurality of core dies, an HBM interface IP core 820 , an HBM controller 830 , a bus 840 , and a CPU 850 .

[0090] The HBM interface IP core 820 can directly convert the interface of the core device included in the HBM 810 into the DFI protocol and bypass (or skip) the conversion to the JEDEC interface. The HBM interface IP core 820 can include a TSV IO block 821 configured to receive a signal from the HBM 810 or provide a signal to the HBM 810, and an SM block 823 configured to convert the output of the TSV IO block 821 into a format suitable for the HBM controller 830.

[0091] The HBM controller 830 may perform protocol conversion for communication with the main memory. For example, the HBM interface IP core 820 may be based on the DFI protocol. The HBM controller 830 may convert the DFI protocol into the AMBA protocol supported by the bus 840 and the CPU 850. The CPU 850 may perform various calculations by using data received from the HBM controller 830 via the bus 840.

[0092] 9A to 9C A semiconductor device layout according to one or more embodiments is shown.

[0093] refer to Fig.9A , according to various embodiments, the CXL HBM 901 may be connected in parallel to four GPUs 910. For example, referring to Figure 5 and Fig.9A , the computing subsystem 521 of the ASIC die 520 may include four GPUs 910. The CXL HBM 901 may be connected to the four GPUs 910 via UCIe ports. For example, the CXL HBM 901 may be connected to one GPU 910 by using two UCIe ports. This configuration enables transmission and reception through two lanes for each UCIe port, thereby allowing the CXL HBM 901 to perform data transmission and reception through four lanes for each GPU 910.

[0094] According to one or more embodiments, four GPUs 910 may be connected to dedicated HBMs 915, respectively. In this case, each dedicated HBM 915 may support the JEDEC standard. One dedicated HBM 915 connected to one GPU 910 may only send data to and receive data from the one GPU 910 connected to the one dedicated HBM 915. However, the CXL HBM 901 may be used as a shared resource for the four GPUs 910. For example, one GPU 910 may require a high channel bandwidth for graphics processing, while the other three GPUs 910 may require a lower channel bandwidth. In response, the resource allocation of the CXL HBM 901 may be dynamically adjusted according to the channel bandwidth requirements of each GPU 910.

[0095] refer to Fig. 9B , the CXL HBM 902 according to various embodiments may be connected in parallel to the CPU 921, the GPU 922, the first NPU 923, and the second NPU 924. For example, referring to Figure 5 and Fig. 9B, the computing subsystem 521 of the ASIC die 520 may include a CPU 921, a GPU 922, a first NPU 923, and a second NPU 924. The CXL HBM 902 may be connected to the CPU 921, the GPU 922, the first NPU 923, and the second NPU 924 via a UCIe port. For example, the CXL HBM 902 may be connected to each of the CPU 921, the GPU 922, the first NPU 923, and the second NPU 924 by using two UCIe ports. That is, two lanes may be transmitted and received for each UCIe port, and the CXL HBM 902 may transmit and receive data through four lanes for each of the CPU 921, the GPU 922, the first NPU 923, and the second NPU 924.

[0096] According to one or more embodiments, CXL HBM 902 may be used as a shared resource for CPU 921, GPU 922, first NPU 923, and second NPU 924. For example, when CPU 921 requires a large amount of resources to perform a task, the channel bandwidth allocated to CPU 921 may be increased, while the channel bandwidth allocated to the other three processing units (e.g., GPU 922, first NPU 923, and second NPU 924) may be reduced. This dynamic adjustment may optimize resource utilization in CXL HBM 902.

[0097] refer to Fig. 9C According to various embodiments, four CXL HBMs (e.g., first to fourth CXL HBMs 903 to 906) may be connected to the first NPU 931 and the second NPU 932. For example, the first NPU 931 may be connected to the first CXL HBM 903 and the second CXL HBM 904, and the second NPU 932 may be connected to the third CXL HBM 905 and the fourth CXL HBM 906. Each of the first NPU 931 and the second NPU 932 may be connected to the CXL HBM via a UCIe port. For example, each of the first CXL HBM 903 and the second CXL HBM 904 may be connected to the first NPU 931 by using two UCIe ports, and each of the third CXL HBM 905 and the fourth CXL HBM 906 may be connected to the second NPU 932 by using two UCIe ports.

[0098] According to one or more embodiments, the first NPU 931 may be shared by the first CXL HBM 903 and the second CXL HBM 904, and the second NPU 932 may be shared by the third CXL HBM 905 and the fourth CXL HBM 906. For example, the first NPU 931 may perform training or inference of a neural network, while the second NPU 932 may not perform training or inference. The first CXL HBM 903 and the second CXL HBM 904 connected to the first NPU 931 may set the channel bandwidth to high for the first NPU 931, and the third CXL HBM 905 and the fourth CXL HBM 906 connected to the second NPU 932 may set the channel bandwidth to low for the second NPU 932, thereby dynamically using resources.

[0099] Fig.10 is a block diagram illustrating a system 2000 of an electronic device including a D2D interface according to an embodiment.

[0100] refer to Fig.10 , the system 2000 may include a camera 2100, a display 2200, an audio processor 2300, a modem 2400, CXL HBMs 2500a and 2500b, flash memory devices 2600a and 2600b, I / O devices 2700a and 2700b, and an application processor (AP) 2800. Each of the flash memory devices 2600a and 2600b may include a storage controller 2610 and a flash memory 2620 including a storage unit. The system 2000 may be implemented by a notebook computer, a mobile terminal, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. Alternatively, the system 2000 may be implemented by a server or a PC.

[0101] The camera 2100 can capture still images or moving images according to the control of the user, and store the captured image / video data therein, or send the captured image / video data to the display 2200. The audio processor 2300 can process the audio data included in the content in the flash memory devices 2600a and 2600b or the audio data from the network. The modem 2400 can modulate and send a signal for wired / wireless data transmission and reception, and demodulate the signal to the original signal at the receiving side. The I / O devices 2700a and 2700b may include devices such as USB, memory, digital camera, secure digital (SD) card, digital versatile disk (DVD), network adapter, and touch screen configured to provide digital input and / or output functions.

[0102] The AP 2800 may control the overall operation of the system 2000. The AP 2800 may include a controller 2810, an accelerator block or an accelerator chip 2820, and an interface block 2830. The AP 2800 may control the display 2200 to display a portion of the content stored in the flash memory devices 2600a and 2600b on the display 2200. If a user input is received through the I / O devices 2700a and 2700b, the AP 2800 may perform a control operation corresponding to the user input. The AP 2800 may include an accelerator block 2820 as a dedicated circuit for artificial intelligence (AI) data calculation, or the accelerator chip 2820 may be provided separately from the AP 2800. The CXL HBM 2500b may be additionally mounted in the accelerator block or the accelerator chip 2820. The accelerator is a functional block configured to professionally perform specific functions of the AP 2800, and may include a GPU as a functional block configured to professionally perform graphic data processing, an NPU as a block configured to professionally perform AI calculations and reasoning, and a data processing unit (DPU) as a block configured to professionally perform data transmission.

[0103] The system 2000 may include CXL HBMs 2500a and 2500b. The AP 2800 may control the CXL HBMs 2500a and 2500b through a command and mode register set (MRS) according to the JEDEC standard, or communicate with the CXL HBMs 2500a and 2500b by setting a DRAM interface protocol to use company-specific functions (e.g., low voltage / high speed / reliability) and a cyclic redundancy check (CRC) / error correction code (ECC) function. For example, the AP 2800 may communicate with the CXL HBM 2500a by using an interface (e.g., LPDDR4 or LPDDR5) compliant with the JEDEC standard, and the accelerator block or accelerator chip 2820 may communicate with the CXL HBM 2500b by setting a new DRAM interface protocol to control the CXL HBM 2500b having a higher bandwidth than the CXL HBM 2500a, which is used for the accelerator.

[0104] The CXL HBMs 2500 a and 2500 b may be initialized at a power-on time point of the system 2000 , and used as a temporary storage of an OS and application data by loading the OS and application data thereon, or used as an execution space of various software codes.

[0105] Fig.11 is a block diagram illustrating a data center 3000 including a CXL storage device according to one or more embodiments.

[0106] refer to Fig.11, the data center 3000 is a facility configured to store various data and provide services, and may be referred to as a data storage center. The data center 3000 may be a system for operating a search engine and a database, and may be a computing system for a company or government organization such as a bank. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be selected differently according to the embodiment, and the number of application servers 3100 to 3100n may be different from the number of storage servers 3200 to 3200m.

[0107] The application server 3100 or the storage server 3200 may include at least one of a processor 3110 or 3210 and a memory 3120 or 3220, respectively. When the storage server 3200 is described as an example, the processor 3210 may control the overall operation of the storage server 3200 and access the memory 3220 to execute instructions and / or data loaded on the memory 3220. The memory 3220 may be a double data rate synchronous DRAM (DDR SDRAM), HBM, a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, a non-volatile DIMM (NVMDIMM), or a CXL storage device including HBM (CXL HBM). According to one or more embodiments, the number of processors 3210 and memory 3220 included in the storage server 3200 may be selected differently. In one or more embodiments, the processor 3210 and the memory 3220 may provide a processor-memory pair. In one or more embodiments, the number of processors 3210 may be different from the number of memories 3220. The processor 3210 may include a single-core processor or a multi-core processor. The description of the storage server 3200 may also be similarly applied to the application server 3100. According to one or more embodiments, the application server 3100 may not include the storage device 3150. The storage server 3200 may include at least one storage device 3250. The number of storage devices 3250 included in the storage server 3200 may be selected differently according to the embodiment.

[0108] In the application server 3100 or the storage server 3200, the memory 3120 or 3220 may be as described above with reference to Figures 1A to 9CThe CXL memory device or main memory device described. For example, the CXL memory device or main memory device may include HBM 410. The memory 3120 or 3220 may be coupled to a memory controller configured to perform control so that the computing tasks according to the kernel offloaded from the processor 3110 or 3210 are performed. The CXL memory device including the HBM 410 may directly convert the communication protocol or interface of the HBM core die into the DFI protocol according to the non-JEDEC PHY through the HBM interface IP core, thereby providing reduced latency.

[0109] The application servers 3100 to 3100n and the storage servers 3200 to 3200m can communicate with each other via the network 3300. The network 3300 can be implemented using FC, Ethernet, etc. Herein, FC is a medium for relatively high-speed data transmission, and an optical switch providing high performance / high availability can be used. Depending on the access scheme of the network 3300, the storage servers 3200 to 3200m can be set to file storage, block storage, or object storage.

[0110] In one or more embodiments, the network 3300 may be a storage-specific network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN implemented using an FC network and according to an FC protocol (FCP). As another example, the SAN may be an IP-SAN implemented using a transmission control protocol (TCP) / Internet protocol (IP) network and according to a SCSI or iSCSI protocol based on TCP / IP. In another embodiment, the network 3300 may be a general network, such as a TCP / IP network. For example, the network 3300 may be implemented according to an FCoE protocol, a network attached storage (NAS) protocol, a non-volatile memory express (NVMe-oF) protocol based on an architecture, and the like.

[0111] Hereinafter, the application server 3100 and the storage server 3200 are mainly described. The description of the application server 3100 may also be applied to other application servers 3100n, and the description of the storage server 3200 may also be applied to other storage servers 3200m.

[0112] The application server 3100 may store data requested to be stored by a user or client in one of the storage servers 3200 to 3200m via the network 3300. In addition, the application server 3100 may obtain data requested to be read by a user or client from one of the storage servers 3200 to 3200m via the network 3300. For example, the application server 3100 may be implemented by a web server, a database management system (DBMS), etc.

[0113] The application server 3100 may access a memory 3120n or a storage device 3150n included in another application server 3100n via the network 3300, or access one of the memories 3220 to 3220m and the storage devices 3250 to 3250m included in the storage servers 3200 to 3200m via the network 3300. By doing so, the application server 3100 may perform various operations on the data stored in the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. For example, the application server 3100 may execute an instruction for moving or copying data between the application servers 3100 to 3100n and / or the storage servers 3200 to 3200m. In this case, data may be moved from the storage devices 3250 to 3250m of the storage servers 3200 to 3200m via the memories 3220 to 3220m of the storage servers 3200 to 3200m or directly to the memories 3120 to 3120n of the application servers 3100 to 3100n. The data moved via the network 3300 may be data encrypted for security or privacy.

[0114] When the storage server 3200 is described as an example, the interfaces (I / F) 3254 to 3254m can provide physical connections between the processors 3210 to 3210m and the controllers (CTRL) 3251 to 3251m, and physical connections between the network interface cards (NIC) 3240 to 3240m and the controllers 3251 to 3251m, respectively. For example, the interface 3254 can be implemented by a direct attached storage (DAS) solution that is directly connected to the storage device 3250 through a dedicated cable. In addition, for example, interface 3254 can be implemented by various interfaces such as an Advanced Technology Attachment (ATA) interface, a SATA interface, an external SATA (e-SATA) interface, SCSI, SAS, a PCI interface, a PCIe interface, an NVMe interface, an Institute of Electrical and Electronics Engineers (IEEE) 1394 interface, a USB interface, an SD card interface, a MultiMediaCard (MMC) interface, an embedded MMC (eMMC) interface, a Universal Flash Storage (UFS) interface, an embedded UFS (eUFS) interface, and a Compact Flash (CF) card interface.

[0115] The storage servers 3200 to 3200m may further include switches 3230 to 3230m and NICs 3240 to 3240m, respectively. The switch 3230 may selectively connect the processor 3210 to the storage device 3250 or selectively connect the NIC 3240 to the storage device 3250 under the control of the processor 3210.

[0116] In one or more embodiments, the NICs 3240 to 3240m may include a network adapter. The NICs 3240 to 3240m may be connected to the network 3300 through a wired interface, a wireless interface, a Bluetooth interface, an optical interface, etc. The NICs 3240 to 3240m may include an internal memory, a digital signal processor (DSP), a host bus interface, etc., and may be connected to the processor 3210, the switch 3230, etc. via the host bus interface. The host bus interface may be implemented by one of the examples of the above-mentioned interface 3254. In one or more embodiments, the NICs 3240 to 3240m may be integrated with at least one of the processors 3210 to 3210m, the switches 3230 to 3230m, and the storage devices 3250 to 3250m, respectively.

[0117] In one of the application servers 3100 to 3100n and the storage servers 3200 to 3200m, the processor can program or read the data by sending a command to one of the storage devices 3150 to 3150n and 3250 to 3250m and the memories 3120 to 3120n and 3220 to 3220m. In this case, the data may be data corrected by an ECC engine. The data may be data processed by a data bus inversion (DBI) or data masking (DM) and include cyclic redundancy code (CRC) information. The data may be data encrypted for security or privacy.

[0118] One of the storage devices 3150 to 3150n and 3250 to 3250m may send a control signal and a CA signal to one of the NAND flash memory devices 3252 to 3252m in response to a read command received from the processor. Accordingly, when data is read from one of the NAND flash memory devices 3252 to 3252m, a read enable (RE) signal may be input as a data output control signal so that data is output to the DQ bus. A data strobe (DQS) may be generated using the RE signal. Command and address signals may be latched to the page buffer according to the rising edge or falling edge of a write enable (WE) signal.

[0119] The controllers 3251 to 3251m may control the overall operation of the storage devices 3250 to 3250m. In one or more embodiments, the controller 3251 may include a static random access memory (SRAM). The controllers 3251 to 3251m may write data to the NAND flash memory devices 3252 to 3252m in response to a write command, or read data from the NAND flash memory devices 3252 to 3252m in response to a read command. For example, a write command and / or a read command may be provided from a processor 3210 in the storage server 3200, a processor 3210m in the storage server 3200m, or one of the processors 3110 to 3110n in the application servers 3100 to 3100n. The DRAM 3253 may temporarily store (buffer) data to be written to the NAND flash memory device 3252, or data read from the NAND flash memory device 3252. In addition, the DRAM 3253 may store metadata. Herein, metadata is user data or data generated by the controller 3251 to manage the NAND flash memory device 3252. The storage device 3250 may include a secure element (SE) for security or privacy.

[0120] The above exemplary embodiments are merely examples and should not be construed as limiting. The present teachings can be easily applied to other types of devices. In addition, the description of the exemplary embodiments is intended to be illustrative rather than to limit the scope of the claims, and a variety of substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A computing fast link CXL storage device, comprising: A high bandwidth memory HBM comprises a CXL base die and a plurality of core dies sequentially stacked on the CXL base die. Wherein, the CXL-based die comprises: The HBM interface intellectual property core is an HBM interface IP core, configured to convert data transmission and reception between the plurality of core dies and a dynamic random access memory DRAM according to the CXL specification, and The HBM interface IP core corresponds to the non-Joint Electron Device Engineering Council JEDEC standard.

2. The CXL storage device according to claim 1, wherein: The CXL-based die further comprises: HBM controller; CXL interface circuitry; and A bus connects the HBM controller to the CXL interface circuit.

3. The CXL storage device according to claim 2, wherein: The bus operates based on the Double Data Rate DDR PHY Interface DFI protocol, and Wherein, the HBM interface IP core also includes: a through silicon via (TSV) input and output IO block configured to handle input to and output from the plurality of core dies; and The soft macro block is configured to perform communication interface conversion to comply with the DFI protocol.

4. The CXL storage device according to claim 2, wherein: The CXL interface circuit further comprises: CXL controller; and A communication interface block is configured to support at least one of a peripheral component interconnect express (PCIe) communication interface and a universal chiplet interconnect express (UCIe) communication interface.

5. The CXL storage device according to claim 2, wherein: The CXL interface circuit is configured to connect the CXL memory device to an application specific integrated circuit ASIC die via an interposer, and The ASIC die includes at least one central processing unit CPU, at least one graphics processing unit GPU and at least one neural processing unit NPU.

6. The CXL storage device according to claim 1, wherein: The CXL base die and the plurality of core dies of the HBM are stacked through through silicon vias (TSVs) to form a three-dimensional (3D) memory stack.

7. The CXL storage device according to claim 1, wherein: The CXL-based die further comprises: a test module configured to verify normal operation of the HBM; and The boot module is configured to execute the boot process of the HBM.

8. A system-level package SiP, comprising: Application-specific integrated circuit ASIC die; A compute fast link CXL base die is vertically connected to a high bandwidth memory HBM including multiple core dies through through silicon vias TSV; as well as an interposer, connecting the ASIC die to the CXL base die, The CXL base die includes an HBM interface intellectual property core, namely an HBM interface IP core, to convert data transmission and reception between the plurality of core dies and a dynamic random access memory DRAM according to the CXL specification, and The HBM interface IP core corresponds to the non-Joint Electron Device Engineering Council JEDEC standard.

9. The SiP according to claim 8, wherein: The CXL-based die further comprises: HBM controller; CXL interface circuitry; and A bus connects the HBM controller to the CXL interface circuit.

10. The SiP according to claim 9, wherein: The bus operates based on the Double Data Rate DDR PHY Interface DFI protocol, and Wherein, the HBM interface IP core also includes: a TSV input and output IO block configured to handle input to and output from the plurality of core dies; and The soft macro block is configured to perform communication protocol conversion to comply with the DFI protocol.

11. The SiP according to claim 9, wherein: The CXL interface circuit further comprises: CXL controller; and A communication interface block is configured to support at least one of a peripheral component interconnect express (PCIe) communication interface and a universal chiplet interconnect express (UCIe) communication interface.

12. The SiP according to claim 9, wherein: The ASIC die includes at least one central processing unit CPU, at least one graphics processing unit GPU and at least one neural processing unit NPU.

13. The SiP according to claim 8, wherein: The CXL-based die further comprises: a test module configured to verify normal operation of the HBM; and The boot module is configured to execute the boot process of the HBM.

14. A storage device comprising: A high bandwidth memory HBM comprises a base die and a plurality of core dies sequentially stacked on the base die. The base die includes an HBM interface intellectual property core, namely, an HBM interface IP core, which is configured to convert data transmission and reception between the plurality of core dies and a dynamic random access memory DRAM according to a peripheral component interconnect express PCIe interface, a universal chiplet interconnect express UCIe interface, and a die-to-die D2D interface, and The HBM interface IP core corresponds to the non-Joint Electron Device Engineering Council JEDEC standard.

15. The storage device according to claim 14, wherein: The base die also includes an HBM controller, a communication interface circuit, and a bus connecting the HBM controller to the communication interface circuit.

16. The storage device according to claim 15, wherein: The bus operates based on the Double Data Rate DDR PHY Interface DFI protocol, and Wherein, the HBM interface IP core also includes: a through silicon via (TSV) input and output IO block configured to handle input to and output from the plurality of core dies; and The soft macro block is configured to perform communication protocol conversion to comply with the DFI protocol.

17. The storage device according to claim 15, wherein: The communication interface circuit connects the storage device to an application specific integrated circuit ASIC die via an interposer.

18. The storage device according to claim 17, wherein: The ASIC die includes at least one central processing unit CPU, at least one graphics processing unit GPU and at least one neural processing unit NPU.

19. The storage device according to claim 14, wherein: The base die and the plurality of core dies of the HBM are stacked through through silicon vias (TSVs) to form a three-dimensional (3D) memory stack.

20. The storage device according to claim 14, wherein: The base die also includes: a test module configured to verify normal operation of the HBM; and The boot module is configured to execute the boot process of the HBM.

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