Double-CPU data real-time interaction method

Abstract

The invention discloses a double-CPU data real-time interaction method, and relates to the technical field of double-CPU data real-time interaction, and the method comprises the following steps: judging whether a first CPU sends data to a second CPU or the second CPU sends data to the first CPU; if the first CPU sends data to the second CPU, the first CPU sends write-in data to the first FPGA module through the first LPC bus; obtaining the size of the write-in data, packaging the write-in data based on the size of the write-in data, marking the packaged data as write-in packaged data, sending the write-in packaged data to a second FPGA module, and storing the write-in packaged data by the second FPGA module; and the second CPU sends an instruction for reading the written packaged data stored by the second FPGA module to the second FPGA module through the fourth LPC bus. The method and the device are used for solving the problems of low data transmission efficiency and excessive occupation of CPU resources caused by direct transmission without considering the data size in the existing double-CPU data real-time interaction technology.

Description

Technical Field

[0001] The invention relates to the technical field of dual CPU data real-time interaction, in particular to a dual CPU data real-time interaction method. Background Art

[0002] In modern industrial automation and control systems, the real-time and reliability requirements for data processing and communication are becoming increasingly higher. In order to meet these requirements, a dual-CPU data real-time interaction method has been proposed and applied.

[0003] Dual-port RAM is often used for data exchange in common dual-CPU system data exchange methods. In the process of localization practice, the interface bus of domestic dual-port RAM is LOCALBUS, which needs to occupy more CPU ports. In complex rail transit control systems, there is often a lack of IO ports, which cannot meet the bus pin requirements of localbus. At the same time, when the dual-CPU data is interacting in real time, if the data size is not considered to be directly transmitted, it may cause increased communication delays because each data transmission takes time. At the same time, the continuous work of the CPU leads to excessive occupation of memory and CPU resources. That is, the existing dual-CPU data real-time interaction technology does not consider the data size and directly transmits it, resulting in low data transmission efficiency and excessive occupation of CPU resources. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems in the prior art to a certain extent, by which a first CPU sends write data to a first FPGA module through a first LPC bus, obtains the size of the write data, packages the write data based on the size of the write data, and sends the write packaged data to a second FPGA module; the second CPU sends an instruction to read the write packaged data saved by the second FPGA module to the second FPGA module through a fourth LPC bus, packages the read data, and sends the read packaged data to the second CPU through the fourth LPC bus, so as to solve the problem of direct transmission without considering the size of the data in the existing dual-CPU data real-time interaction technology, resulting in low data transmission efficiency and excessive occupation of CPU resources.

[0005] To achieve the above object, the present application provides a dual CPU data real-time interaction method, comprising the following steps:

[0006] Determine whether the first CPU sends data to the second CPU or the second CPU sends data to the first CPU;

[0007] If the first CPU sends data to the second CPU, the first CPU sends the write data to the first FPGA module via the first LPC bus;

[0008] Obtain the size of the write data, package the write data based on the size of the write data, mark it as write packaged data, send the write packaged data to the second FPGA module, and the second FPGA module saves the write packaged data;

[0009] The second CPU sends an instruction to read the write packaged data saved by the second FPGA module to the second FPGA module through the fourth LPC bus, marking it as a read instruction, obtains data corresponding to the read instruction, marks it as read data, packages the read data, marks it as read packaged data, and sends the read packaged data to the second CPU through the fourth LPC bus;

[0010] If the second CPU sends data to the first CPU, similarly, the step of the first CPU sending data to the second CPU is completed, and the second CPU sends data to the first CPU.

[0011] Furthermore, obtaining the size of the written data includes the following sub-steps:

[0012] The first FPGA module includes a first LPC transfer unit, a first dual-port RAM unit, a first dual-port RAM control unit, a first LPC parsing unit and a second LPC parsing unit;

[0013] The size of the written data obtained by the first LPC parsing unit is A i .

[0014] Furthermore, packaging the written data based on the size of the written data includes the following sub-steps:

[0015] The write data and the size of the write data A i Sending to the first LPC forwarding unit;

[0016] The first LPC forwarding unit determines A i Is it greater than the sending threshold Ay? If A i If it is less than the sending threshold Ay, A i The size of the next data to be written is A i+1 Accumulate until the accumulated sum is greater than the sending threshold Ay, pack all the accumulated write data and mark them as accumulated packed data. i If it is greater than the sending threshold Ay, the written data is directly packaged and marked as directly packaged data.

[0017] Further, sending the packaged write data to the second FPGA module includes the following sub-steps:

[0018] Mark the accumulated packaged data and the direct packaged data as written packaged data;

[0019] Each time the packing of the write-packed data is completed, the write-packed data is sent to the second FPGA module via the third LPC bus.

[0020] Furthermore, the second FPGA module saves the written packaged data and includes the following sub-steps:

[0021] The second FPGA module includes a second LPC transfer unit, a second dual-port RAM unit, a second dual-port RAM control unit, a third LPC parsing unit and a fourth LPC parsing unit;

[0022] The third LPC parsing unit receives the write-packed data and performs frame parsing on the write-packed data, and sends the write-packed data after frame parsing to the second dual-port RAM control unit, and the second dual-port RAM control unit writes the write-packed data after frame parsing into the second dual-port RAM unit.

[0023] Further, obtaining corresponding data based on reading the instruction of the second FPGA module to save the written packaged data includes the following sub-steps:

[0024] The third LPC parsing unit receives the read instruction and performs frame parsing on the read instruction, and sends the frame-parsed read instruction to the second dual-port RAM control unit.

[0025] Furthermore, packaging the read data includes the following sub-steps:

[0026] The second dual-port RAM control unit reads the read data from the second dual-port RAM module according to the read instruction after the frame analysis, and sends the read data to the third LPC analysis unit.

[0027] Further, sending the read packaged data to the second CPU via the fourth LPC bus includes the following sub-steps:

[0028] The third LPC parsing unit performs frame packaging on the read data, marks the read packaged data, and sends the read packaged data to the second CPU module through the fourth LPC bus.

[0029] Furthermore, completing the second CPU sending data to the first CPU includes the following sub-steps:

[0030] The second CPU sends write data to the second FPGA module via the fourth LPC bus;

[0031] Obtain the size of the write data, package the write data based on the size of the write data, mark it as write packaged data, send the write packaged data to the first FPGA module, and the first FPGA module saves the write packaged data;

[0032] The first CPU sends an instruction to read the write packaged data saved by the first FPGA module to the first FPGA module through the first LPC bus, marks it as a read instruction, obtains data corresponding to the read instruction, marks it as read data, packages the read data, marks it as read packaged data, and sends the read packaged data to the first CPU through the first LPC bus.

[0033] Beneficial effects of the present invention: The present invention sends write data to the first FPGA module through the first LPC bus by the first CPU, obtains the size of the write data, packages the write data based on the size of the write data, and sends the write packaged data to the second FPGA module. The second CPU sends an instruction to read the write packaged data saved by the second FPGA module to the second FPGA module through the fourth LPC bus, packages the read data, and sends the read packaged data to the second CPU through the fourth LPC bus. The advantage is that the LPC bus is used to realize dual-port RAM data interaction compared with the dual-port RAM of the traditional localbus bus, which saves the main processor IO port resources, and the write data is packaged based on the size of the write data, resulting in improved data transmission efficiency and less CPU resource occupation. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a functional block diagram of the system of the present invention;

[0035] Figure 2 A schematic diagram of the overall process of dual CPU data interaction of the present invention;

[0036] Figure 3 is a schematic diagram of a first FPGA module of the present invention;

[0037] Figure 4 Schematic diagram of the second FPGA module of the present invention. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Example 1, please refer to Figure 1 , Figure 2 , Figure 3 and Figure 4As shown, a dual-CPU data real-time interaction method includes: step S1, judging whether the first CPU sends data to the second CPU or the second CPU sends data to the first CPU; because the units through which the first CPU sends data to the second CPU and the second CPU sends data to the first CPU are different, two processes are separated, and the corresponding process operations are performed after the process is determined.

[0040] Step S2, if the first CPU sends data to the second CPU, step S2 includes the following sub-steps:

[0041] Step S21, the first CPU sends write data to the first FPGA module through the first LPC bus; wherein the use of the LPC bus to implement dual-port RAM data interaction compared with the traditional localbus bus dual-port RAM greatly saves the number of IO pins of the CPU system and saves the IO port resources of the main processor;

[0042] Step S22, obtaining the size of the write data, packaging the write data based on the size of the write data, marking it as write packaged data, sending the write packaged data to the second FPGA module, and the second FPGA module saving the write packaged data;

[0043] Step S22 includes the following steps:

[0044] Step S2201, wherein the first FPGA module includes a first LPC transfer unit, a first dual-port RAM unit, a first dual-port RAM control unit, a first LPC parsing unit, and a second LPC parsing unit;

[0045] Step S2202: using the first LPC parsing unit to obtain the size of the written data as A i ;

[0046] Step S2203: write the data and the size of the data to be written A i Sending to the first LPC forwarding unit;

[0047] Step S2204: The first LPC forwarding unit determines A i Is it greater than the sending threshold Ay? If A i If it is less than the sending threshold Ay, A i The size of the next data to be written is A i+1 Accumulate until the accumulated sum is greater than the sending threshold Ay, pack all the accumulated write data and mark them as accumulated packed data. iIf the value is greater than the sending threshold Ay, the written data is directly packaged and marked as directly packaged data; because each data transmission takes time, it may cause increased communication delays, and the continuous operation of the CPU leads to excessive occupation of memory and CPU resources. Therefore, it is judged whether the sending threshold is reached. When the transmission is multiple times and the transmission memory is small, the transmission time is saved and the excessive occupation of CPU resources is reduced; the setting of the sending threshold Ay does not affect the efficiency of data transmission and reduces the excessive occupation of CPU resources according to the CPU data. Therefore, the setting of the sending threshold Ay cannot be too large or too small. The sending threshold Ay is set to 7300 bytes;

[0048] In a specific implementation, the size of the written data obtained by the first LPC parsing unit is A. i = 2040 bytes, the write data and the write data size A i = 2040 bytes are sent to the first LPC transfer unit, and the first LPC transfer unit determines A i = 2040 bytes is greater than the sending threshold Ay = 7300 bytes,

[0049] A i = 2040 bytes is less than the sending threshold Ay = 7300 bytes, A i = 2040 bytes plus the size of the next written data is 3040 bytes, 2040 bytes + 3040 bytes is less than 7300 bytes, and the next 3204 bytes are accumulated. 2040 bytes + 3040 bytes + 3204 bytes is greater than 7300 bytes, so the three data are packaged and marked as cumulative packaged data;

[0050] Step S2205, marking the accumulated packaged data and the direct packaged data as written packaged data;

[0051] Step S2206, each time the packing of the write-packed data is completed, the write-packed data is sent to the second FPGA module through the third LPC bus;

[0052] Step S2207, wherein the second FPGA module includes a second LPC transfer unit, a second dual-port RAM unit, a second dual-port RAM control unit, a third LPC parsing unit, and a fourth LPC parsing unit; the third LPC parsing unit receives the write-packed data and performs frame parsing on the write-packed data, and sends the write-packed data after frame parsing to the second dual-port RAM control unit, and the second dual-port RAM control unit writes the write-packed data after frame parsing into the second dual-port RAM unit; the second dual-port RAM unit is connected to a storage unit to store data;

[0053] Step S23, the second CPU sends an instruction to read the write packaged data saved by the second FPGA module to the second FPGA module through the fourth LPC bus, marked as a read instruction, obtains data corresponding to the read instruction, marked as read data, packages the read data, marks as read packaged data, and sends the read packaged data to the second CPU through the fourth LPC bus; Step S23 also includes the following steps:

[0054] Step S2301, the third LPC parsing unit receives the read instruction and performs frame parsing on the read instruction, and sends the read instruction after frame parsing to the second dual-port RAM control unit; the frame parsing step identifies the frame boundary in the data stream, determines the start and end positions of the frame, and identifies the head and tail of the frame, which usually contain specific flags or sequences to indicate the start and end of the frame; extracts data fields from the frame, which may include length, instructions, data load, etc., calculates the checksum of the data frame to verify the integrity and correctness of the data; if the checksum does not match or the data format is incorrect, error processing is performed. Frame parsing is an important link in data communication, which ensures the correct reception and processing of data; through frame parsing, the purpose of data transmission can be effectively achieved and the reliability and security of communication can be improved.

[0055] Step S2302, the second dual-port RAM control unit reads the read data from the second dual-port RAM module according to the read instruction after the frame analysis, and sends the read data to the third LPC analysis unit; the storage unit connected to the second dual-port RAM control unit obtains the read data from the storage unit;

[0056] Step S2303: the third LPC parsing unit performs frame packing on the read data, marks the read packed data as read packed data, and sends the read packed data to the second CPU module through the fourth LPC bus.

[0057] Step S3, if the second CPU sends data to the first CPU, similarly, if the first CPU sends data to the second CPU, the second CPU sends data to the first CPU; step S3 includes the following sub-steps:

[0058] Step S31, the second CPU sends write data to the second FPGA module through the fourth LPC bus;

[0059] Step S32, obtaining the size of the write data, packaging the write data based on the size of the write data, marking it as write packaged data, sending the write packaged data to the first FPGA module, and the first FPGA module saving the write packaged data;

[0060] Step S33, the first CPU sends an instruction to read the write packaged data saved by the first FPGA module to the first FPGA module through the first LPC bus, marked as a read instruction, obtains the data corresponding to the read instruction, marked as read data, packages the read data, marked as read packaged data, and sends the read packaged data to the first CPU through the first LPC bus. For detailed steps, refer to step S2.

[0061] Embodiment 2, the present application also provides an electronic device, which may include: a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus. The memory stores computer-readable instructions, and the processor can call the instructions in the memory. When the computer-readable instructions are executed by the processor, the steps in a dual-CPU data real-time interaction method are executed to achieve the following functions: the first CPU sends write data to the first FPGA module through the first LPC bus, obtains the size of the write data, packages the write data based on the size of the write data, and sends the write packaged data to the second FPGA module, the second CPU sends an instruction to read the write packaged data saved by the second FPGA module to the second FPGA module through the fourth LPC bus, packages the read data, and sends the read packaged data to the second CPU through the fourth LPC bus.

[0062] In addition, the logic instructions in the above-mentioned memory can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art, and the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk.

[0063] Embodiment 3. The present application also provides a computer program product, which includes a computer program stored on a computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute a dual-CPU data real-time interaction method provided by the above methods, and the method includes: sending write data to a first FPGA module through a first LPC bus by a first CPU, obtaining the size of the write data, packaging the write data based on the size of the write data, and sending the write packaged data to a second FPGA module, the second CPU sending an instruction to read the write packaged data saved by the second FPGA module to the second FPGA module through a fourth LPC bus, packaging the read data, and sending the read packaged data to the second CPU through the fourth LPC bus.

[0064] Embodiment 4, the present application also provides a computer-readable storage medium, the present application provides a storage medium, on which a computer program is stored. When the computer program is executed by the processor, the steps in the above dual-CPU data real-time interaction method are executed to achieve the following functions: the first CPU sends write data to the first FPGA module through the first LPC bus, obtains the size of the write data, packages the write data based on the size of the write data, and sends the write packaged data to the second FPGA module, the second CPU sends an instruction to read the write packaged data saved by the second FPGA module to the second FPGA module through the fourth LPC bus, packages the read data, and sends the read packaged data to the second CPU through the fourth LPC bus.

[0065] Through the description of the above implementation methods, the embodiments of the present invention can be provided as methods, systems or computer program products. Based on such an understanding, the above technical solutions can be essentially or partly contributed to the prior art in the form of software products, which can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and include several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0066] In the embodiments provided in the present application, it should be understood that the disclosed system or method can be implemented in other ways. The embodiments described above are merely schematic. For example, the division of modules or units is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or units can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of systems, modules and units can be electrical, mechanical or other forms.

[0067] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A dual CPU data real-time interaction method, characterized in that: The steps include: Determine whether the first CPU sends data to the second CPU or the second CPU sends data to the first CPU; If the first CPU sends data to the second CPU, the first CPU sends the write data to the first FPGA module via the first LPC bus; Obtain the size of the write data, package the write data based on the size of the write data, mark it as write packaged data, send the write packaged data to the second FPGA module, and the second FPGA module saves the write packaged data; The second CPU sends an instruction to read the write packaged data saved by the second FPGA module to the second FPGA module through the fourth LPC bus, marking it as a read instruction, obtains data corresponding to the read instruction, marks it as read data, packages the read data, marks it as read packaged data, and sends the read packaged data to the second CPU through the fourth LPC bus; If the second CPU sends data to the first CPU, similarly, the step of the first CPU sending data to the second CPU is completed, and the second CPU sends data to the first CPU.

2. A dual CPU data real-time interaction method according to claim 1, characterized in that: Obtaining the size of the written data includes the following sub-steps: The first FPGA module includes a first LPC transfer unit, a first dual-port RAM unit, a first dual-port RAM control unit, a first LPC parsing unit and a second LPC parsing unit; The size of the written data obtained by the first LPC parsing unit is A i .

3. A dual CPU data real-time interaction method according to claim 2, characterized in that: Packing the written data based on the size of the written data includes the following sub-steps: The write data and the size of the write data A i Sending to the first LPC forwarding unit; The first LPC forwarding unit determines A i Is it greater than the sending threshold Ay? If A i If it is less than the sending threshold Ay, A i The size of the next data to be written is A i+1 Accumulate until the accumulated sum is greater than the sending threshold Ay, pack all the accumulated write data and mark them as accumulated packed data. i If it is greater than the sending threshold Ay, the written data is directly packaged and marked as directly packaged data.

4. A dual CPU data real-time interaction method according to claim 3, characterized in that: Sending the packaged write data to the second FPGA module includes the following sub-steps: Mark the accumulated packaged data and the direct packaged data as written packaged data; Each time the packing of the write-packed data is completed, the write-packed data is sent to the second FPGA module via the third LPC bus.

5. A dual CPU data real-time interaction method according to claim 4, characterized in that: The second FPGA module saves and writes the packaged data, including the following sub-steps: The second FPGA module includes a second LPC transfer unit, a second dual-port RAM unit, a second dual-port RAM control unit, a third LPC parsing unit and a fourth LPC parsing unit; The third LPC parsing unit receives the write-packed data and performs frame parsing on the write-packed data, and sends the write-packed data after frame parsing to the second dual-port RAM control unit, and the second dual-port RAM control unit writes the write-packed data after frame parsing into the second dual-port RAM unit.

6. A dual CPU data real-time interaction method according to claim 5, characterized in that: Acquiring corresponding data based on the instruction of reading the second FPGA module to save the written packaged data includes the following sub-steps: The third LPC parsing unit receives the read instruction and performs frame parsing on the read instruction, and sends the frame-parsed read instruction to the second dual-port RAM control unit.

7. A dual CPU data real-time interaction method according to claim 6, characterized in that: Packaging the read data includes the following sub-steps: The second dual-port RAM control unit reads the read data from the second dual-port RAM module according to the read instruction after the frame analysis, and sends the read data to the third LPC analysis unit.

8. A dual CPU data real-time interaction method according to claim 7, characterized in that: Sending the read packaged data to the second CPU via the fourth LPC bus comprises the following sub-steps: The third LPC parsing unit performs frame packaging on the read data, marks the read packaged data, and sends the read packaged data to the second CPU module through the fourth LPC bus.

9. A dual CPU data real-time interaction method according to claim 8, characterized in that: The second CPU sending data to the first CPU includes the following sub-steps: The second CPU sends write data to the second FPGA module via the fourth LPC bus; Obtain the size of the write data, package the write data based on the size of the write data, mark it as write packaged data, send the write packaged data to the first FPGA module, and the first FPGA module saves the write packaged data; The first CPU sends an instruction to read the write packaged data saved by the first FPGA module to the first FPGA module through the first LPC bus, marks it as a read instruction, obtains data corresponding to the read instruction, marks it as read data, packages the read data, marks it as read packaged data, and sends the read packaged data to the first CPU through the first LPC bus.

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