Two-wire communication method and device for integrated chip, and integrated chip

Abstract

The invention relates to the technical field of chip communication, and discloses a double-line communication method for an integrated chip, and the method comprises the steps: filling received to-be-verified data into a first transmission cache region under the condition that a verification demand is received; sending the to-be-verified data in the first sending cache region to a slave chip through a first data bus; the address of the first receiving cache region is configured, and data sampling is carried out on the second data bus to receive verification data sent by the slave chip; and storing the received verification data into the first receiving cache region so as to read the verification data. Two-wire communication between integrated chips can be realized, and the chip area can be reduced. The invention further discloses a two-wire communication device for the integrated chip and the integrated chip.

Description

Technical Field

[0001] The present application relates to the field of chip communication technology, for example, to a two-wire communication method and device for an integrated chip, and an integrated chip. Background Art

[0002] At present, with the improvement of the maturity of the chip industry, integrated chips have become a common chip architecture model. Integrated chips may contain independent modules with different functions. For example, the NFC integrated chip used for financial payment contains CLF (ContantLess Frontend, contactless communication module) and SE (Secure Element, security unit). The two modules are two different circuits with independent functions. The main function of CLF is to complete the contactless communication, and SE is mainly to complete the encryption and decryption authentication of financial information. Therefore, transactions based on NFC chips require several communications between CLF and SE to complete.

[0003] In order to realize the interconnection communication of integrated chips, the relevant technology discloses a two-wire transmission protocol Uart. The baud rate of Uart usually includes 9600baud, 19200baud, 38400baud, 57600baud and 115200baud, etc. The transmission rate of Uart is relatively low. At the same time, in order to correctly send or receive Uart data, a specific high-frequency osc clock is required in the chip to serve as the sampling clock of Uart to ensure the reliability of Uart long frame communication.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] Currently, NFC is most widely used in mobile terminals such as mobile phones and watches, so the area of ​​NFC chips should be as small as possible to be suitable for the application end. Related technologies A specific osc clock will add an osc analog circuit, increase the circuit design tasks, and occupy the chip area, increasing the area overhead.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a two-wire communication method and device for an integrated chip, and an integrated chip, so as to realize two-wire communication between integrated chips and reduce the chip area.

[0009] In some embodiments, the two-wire communication method for integrated chips is applied to a host chip, including: when a verification request is received, filling the received data to be verified into a first sending buffer; sending the data to be verified in the first sending buffer to the slave chip via a first data bus; configuring the address of the first receiving buffer, and performing data sampling on the second data bus to receive the verification data sent by the slave chip; storing the received verification data in the first receiving buffer to read the verification data.

[0010] Optionally, when a verification requirement is received, the received data to be verified is filled into a first sending buffer, including: when contactless communication data is received, decoding the contactless communication data to determine whether the contactless communication data contains a verification requirement; when the contactless communication data contains a verification requirement, configuring the physical location of the first sending buffer; and filling the data to be verified in the contactless communication data into the first sending buffer.

[0011] Optionally, the data to be verified in the first sending buffer area is sent to the slave chip via the first data bus, including: starting the data management platform DMP module and configuring the length of the data to be verified; pre-fetching the data to be verified in the first sending buffer area through the DMP module; using the direct memory access DMA module to put the pre-fetched data to be verified into the first data bus for sending; and reporting an interrupt signal after all the pre-fetched data to be verified are sent.

[0012] Optionally, the received verification data is stored in the first receiving buffer area to read the verification data, including: combining the received verification data into byte and / or word form; storing the verification data in the first receiving buffer area through a direct memory access DMA module; and reading the verification data after the interrupt signal is reported.

[0013] In some embodiments, the two-wire communication method for integrated chips is applied to a slave chip, including: configuring the address of a second receiving buffer area, performing data sampling on a first data bus to receive data to be verified sent by a host chip; storing the received data to be verified in a second receiving buffer area; verifying the received data to be verified, obtaining verification data and filling it into a second sending buffer area; and sending the verification data of the second sending buffer area to the host chip via a second data bus.

[0014] Optionally, storing the received data to be verified in the second receiving buffer area includes: combining the received data to be verified into byte and / or word form; storing the data to be verified in the second receiving buffer area through a direct memory access DMA module; and reporting an interrupt signal when reception is completed.

[0015] Optionally, when the reception is completed, the interrupt signal reported includes: detecting whether there is valid data on the first data bus; and reporting the interrupt signal when there is no valid data on the first data bus.

[0016] Optionally, the verification data of the second sending buffer area is sent to the host chip via the second data bus, including: starting the data management platform DMP module and configuring the length of the verification data; pre-fetching the verification data of the second sending buffer area via the DMP module; using the direct memory access DMA module to put the pre-fetched verification data into the second data bus for sending; and reporting an interrupt signal after all the pre-fetched verification data are sent.

[0017] In some embodiments, the two-wire communication device for an integrated chip includes: a processor and a memory storing program instructions, and the processor is configured to execute the two-wire communication method for an integrated chip as described above when running the program instructions.

[0018] In some embodiments, the integrated chip includes: a host chip; a slave chip; and the two-wire communication device for the integrated chip as described above is installed on the host chip and / or the slave chip.

[0019] The two-wire communication method and device for integrated chips and the integrated chip provided by the embodiments of the present disclosure can achieve the following technical effects:

[0020] In the disclosed embodiment, when data that needs to be verified is received, the data is filled into the first sending buffer area for subsequent processing. Then, the data to be verified in the first sending buffer area is sent to the slave chip through the first data bus. At the same time, the host chip needs to configure the address of the first receiving buffer area and perform data sampling on the second data bus to prepare to receive the verification data sent back by the slave chip. When the slave chip completes the verification operation, it will send the verification data back to the host chip through the second data bus, and the host chip will store the verification data in the first receiving buffer area through sampling of the second data bus. In this way, the host chip can read the verification data from the first receiving buffer area to complete the entire verification process. Full-duplex communication between chips is achieved, the number of pads required for communication is reduced, the chip area and cost are reduced, and the data processing speed and communication efficiency are improved, meeting the needs of integrated chips for high-performance communication.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 is a schematic diagram of an implementation environment of a two-wire communication method for an integrated chip according to an embodiment of the present disclosure;

[0024] Figure 2 is a schematic diagram of a two-wire communication method for an integrated chip provided by an embodiment of the present disclosure;

[0025] Figure 3 is a schematic diagram of another two-wire communication method for an integrated chip provided by an embodiment of the present disclosure;

[0026] Figure 4 It is a schematic diagram of the representation of logic 1 and logic 0 of the first data bus provided by the embodiment of the present disclosure;

[0027] Figure 5 is a DWP module maximum rate bus timing diagram provided by an embodiment of the present disclosure;

[0028] Figure 6 It is a schematic diagram of a two-wire communication device for an integrated chip provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0030] The terms "first", "second", etc. in the technical solutions described in the embodiments of the present disclosure are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged where appropriate, so as to describe the embodiments of the present disclosure described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0031] Unless otherwise stated, the term "plurality" means two or more.

[0032] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0033] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0034] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0035] At present, with the rapid development of intelligent devices and the increase in diversified application scenarios, higher requirements are placed on the size and cost of NFC chips. NFC chips need to reduce their size as much as possible while maintaining functionality to adapt to the compact space requirements of mobile devices such as smartphones and smart watches. This not only helps to improve the portability and aesthetics of the device, but also integrates more functional modules in a limited space. At the same time, design manufacturers are under pressure to reduce costs in order to improve market competitiveness.

[0036] Figure 1 FIG. 1 is a schematic diagram of an implementation environment of a two-wire communication method for an integrated chip according to an embodiment of the present disclosure. Figure 1 As shown, the implementation environment may include a host chip 100 , a slave chip 200 , a first data bus 300 , and a second data bus 400 .

[0037] The host chip 100 receives the contactless data communication, and after decoding, sends the information to be verified to the slave chip 200 via the first data bus 300 .

[0038] After receiving the authentication request, the slave chip 200 performs an authentication operation on the data and sends the result back to the host through the second data bus 400 to complete the entire verification process.

[0039] Combination Figure 2 As shown, the embodiment of the present disclosure provides a two-wire communication method for an integrated chip, which is applied to a host chip, including:

[0040] S201, when receiving a verification request, the host chip fills the received data to be verified into a first sending buffer area.

[0041] S202, the host chip sends the to-be-verified data in the first sending buffer area to the slave chip via the first data bus.

[0042] S203, the host chip configures the address of the first receiving buffer area, and performs data sampling on the second data bus to receive the verification data sent by the slave chip.

[0043] S204, the host chip stores the received verification data into the first receiving buffer area to read the verification data.

[0044] Using the two-wire communication method for integrated chips provided by the embodiment of the present disclosure, when receiving data that needs to be verified, the data is filled into the first sending buffer area for subsequent processing. Then, the data to be verified in the first sending buffer area is sent to the slave chip through the first data bus. At the same time, the host chip needs to configure the address of the first receiving buffer area and perform data sampling on the second data bus to prepare to receive the verification data sent back by the slave chip. When the slave chip completes the verification operation, it will send the verification data back to the host chip through the second data bus, and the host chip will store the verification data in the first receiving buffer area through sampling of the second data bus. In this way, the host chip can read the verification data from the first receiving buffer area to complete the entire verification process. Full-duplex communication between chips is realized, the number of pads required for communication is reduced, the chip area and cost are reduced, and the data processing speed and communication efficiency are improved, meeting the needs of integrated chips for high-performance communication.

[0045] Optionally, when a verification requirement is received, the received data to be verified is filled into a first sending buffer, including: when contactless communication data is received, decoding the contactless communication data to determine whether the contactless communication data contains a verification requirement; when the contactless communication data contains a verification requirement, configuring the physical location of the first sending buffer; and filling the data to be verified in the contactless communication data into the first sending buffer.

[0046] In the disclosed embodiment, when the host chip receives contactless communication data, it will first decode the data to identify whether the data contains requirements that require security verification. This is the key to ensuring data security, because only data containing verification requirements will trigger the subsequent security verification process. If it is found after decoding that the contactless communication data does contain verification requirements, the physical location of the first sending buffer is configured. The buffer is specially prepared for the data to be verified, and the configuration of its physical location ensures that the data can be accurately stored and subsequently processed. The part of the contactless communication data that needs to be verified is filled in the first sending buffer to be sent to the slave chip. The disclosed embodiment not only improves the efficiency of data processing, but also enhances the security of data transmission. In this way, the NFC chip can meet the growing demand for data security and processing speed of intelligent devices while maintaining miniaturization and low cost.

[0047] Optionally, the data to be verified in the first sending buffer area is sent to the slave chip via the first data bus, including: starting the data management platform DMP module and configuring the length of the data to be verified; pre-fetching the data to be verified in the first sending buffer area through the DMP module; using the direct memory access DMA module to put the pre-fetched data to be verified into the first data bus for sending; and reporting an interrupt signal after all the pre-fetched data to be verified are sent.

[0048] In the disclosed embodiment, when the host chip needs to send the data to be verified to the slave chip, the DMP (Data Management Platform) module will be started first, and the DMP module is responsible for managing and scheduling data transmission. After starting the DMP module, it is necessary to configure the length of the data to be verified to ensure the integrity and accuracy of data transmission. The DMP module will pre-fetch the data to be verified in the first sending buffer area, which can improve the efficiency of data transmission.

[0049] The DMA (Direct Memory Access) module allows data to be transferred directly between the memory and other peripherals without passing through the CPU (Central Processing Unit), thereby reducing the burden on the CPU and increasing the data transfer rate. The DMA module puts the pre-fetched data to be verified into the first data bus for transmission, so that the data can be quickly transmitted to the slave chip. After all the pre-fetched data to be verified are sent, the system will report an interrupt signal to notify the CPU that the data transmission has been completed, and the CPU can proceed to the next step of processing. The disclosed embodiment not only improves the efficiency of data transmission, but also reduces the energy consumption of the chip because the CPU intervention is reduced. At the same time, because data transmission and processing can be performed in parallel, the response speed of the system is also improved.

[0050] Optionally, the received verification data is stored in the first receiving buffer area to read the verification data, including: combining the received verification data into byte and / or word form; storing the verification data in the first receiving buffer area through a direct memory access DMA module; and reading the verification data after the interrupt signal is reported.

[0051] In the disclosed embodiment, after completing the verification operation, the slave chip will send the verification data back to the host chip. After the host chip receives the data, it first needs to combine these scattered verification data into the form of byte and / or word, so that the verification data conforms to the standard unit of data processing, which is convenient for subsequent processing and analysis. Then, the DMA module is used to store these combined verification data directly into the first receiving buffer area. This area is pre-configured and is specifically used to store data received from the slave chip. After all the verification data are stored in the first receiving buffer area through the DMA module, the system will report an interrupt signal to the CPU, notifying the CPU that the data is ready and can be read and further processed. After receiving the interrupt signal, the CPU will read the verification data from the first receiving buffer area and perform subsequent logical judgments and decisions.

[0052] This process reduces the involvement of the CPU, which not only improves the efficiency of data transmission, but also reduces energy consumption. This enables NFC chips to meet the needs of modern mobile devices for high-speed data processing and low energy consumption, especially in application scenarios such as financial payments that require extremely high security and speed, which can significantly improve user experience and system reliability.

[0053] In some embodiments, the two-wire communication method for integrated chips is applied to a slave chip, including: configuring the address of a second receiving buffer area, performing data sampling on a first data bus to receive data to be verified sent by a host chip; storing the received data to be verified in a second receiving buffer area; verifying the received data to be verified, obtaining verification data and filling it into a second sending buffer area; and sending the verification data of the second sending buffer area to the host chip via a second data bus.

[0054] Combination Figure 3 As shown, the embodiment of the present disclosure provides another two-wire communication method for an integrated chip, which is applied to a slave chip, including:

[0055] S301, the slave chip configures the address of the second receiving buffer area, and performs data sampling on the first data bus to receive the data to be verified sent by the host chip.

[0056] S302, the slave chip stores the received data to be verified into a second receiving buffer area.

[0057] S303, the slave chip verifies the received data to be verified, obtains verification data and fills it into the second sending buffer area.

[0058] S304, the slave chip sends the verification data in the second sending buffer area to the host chip through the second data bus.

[0059] In the disclosed embodiment, the communication process of the slave chip is a key link to improve data security and communication efficiency. First, the slave chip needs to configure the address of the second receiving buffer area to ensure that the data to be verified sent from the host chip can be correctly received and stored. Next, the slave chip performs data sampling on the first data bus. The slave chip monitors the signal changes on the data bus and converts these changes into digital signals in order to read the data to be verified sent by the host chip. The data is then stored in the second receiving buffer area configured previously. The slave chip performs a verification operation on the data to be verified in the second receiving buffer area. After the verification is completed, the slave chip fills the obtained verification data into the second sending buffer area. Finally, the verification data in the second sending buffer area is sent to the host chip via the second data bus to complete the entire communication process.

[0060] like Figure 4 As shown, Figure 4 It is the representation form of logic 1 and logic 0 of the first data bus, with two rising edges as the representation cycle of 1 bit data, where if the ratio of high level to low level is 1:3, it indicates that the cycle is logic 0, and if the ratio of high level to low level is 3:1, it indicates that the cycle is logic 1. After the slave chip receives the data of the first data bus, it needs to parse the data to be verified by the ratio of high and low levels in the cycle to verify the data to be verified.

[0061] The disclosed embodiments not only improve the security of data transmission, because the verification process ensures the accuracy and integrity of the data, but also improve the communication efficiency. Because the transmission and reception of data are carried out in parallel through two independent data buses, full-duplex communication is achieved. In this way, the physical connection required for communication is reduced, the complexity and cost of the chip are reduced, and the speed and security of data processing are improved.

[0062] Optionally, storing the received data to be verified in the second receiving buffer area includes: combining the received data to be verified into byte and / or word form; storing the data to be verified in the second receiving buffer area through a direct memory access DMA module; and reporting an interrupt signal when reception is completed.

[0063] In the disclosed embodiment, the slave chip receives the data to be verified from the master chip on the first data bus. The data may initially exist in the form of a bit stream, which needs to be recognized by the slave chip and combined into a higher-level data structure, such as a byte or word form, for subsequent processing and verification. This step involves parsing and reorganizing the data to ensure the integrity and accuracy of the data during transmission.

[0064] Optionally, when the reception is completed, the interrupt signal reported includes: detecting whether there is valid data on the first data bus; and reporting the interrupt signal when there is no valid data on the first data bus.

[0065] In the disclosed embodiment, the slave chip will continuously detect whether there is valid data on the bus. This is usually achieved by checking the level change on the bus, the structure of the data frame, or a specific data tag to ensure that only when the data is complete and conforms to the expected format, it is considered valid data.

[0066] like Figure 5 As shown, Figure 5 The figure shows the maximum bus speed timing diagram of the DWP module. In the figure, DWP_CYCLE is based on 4 CLF_SYS_CLK as a cycle (the cycle is configurable, and the DWP bus speed can be configured according to the main frequency of the master and slave chips. This figure takes the maximum speed as an example). During this cycle, the host chip drives the high and low level ratio of the first data bus D1 to indicate the transmission of logic 0 or logic 1. Figure 5 The dotted line in the middle is the rising edge of the first data bus D1. When the first data bus D1 is at the rising edge, the slave chip drives the second data bus d2 to transmit data at high and low levels. Figure 5 Given the timing and sampling point, the slave chip detects whether the level on the first data bus D1 meets the requirements. Figure 5 Given a logic 0 or logic 1 for valid data.

[0067] Once the slave chip confirms that there is no valid data on the first data bus, that is, all expected data has been received, it will trigger an interrupt signal to notify the CPU of the end of the communication event, thereby allowing the system to proceed to the next step, such as processing the received data, releasing occupied resources, or preparing for the next communication.

[0068] Combination Figure 5 As shown, the slave chip performs data sampling on the first data bus D1, including the slave chip according to Figure 5 With given timing and sampling points, data is collected on the first data bus D1.

[0069] Combination Figure 5 As shown, the host chip performs data sampling on the second data bus D2, including: the host chip samples the level transmitted by the second data bus D2 at the rising edge of the first data bus D1, and receives data from the slave chip. The dotted line position is the rising edge of the first data bus D1, and the slave chip transmits data through the high and low levels of the second data bus D2 at the rising edge of the first data bus D1.

[0070] Optionally, the verification data of the second sending buffer area is sent to the host chip via the second data bus, including: starting the data management platform DMP module and configuring the length of the verification data; pre-fetching the verification data of the second sending buffer area via the DMP module; using the direct memory access DMA module to put the pre-fetched verification data into the second data bus for sending; and reporting an interrupt signal after all the pre-fetched verification data are sent.

[0071] The slave chip performs corresponding verification operations on the data and needs to feedback the processed results. The communication between chips uses the DWP module. The slave chip configures the sending buffer address. At the same time, the DWP module actively starts pre-fetching, requests the DMA module, and moves the first byte of the data to be sent. At the same time, the 7th bit (big endian mode) of the first byte is directly placed on the second data bus D2, waiting for the rising edge signal of the first data bus D1, and then the 6th bit of the first byte is placed on the second data bus D2. By analogy, the transmission of the slave chip depends on the change of the signal on the first data bus D1. According to the configured number of data to be sent, the second data bus D2 is driven to present logic 1 and logic 0 data in a high and low level manner through the configuration with the first data bus D1. The slave chip only needs to ensure the stability of the data of the second data bus D2 at the rising edge of the dotted line, which can effectively reduce the timing requirements for the second data bus D2, making the DWP module run faster.

[0072] In the disclosed embodiment, the slave chip starts the DMP module to configure the length of the verification data and pre-fetches the verification data in the second sending buffer. After the pre-fetch is completed, the DMA module is used to directly transmit between the memory and other peripherals, which reduces the burden of the CPU and increases the data transmission rate. The DMA module puts the pre-fetched verification data into the second data bus for transmission, and can quickly transfer the data to the host chip.

[0073] After all pre-fetched verification data is sent through the DMA module, an interrupt signal is reported to the CPU to notify the CPU that the data has been sent and that the next step of processing or related resources can be released.

[0074] Combination Figure 6As shown, the embodiment of the present disclosure provides a two-wire communication device 60 for an integrated chip, including a processor 600 and a memory 601. Optionally, the device 60 may also include a communication interface 602 and a bus 603. The processor 600, the communication interface 602, and the memory 601 may communicate with each other through the bus 603. The communication interface 602 may be used for information transmission. The processor 600 may call the logic instructions in the memory 601 to execute the two-wire communication method for an integrated chip of the above embodiment.

[0075] In addition, the logic instructions in the memory 601 described above can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0076] The memory 601 is a computer-readable storage medium that can be used to store software programs and computer executable programs, such as program instructions / modules corresponding to the method in the embodiment of the present disclosure. The processor 600 executes the functional application and data processing by running the program instructions / modules stored in the memory 601, that is, the two-wire communication method for the integrated chip in the above embodiment is implemented.

[0077] The memory 601 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application required for at least one function; the data storage area may store data created according to the use of the terminal device, etc. In addition, the memory 601 may include a high-speed random access memory and may also include a non-volatile memory.

[0078] The disclosed embodiments provide an integrated chip, including: a host chip, a slave chip, and the above-mentioned two-wire communication device for the integrated chip. The two-wire communication device for the integrated chip is installed in the host chip and / or the slave chip. The installation relationship described here is not limited to placement inside the host chip and / or the slave chip, but also includes installation connections with other components of the host chip and / or the slave chip, including but not limited to physical connections, electrical connections or signal transmission connections, etc. Those skilled in the art can understand that the two-wire communication device for the integrated chip can be adapted to a feasible host chip and / or slave chip body, thereby realizing other feasible embodiments.

[0079] The technical solution of the embodiment of the present disclosure can be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the embodiment of the present disclosure. The aforementioned storage medium may be a non-transient storage medium, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk, and other media that can store program codes.

[0080] The above description and the accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible changes. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the claims. As used in the description of the embodiments and the claims, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0081] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods for each specific application to implement the described functions, but such implementations should not be considered to exceed the scope of the embodiments of the present disclosure. The technicians may clearly understand that, for the convenience and simplicity of description, the specific working processes of the systems, devices and units described above may refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0082] In the embodiments disclosed herein, the disclosed methods and products (including but not limited to devices, equipment, etc.) can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units can be only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between each other shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the units may be selected according to actual needs to implement this embodiment. In addition, each functional unit in the embodiment of the present disclosure may be integrated in a processing unit, or each unit may exist physically alone, or two or more units may be integrated in one unit.

[0083] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A two-wire communication method for an integrated chip, applied to a host chip, characterized in that: include: When receiving a verification request, filling the received data to be verified into the first sending buffer; Sending the to-be-verified data in the first sending buffer area to the slave chip via the first data bus; Configure the address of the first receiving buffer area, and perform data sampling on the second data bus to receive the verification data sent by the slave chip; The received verification data is stored in the first receiving buffer area to read the verification data.

2. The two-wire communication method according to claim 1, characterized in that: When a verification request is received, the received data to be verified is filled into a first sending buffer, including: When receiving the contactless communication data, decoding the contactless communication data to determine whether the contactless communication data contains the verification requirement; In the case where the contactless communication data includes a verification requirement, configuring a physical location of the first sending buffer; The data to be verified in the contactless communication data is filled into the first sending buffer area.

3. The two-wire communication method according to claim 1, characterized in that: The method includes sending the to-be-verified data in the first sending buffer area to the slave chip via the first data bus, including: Start the data management platform DMP module and configure the length of the data to be verified; Pre-fetching the data to be verified in the first sending buffer area through the DMP module; Using a direct memory access (DMA) module, the pre-fetched data to be verified is put into a first data bus for transmission; After all pre-fetched data to be verified are sent, an interrupt signal is reported.

4. The two-wire communication method according to claim 3, characterized in that: The received verification data is stored in a first receiving buffer area to read the verification data, including: Combine the received verification data into byte and / or word form; Storing the verification data in a first receiving buffer area through a direct memory access DMA module; After the interrupt signal is reported, the verification data is read.

5. A two-wire communication method for an integrated chip, applied to a slave chip, characterized in that: include: Configure the address of the second receiving buffer area, perform data sampling on the first data bus to receive the data to be verified sent by the host chip; Storing the received data to be verified in a second receiving buffer area; Verifying the received data to be verified, obtaining verification data and filling it into the second sending buffer; The verification data in the second sending buffer area is sent to the host chip through the second data bus.

6. The two-wire communication method according to claim 5, characterized in that: Storing the received data to be verified in the second receiving buffer area includes: Combine the received data to be verified into byte and / or word form; The data to be verified is stored in the second receiving buffer area through a direct memory access DMA module; When reception is completed, the interrupt signal is reported.

7. The two-wire communication method according to claim 6, characterized in that: When reception is completed, the interrupt signal reported includes: Detecting whether there is valid data on the first data bus; When there is no valid data on the first data bus, an interrupt signal is reported.

8. The two-wire communication method according to claim 5, characterized in that: Sending the verification data of the second sending buffer area to the host chip through the second data bus includes: Start the data management platform DMP module and configure the length of the verification data; Pre-fetching the verification data of the second sending buffer area through the DMP module; Using a direct memory access (DMA) module, the pre-fetched verification data is placed on a second data bus for transmission; After all pre-fetched verification data is sent, an interrupt signal is reported.

9. A two-wire communication device for an integrated chip, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the two-wire communication method for an integrated chip according to any one of claims 1 to 8 when running the program instructions.

10. An integrated chip, characterized in that: include: Host chip; Slave chip; The two-wire communication device for integrated chip as claimed in claim 9 is installed in the host chip and / or the slave chip.

Images