Data transmission method and device, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a data transmission method and device, electronic equipment and a storage medium, and relates to the technical field of data transmission. The method is applied to a network-on-chip, and the network-on-chip comprises a routing node; the routing node comprises a crossbar switch, a plurality of input ports and a plurality of output ports, and the crossbar switch processes requests of the input ports in a fixed priority arbitration mode; the method comprises the following steps: dividing input buffer areas of at least part of input ports in a plurality of input ports into a plurality of sub-buffer areas corresponding to output ports; storing the data in the input buffer area of the input port to the corresponding sub-buffer areas according to the difference of the output ports; and under the condition that the sub-buffer area of one input port is subjected to head blocking, sending data in the rest sub-buffer areas of the input port and in the idle sub-buffer area of the output port corresponding to the current moment. According to the invention, the head blocking does not affect the data transmission in the other sub-buffers of the input port, and the time delay is less.

Description

Technical Field

[0001] The present invention relates to the technical field of data transmission, and in particular to a data transmission method, a data transmission device, an electronic device and a storage medium. Background Art

[0002] Network-on-Chip (NoC) is an interconnection architecture of System-on-Chip (SoC). It has broad application prospects due to its advantages such as higher bandwidth.

[0003] When a crossbar switch of a routing node of an on-chip network uses a fixed-priority arbitration method to process requests from various input ports, head blocking is prone to occur.

[0004] However, other output ports may be idle at this time, but other data is still blocked in the input buffer where the head is blocked, resulting in further increase in data transmission delay. Summary of the invention

[0005] In view of the above problems, an embodiment of the present invention is proposed to provide a data transmission method that overcomes the above problems or at least partially solves the above problems, so as to reduce data transmission delay.

[0006] In a first aspect, the present invention provides a data transmission method, which is applied to an on-chip network, wherein the on-chip network comprises: a routing node; the routing node comprises: a cross switch, a plurality of input ports and a plurality of output ports, the cross switch processes requests of each of the input ports in an arbitration manner with a fixed priority; the method comprises: Splitting the input buffers of at least some of the input ports into a plurality of sub-buffers corresponding to the output ports; The data in the input buffer of the input port is stored in the corresponding sub-buffer according to different output ports; When head blocking occurs in the sub-buffer of one of the input ports, data in the idle sub-buffer of the output port corresponding to the current moment among the remaining sub-buffers of the input port is sent out.

[0007] In a second aspect, the present invention provides a data transmission device, which is applied to an on-chip network, wherein the on-chip network includes: a routing node; the routing node includes: a cross switch, a plurality of input ports and a plurality of output ports, and the cross switch processes requests of each of the input ports in an arbitration manner with a fixed priority; the device includes: A splitting module, used for splitting the input buffers of at least some of the input ports into a plurality of sub-buffers corresponding to the output ports; A storage module, used for storing the data in the input buffer of the input port into the corresponding sub-buffer according to different output ports; The sending module is used to send out the data in the idle sub-buffer of the output port corresponding to the current moment among the remaining sub-buffers of the input port when the sub-buffer of one of the input ports is blocked by the head.

[0008] In a third aspect, the present invention provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the above-mentioned data transmission method when executing the program.

[0009] In a fourth aspect, the present invention provides a readable storage medium, which, when instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to execute the above-mentioned data transmission method.

[0010] In a fifth aspect, the present invention provides a computer program product, comprising instructions, which, when executed by a processor in an electronic device, enable the electronic device to execute any one of the aforementioned data transmission methods.

[0011] The present invention includes at least the following advantages: In the present invention, when the cross switch of the routing node of the on-chip network processes the request of each input port by using a fixed priority arbitration method, the input buffer of at least part of the input ports among the plurality of input ports is divided into a plurality of sub-buffers corresponding to the output ports, and the data in the input buffer of the input port is stored in the corresponding sub-buffer according to the different output ports. Therefore, in the case of header blocking in the sub-buffer of an input port, the header blocking will only block the sub-buffer of the input port, and will not block the remaining sub-buffers of the input port, that is, the header blocking will basically not affect the sending of the data in the remaining sub-buffers of the input port, and the data in the idle sub-buffer of the output port corresponding to the current moment among the remaining sub-buffers of the input port will be sent, that is, the header blocking will basically not increase the transmission delay of the data in the remaining sub-buffers of the input port, thereby reducing the transmission delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0013] Figure 1 A schematic structural diagram of a routing node of the present invention is shown; Figure 2 A schematic diagram of a head blocking of the present invention is shown; Figure 3 A flowchart showing a data transmission method embodiment of the present invention; Figure 4 A flowchart showing another data transmission method embodiment of the present invention is shown; Figure 5 A schematic diagram of data transmission according to the present invention is shown; Figures 6 to 10 A schematic diagram of a data transmission process of the present invention is shown; Fig.11 A structural block diagram of an embodiment of a data transmission device of the present invention is shown; Fig.12 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] The present application provides a data transmission method, which is applied to an on-chip network. The on-chip network includes: a routing node (Router), and the number of routing nodes in the on-chip network is not limited. Figure 1 This is a schematic diagram of a routing node. Figure 1 , the routing node includes: a crossbar, a number of input ports and a number of output ports, wherein the direction toward the crossbar indicates the input, and the direction away from the crossbar indicates the output. There is no limit on the number of input ports and the number of output ports included in a routing node, and there is no specific limit on whether the number of input ports and the number of output ports are equal. For example, Figure 1 In the example, a routing node includes: a crossbar switch, 6 input ports and 6 output ports.

[0016] In the present application, the cross switch of the routing node uses a fixed priority arbitration method to process the requests of each input port, that is, the cross switch of the routing node always uses a fixed priority arbitration method to process the requests of each input port, in which case head blocking is prone to occur. Figure 2 A schematic diagram of head blocking is shown. Figure 2 , Figures 5 to 10 In the data, N refers to the data to be transmitted to the north output port, W refers to the data to be transmitted to the west output port, P0 refers to the data to be transmitted to the output port 0 connected to the device and the routing node, and P1 refers to the data to be transmitted to the output port 1 connected to the device and the routing node. The data here can refer to Flit (the smallest unit of routing transmission). For example, Figure 2 In the , the crossbar switch of the routing node uses a fixed priority arbitration method to process the requests of each input port, and the priority of the east input port is higher than that of the south input port. Figure 2 In the case shown, both the input buffer of the east input port and the input buffer of the south input port have N. Since the priority of the east input port is higher than that of the south input port, the N in the input buffer of the east input port will be sent to the north output port through the cross switch first, and the N in the input buffer of the south input port will be blocked, and it is necessary to wait for all the N in the input buffer of the east input port to be sent before it can be sent. However, P0 and P1 in the input buffer of the south input port are ranked after N, so it is necessary to wait for N in the input buffer of the south input port to be sent before it can be sent. Even if the output port 0 connected to the device and the routing node and the output port 1 connected to the device and the routing node are idle at the current moment, P0 and P1 in the input buffer of the south input port cannot be sent. This is head blocking, which will cause the output port 0 connected to the device and the routing node and the output port 1 connected to the device and the routing node to waste resources, and the transmission delay will be more. The present application can solve the problem of head blocking described above, and the data transmission method of the present application is explained in detail below.

[0017] Reference Figure 3 , the data transmission method may specifically include the following steps.

[0018] Step 101: divide the input buffers of at least some of the input ports into a plurality of sub-buffers corresponding to the output ports.

[0019] Here, the input buffers of all input ports of the routing node may be divided into a number of sub-buffers corresponding to the output ports, or only the input buffers of some input ports of the routing node may be divided into a number of sub-buffers corresponding to the output ports. The number of sub-buffers obtained by dividing an input buffer may be equal to the number of output ports of the routing node, or the number of sub-buffers obtained by dividing an input buffer may be less than the number of output ports of the routing node.

[0020] After the input buffer of an input port is divided into a plurality of sub-buffers corresponding to the output ports, the output ports of the data of each sub-buffer are different. It should be noted that the "several" mentioned in this application refers to a natural number greater than or equal to 2. Specifically, the number of sub-buffers into which the input buffer of an input port is divided can be determined according to the number of output ports, routing methods, etc.

[0021] Optionally, the aforementioned step 101 may include: when header blocking occurs in the input buffer of an input port, dividing the input buffer of the input port into a number of sub-buffers corresponding to the output ports; the output port of the data corresponding to the header blocking of the input buffer of the input port is the same as the output port corresponding to the sub-buffer of the input port where the header blocking occurs. That is to say, the input buffer of an input port may be divided into a number of sub-buffers corresponding to the output ports only when header blocking occurs in the input buffer of the input port, or the input buffer of the input port may not be divided when header blocking does not occur in the input buffer of the input port, so the division of the input buffer of the input port is more targeted and can improve resource utilization. With respect to the aforementioned Figure 2 The output port of the data corresponding to the head blocking of the input buffer of the input port (i.e., the south input port) is the north output port, and the output port corresponding to the sub-buffer where the head blocking occurs of the input port (i.e., the south input port) is also the north output port, and the two are the same.

[0022] Step 102: Store the data in the input buffer of the input port into the corresponding sub-buffer according to different output ports.

[0023] The output port to which the data needs to be output is the output port corresponding to the data here. The data in the input buffer of the input port is stored in the corresponding sub-buffer according to the different output ports.

[0024] Step 103: When head blocking occurs in the sub-buffer of one of the input ports, data in the idle sub-buffer of the output port corresponding to the current moment among the remaining sub-buffers of the input port is sent out.

[0025] If header blocking occurs in the data in a sub-buffer of an input port, the remaining data in the sub-buffer of the input port cannot be sent out. In this case, the data in the idle sub-buffer of the output port corresponding to the current moment among the remaining sub-buffers of the input port will be sent out. That is to say, after header blocking occurs in the data in the sub-buffer of the input port, the header blocking will only affect the sending of the data in the sub-buffer of the input port, but will basically not affect the sending of the data in the remaining sub-buffers of the input port, and will basically not increase the transmission delay of the data in the remaining sub-buffers of the input port, thereby reducing the transmission delay.

[0026] It should be noted that the data in the idle sub-buffer of the output port corresponding to the current moment in the remaining sub-buffers of the input port mentioned in this application refers to the data in the sub-buffer of the output port that is not occupied or blocked at the current moment in the remaining sub-buffers of the input port.

[0027] Optionally, the aforementioned step 103 may include: in the case of head blocking in a sub-buffer of an input port, in any of the three methods of polling, fixed priority, and random, the data in the idle sub-buffer corresponding to the output port at the current moment in the remaining sub-buffers of the input port is sent out. Specifically, the number of the remaining sub-buffers of the input port may be greater than or equal to 2. The polling here may mean: after each encounter with head blocking, which sub-buffer in the remaining sub-buffers of the input port is queried first each time, and it is polled in a certain order, and then each sub-buffer in the remaining sub-buffers of the input port is queried one by one in a certain order or period, and when it is found that the output port corresponding to the data in a sub-buffer in the remaining sub-buffers of the input port is idle at the current moment, the data in the sub-buffer in the remaining sub-buffers of the input port is sent out; the fixed priority here means: each sub-buffer in the input port has a fixed priority, and after each encounter with head blocking, it is polled in accordance with each of the remaining sub-buffers of the input port. The fixed priority of the sub-buffers is from high to low, and each sub-buffer in the remaining sub-buffers of the input port is queried in turn. When the output port corresponding to the data in a sub-buffer in the remaining sub-buffers of the input port is idle at the current moment, the data in the sub-buffer in the remaining sub-buffers of the input port is sent out; random here can mean: after each head blocking, each sub-buffer in the remaining sub-buffers of the input port is queried one by one in a random manner from the remaining sub-buffers of the input port, and when the output port corresponding to the data in a sub-buffer in the remaining sub-buffers of the input port is idle at the current moment, the data in the sub-buffer in the remaining sub-buffers of the input port is sent out. The above three methods are easy to implement and have little impact on transmission delay.

[0028] In summary, in the present invention, when the cross switch of the routing node of the on-chip network processes the request of each input port by using a fixed priority arbitration method, the input buffer of at least part of the input ports among the input ports is divided into a plurality of sub-buffers corresponding to the output ports, and the data in the input buffer of the input port is stored in the corresponding sub-buffer according to the different output ports. Therefore, in the case of header blocking in the sub-buffer of an input port, the header blocking will only block the sub-buffer of the input port, and will not block the remaining sub-buffers of the input port, that is, the header blocking will basically not affect the sending of the data in the remaining sub-buffers of the input port, and the data in the idle sub-buffers of the output port corresponding to the current moment in the remaining sub-buffers of the input port will be sent, that is, the header blocking will basically not increase the transmission delay of the data in the remaining sub-buffers of the input port, thereby reducing the transmission delay.

[0029] Figure 4 FIG. 1 is a flowchart showing another embodiment of a data transmission method of the present invention. Figure 4 The data transmission party is also applied to the on-chip network, which includes: a routing node; the routing node includes: a cross switch, a plurality of input ports and a plurality of output ports, and the cross switch uses a fixed priority arbitration method to process the requests of each input port. Here, refer to the above-mentioned related records, and in order to avoid repetition, it will not be repeated here. The method may specifically include the following steps.

[0030] Step 201: Divide at least some of the input ports into input ports of a first priority and input ports of a second priority according to different priorities; the first priority is higher than the second priority.

[0031] Here, all input ports of a routing node may be divided into input ports of the first priority and input ports of the second priority according to different priorities, or, here, some input ports of all input ports of a routing node may be divided into input ports of the first priority and input ports of the second priority according to different priorities. Here, the first priority is higher than the second priority, that is, at the same time, when the input buffer of the input port of the first priority and the input buffer of the input port of the second priority both have data to be sent to the same output port, the cross switch will give priority to sending the data in the input buffer of the input port of the first priority to the same output port, and then send the data in the input buffer of the input port of the second priority to the same output port.

[0032] Optionally, the aforementioned step 201 may include: step 2011 and step 2012. Step 2011, classify the input port with the highest priority among the several input ports as an input port of the first priority; step 2012, classify at least some of the remaining input ports of the several input ports as input ports of the second priority. The number of input ports with the highest priority among the several input ports is not limited here, and it can be only one input port with the highest priority among the several input ports, or it can be multiple input ports with the highest priority among the several input ports, and the priorities of these multiple input ports are different, and there is no specific limitation on this. Step 2012 here can be: classify all input ports among the remaining input ports of the several input ports as input ports of the second priority, or it can be classify some of the remaining input ports of the several input ports as input ports of the second priority, and there is no specific limitation on this.

[0033] Specifically, the data in the input buffer of the input port with the highest priority has the highest priority, so the cross switch will give priority to processing the data in the input buffer of the input port with the highest priority. Therefore, the probability of head blocking of the data in the input buffer of the input port with the highest priority is very small. Therefore, there is no need to split the input buffer of the input port with the highest priority. Only the input buffer of the input port with lower priority can be split into several sub-buffers corresponding to the output ports. The data in the input buffer of the input port with lower priority has a higher probability of head blocking due to the lower priority of the input port, which can avoid waste of resources, improve resource utilization, and reduce transmission delay.

[0034] Optional, see Figure 1 , the several input ports here may include: a first input port, a second input port, a third input port, a fourth input port, a fifth input port and a sixth input port. The cross switch uses a fixed priority arbitration method from high to low, which is the first input port, the second input port, the third input port, the fourth input port, the fifth input port and the sixth input port, to process the requests of each input port. The aforementioned step 2011 may include: classifying the first input port and the second input port as input ports of the first priority; the aforementioned step 2012 may include: classifying the third input port and the fourth input port as input ports of the second priority. Among the first input port to the sixth input port here, the first input port and the second input port are the two input ports with the highest priority. Here, the two input ports with the highest priority among the first input port to the sixth input port are classified as input ports with the first priority. Then, the input buffers for the two input ports with the highest priority do not need to be divided in the subsequent step, which can avoid waste of resources. The priorities of the third input port and the fourth input port here are lower than those of the aforementioned first input port and the second input port. The third input port and the fourth input port with slightly lower priorities are classified as input ports of the second priority. Subsequently, only the input buffer of the input port with slightly lower priority is divided into several sub-buffers corresponding to the output ports. The data in the input buffer of the input port with slightly lower priority has a higher probability of head blocking due to the lower priority of the input port, which can avoid resource waste, improve resource utilization, and reduce transmission delay.

[0035] Step 202: Divide the input buffer of the input port of the second priority into a plurality of sub-buffers corresponding to the output ports.

[0036] That is, in the present application, the input buffers of all input ports may be divided into several sub-buffers corresponding to the output ports; or, here, only the input buffers of the input ports with a slightly lower priority may be divided into several sub-buffers corresponding to the output ports, while the input buffers of the input ports with a higher priority may not be divided, thereby reducing unnecessary waste of resources.

[0037] Specifically, the data in the input buffer of the input port with higher priority will be processed by the cross switch with priority due to the higher priority of the input port. Therefore, the probability of head blocking of the data in the input buffer of the input port with higher priority is relatively small. Therefore, there is no need to split the input buffer of the input port with higher priority. The input buffer of the input port with slightly lower priority can be split into several sub-buffers corresponding to the output ports. The data in the input buffer of the input port with slightly lower priority will be more likely to be blocked due to the lower priority of the input port. This can avoid waste of resources, improve resource utilization, and reduce transmission delay.

[0038] Optionally, in the case where head blocking occurs in the input buffer of an input port as mentioned above, the input buffer of the input port is divided into several sub-buffers corresponding to the output ports. Step 202 here may include: in the case where head blocking occurs in the input buffer of an input port, and the input port is an input port of the second priority, the input buffer of the input port is divided into several sub-buffers corresponding to the output port. Usually, the input port of the first priority has the highest priority and is generally not prone to head blocking. Even if head blocking occurs, the transmission delay caused by its higher priority is very small. Therefore, in the case where head blocking occurs in the input buffer of an input port, and the input port is an input port of the second priority, the input buffer of the input port can be divided into several sub-buffers corresponding to the output ports. The division of the input buffer of the input port is more targeted, which can improve resource utilization.

[0039] Optionally, the on-chip network adopts XY routing for routing. Specifically, the XY routing algorithm is mainly used in a two-dimensional mesh on-chip network. It represents all routing nodes in the on-chip network with a two-dimensional coordinate (X, Y). The data packet first moves along the X dimension (horizontal direction) until it reaches the same X coordinate position as the destination node; then, it moves along the Y dimension (vertical direction) until it reaches the destination node. XY routing avoids loop deadlock by prohibiting certain turns. Specifically, it only allows data packets moving east (or west) to turn north (or south), and does not allow data packets moving north (or south) to turn east (or west). This turn restriction ensures that the data packet will not fall into an infinite loop; at the same time, XY routing greatly simplifies the logical structure of the routing node, can reduce power consumption, and improve performance, XY routing greatly simplifies the logical structure of the routing node, can reduce power consumption, and improve performance, XY routing can also improve network latency and throughput.

[0040] Optional, see above Figure 1 and Figure 2 , the first input port includes the east input port; the second input port includes the west input port; the third input port includes the north input port; the fourth input port includes the south input port; the fifth input port includes the input port 0 connected to the device and the routing node; the sixth input port includes the input port 1 connected to the device and the routing node. The aforementioned output ports include the east output port, the west output port, the north output port, the south output port, the output port 0 connected to the device and the routing node, and the output port 1 connected to the device and the routing node. The aforementioned step 202 may include: dividing the input buffer of the north input port into a sub-buffer toward the south output port, a sub-buffer toward the output port 0, and a sub-buffer toward the output port 1; dividing the input buffer of the south input port into a sub-buffer toward the north output port, a sub-buffer toward the output port 0, and a sub-buffer toward the output port 1.

[0041] Specifically, the on-chip network adopts XY routing for routing, so the data of the north input port and the south input port will not be deflected to the east output port and the west output port, so the input buffer of the north input port is divided into three sub-buffers, namely, the sub-buffer to the south output port, the sub-buffer to the aforementioned output port 0, and the sub-buffer to the aforementioned output port 1; the input buffer of the south input port is divided into three sub-buffers, namely, the sub-buffer to the north output port, the sub-buffer to the output port 0, and the sub-buffer to the output port 1. Based on the characteristics of XY routing, the present application performs the above-mentioned division on the input buffer of the north input port and the input buffer of the south input port, which can avoid resource waste and further reduce transmission delay; at the same time, the above-mentioned division is performed on the input buffer of the north input port and the input buffer of the south input port, and the area loss and timing loss will not be significantly increased. That is to say, based on the characteristics of XY routing, the aforementioned division of the input buffer of the north input port and the input buffer of the south input port is at least an optimization result that integrates multiple factors such as resource utilization, transmission delay, area loss and timing loss, with high resource utilization, low transmission delay, and less area loss and timing loss.

[0042] At the same time, for the network on chip that uses the XY routing method for routing, the present application may not split the input buffer of the output port 0 connected to the device and the routing node, and the input buffer of the output port 1 connected to the device and the routing node. Specifically, in the network on chip that uses the XY routing method for routing, there are many output ports for data in the output port 0 connected to the device and the routing node, and the output port 1 connected to the device and the routing node (for example, it may be 4 or 5). If the input buffer of the output port 0 connected to the device and the routing node, and the input buffer of the output port 1 connected to the device and the routing node are split, the number of sub-buffers obtained by the splitting may be large, and the area loss and timing loss may be large. Therefore, it is possible to choose not to split the input buffer of the output port 0 connected to the device and the routing node, and the input buffer of the output port 1 connected to the device and the routing node, which can avoid bringing about a large area loss, and in the subsequent process of sending data in other sub-buffers that have not been blocked by the head, it may bring about a large timing loss.

[0043] Step 203: Store the data in the input buffer of the input port into the corresponding sub-buffer according to different output ports.

[0044] The step 203 may refer to the aforementioned step 102. The main difference between the aforementioned step 201 and step 202 is that the data in the input buffer of the second priority input port is stored in the corresponding sub-buffer according to different output ports.

[0045] Step 204: When head blocking occurs in the sub-buffer of one of the input ports, data in the idle sub-buffer of the output port corresponding to the current moment among the remaining sub-buffers of the input port is sent out.

[0046] Step 204 can refer to the aforementioned step 103. With respect to the aforementioned steps 201 and 202, the main difference here is that when head blocking occurs in the sub-buffer of the second-priority input port, the data in the idle sub-buffer of the output port corresponding to the current moment among the remaining sub-buffers of the second-priority input port will be sent out.

[0047] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0048] The present application is further explained below in conjunction with the examples and comparative examples. Figure 2 In all the drawings of this application, N refers to the data to be transmitted to the north output port, W refers to the data to be transmitted to the west output port, P0 refers to the data to be transmitted to the output port 0 connected to the device and the routing node, and P1 refers to the data to be transmitted to the output port 1 connected to the device and the routing node. The data here can refer to Flit (the smallest unit of routing transmission). Figure 2 and Figure 5 In the arbitration mode, the crossbar switches use a fixed priority arbitration method from high to low, which is the east input port, the west input port, the north input port, the south input port, the output port 0 connected to the device and the routing node, and the output port 1 connected to the device and the routing node to process the requests of each input port. Figure 2 and Figure 5 The corresponding on-chip networks are all routed using the XY routing method. Figure 2 and Figure 5 The working mode of the routing node shown is roughly as follows: when the input buffer of a certain input port receives a Flit, the XY routing algorithm is first used to perform routing calculations, and then an output channel authorization is applied to the cross switch based on the result of the routing calculation. After obtaining the channel authorization, the Flit is finally popped out of the input buffer and output from the corresponding output port after being deflected by the cross switch. Figure 2 and Figure 5In the example, the south input port and the east input port compete for the north output port, but because the east input port has a higher priority than the south input port, the south input port is blocked at the head of the network.

[0049] Example 1 Reference Figure 5 , we can first divide the input buffer of the south input port into three sub-buffers: the sub-buffer to the north output port, the sub-buffer to the aforementioned output port 0, and the sub-buffer to the aforementioned output port 1, and divide the input buffer of the north input port into three sub-buffers: the sub-buffer to the south output port, the sub-buffer to the aforementioned output port 0, and the sub-buffer to the aforementioned output port 1. Figure 5 N) in the south input port is stored in the sub-buffer of the north output port, and the input buffer of the south input port is sent to the Flit to be output at the aforementioned output port 0 (i.e. Figure 5 The south input port P0) is stored in the sub-buffer to the aforementioned output port 0, and the input buffer of the south input port is sent to the Flit to be outputted to the aforementioned output port 1 (i.e. Figure 5 The south input port P1) is stored in the sub-buffer of the output port 1. The input buffer of the north input port is sent to the south output port to be output Flit (i.e. Figure 5 The north input port S) is stored in the sub-buffer of the south output port, and the input buffer of the north input port is sent to the Flit to be output at the aforementioned output port 0 (i.e. Figure 5 The north input port P0) is stored in the sub-buffer of the aforementioned output port 0, and the input buffer of the north input port is sent to the Flit to be outputted from the aforementioned output port 1 (i.e. Figure 5 The north input port P1) is stored in the sub-buffer of the aforementioned output port 1. The reason for this division is that the east input port and the west input port have the highest priority, and the probability of head blocking is very small. At the same time, the on-chip network adopts XY routing, and the Flit of the north input port and the south input port will not be deflected to the east output port and the west output port, so as to divide the input buffer in a targeted manner to reduce resource waste. Figure 5 In the example, the input buffer of the south input port is head-blocked, device 0 is connected to the aforementioned output port 0, and device 1 is connected to the aforementioned output port 0. After the aforementioned splitting and restoring, the sub-buffer of the south input port to the north output port competes with the east input port to the north output port, that is, the sub-buffer of the south input port to the north output port is head-blocked.

[0050] Although the sub-buffer of the south input port to the north output port still exists, and competes with the east input port for the north output port, after the input buffer of the south input port is split and re-stored as mentioned above, the sub-buffer to the output port 0 and the sub-buffer to the output port 1 in the south input port can still be deflected normally. Figure 5 , the Flit to be output from the north output port of the east input port of routing node 0 ( Figure 5 The N in the east input port is sent, and routing node 1 receives the Flit, as well as the Flit ( Figure 5 The Flit is sent from the south input port P1 and received by device 1.

[0051] Example 2 Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 The steps from time 1 to time 5 in the embodiment are shown in sequence. Figures 6 to 10 Routing node 0 in Figure 2 The corresponding routing node in. Figure 6 At time 1, the input buffer of the south input port is blocked by the head, so the input buffer of the south input port is divided into three sub-buffers: the sub-buffer to the north output port, the sub-buffer to the aforementioned output port 0, and the sub-buffer to the aforementioned output port 1. The Flit to be output by the north output port (i.e. Figures 6 to 10 N) in the south input port is stored in the sub-buffer of the north output port, and the input buffer of the south input port is sent to the Flit to be output at the aforementioned output port 0 (i.e. Figures 6 to 10 The south input port P0) is stored in the sub-buffer to the aforementioned output port 0, and the input buffer of the south input port is sent to the Flit to be outputted to the aforementioned output port 1 (i.e. Figures 6 to 10The reason for this division is that the east input port and the west input port have the highest priority, and the probability of head blocking is very small. At the same time, the on-chip network adopts the XY routing method, and the Flits of the north input port and the south input port will basically not be deflected to the east output port and the west output port, so as to divide the input buffer in a targeted manner to reduce resource waste. Device 0 and device 1 here both refer to peripheral devices of the on-chip network, where device 0 is connected to the aforementioned output port 0, and device 1 is connected to the aforementioned output port 0. After the above division and re-storage, at time 1, the sub-buffer of the south input port to the north output port competes with the east input port to the north output port, that is, the sub-buffer of the south input port to the north output port is head blocked.

[0052] Reference Figure 7 and Figure 8 At time 2 and time 3, although the sub-buffer of the south input port to the north output port still exists, and competes with the east input port for the north output port, after the input buffer of the south input port is divided and re-stored as mentioned above, the sub-buffer to the output port 0 and the sub-buffer to the output port 1 in the south input port can still be deflected normally. Therefore, referring to Figure 7 , at time 2, the Flit to be output from the east input port of routing node 0 to the north output port ( Figures 6 to 10 The N in the east input port is sent, and routing node 1 receives the Flit, as well as the Flit ( Figures 6 to 10 The Flit is sent from the south input port P0 and received by device 0. Figure 8 At time 3, the Flit to be output from the east input port of routing node 0 to the north output port is sent, and routing node 1 receives the Flit, as well as the Flit to be output from the sub-buffer of the south input port of routing node 0 to the aforementioned output port 1 ( Figures 6 to 10 The Flit is sent from the P1 of the central and southern input port and received by device 0.

[0053] Reference Fig. 9 and Fig.10 At time 4 and time 5, the subbuffer of the south input port to the north output port has no head blocking problem, so, referring to Fig. 9 , the Flit to be output from the east input port of routing node 0 to the west output port ( Figures 6 to 10 The W of the middle input port is sent out, and routing node 2 receives the Flit. In addition, the Flit to be output from the sub-buffer of the north output port in the south input port of routing node 0 is sent out to the north output port, and routing node 1 receives the Flit. Fig.10 , the Flit to be output to the west output port in the east input port of routing node 0 is sent, and routing node 2 receives the Flit, and the Flit to be output to the north output port in the sub-buffer of the north output port in the south input port of routing node 0 is sent, and routing node 1 receives the Flit. The data in routing node 0 is output.

[0054] The main difference between Example 1 and Example 2 is that in Example 1, the input buffers of the south input port and the north input port of routing node 0 are segmented, while in Example 2, only the input buffer of the south input port of routing node 0 where head blocking occurs is segmented. At the same time, Example 2 explains the data transmission process in more detail.

[0055] Comparative Example The main difference between the comparative example and Examples 1 and 2 is that in the comparative example, the input buffer of the south input port is not divided. Since there is head blocking in the input buffer of the south input port, it is necessary to wait until the two Flits to be output by the north output port in the east input port are sent before the head blocking of the input buffer of the south input port can be released, and then the data in the input buffer of the south input port can be sent out. Therefore, the comparative example needs 7 moments to complete the output of the data in routing node 0.

[0056] Obviously, in the case where there is head blocking in the input buffer of the south input port in Example 1 and Example 2 and the comparative example, or in the same case of head blocking, Example 1 and Example 2 have almost no transmission delay, while the comparative example has transmission delay at at least two moments relative to Example 1 and Example 2. Example 1 and Example 2 of the present application significantly reduce the transmission delay, and Example 1 and Example 2 basically do not introduce excessive area loss and timing loss.

[0057] Reference Fig.11 , Fig.11 The structural block diagram of an embodiment of a data transmission device of the present invention is shown. The device is applied to an on-chip network, and the on-chip network includes: a routing node; the routing node includes: a cross switch, a plurality of input ports and a plurality of output ports, and the cross switch uses a fixed priority arbitration method to process the requests of each input port. Here, refer to the above-mentioned related records. In order to avoid repetition, it will not be repeated here. The device may specifically include the following modules: A splitting module 301 is used to split the input buffer of at least part of the input ports into a plurality of sub-buffers corresponding to the output ports; The storage module 302 is used to store the data in the input buffer of the input port into the corresponding sub-buffer according to different output ports; The sending module 303 is used to send out data in an idle sub-buffer of an output port corresponding to the current moment among the remaining sub-buffers of the input port when head blocking occurs in the sub-buffer of one of the input ports.

[0058] Optionally, the segmentation module 301 includes: The first splitting submodule is used to split the input buffer of the input port into a plurality of sub-buffers corresponding to the output ports when header blocking occurs in the input buffer of the input port; the output port of the data corresponding to the header blocking of the input buffer of the input port is the same as the output port corresponding to the sub-buffer of the input port where header blocking occurs.

[0059] Optionally, the device further comprises: A division module, used for dividing at least part of the plurality of input ports into input ports of a first priority and input ports of a second priority according to different priorities; the first priority is higher than the second priority; The segmentation module 301 includes: The second segmentation submodule is used to segment the input buffer of the input port of the second priority into a plurality of sub-buffers corresponding to the output ports.

[0060] Optionally, the division module includes: A first division submodule, used to divide the input port with the highest priority among the plurality of input ports into an input port with a first priority; The second division submodule is used to divide at least part of the remaining input ports of the plurality of input ports into input ports of a second priority.

[0061] Optionally, the plurality of input ports include: a first input port, a second input port, a third input port, a fourth input port, a fifth input port and a sixth input port; the cross switch processes requests of each of the input ports by using an arbitration method with fixed priorities of the first input port, the second input port, the third input port, the fourth input port, the fifth input port and the sixth input port from high to low; The first division submodule includes: A first dividing unit, configured to divide the first input port and the second input port into input ports of a first priority; The second division submodule includes: The second dividing unit is used to divide the third input port and the fourth input port into input ports of a second priority.

[0062] Optionally, the on-chip network adopts an XY routing method for routing; the first input port includes an east input port; the second input port includes a west input port; the third input port includes a north input port; the fourth input port includes a south input port; the fifth input port includes an input port 0 connected to the device and the routing node; the sixth input port includes an input port 1 connected to the device and the routing node; the output ports include an east output port, a west output port, a north output port, a south output port, an output port 0 connected to the device and the routing node, and an output port 1 connected to the device and the routing node; The second segmentation submodule includes: A first segmentation unit, configured to segment the input buffer of the north input port into a sub-buffer toward the south output port, a sub-buffer toward the output port 0, and a sub-buffer toward the output port 1; The second segmentation unit is used to segment the input buffer of the south input port into a sub-buffer toward the north output port, a sub-buffer toward the output port 0, and a sub-buffer toward the output port 1.

[0063] Optionally, the issuing module 303 includes: The sending submodule is used to send out the data in the idle sub-buffer of the output port corresponding to the current moment among the remaining sub-buffers of the input port in any of the three methods: polling, fixed priority and random.

[0064] It should be noted that the data transmission device can refer to the relevant aspects of the aforementioned data transmission method. Both have the same or similar beneficial effects. In order to avoid repetition, they will not be described here.

[0065] Fig.12 is a structural diagram of an electronic device provided by an embodiment of the present invention. Fig.12 The present invention also provides an electronic device, see Fig.12 , including: a processor 501, a memory 502, and a computer program 5021 stored in the memory and executable on the processor, wherein the processor implements the steps of each embodiment of the above-mentioned data transmission when executing the program.

[0066] The present invention also provides a readable storage medium. When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device can execute the steps of each embodiment of the above-mentioned data transmission method.

[0067] The present invention also provides a computer program product, comprising instructions, which, when executed by a processor in an electronic device, enable the electronic device to execute the steps of any one of the aforementioned data transmission method embodiments.

[0068] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0069] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0070] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data transmission terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data transmission terminal device generate instructions for implementing the process in the flowchart. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0071] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data transmission terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0072] These computer program instructions can also be loaded onto a computer or other programmable data transmission terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1The steps for the functions specified in one or more boxes.

[0073] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0074] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0075] The data transmission method and device, an electronic device and a storage medium provided by the present invention are introduced in detail above. The principle and implementation mode of the present invention are explained in detail using specific examples. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A data transmission method, characterized in that: Applied to a network on chip, the network on chip includes: a routing node; the routing node includes: a cross switch, a plurality of input ports and a plurality of output ports, the cross switch uses a fixed priority arbitration method to process requests of each input port; the method includes: Splitting the input buffers of at least some of the input ports into a plurality of sub-buffers corresponding to the output ports; The data in the input buffer of the input port is stored in the corresponding sub-buffer according to different output ports; When head blocking occurs in the sub-buffer of one of the input ports, data in the idle sub-buffer of the output port corresponding to the current moment among the remaining sub-buffers of the input port is sent out.

2. The data transmission method according to claim 1, characterized in that: The step of dividing the input buffer of at least part of the input ports into a plurality of sub-buffers corresponding to the output ports comprises: In the event that header blocking occurs in the input buffer of one of the input ports, the input buffer of the input port is divided into a plurality of sub-buffers corresponding to the output ports; the output port of the data corresponding to the header blocking occurring in the input buffer of the input port is the same as the output port corresponding to the sub-buffer of the input port where header blocking occurs.

3. The data transmission method according to claim 1 or 2, characterized in that: Before dividing the input buffers of at least some of the input ports into a plurality of sub-buffers corresponding to the output ports, the method further comprises: dividing at least some of the plurality of input ports into input ports of a first priority and input ports of a second priority according to different priorities; the first priority is higher than the second priority; The step of dividing the input buffer of at least part of the input ports into a plurality of sub-buffers corresponding to the output ports comprises: The input buffer of the input port of the second priority level is divided into a plurality of sub-buffers corresponding to the output ports.

4. The data transmission method according to claim 3, characterized in that: The step of dividing at least some of the plurality of input ports into input ports of a first priority and input ports of a second priority according to different priorities comprises: Classify the input port with the highest priority among the plurality of input ports as an input port of first priority; At least some of the remaining input ports of the plurality of input ports are divided into input ports of a second priority.

5. The data transmission method according to claim 4, characterized in that: The plurality of input ports include: a first input port, a second input port, a third input port, a fourth input port, a fifth input port and a sixth input port; the cross switch processes requests of the input ports by using an arbitration method with fixed priorities of the first input port, the second input port, the third input port, the fourth input port, the fifth input port and the sixth input port from high to low; The step of classifying the input port with the highest priority among the plurality of input ports as an input port with a first priority includes: Classify the first input port and the second input port as input ports of a first priority; The step of dividing at least some of the remaining input ports of the plurality of input ports as input ports of a second priority level comprises: The third input port and the fourth input port are classified as input ports of a second priority.

6. The data transmission method according to claim 5, characterized in that: The on-chip network adopts XY routing mode for routing; The first input port includes an east input port; The second input port includes: a west input port; the third input port includes: a north input port; the fourth input port includes: a south input port; the fifth input port includes: an input port 0 connected to the device and the routing node; the sixth input port includes: an input port 1 connected to the device and the routing node; the output port includes: an east output port, a west output port, a north output port, a south output port, an output port 0 connected to the device and the routing node, and an output port 1 connected to the device and the routing node; The step of dividing the input buffer of the input port of the second priority into a plurality of sub-buffers corresponding to the output ports comprises: Splitting the input buffer of the north input port into a sub-buffer toward the south output port, a sub-buffer toward the output port 0, and a sub-buffer toward the output port 1; The input buffer of the south input port is divided into a sub-buffer toward the north output port, a sub-buffer toward the output port 0, and a sub-buffer toward the output port 1.

7. The data transmission method according to claim 1 or 2, characterized in that: When the sub-buffer of one of the input ports is blocked by a head, sending data in the idle sub-buffer of the output port corresponding to the current moment among the remaining sub-buffers of the input port comprises: When head blocking occurs in the sub-buffer of one of the input ports, data in the idle sub-buffer of the output port corresponding to the current moment among the remaining sub-buffers of the input port are sent out in any one of the three methods: polling, fixed priority, and random.

8. A data transmission device, characterized in that: Applied to a network on chip, the network on chip includes: a routing node; the routing node includes: a cross switch, a plurality of input ports and a plurality of output ports, the cross switch uses a fixed priority arbitration method to process requests of each input port; the device includes: A splitting module, used for splitting the input buffers of at least some of the input ports into a plurality of sub-buffers corresponding to the output ports; A storage module, used for storing the data in the input buffer of the input port into the corresponding sub-buffer according to different output ports; The sending module is used to send out the data in the idle sub-buffer of the output port corresponding to the current moment among the remaining sub-buffers of the input port when the sub-buffer of one of the input ports is blocked by the head.

9. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor implements the data transmission method according to any one of claims 1 to 7 when executing the program.

10. A readable storage medium, characterized in that: When the instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the data transmission method according to any one of claims 1 to 7.

11. A computer program product, characterized in that The method comprises instructions, which, when executed by a processor in an electronic device, enable the electronic device to execute the data transmission method according to any one of claims 1 to 7.

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