A data transmission method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application provide a data transmission method and device, electronic equipment and storage medium, and relate to the technical field of data transmission. The method is applied to a network on a chip, and the network on a chip comprises a routing node. The routing node comprises a crossbar switch, a plurality of input ports and a plurality of output ports. The crossbar switch adopts a fixed priority arbitration mode to process requests of the input ports. The method comprises the following steps: dividing input buffers of at least part of the input ports into a plurality of sub-buffers corresponding to the output ports; storing data in the input buffers of the input ports into corresponding sub-buffers according to different output ports; and in the case of head blocking occurring in a sub-buffer of an input port, sending out data in a sub-buffer of the input port, which is idle at the current time, from the remaining sub-buffers of the input port. In the present application, head blocking does not affect the sending out of data in the remaining sub-buffers of the input port, and the delay is small.

Description

Technical Field

[0001] This invention relates to the field of data transmission technology, and in particular to a data transmission method, a data transmission device, an electronic device, and a storage medium. Background Technology

[0002] Network-on-Chip (NoC) is an interconnect architecture for System-on-Chip (SoC). Due to its advantages such as higher bandwidth, it has broad application prospects.

[0003] When the crossbar switches of routing nodes in an on-chip network use a fixed-priority arbitration method to handle requests from each input port, head blocking can easily occur.

[0004] However, while other output ports may be idle at this time, other data is still blocked in the input buffer where headblocking has occurred, causing the data transmission delay to increase further. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide a data transmission method that overcomes or at least partially solves the above problems, thereby reducing data transmission latency.

[0006] In a first aspect, the present invention provides a data transmission method applied to a network-on-a-chip (NIC), the NIC comprising: a routing node; the routing node comprising: a crossbar switch, a plurality of input ports, and a plurality of output ports, wherein the crossbar switch processes requests from each of the input ports using a fixed-priority arbitration method; the method comprising:

[0007] The input buffers of at least some of the input ports are divided into several sub-buffers corresponding to the output ports;

[0008] The data in the input buffer of the input port is stored in the corresponding sub-buffer according to the different output ports;

[0009] In the event of head blocking in a sub-buffer of an input port, the data in the currently available sub-buffer of the output port corresponding to the remaining sub-buffers of the input port will be sent out.

[0010] Secondly, the present invention provides a data transmission apparatus applied to a network-on-a-chip (NIC), the NIC comprising: a routing node; the routing node comprising: a crossbar switch, a plurality of input ports, and a plurality of output ports, the crossbar switch processing requests from each of the input ports using a fixed-priority arbitration method; the apparatus comprising:

[0011] The segmentation module is used to segment the input buffers of at least some of the input ports into several sub-buffers corresponding to the output ports;

[0012] The storage module is used to store the data in the input buffer of the input port into the corresponding sub-buffer according to the different output ports;

[0013] The sending module is used to send out the data in the currently free sub-buffer of the output port in the remaining sub-buffers of the input port when head blocking occurs in the sub-buffer of one of the input ports.

[0014] Thirdly, the present invention provides an electronic device, comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the above-described data transmission method.

[0015] Fourthly, the present invention provides a readable storage medium that, when the instructions in the storage medium are executed by the processor of an electronic device, enables the electronic device to perform the above-described data transmission method.

[0016] Fifthly, the present invention provides a computer program product including instructions that, when executed by a processor in an electronic device, cause the electronic device to perform any of the aforementioned data transmission methods.

[0017] This invention has at least the following advantages:

[0018] In this invention, when the cross-connect of the routing node in the on-chip network uses a fixed-priority arbitration method to handle requests from each input port, the input buffers of at least some of the input ports are divided into several sub-buffers corresponding to the output ports. Data in the input buffers of the input ports is stored in the corresponding sub-buffers according to the output ports. Therefore, if a head-blocking occurs in a sub-buffer of an input port, the head-blocking only blocks that sub-buffer of the input port and does not block the other sub-buffers of the input port. That is, the head-blocking basically does not affect the transmission of data in the other sub-buffers of the input port. Instead, the data in the currently available sub-buffer of the output port corresponding to the other sub-buffers of the input port is transmitted. In other words, the head-blocking basically does not increase the transmission latency of data in the other sub-buffers of the input port, thus reducing transmission latency. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 A schematic diagram of the structure of a routing node according to the present invention is shown;

[0021] Figure 2 A schematic diagram of a head blocker according to the present invention is shown;

[0022] Figure 3 A flowchart illustrating the steps of an embodiment of the data transmission method of the present invention is shown;

[0023] Figure 4 A flowchart illustrating the steps of another embodiment of the data transmission method of the present invention is shown;

[0024] Figure 5 A schematic diagram of a data transmission according to the present invention is shown;

[0025] Figures 6 to 10 A schematic diagram of a data transmission process according to the present invention is shown;

[0026] Figure 11 A structural block diagram of an embodiment of the data transmission device of the present invention is shown;

[0027] Figure 12 This is a structural diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0029] This application provides a data transmission method applied to an on-chip network. The on-chip network includes routing nodes (Routers), and the number of routing nodes in the on-chip network is not limited. Figure 1 This is a schematic diagram of the routing nodes. (Refer to...) Figure 1The routing node includes a crossbar, several input ports, and several output ports. Ports facing the crossbar indicate inputs, and ports facing away from the crossbar indicate outputs. The number of input and output ports in a routing node is not limited, nor is it specifically limited whether the number of input and output ports is equal. For example, Figure 1 In this configuration, a routing node includes: a crossbar switch, 6 input ports, and 6 output ports.

[0030] In this application, the crossbar switch of the routing node uses a fixed priority arbitration method to handle the requests of each input port. In other words, the crossbar switch of the routing node always uses a fixed priority arbitration method to handle the requests of each input port. Under this situation, head blocking is likely to occur. Figure 2 This illustrates a head blockage. Figure 2 , Figures 5 to 10 In this context, N refers to the data to be transmitted at the northbound output port, W refers to the data to be transmitted at the westbound output port, P0 refers to the data to be transmitted at output port 0 connecting the device and the routing node, and P1 refers to the data to be transmitted at output port 1 connecting the device and the routing node. Here, data can refer to Flit (the smallest unit of routing transmission). For example, Figure 2 In the routing node, the crossbar switches use a fixed-priority arbitration method to process requests from each input port, with the east input port having a higher priority than the south input port. Figure 2 In the scenario shown, both the input buffers of the east input port and the south input port contain N. Since the east input port has a higher priority than the south input port, the N in the east input port's input buffer will be prioritized and sent to the north output port via the crossbar switch. This causes the N in the south input port's input buffer to become congested, waiting for all N in the east input port's input buffer to be sent before it can be sent. However, P0 and P1 in the south input port's input buffer are after N, so they also need to wait for N in the south input port's input buffer to be sent before they can be sent. Even if output ports 0 and 1 connected to the routing node are currently idle, P0 and P1 in the south input port's input buffer cannot be sent. This is head-blocking, which leads to wasted resources on output ports 0 and 1 connected to the routing node and increased transmission delay. This application solves the head-blocking problem described above. The data transmission method of this application is explained in detail below.

[0031] Reference Figure 3 The data transmission method may specifically include the following steps.

[0032] Step 101: Divide the input buffer of at least some of the input ports into several sub-buffers corresponding to the output ports.

[0033] This can involve dividing the input buffers of all input ports of the routing node into sub-buffers corresponding to the output ports, or dividing only the input buffers of some input ports of the routing node into sub-buffers corresponding to the output ports. The number of sub-buffers obtained by dividing an input buffer can be equal to the total number of output ports of the routing node, or the number of sub-buffers obtained by dividing an input buffer can be less than the total number of output ports of the routing node.

[0034] For an input port's input buffer, after being divided into several sub-buffers corresponding to output ports, the data from each sub-buffer is output to a different port. It should be noted that "several" in this application refers to a natural number greater than or equal to 2. Specifically, the number of sub-buffers into which an input port's input buffer is divided can be determined based on the number of output ports and the routing method, etc.

[0035] Optionally, step 101 may include: if headblock occurs in the input buffer of an input port, dividing the input buffer of that input port into several sub-buffers corresponding to the output ports; the output port of the data corresponding to the headblock in the input buffer of that input port is the same as the output port corresponding to the headblocked sub-buffer of that input port. That is, the input buffer of an input port can be divided into several sub-buffers corresponding to the output ports only when headblock occurs, or the input buffer of an input port can be left undivided if headblock does not occur. This more targeted division of the input buffer of an input port can improve resource utilization. Regarding the aforementioned... Figure 2 The output port of the data corresponding to the head-blocking of the input buffer of the input port (i.e., the south input port) is the north output port, and the output port corresponding to the head-blocking of the sub-buffer of the input port (i.e., the south input port) is also the north output port; the two are the same.

[0036] Step 102: Store the data in the input buffer of the input port into the corresponding sub-buffer according to the different output ports.

[0037] The output port for this data is the same as the output port for this data here. The data in the input buffer of this input port is then stored in the corresponding sub-buffer according to the different output ports.

[0038] Step 103: In the event of head blocking in a sub-buffer of an input port, send out the data in the currently available sub-buffer of the output port corresponding to the remaining sub-buffers of the input port.

[0039] If head-blocking occurs in the sub-buffer of an input port, the remaining data in that sub-buffer cannot be sent. In this case, the data in the currently available sub-buffer of the output port corresponding to the remaining sub-buffers of the input port will be sent. In other words, head-blocking only affects the sending of data in that sub-buffer of the input port and has virtually no impact on the sending of data in the remaining sub-buffers of the input port. This reduces the transmission latency of the data in the remaining sub-buffers of the input port.

[0040] It should be noted that the data in the sub-buffer of the input port that is currently free at the corresponding time refers to the data in the sub-buffer of the input port that is not occupied or blocked at the current time.

[0041] Optionally, step 103 may include: in the event of head-blocking in a sub-buffer of an input port, data from the currently available sub-buffer of the remaining sub-buffers of the input port is sent out according to any one of three methods: polling, fixed priority, or random. Specifically, the number of remaining sub-buffers of the input port may be greater than or equal to 2. Polling here means that after each head-blocking event, the data from the remaining sub-buffers of the input port is first queried in a certain order, and then each sub-buffer of the remaining sub-buffers of the input port is queried one by one in a certain order or period. If the output port corresponding to the data in a certain sub-buffer of the remaining sub-buffer of the input port is currently available, then the data from that sub-buffer of the input port is sent out. Fixed priority here means that each sub-buffer in the input port has a fixed priority, and after each head-blocking event, the data from the remaining sub-buffers of the input port is sent out according to the priority of the data in that sub-buffer. The sub-buffers are queried sequentially from highest to lowest priority among the remaining sub-buffers of the input port. If the output port corresponding to data in a sub-buffer of the input port is currently idle, then the data in that sub-buffer of the input port is sent. The "randomness" here refers to the fact that after each head-blocking event, the remaining sub-buffers of the input port are queried one by one in a random manner. If the output port corresponding to data in a sub-buffer of the input port is currently idle, then the data in that sub-buffer of the input port is sent. These three methods are easy to implement and have a relatively small impact on transmission latency.

[0042] In summary, in this invention, when the cross-connection of the routing node in the on-chip network uses a fixed-priority arbitration method to handle requests from each input port, the input buffers of at least some of the input ports are divided into several sub-buffers corresponding to the output ports. Data in the input buffers of the input ports is stored in the corresponding sub-buffers according to the output ports. Therefore, if a head-blocking occurs in a sub-buffer of an input port, the head-blocking only blocks that sub-buffer of the input port and does not block the remaining sub-buffers of the input port. That is, the head-blocking basically does not affect the transmission of data in the remaining sub-buffers of the input port. Instead, the data in the currently available sub-buffer of the output port corresponding to the remaining sub-buffers of the input port is transmitted. In other words, the head-blocking basically does not increase the transmission delay of data in the remaining sub-buffers of the input port, thus reducing transmission delay.

[0043] Figure 4 A flowchart illustrating the steps of another embodiment of the data transmission method of the present invention is shown. (Refer to...) Figure 4 This data transmission method is also applied to an on-chip network, which includes a routing node. The routing node includes a crossbar switch, several input ports, and several output ports. The crossbar switch uses a fixed-priority arbitration method to handle requests from each input port, as described in the aforementioned relevant records. To avoid repetition, it will not be repeated here. Specifically, this method may include the following steps.

[0044] Step 201: Divide at least some of the input ports into first priority input ports and second priority input ports according to their different priorities; the first priority is higher than the second priority.

[0045] This could mean dividing all input ports in a routing node into first-priority input ports and second-priority input ports according to their priorities, or it could mean dividing a subset of the input ports in a routing node into first-priority input ports and second-priority input ports according to their priorities. Here, first priority is higher than second priority. That is, if at the same time, both the input buffer of a first-priority input port and the input buffer of a second-priority input port contain data to be sent to the same output port, the crossbar switch will prioritize sending the data from the input buffer of the first-priority input port to the same output port, and only then will it send the data from the input buffer of the second-priority input port to the same output port.

[0046] Optionally, step 201 may include steps 2011 and 2012. Step 2011: Assign the highest-priority input port among the plurality of input ports as a first-priority input port. Step 2012: Assign at least a portion of the remaining input ports among the plurality of input ports as second-priority input ports. The number of highest-priority input ports among the plurality of input ports is not limited here; it can be only one highest-priority input port among the plurality of input ports, or it can be multiple highest-priority input ports among the plurality of input ports, where these multiple input ports have different priorities, and this is not specifically limited. Step 2012 may be: Assigning all remaining input ports among the plurality of input ports as second-priority input ports, or assigning a portion of the remaining input ports among the plurality of input ports as second-priority input ports, and this is not specifically limited.

[0047] Specifically, the data in the input buffer of the highest priority input port is processed first by the crossbar switch because the highest priority input port has the highest priority. Therefore, the probability of head blocking in the input buffer of the highest priority input port is very small, so it is not necessary to divide the input buffer of the highest priority input port. Instead, the input buffers of the lower priority input ports can be divided into several sub-buffers corresponding to the output ports. The data in the input buffers of the lower priority input ports has a higher probability of head blocking because the input ports have lower priority. This can avoid resource waste, improve resource utilization, and reduce transmission latency.

[0048] Optional, refer to Figure 1 The input ports here may include: a first input port, a second input port, a third input port, a fourth input port, a fifth input port, and a sixth input port. The crossbar switch uses an arbitration method with a fixed priority, from high to low, for the first, second, third, fourth, fifth, and sixth input ports to process requests from each input port. Step 2011 may include: classifying the first and second input ports as first-priority input ports; step 2012 may include: classifying the third and fourth input ports as second-priority input ports. Here, among the first to sixth input ports, the first and second input ports are the two highest-priority input ports. Therefore, by classifying the two highest-priority input ports as first-priority input ports, the input buffers for these two highest-priority input ports do not need to be divided, avoiding resource waste. The third and fourth input ports here have lower priorities than the first and second input ports mentioned above. The third and fourth input ports, which have slightly lower priorities, are classified as second-priority input ports. Subsequently, the input buffers of the input ports with slightly lower priorities are divided into several sub-buffers corresponding to the output ports. Data in the input buffers of the input ports with slightly lower priorities have a higher probability of head blocking due to the lower priority of the input ports. This can avoid resource waste, improve resource utilization, and reduce transmission latency.

[0049] Step 202: Divide the input buffer of the second priority input port into several sub-buffers corresponding to the output port.

[0050] In other words, in this application, the input buffers of all input ports can be divided into several sub-buffers corresponding to the output ports; or, here, only the input buffers of input ports with slightly lower priority can be divided into several sub-buffers corresponding to the output ports, while the input buffers of input ports with higher priority are not divided, which can reduce unnecessary waste of resources.

[0051] Specifically, the data in the input buffer of a higher-priority input port is processed first by the crossbar switch because of its higher priority. Therefore, the probability of head blocking is lower for the data in the input buffer of a higher-priority input port, so it is not necessary to divide the input buffer of the higher-priority input port. Instead, the input buffer of a slightly lower-priority input port can be divided into several sub-buffers corresponding to the output ports. The data in the input buffer of a slightly lower-priority input port is more likely to be head blocked because of its lower priority. This avoids resource waste, improves resource utilization, and reduces transmission latency.

[0052] Optionally, in the case of head-blocking in the input buffer of an input port, where the input buffer of that input port is divided into several sub-buffers corresponding to the output port, step 202 here may include: when head-blocking occurs in the input buffer of an input port, and that input port is a second-priority input port, dividing the input buffer of that input port into several sub-buffers corresponding to the output port. Generally, first-priority input ports have the highest priority and are less prone to head-blocking. Even if head-blocking occurs, the transmission delay caused by their high priority is very small. Therefore, when head-blocking occurs in the input buffer of an input port, and that input port is a second-priority input port, dividing the input buffer of that input port into several sub-buffers corresponding to the output port makes the division of the input buffer of the input port more targeted and can improve resource utilization.

[0053] Optionally, the on-chip network uses XY routing. Specifically, the XY routing algorithm is mainly used in two-dimensional mesh on-chip networks. It represents all routing nodes in the on-chip network with a two-dimensional coordinate (X, Y). Data packets first move along the X dimension (horizontal direction) until they reach the same X coordinate position as the destination node; then, they move along the Y dimension (vertical direction) until they reach the destination node. XY routing avoids loop deadlock by prohibiting certain turns. Specifically, it only allows data packets moving east (or west) to turn north (or south), but does not allow data packets moving north (or south) to turn east (or west). This turn restriction ensures that data packets do not get stuck in an infinite loop. At the same time, XY routing greatly simplifies the logical structure of routing nodes, reduces power consumption, and improves performance. XY routing can also improve network latency and throughput.

[0054] Optionally, refer to the above. Figure 1 and Figure 2 The system comprises: a first input port, including an east input port; a second input port, including a west input port; a third input port, including a north input port; a fourth input port, including a south input port; a fifth input port, including input port 0 connected to the device and the routing node; and a sixth input port, including input port 1 connected to the device and the routing node. The aforementioned output ports include: an east output port, a west output port, a north output port, a south output port, output port 0 connected to the device and the routing node, and output port 1 connected to the device and the routing node. Step 202 may include: dividing the input buffer of the north input port into a sub-buffer leading to the south output port, a sub-buffer leading to output port 0, and a sub-buffer leading to output port 1; and dividing the input buffer of the south input port into a sub-buffer leading to the north output port, a sub-buffer leading to output port 0, and a sub-buffer leading to output port 1.

[0055] Specifically, the on-chip network uses XY routing. Therefore, data from the north and south input ports will not be deflected to the east and west output ports. Thus, the input buffer of the north input port is divided into three sub-buffers: one for the south output port, one for the aforementioned output port 0, and one for the aforementioned output port 1. Similarly, the input buffer of the south input port is divided into three sub-buffers: one for the north output port, one for the output port 0, and one for the output port 1. Based on the characteristics of XY routing, this application performs the aforementioned division of the input buffers of the north and south input ports, which avoids resource waste and further reduces transmission latency. Furthermore, this division of the input buffers of the north and south input ports does not significantly increase area loss or timing loss. In other words, based on the characteristics of XY routing, the aforementioned division of the input buffer of the north input port and the input buffer of the south input port is at least an optimization result that takes into account multiple factors such as resource utilization, transmission delay, area loss and timing loss. It has high resource utilization, low transmission delay, and less area loss and timing loss.

[0056] Meanwhile, for this on-chip network using XY routing, this application allows for the omission of segmenting the input buffers of output port 0 and output port 1, which are connected to the device and the routing node. Specifically, in this on-chip network using XY routing, there are multiple data output ports (e.g., 4 or 5) at output ports 0 and 1. Segmenting the input buffers of output ports 0 and 1 would result in a large number of sub-buffers, potentially leading to significant area and timing overhead. Therefore, choosing not to segment the input buffers of output ports 0 and 1 avoids substantial area overhead and prevents significant timing overhead during subsequent transmission of data from other sub-buffers that have not experienced head-blocking.

[0057] Step 203: Store the data in the input buffer of the input port into the corresponding sub-buffer according to the different output ports.

[0058] Step 203 can refer to the aforementioned step 102. The main difference between steps 201 and 202 is that the data in the input buffer of the second priority input port is stored in the corresponding sub-buffer according to the different output ports.

[0059] Step 204: In the event of head blocking in a sub-buffer of one of the input ports, the data in the currently available sub-buffer of the output port corresponding to the remaining sub-buffers of the input port is sent out.

[0060] Step 204 can refer to the aforementioned step 103. The main difference between steps 201 and 202 is that, in the case of head blocking in the sub-buffer of the second priority input port, the data in the currently available sub-buffer of the corresponding output port in the remaining sub-buffers of the second priority input port will be sent out.

[0061] It should be noted that, for the sake of simplicity, the method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of the present invention are not limited to the described order of actions, because according to the embodiments of the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to the embodiments of the present invention.

[0062] The present application will be further explained below with reference to embodiments and comparative examples. Embodiment 2 and the comparative examples are both... Figure 2 The head blocking is illustrated in the figure. In all the figures of this application, N refers to the data to be transmitted at the northbound output port, W refers to the data to be transmitted at the westbound output port, P0 refers to the data to be transmitted at output port 0 connected to the device and the routing node, and P1 refers to the data to be transmitted at output port 1 connected to the device and the routing node. The data here can refer to Flit (the smallest unit of routing transmission). Figure 2 and Figure 5 In this system, all cross switches use a fixed priority arbitration method to process requests from each input port, in descending order of priority: East input port, West input port, North input port, South input port, Output port 0 connected to the device and routing node, and Output port 1 connected to the device and routing node. Figure 2 and Figure 5 The corresponding on-chip networks all use XY routing for routing. Figure 2 and Figure 5 The routing node shown works roughly as follows: when a Flit is received in the input buffer of an input port, the XY routing algorithm is first used to calculate the route. Then, based on the result of the route calculation, the output channel authorization is requested from the crossbar switch. After obtaining the channel authorization, the Flit is finally popped from the input buffer, deflected by the crossbar switch, and output from the corresponding output port. Figure 2 and Figure 5In the middle, the south input port and the east input port compete for the north output port. However, because the east input port has a higher priority than the south input port, the south input port is blocked.

[0063] Example 1

[0064] Reference Figure 5 First, the input buffer of the south input port can be divided into three sub-buffers: a sub-buffer to the north output port, a sub-buffer to the aforementioned output port 0, and a sub-buffer to the aforementioned output port 1. Similarly, the input buffer of the north input port can be divided into three sub-buffers: a sub-buffer to the south output port, a sub-buffer to the aforementioned output port 0, and a sub-buffer to the aforementioned output port 1. Then, the Flit (i.e., the output data to be output from the south input port's input buffer to the north output port) can be... Figure 5 The input buffer N in the south input port is stored in the sub-buffer of the north output port. The Flit (i.e., the input buffer of the south input port) to be output to the aforementioned output port 0 is then stored in the sub-buffer of the north output port. Figure 5 The input buffer of the south input port (P0) is stored in the sub-buffer of the aforementioned output port 0. The input buffer of the south input port is used to store the Flit (i.e., the output to be sent to the aforementioned output port 1) to be sent to the aforementioned output port 1. Figure 5 The P1 in the south input port is stored in the sub-buffer of the aforementioned output port 1. The Flit (i.e., the input buffer of the north input port) to be output to the south output port is stored in the sub-buffer of the north input port. Figure 5 The input buffer (S) at the north input port is stored in the sub-buffer of the south output port. The input buffer at the north input port stores the Flit (i.e., Flit to be output to the aforementioned output port 0) from the aforementioned output port 0. Figure 5 The input buffer of the north input port (P0) is stored in the sub-buffer of the aforementioned output port 0. The input buffer of the north input port is used to store the Flit (i.e., the Flit to be output to the aforementioned output port 1) in the aforementioned output port 1. Figure 5 P1 in the north input port is stored in the sub-buffer of the aforementioned output port 1. The reason for this division is that the east and west input ports have the highest priority and the probability of head blocking is very small. At the same time, the on-chip network uses XY routing, so the Flit of the north and south input ports will not be deflected to the east and west output ports, so the input buffer is divided in a targeted manner to reduce resource waste. Figure 5 In the process, the input buffer of the south input port experiences head blocking. Device 0 is connected to the aforementioned output port 0, and device 1 is also connected to the aforementioned output port 0. After the aforementioned segmentation and re-storage, the sub-buffer of the northward output port of the south input port is in contention with the northward output port of the east input port, meaning that the sub-buffer of the northward output port of the south input port experiences head blocking.

[0065] Although the sub-buffer of the south input port's northward output port still exists, competing with the east input port's northward output port, after the aforementioned segmentation and re-storage of the south input port's input buffer, the sub-buffers of the south input port leading to the aforementioned output port 0 and the sub-buffers of the south input port leading to the aforementioned output port 1 can still deflect normally. Therefore, referring to... Figure 5 The Flit to be output from the northward output port of the east input port of routing node 0. Figure 5 The Flit is sent from the N in the east input port, and the Flit to be output to the aforementioned output port 1 is received by routing node 1, as well as the Flit to be output to the aforementioned output port 1 from the sub-buffer in the south input port of routing node 0. Figure 5 The Flit is sent from P1 in the south input port and received by device 1.

[0066] Example 2

[0067] Figure 6 , Figure 7 , Figure 8 , Figure 9 and Figure 10 The steps from time 1 to time 5 in the embodiment are shown in sequence. Figures 6 to 10 In the routing node 0, and Figure 2 The corresponding routing node. See reference. Figure 6 At time 1, if head blocking occurs in the input buffer of the south input port, the input buffer of the south input port is divided into three sub-buffers: a sub-buffer to the north output port, a sub-buffer to the aforementioned output port 0, and a sub-buffer to the aforementioned output port 1. The Flit (i.e., the output to be sent to the north output port) in the input buffer of the south input port is then... Figures 6 to 10 The input buffer N in the south input port is stored in the sub-buffer of the north output port. The Flit (i.e., the input buffer of the south input port) to be output to the aforementioned output port 0 is then stored in the sub-buffer of the north output port. Figures 6 to 10 The input buffer of the south input port (P0) is stored in the sub-buffer of the aforementioned output port 0. The input buffer of the south input port is used to store the Flit (i.e., the output to be sent to the aforementioned output port 1) to be sent to the aforementioned output port 1. Figures 6 to 10P1 in the south input port is stored in the sub-buffer of the aforementioned output port 1. This partitioning is because the east and west input ports have the highest priority, making head-blocking unlikely. Furthermore, the on-chip network uses XY routing, so the Flits from the north and south input ports are unlikely to deviate to the east and west output ports. This targeted partitioning of the input buffer reduces resource waste. Device 0 and Device 1 here refer to peripheral devices of the on-chip network; Device 0 is connected to the aforementioned output port 0, and Device 1 is also connected to the aforementioned output port 0. After the partitioning and re-storage, at time 1, the sub-buffer of the south input port's northward output port is subject to contention with the east input port's northward output port, meaning head-blocking occurs in the sub-buffer of the south input port's northward output port.

[0068] Reference Figure 7 and Figure 8 At times 2 and 3, although the sub-buffer of the south input port's northward output port still exists and competes with the east input port's northward output port, after the aforementioned segmentation and re-storage of the south input port's input buffer, the sub-buffers of the south input port leading to the aforementioned output port 0 and the sub-buffers of the south input port leading to the aforementioned output port 1 can still deflect normally. Therefore, referring to... Figure 7 At time 2, the Flit to be output from the east input port of routing node 0 to the north output port ( Figures 6 to 10 The Flit is sent from the N in the east input port, and received by routing node 1, as well as the Flit to be output to the aforementioned output port 0 in the sub-buffer of the south input port of routing node 0. Figures 6 to 10 The Flit is sent from P0 in the south input port and received by device 0. (See reference...) Figure 8 At time 3, the Flit to be output from the east input port of routing node 0 to the north output port is sent, and routing node 1 receives the Flit, as well as the Flit to be output from the sub-buffer of the south input port of routing node 0 to the aforementioned output port 1. Figures 6 to 10 The Flit is sent from P1 at the South Central Input Port and received by device 0.

[0069] Reference Figure 9 and Figure 10 At times 4 and 5, the sub-buffer of the south input port to the north output port does not have a head-blocking problem; therefore, referring to... Figure 9 The Flit to be output from the east input port to the west output port of routing node 0. Figures 6 to 10 The Flit is sent from the Middle East input port (W), received by routing node 2, and the Flit to be output from the northward output port in the sub-buffer of the south input port of routing node 0 is sent, received by routing node 1. (See reference...) Figure 10 The Flit to be output from the east input port to the west output port of routing node 0 is sent out, and routing node 2 receives the Flit. Similarly, the Flit to be output from the sub-buffer of the south input port to the north output port of routing node 0 is sent out, and routing node 1 receives the Flit. The data output from routing node 0 is now complete.

[0070] The main difference between Example 1 and Example 2 is that in Example 1, the input buffers of both the south and north input ports of routing node 0 are divided, while in Example 2, only the input buffer of the south input port of routing node 0, where head blocking occurs, is divided. Additionally, Example 2 provides a more detailed explanation of the data transmission process.

[0071] Comparative Example

[0072] The main difference between the comparative example and Examples 1 and 2 is that the input buffer of the south input port is not segmented in the comparative example. Since the input buffer of the south input port is blocked, the head blockage of the input buffer of the south input port can only be released after the two Flits to be output to the north output ports in the east input port have been sent. Only then can the data in the input buffer of the south input port be sent. Therefore, the comparative example needs 7 time steps to finish outputting the data in the routing node 0.

[0073] Clearly, in the case of head blocking in the input buffer of the south input port of Embodiments 1 and 2 and the comparative example, or in the case of the same head blocking, Embodiments 1 and 2 have almost no transmission delay, while the comparative example has at least two moments of transmission delay compared to Embodiments 1 and 2. Embodiments 1 and 2 of this application significantly reduce transmission delay, and Embodiments 1 and 2 basically do not introduce excessive area loss and timing loss.

[0074] Reference Figure 11 , Figure 11 A structural block diagram of an embodiment of the data transmission device of the present invention is shown. This device is applied to a network-on-a-chip (NAT), which includes a routing node. The routing node includes a crossbar switch, several input ports, and several output ports. The crossbar switch processes requests from each input port using a fixed-priority arbitration method, as described above. To avoid repetition, further details are omitted here. Specifically, the device may include the following modules:

[0075] The segmentation module 301 is used to segment the input buffer of at least some of the input ports into a plurality of sub-buffers corresponding to the output ports;

[0076] Storage module 302 is used to store the data in the input buffer of the input port into the corresponding sub-buffer according to the different output ports;

[0077] The transmitting module 303 is used to transmit the data in the currently free sub-buffer of the output port in the remaining sub-buffers of the input port when head blocking occurs in the sub-buffer of one of the input ports.

[0078] Optionally, the segmentation module 301 includes:

[0079] The first segmentation submodule is used to divide the input buffer of an input port into several sub-buffers corresponding to the output ports when head blocking occurs in the input buffer of an input port; the output port of the data corresponding to the head blocking of the input buffer of the input port is the same as the output port corresponding to the sub-buffer of the input port that is head-blocked.

[0080] Optionally, the device further includes:

[0081] The partitioning module is used to partition at least a portion of the input ports among the plurality of input ports into first priority input ports and second priority input ports according to different priorities; the first priority is higher than the second priority.

[0082] The segmentation module 301 includes:

[0083] The second segmentation submodule is used to segment the input buffer of the input port of the second priority into several sub-buffers corresponding to the output port.

[0084] Optionally, the partitioning module includes:

[0085] The first partitioning submodule is used to partition the input port with the highest priority among the plurality of input ports into the first priority input port;

[0086] The second partitioning submodule is used to partition at least a portion of the remaining input ports of the plurality of input ports into input ports of second priority.

[0087] Optionally, the plurality of input ports include: a first input port, a second input port, a third input port, a fourth input port, a fifth input port, and a sixth input port; the cross switch uses an arbitration method with a fixed priority from high to low, namely the first input port, the second input port, the third input port, the fourth input port, the fifth input port, and the sixth input port, to process the requests of each of the input ports;

[0088] The first partitioning submodule includes:

[0089] The first partitioning unit is used to partition the first input port and the second input port into input ports with a first priority.

[0090] The second partitioning submodule includes:

[0091] The second partitioning unit is used to partition the third input port and the fourth input port into second priority input ports.

[0092] Optionally, the on-chip network uses an XY routing method for routing; the first input port includes an east input port; the second input port includes a west input port; the third input port includes a north input port; the fourth input port includes a south input port; the fifth input port includes input port 0, which connects the device to the routing node; the sixth input port includes input port 1, which connects the device to the routing node; the output ports include an east output port, a west output port, a north output port, a south output port, output port 0, which connects the device to the routing node, and output port 1, which connects the device to the routing node.

[0093] The second segmentation submodule includes:

[0094] The first segmentation unit is used to segment the input buffer of the north input port into a sub-buffer to the south output port, a sub-buffer to the output port 0, and a sub-buffer to the output port 1.

[0095] The second segmentation unit is used to segment the input buffer of the south input port into a sub-buffer leading to the north output port, a sub-buffer leading to the output port 0, and a sub-buffer leading to the output port 1.

[0096] Optionally, the transmitting module 303 includes:

[0097] The output submodule is used to send out the data in the currently free sub-buffer of the output port in the other sub-buffers of the input port in the case of head blocking in the sub-buffer of the input port, according to any one of three methods: polling, fixed priority, or random.

[0098] It should be noted that the data transmission device can refer to the relevant aspects of the aforementioned data transmission method, as both have the same or similar beneficial effects. To avoid repetition, they will not be described again here.

[0099] Figure 12 This is a structural diagram of an electronic device provided in an embodiment of the present invention. (Refer to...) Figure 12The present invention also provides an electronic device, see [link to relevant documentation]. Figure 12 It includes: a processor 501, a memory 502, and a computer program 5021 stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the above-described data transmission embodiments.

[0100] The present invention also provides a readable storage medium, wherein when the instructions in the storage medium are executed by the processor of an electronic device, the electronic device is able to perform the steps of the embodiments of the above-described data transmission method.

[0101] The present invention also provides a computer program product including instructions that, when executed by a processor in an electronic device, cause the electronic device to perform the steps of any of the foregoing embodiments of the data transmission method.

[0102] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0103] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0104] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data transfer terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data transfer terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0105] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data transmission terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0106] These computer program instructions can also be loaded onto a computer or other programmable data transmission terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0107] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0108] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0109] The present invention has provided a detailed description of a data transmission method and apparatus, an electronic device, and a storage medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A data transmission method, characterized in that, The method is applied to an on-chip network, wherein the on-chip network includes: a routing node; the routing node includes: a crossbar switch, several input ports, and several output ports, wherein the crossbar switch processes requests from each of the input ports using a fixed-priority arbitration method; the method includes: The input buffers of at least some of the input ports are divided into several sub-buffers corresponding to the output ports; The data in the input buffer of the input port is stored in the corresponding sub-buffer according to the different output ports; In the event of head blocking in a sub-buffer of an input port, the data in the currently available sub-buffer of the output port corresponding to the remaining sub-buffers of the input port will be sent out. The on-chip network uses an XY routing method for routing. The input ports include: an east input port, a west input port, a north input port, a south input port, input port 0 connecting the device to the routing node, and input port 1 connecting the device to the routing node. The east and west input ports are first-priority input ports, and the north and south input ports are second-priority input ports, with the first priority being higher than the second priority. The output ports include: an east output port, a west output port, a north output port, a south output port, output port 0 connecting the device to the routing node, and output port 1 connecting the device to the routing node. The crossbar switch uses an arbitration method with a fixed priority from high to low: east input port, west input port, north input port, south input port, input port 0 connecting the device to the routing node, and input port 1 connecting the device to the routing node, to process requests from each input port. The step of dividing the input buffer of at least a portion of the input ports into a plurality of sub-buffers corresponding to the output ports includes: The input buffer of the north input port is divided into a sub-buffer to the south output port, a sub-buffer to the output port 0, and a sub-buffer to the output port 1; The input buffer of the south input port is divided into a sub-buffer to the north output port, a sub-buffer to the output port 0, and a sub-buffer to the output port 1; The input buffers of the east input port and the west input port are not divided.

2. The data transmission method according to claim 1, characterized in that, The step of dividing the input buffer of at least a portion of the input ports into a plurality of sub-buffers corresponding to the output ports includes: In the event of headblocking in the input buffer of one of the input ports, the input buffer of the input port is divided into several sub-buffers corresponding to the output ports; the output port of the data corresponding to the headblocking in the input buffer of the input port is the same as the output port corresponding to the sub-buffer of the input port that is headblocked.

3. The data transmission method according to claim 1 or 2, characterized in that, Before dividing the input buffer of at least a portion of the input ports into a plurality of sub-buffers corresponding to the output ports, the method further includes: At least some of the input ports are divided into first priority input ports and second priority input ports according to their priority. The step of dividing the input buffer of at least a portion of the input ports into a plurality of sub-buffers corresponding to the output ports includes: The input buffer of the second priority input port is divided into several sub-buffers corresponding to the output ports.

4. The data transmission method according to claim 3, characterized in that, The step of dividing at least a portion of the input ports among the plurality of input ports into first-priority input ports and second-priority input ports according to different priorities includes: The input port with the highest priority among the input ports is designated as the first priority input port; At least a portion of the remaining input ports of the plurality of input ports are classified as input ports of second priority.

5. The data transmission method according to claim 1 or 2, characterized in that, In the event of head-blocking in a sub-buffer of one of the input ports, the data in the currently available sub-buffer of the corresponding output port in the remaining sub-buffers of the input port is sent out, including: In the event of head blocking in a sub-buffer of an input port, data from the currently available sub-buffer of the output port in the remaining sub-buffers of the input port will be sent out according to one of three methods: polling, fixed priority, or random.

6. A data transmission device, characterized in that, The device is applied to an on-chip network, the on-chip network including: a routing node; the routing node including: a crossbar switch, several input ports and several output ports, the crossbar switch using a fixed-priority arbitration method to process requests from each of the input ports; the device includes: The partitioning module is used to divide at least a portion of the input ports among the plurality of input ports into first-priority input ports and second-priority input ports according to different priorities; the first priority is higher than the second priority; the first-priority input ports include: east input ports and west input ports; the second-priority input ports include: north input ports and south input ports; The segmentation module is used to segment the input buffers of at least some of the input ports into several sub-buffers corresponding to the output ports; The storage module is used to store the data in the input buffer of the input port into the corresponding sub-buffer according to the different output ports; The sending module is used to send out the data in the currently free sub-buffer of the output port in the remaining sub-buffers of the input port when head blocking occurs in the sub-buffer of the input port. The on-chip network uses an XY routing method for routing. The input ports include: an east input port, a west input port, a north input port, a south input port, input port 0 connecting the device to the routing node, and input port 1 connecting the device to the routing node. The east and west input ports are first-priority input ports, and the north and south input ports are second-priority input ports, with the first priority being higher than the second priority. The output ports include: an east output port, a west output port, a north output port, a south output port, output port 0 connecting the device to the routing node, and output port 1 connecting the device to the routing node. The crossbar switch uses an arbitration method with a fixed priority from high to low: east input port, west input port, north input port, south input port, input port 0 connecting the device to the routing node, and input port 1 connecting the device to the routing node, to process requests from each input port. The segmentation module is specifically used to: divide the input buffer of the north input port into a sub-buffer to the south output port, a sub-buffer to the output port 0, and a sub-buffer to the output port 1; The input buffer of the south input port is divided into a sub-buffer to the north output port, a sub-buffer to the output port 0, and a sub-buffer to the output port 1; The input buffers of the east and west input ports are not divided.

7. An electronic device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and executable on the processor, characterized in that the processor, when executing the program, implements the data transmission method as described in any one of claims 1 to 5.

8. A readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the data transmission method according to any one of claims 1 to 5.

9. A computer program product, characterized in that, The instruction includes instructions that, when executed by a processor in an electronic device, cause the electronic device to perform the data transmission method according to any one of claims 1 to 5.

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