Method, device and equipment for converting STIL file into test board file and storage medium

Abstract

The invention relates to a method, device and equipment for converting an STIL file into a test board file and a storage medium, the method and device are applied to the field of chip testing, and the method comprises the steps that the STIL file is acquired and analyzed, and the STIL file comprises a test protocol configuration file and a test vector; a pattern keyword in the STIL file is searched for, and whether the STIL file is valid or not is judged according to the pattern keyword; if the STIL file is valid, searching a test vector according to a fixed format of the test vector, converting the searched test vector into a plurality of test signals, and outputting the test signals; outputting a test board configuration file according to the conversion process of the plurality of test signals; and generating and outputting a test board file in a Verilog format according to the test protocol configuration file and the conversion process of the plurality of test signals. The method has the technical effects that the conversion time is saved, and the conversion efficiency is improved.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to a method, device, equipment and storage medium for converting a STIL file to a test bench file. Background Art

[0002] STIL file refers to Standard Test Interface Language, which is a language used to describe the interface between ATE (automatic test equipment) and ATPG (automatic test vector generation tool). STIL files are mainly used to define test vectors, which are used by ATE to test the functionality and structure of digital circuits. STIL files are file formats for ATE test machines. Before the chip is officially tested on the ATE machine, the correctness of the test vectors needs to be verified first, usually using the VCS (Verification Compiler System) verification tool; however, the VCS verification tool only supports test vectors in Verilog format, so the STIL file needs to be converted into a test bench file in Verilog format for simulation verification by the VCS verification tool.

[0003] The existing STIL file to Verilog test bench file conversion is generally performed through ATPG conversion and output. The ATPG tool converts the STIL file into a Verilog test bench file while generating the STIL file, and outputs the STIL file and the Verilog test bench file together. However, the method of converting the Verilog test bench file while generating the STIL file consumes a lot of time, which may affect the efficiency of chip testing. Summary of the invention

[0004] In order to help solve the problem that generating STIL files through ATPG tools and converting Verilog test bench files at the same time consumes a lot of time, thus affecting the efficiency of chip testing, the present application provides a method, device, equipment and storage medium for converting STIL files to test bench files.

[0005] In a first aspect, the present application provides a method for converting a STIL file to a test bench file, which adopts the following technical solution: the method comprises: Obtain and parse a STIL file, wherein the STIL file includes a test protocol configuration file and a test vector; Searching for a pattern keyword in the STIL file, and determining whether the STIL file is valid according to the pattern keyword; If the STIL file is valid, searching for a test vector according to a fixed format of the test vector, converting the found test vector to generate a number of test signals and outputting the signals; Outputting a test bench configuration file according to the process of converting the test signals; A test bench file in Verilog format is generated and output according to the test protocol configuration file and the conversion process of several test signals.

[0006] In a specific implementation scheme, before searching for a test vector according to a fixed format of the test vector and converting the found test vector to generate a plurality of test signals and outputting the signals, the method further includes: A test preparation vector is generated according to the test protocol configuration file, wherein the test preparation vector includes a plurality of test preparation signals.

[0007] In a specific implementation scheme, the test preparation vector is generated according to the test protocol configuration file, and the test preparation vector contains several test preparation signals including: assigning a value to an input portion of the test preparation signal according to a value of a test preparation process in the test protocol configuration file; According to the test protocol configuration file, the fixed signal value in the test preparation signal is fixedly set to 0 or 1; Setting the unassigned values, signal input port values ​​and signal output port values ​​in the test preparation signal to X; A plurality of assigned test-ready signals are set as the test-ready vector.

[0008] In a specific possible implementation scheme, the found test vector includes a dummy input value, a dummy output value, a main input value and a main output value; The step of searching for a test vector according to a fixed format of the test vector, converting the found test vector to generate a plurality of test signals and outputting the signals comprises: Process and generate a plurality of shift signals according to the pseudo input value and the pseudo output value; Determining the type of the STIL file capture process according to the test protocol configuration file; Generate and output a plurality of capture signals according to the type of the STIL file capture process, the main input value and the main output value; A plurality of the shift signals and a plurality of the capture signals are set as the test signals.

[0009] In a specific implementation manner, the processing and generating of a plurality of shift signals according to the pseudo input value and the pseudo output value comprises: Inputting the pseudo input values ​​into the scan chain in sequence according to the beats, and outputting the corresponding pseudo output values ​​in sequence according to the beats through the scan chain; Compare the dummy output value output by the scan chain with the dummy output value in the test vector in sequence, and output a comparison result; Setting the pseudo input value, the pseudo output value, the comparison result and a preset control signal as the shift signal; All the dummy input values ​​and the dummy output values ​​are looped, and a plurality of the shift signals are generated.

[0010] In a specific possible implementation scheme, the types of the STIL file capture process include: multi-clock capture, reset capture and on-chip clock capture; The generating and outputting a plurality of capture signals according to the type of the STIL file capture process, the main input value and the main output value comprises: If the STIL file capture process type is multi-clock capture, the enable signal is fixedly set to 0, the reset signal is fixedly set to 1, the test mode is fixedly set to 1, and all the main input values, all the main output values ​​and the fixed set values ​​are assigned to the capture signal according to the preset signal format; If the STIL file capture process type is reset capture, the enable signal is fixedly set to 1, the reset signal is fixedly set to 0, the test mode is fixedly set to 1, and all the main input values, all the main output values ​​and the fixed set values ​​are assigned to the capture signal according to the preset signal format; If the STIL file capture process type is on-chip clock capture, the enable signal is fixed to 0, the reset signal is fixed to 1, the test mode is fixed to 1, and according to the preset signal format, all the main input values, all the main output values ​​and the fixed set values ​​are assigned to the capture signal.

[0011] In a specific implementation scheme, the test bench file in Verilog format is generated and output according to the test protocol configuration file and the conversion process of the plurality of test signals, including: According to the test protocol configuration file, converting the main output port name for executing the test vector conversion into a hexadecimal character representation and generating a main output port name file; The test bench file in the Verilog format is generated and output according to the test protocol configuration file, the file name and file path of the main output port name file and the conversion process of several test signals.

[0012] In a second aspect, the present application provides a device for converting a STIL file to a test bench file, which adopts the following technical solution: the device comprises: The original file acquisition module is used to acquire and parse the STIL file, wherein the STIL file includes a test protocol configuration file; A keyword acquisition module, used to search for a pattern keyword in the STIL file, and determine whether the STIL file is valid according to the pattern keyword; A test vector conversion module, used for searching for a test vector according to a fixed format of the test vector if the STIL file is valid, converting the found test vector to generate a plurality of test signals and outputting the signals; A configuration file output module, used for outputting a test bench configuration file according to a process of converting a number of test signals; A test bench file output module is used to generate and output a test bench file in Verilog format according to the test protocol configuration file and the conversion process of several test signals.

[0013] In a third aspect, the present application provides a computer device, which adopts the following technical solution: it includes a memory and a processor, and the memory stores a computer program that can be loaded by the processor and execute any of the above-mentioned STIL file to test bench file conversion methods.

[0014] In a fourth aspect, the present application provides a computer-readable storage medium, which adopts the following technical solution: storing a computer program that can be loaded by a processor and execute any of the above-mentioned STIL file to test bench file conversion methods.

[0015] In summary, this application has the following beneficial technical effects: According to the STIL file that has been generated, the test vector of the STIL file is converted so that it can be converted into a Verilog test bench file for simulation testing. During the chip design process, VCS simulation verification can help designers preliminarily verify whether the design meets the specification requirements, ensure that the chip functions correctly before mass production, and that parameter characteristics meet the specifications, which can effectively avoid the economic losses caused by the mass production of problematic chips. The traditional conversion method generally needs to be carried out together with the STIL file generation process. Through this solution, the conversion process and the STIL file generation process are separated, so that the conversion can be performed in spare time, saving time for key business processes, and thus improving the efficiency of chip verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a flowchart of a method for converting a STIL file to a test bench file in an embodiment of the present application; Figure 2 is a schematic diagram for illustrating a shift signal generation process in an embodiment of the present application; Figure 3is a schematic diagram of a device for converting a STIL file to a test bench file in an embodiment of the present application; Figure 4 It is a schematic diagram used to embody a computer device in an embodiment of the present application.

[0017] Attached figure numbers: 301, original file acquisition module; 302, keyword acquisition module; 303, test vector conversion module; 304, configuration file output module; 305, test bench file output module. DETAILED DESCRIPTION

[0018] The following combination Figure 1-Figure 4 This application is described in further detail.

[0019] An embodiment of the present application discloses a method for converting a STIL file to a test bench file. The method is applied to converting a STIL file to a test bench file system. By adopting the method for converting a STIL file to a Verilog test bench file of the present application, the generation and conversion of the STIL file can be separated. The process of converting the STIL file to the test bench file can be performed separately in idle time, saving time for key business processes and avoiding taking up a large amount of time for the STIL file generation process, which would affect the efficiency of chip ATE machine testing.

[0020] The STIL file is a file format used for ATE test machines. Before the chip officially enters the ATE machine for testing, the correctness of the test vector needs to be verified first, usually using the VCS (Verification Compiler System) verification tool for verification; however, the VCS verification tool only supports test vectors in the Verilog format, so the STIL file needs to be converted into a test bench file in the Verilog format for use by the VCS verification tool for simulation verification.

[0021] The existing STIL file to Verilog test bench file conversion is generally performed through ATPG conversion and output. The ATPG tool converts the STIL file into a Verilog test bench file while generating the STIL file, and outputs the STIL file and the Verilog test bench file together; however, the method of converting the Verilog test bench file while generating the STIL file consumes a lot of time, which may affect the efficiency of chip testing. In order to help save time and improve the efficiency of chip verification, the present application provides a method for converting a STIL file to a test bench file.

[0022] Reference Figure 1 , the method comprises the following steps: S10, obtaining and parsing a STIL file, where the STIL file includes a test protocol configuration file and a test vector.

[0023] Specifically, obtain the STIL file. The STIL file is mainly used to describe the test pattern required by the automatic test equipment (ATE). The acquisition method can be to directly obtain the existing STIL file, or to generate the STIL file through the ATPG tool, and then transfer it to the conversion test bench system to convert the STIL file into the required Verilog test bench file. After obtaining the STIL file, parse the STIL file. Specifically, the STIL file can be parsed by the Parser parser to facilitate reading the required test vector from the STIL file. The STIL file contains all the information required to convert the serial Verilog test bench file, including the test protocol configuration information, that is, the spf (STIL test protocol file) configuration information, and the test vector calculated in the process of ATPG generating STIL. In addition, some special information used in the compression mode is not included in the STIL file, but the key information required when converting the test bench file is output to the Header of the STIL file during the process of ATPG generating the STIL file.

[0024] S20, searching for a pattern keyword in the STIL file, and determining whether the STIL file is valid according to the pattern keyword.

[0025] Specifically, in the STIL (Standard Test Interface Language) file, the pattern keyword is the core part for defining the test vector. The pattern keyword can be interpreted as a test mode keyword. In the STIL file, the pattern keyword is usually located in one or more pattern blocks, which define specific test vectors. According to the result of the pattern keyword (test mode keyword) search, it can be determined whether the current STIL file is valid. If the current STIL file is valid, there are test vectors that need to be converted in the STIL file, and the subsequent steps of converting the test vectors into test signals (test vectors) can be performed. If no valid pattern keyword is found, it means that the current STIL file is invalid and the STIL file cannot be converted, so the conversion process is terminated.

[0026] S30, if the STIL file is valid, search for a test vector according to a fixed format of the test vector, convert the found test vector to generate a number of test signals and output them.

[0027] Specifically, if the pattern keyword (test mode keyword) in the STIL file is found, it means that the STIL file is valid. The test vector in the STIL file has a fixed format. When the STIL file is valid, the test vector can be found according to the inherent format of the test vector, and the found test vector is converted into several test signals (test vectors) for output. It should be noted that a STIL file contains multiple test vectors, and a test vector can output multiple test vectors (test signals).

[0028] S40, outputting a test bench configuration file according to a process of converting a plurality of test signals.

[0029] Specifically, in the process of converting the test vectors in the STIL file into several test vectors (signals), some intermediate data will be generated, such as the number of test vectors finally output, the name of the test vector, and the number of patterns (test modes), etc. These intermediate data are combined to generate a test bench configuration file (test bench config file). The data in the test bench configuration file is needed in the actual conversion into a Verilog test bench file.

[0030] The testbench configuration file has multiple lines, which are determined by the number of test vectors files actually output. Each test vector file has a maximum file size (roughly 1.8G). Each line of the configuration file corresponds to the information of a test vector file, with three fields: the name of the test vector file, the number of lines in the vector, and the number of patterns. This information will be used when the test vector file is called by the testbench.

[0031] S50, generating and outputting a test bench file in Verilog format according to the test protocol configuration file and the conversion process of a plurality of test signals.

[0032] Specifically, according to the existing test protocol configuration file (spf configuration file) and the intermediate information saved in the process of outputting the test vectors, a test bench file in the Verilog format that can be actually used is finally generated. Specifically, according to the test protocol configuration file, that is, the spf configuration file, the main output port name for executing the test vector conversion is converted into a hexadecimal character representation and a main output port name file (PO name file) is generated; then, according to the spf configuration file, the file name and file path of the main output port name file and the intermediate information of the conversion process of several test signals (test vectors), a test bench file in the Verilog format is generated and output.

[0033] The main process of generating the test bench file includes: first reading the test vector file according to the test bench configuration file, and according to the vector file, inputting (Shift in operation) the value of PPI (pseudo input value) into the chip one by one (that is, Shift process), comparing the value of SO (output port) once, and then calling the capture process, and then comparing the value of PO (main output value) to see if it is the same as the expected PO value, so as to perform simulation verification.

[0034] When actually simulating, the port information converted from the STIL file is used to generate the input port value list (_inbus) and the output port simulation value list (sim_outbus); _inbus contains all PI (primary input value) signals, sim_outbus contains all PO (primary output value) signals, and bidirectional ports are written in both _inbus and sim_outbus. Each time a vector is read, the corresponding value on the vector is set to _inbus, and then the clock signal is determined to jump based on the value of the clock in the vector. Each time a shift is executed, the SO (output port) value is compared to see if it is equal. After all values ​​are shifted, the capture process is executed, and the value of the output port expected value list (expected_outbus) is obtained based on the vector settings. After the capture clock jumps, the actual simulated value sim_outbus is obtained, and then the values ​​of each bit of expected_outbus and sim_outbus are compared to see if they are the same. If they are different, there is a simulation error; if they are the same, the simulation passes. Repeat this process to compare the results of each test vector.

[0035] In the present application scheme, the test vectors of the STIL file are converted according to the STIL file that has been generated, so that it can be converted into a Verilog test bench file for simulation testing. In the chip design process, VCS simulation verification can help designers preliminarily verify whether the design meets the specification requirements, ensure that the chip functions correctly before mass production, and that the parameter characteristics meet the specifications, which can effectively avoid the economic losses caused by the mass production of problematic chips. The traditional conversion method generally needs to be carried out together with the STIL file generation process. Through this solution, the conversion process and the STIL file generation process are separated, so that the conversion can be performed in spare time, saving time for key business processes, and thus improving the efficiency of chip verification.

[0036] In one embodiment, considering that the system environment may affect the conversion process in actual applications, and that the test environment is one of the factors affecting chip simulation in actual testing, before searching for a test vector according to a fixed format of the test vector and converting the found test vector to generate a number of test signals and outputting the signals, the following steps may be performed: Generate a test setup vector (setup vector) according to the test protocol configuration file. The test setup vector contains several test setup signals (setup vectors). Specifically, assign values ​​to the input part of the test setup signal according to the value of the test setup process in the test protocol configuration file; the test setup signal (setup vector) has a fixed structure, and the fixed structure of the vector is the values ​​of all PIs, all POs, all PO Masks, and other control values.

[0037] The PI value represents the main input value (the value of the input part), the PO value represents the main output value (the value of the output part), and the PO Mask value represents the PO mask value, which can be understood as whether to compare the actual output value with the output value in the test vector calculated in the STIL file. Other control values ​​represent the function of each setup vector. The functions of a vector may include loading data, comparing data, and other functions. Other control values ​​are used to define the functions of each vector.

[0038] The setup vector is assigned values ​​according to the values ​​set in the test_setup process in the Spf configuration file. The number of test preparation vectors output is equal to the number of V{} function settings in the Spf configuration file. The PI value of each vector is set to the corresponding value according to the signal group or signal setting of test_steup.

[0039] Afterwards, according to the test protocol configuration file, the fixed signal values ​​in the test preparation signal are fixedly set to 0 or 1, that is, the signals in FIXED_0 and FIXED_1 in the signal group are set to the corresponding 0 or 1. Afterwards, the unassigned values, signal input port values, and signal output port values ​​in the test preparation signal are set to X (X indicates that the value of the signal is uncertain, which may be 0 or 1, and the signal output port value may also be Z high impedance state). Specifically, each vector has a PO value in addition to the PI value. The PI value includes the SI signal input port value, the PO includes the SO signal output port value, and the remaining signal values. All PO values ​​are set to X (X indicates that the value of the signal is uncertain, which may be 0, 1, or Z high impedance state), all SI and SO port values ​​are set to X (X indicates that the value of the signal is uncertain, which may be 0 or 1, and the SO port value may also be Z high impedance state), and the remaining values ​​are all set to X (X indicates that the value of the signal is uncertain, which may be 0, 1, or Z high impedance state). It should be noted that when setting the SI and SO port values, it is necessary to first determine whether SI and SO exist in the PI value and PO value; if the SI signal exists in PI, the SI value is directly set to X (X indicates that the value of the signal is uncertain, which may be 0 or 1); if there is no SI, the SI signal is added to the end of the PI value and set to X (X indicates that the value of the signal is uncertain, which may be 0 or 1); similarly, if the SO signal already exists in PO, the SO signal is directly set to X (X indicates that the value of the signal is uncertain, which may be 0, 1 or Z high impedance state); if the SO signal does not exist in PO, the SO signal is added to the end of the PO value and set to X (X indicates that the value of the signal is uncertain, which may be 0, 1 or Z high impedance state). Finally, set several assigned test setup signals (setup vectors) as test setup vectors (setup vectors).

[0040] In the present application scheme, the test environment can be initialized and tested first by setting the test preparation vector process. The test preparation process can ensure that the test environment is correctly initialized, and provide necessary preparations for subsequent test vector loading, test execution, and test result capture. Through this process, testers can ensure that the test process can proceed as expected, thereby effectively verifying the functions and performance of the device under test.

[0041] In one embodiment, the found test vector includes a dummy input value, a dummy output value, a main input value, and a main output value; searching for the test vector according to the fixed format of the test vector, converting the found test vector to generate a plurality of test signals and outputting the signals can be specifically performed as follows: After finding the test vector in the STIL file according to the fixed format of the test vector, first process and generate several shift signals according to the pseudo input values ​​and pseudo output values ​​contained in the test vector. It can also be understood as first using pseudo input values ​​(PPI) and pseudo output values ​​(PPO) to perform the shift process and generate several shift vectors (shift signals). The shift process needs to be implemented through the scan chain to set preset values ​​inside the chip. By serializing the preset values ​​into the scan chain, physical defects or failure modes that may exist inside the chip can be detected.

[0042] Specifically, the method of processing and generating a plurality of shift signals according to the pseudo input value and the pseudo output value can be implemented by the following steps: First, the pseudo input values ​​are input into the scan chain in sequence, and the corresponding pseudo output values ​​are output in sequence through the scan chain in sequence. Considering that the length of the pseudo input value (PPI value) and the length of the pseudo output value (PPO value) in the test vector may be less than the length of the scan chain, the PPI value and the PPO value need to be processed first. The processing method includes that since ATPG has two modes in the process of generating STIL files, compression mode and non-compression mode, the mode type is first determined according to the spf configuration information in the STIL file. If it is non-compression mode, if the length of PPI is less than the maximum scan chain length, it is necessary to fill X at the end of PPI (X indicates that the value of the signal is uncertain, which may be 0 or 1) to make up the maximum scan chain length, and it is necessary to add three 0s at the beginning of PPI and two 0s at the end; for PPO, if the length of PPO is less than the maximum scan chain length, it is necessary to fill X at the end of PPO (X indicates that the value of the signal is uncertain, which may be 0 or 1) to make up the maximum scan chain length. In compression mode, if the length of PPI is less than the maximum scan chain length, three zeros are added at the beginning of PPI and two zeros are added at the end; no special processing is performed for PPO.

[0043] The processed PPI value is input into the scan chain in sequence according to the beats, and the scan chain outputs the PPO value in sequence according to the beats. The pseudo output value (PPO value) output by the scan chain and the pseudo output value (PPO value) in the test vector are compared in sequence according to the beats. It can also be understood as comparing the pseudo output value output by the scan chain with the expected value of the pseudo output value in the test vector, and outputting the comparison result; in the shift process, the output port performs a comparison every time a value is output. Among them, in the compression and non-compression modes, the PPO of the previous test vector is compared when the next test vector is shifted out at the port. Therefore, for the PPO of the first test vector, X needs to be completed (X indicates that the value of the signal is uncertain, which may be 0 or 1), and the mask is set to all 0 (no comparison).

[0044] After that, the pseudo input value, pseudo output value, comparison result and preset control signal are set as shift signal, that is, the PPI value, PPO value, PO Mask value and preset control signal are combined to form a shift signal (shift vector). It should be noted that the shift vector, that is, the shift signal, is composed of PI value + PO value + PO Mask value and control signal. Because the SI signal list is included in the PI signal list, and the SO signal list is included in the PO signal list, each shift vector will input a PPI value; there are multiple groups of PPI and PPO signals, refer to Figure 2 , each time take one bit of a group, set it at the position where the SI signal is located, and output the corresponding one bit of PPO value, set it at the position where the SO signal is located.

[0045] During the loading process, a defined V{} function outputs a vector. The first three correspond to the vectors of the first three values ​​of PPI, and the last two correspond to the vectors of the last two values ​​of PPI. The V{} marked by Shift corresponds to the real effective value of PPI. In addition to the set values ​​of these signals, it is also necessary to set all the signals of the signal group ADD_FIXED_0 to 0, all the signals of ADD_FIXED_1 to 1, and set the RESET signal to the corresponding 1 or 0 (there are commands in ATPG that can set the invalid value of the RESET signal). Starting from the fourth bit of the processed PPI, a vector is generated for each PPI, and the value of the position corresponding to SI in PI is set. If the SI signal is not in the PI signal group, the value of SI is placed at the end of the PI value. For the value of PPO after processing, starting from the fourth bit, the value of the position corresponding to SO in PO is set. If the SO signal is not in the PO signal group, the value of SO is placed at the end of the PO value.

[0046] The preset control signal is used to set the function of the vector, and the structure of the shift vector is consistent with the structure of the above setupvector. Finally, all pseudo input values ​​(PPI) and pseudo output values ​​(PPO) in all test vectors are looped to generate several shift signals (shift vectors).

[0047] After generating the shift vector, considering that there are different types of capture processes in the STIL file, the resulting capture signals (capture vector) are also different, which have been pre-defined in the test protocol configuration file (spf configuration file) in the STIL file. Therefore, before capturing, the type of the STIL file capture process is determined according to the test protocol configuration file. The types of STIL file capture processes include: multi-clock capture (multiclock_capture), reset capture (reset_capture) and on-chip clock capture (OCC_clock_capture); after determining the type, generate and output several capture signals according to the type of STIL file capture process, main input value and main output value; finally, set several shift signals (shift vector) and several capture signals (capturevector) as test signals (test vector).

[0048] Specifically, the method of generating and outputting a plurality of capture signals according to the type of the STIL file capture process, the main input value and the main output value may be performed as follows: If the capture process type of the STIL file is multi-clock capture (multiclock_capture), the enable signal is fixedly set to 0, the reset signal is fixedly set to 1, and the test mode is fixedly set to 1. According to the preset signal format, all main input values, all main output values, and fixedly set values ​​are assigned to the capture signal; if the capture process type of the STIL file is reset capture (reset_capture), the enable signal is fixedly set to 1, the reset signal is fixedly set to 0, and the test mode is fixedly set to 1. According to the preset signal format, all main input values, all main output values, and fixedly set values ​​are assigned to the capture signal; if the capture process type of the STIL file is on-chip clock capture (OCC_clock_capture), the enable signal is fixedly set to 0, the reset signal is fixedly set to 1, and the test mode is fixedly set to 1. According to the preset signal format, all main input values, all main output values, and fixedly set values ​​are assigned to the capture signal.

[0049] It should be noted that for the RESET signal, if the invalid value of the RESET signal is set, the valid value and invalid value are set according to the value set by the command, otherwise they are set according to the definition in the capture process. For the value of SI (input port), if the SI signal is not in PI, 0 is added after PI. For PO Mask (PO mask value), if it is a scan chain test vector (chain pattern), PO Mask is set to all 0, otherwise the PO Mask value is set to all 1. For the SO signal, if the SO signal exists in PO, the corresponding bit of PO Mask needs to be set to 1, that is, a comparison is required. If the SO signal is not in PO, X is added at the end of PO (X indicates that the value of the signal is uncertain, which may be 0, 1 or Z high impedance state), and PO Mask is set to 0. In addition, the signals that need to be fixed in the signal group are set to 0 or 1, that is, the signals of ADD_FIXED_0 are all set to 0, and the signals of ADD_FIXED_1 are all set to 1.

[0050] Generally, the number of capture signals (capture vector) is pre-set and determined by the number of pre-defined V{} functions. In the embodiment of the present application, 6 V{} functions are pre-defined, and 6 capture vectors will be output in the end. The clock signal of each vector is set to a different value according to the process definition.

[0051] In the present application, a shift signal (shift vector) is generated through a beat-by-beat movement process, and multiple capture signals (capture vector) are generated according to different capture types. The shift signal and capture signal generated in the end are converted and can be used to generate the test signal (test vector) of the Verilog test bench file. The shift process and capture process can be used to detect the chip and verify the internal faults of the chip during the actual chip simulation process.

[0052] Figure 1 FIG. 1 is a flow chart of a method for converting a STIL file to a test bench file in an embodiment. It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but the steps are not necessarily executed in the order indicated by the arrows; unless otherwise specified in this document, there is no strict order restriction for the execution of the steps, and the steps may be executed in other orders; and Figure 1At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0053] Based on the above method, an embodiment of the present application also discloses a device for converting a STIL file to a test bench file.

[0054] Reference Figure 3 , the device includes the following modules: The original file acquisition module 301 is used to acquire and parse the STIL file, which contains the test protocol configuration file; The keyword acquisition module 302 is used to search for the pattern keyword in the STIL file and determine whether the STIL file is valid according to the pattern keyword; The test vector conversion module 303 is used to search for a test vector according to a fixed format of the test vector if the STIL file is valid, convert the found test vector to generate a number of test signals and output them; A configuration file output module 304 is used to output a test bench configuration file according to a process of converting a number of test signals; The test bench file output module 305 is used to generate and output a test bench file in Verilog format according to the test protocol configuration file and the conversion process of a plurality of test signals.

[0055] In one embodiment, the test vector conversion module 303 is further configured to generate a test preparation vector according to the test protocol configuration file, where the test preparation vector includes a number of test preparation signals.

[0056] In one embodiment, the test vector conversion module 303 is also used to assign a value to the input part of the test preparation signal according to the value of the test preparation process in the test protocol configuration file; according to the test protocol configuration file, the fixed signal value in the test preparation signal is fixed to 0 or 1; the unassigned value, signal input port value and signal output port value in the test preparation signal are set to X; and several assigned test preparation signals are set as test preparation vectors.

[0057] In one embodiment, the test vector conversion module 303 is specifically used to process and generate a number of shift signals based on pseudo input values ​​and pseudo output values; determine the type of the STIL file capture process based on the test protocol configuration file; generate and output a number of capture signals based on the type of the STIL file capture process, the main input value and the main output value; and set a number of shift signals and a number of capture signals as test signals.

[0058] In one embodiment, the test vector conversion module 303 is specifically used to input the pseudo input values ​​into the scan chain in sequence in beats, and output the corresponding pseudo output values ​​in sequence in beats through the scan chain; compare the pseudo output values ​​output by the scan chain with the pseudo output values ​​in the test vector in sequence in beats, and output the comparison results; set the pseudo input values, pseudo output values, comparison results and preset control signals as shift signals; loop all pseudo input values ​​and pseudo output values, and generate a number of shift signals.

[0059] In one embodiment, the test vector conversion module 303 is specifically used to, if the STIL file capture process type is multi-clock capture, fix the enable signal to 0, the reset signal to 1, the test mode to 1, and assign all main input values, all main output values ​​and fixed values ​​to the capture signal according to a preset signal format; if the STIL file capture process type is reset capture, fix the enable signal to 1, the reset signal to 0, the test mode to 1, and assign all main input values, all main output values ​​and fixed values ​​to the capture signal according to a preset signal format; if the STIL file capture process type is on-chip clock capture, fix the enable signal to 0, the reset signal to 1, the test mode to 1, and assign all main input values, all main output values ​​and fixed values ​​to the capture signal according to a preset signal format.

[0060] In one embodiment, the test bench file output module 305 is specifically used to convert the main output port name that performs test vector conversion into hexadecimal character representation and generate a main output port name file according to the test protocol configuration file; generate and output a test bench file in Verilog format according to the test protocol configuration file, the file name and file path of the main output port name file, and the conversion process of several test signals.

[0061] The STIL file conversion test bench file device provided in the embodiment of the present application can be applied to the STIL file conversion test bench file method provided in the above embodiment. For relevant details, refer to the above method embodiment. The implementation principle and technical effect are similar and will not be repeated here.

[0062] It should be noted that: when converting STIL files to test bench files, the STIL file to test bench file device provided in the embodiment of the present application only uses the division of the above-mentioned functional modules / functional units as an example. In actual applications, the above-mentioned functional allocation can be completed by different functional modules / functional units as needed, that is, the internal structure of the STIL file to test bench file device is divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation method of the STIL file to test bench file method provided in the above method embodiment and the implementation method of the STIL file to test bench file device provided in this embodiment belong to the same concept. The specific implementation process of the STIL file to test bench file device provided in this embodiment is detailed in the above method embodiment, which will not be repeated here.

[0063] The embodiment of the present application also discloses a computer device.

[0064] Specifically, if Figure 4 As shown, the computer device can be a computer device such as a desktop computer, a laptop computer, a PDA, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. The processor and the memory may be connected via a bus or other means. The processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, graphics processors (GPU), embedded neural network processors (NPU) or other dedicated deep learning coprocessors, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above chips.

[0065] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the methods in the above-mentioned embodiments of the present application. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the method in the above-mentioned method implementation is realized. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0066] The embodiment of the present application also discloses a computer-readable storage medium.

[0067] Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by the processor, the method in the above-mentioned method implementation is implemented. Those skilled in the art can understand that the implementation of all or part of the process in the above-mentioned implementation method of the present application can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it may include the process of the implementation of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0068] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A method for converting a STIL file to a test bench file, characterized in that: The method comprises: Obtain and parse a STIL file, wherein the STIL file includes a test protocol configuration file and a test vector; Searching for a pattern keyword in the STIL file, and determining whether the STIL file is valid according to the pattern keyword; If the STIL file is valid, searching for a test vector according to a fixed format of the test vector, converting the found test vector to generate a number of test signals and outputting the signals; Outputting a test bench configuration file according to the process of converting the test signals; A test bench file in Verilog format is generated and output according to the test protocol configuration file and the conversion process of several test signals.

2. The method according to claim 1, characterized in that: Before searching for a test vector according to a fixed format of the test vector and converting the found test vector to generate a plurality of test signals and outputting the signals, the method further includes: A test preparation vector is generated according to the test protocol configuration file, wherein the test preparation vector includes a plurality of test preparation signals.

3. The method according to claim 2, characterized in that: The generating of a test preparation vector according to the test protocol configuration file, wherein the test preparation vector includes a plurality of test preparation signals, includes: assigning a value to an input portion of the test preparation signal according to a value of a test preparation process in the test protocol configuration file; According to the test protocol configuration file, the fixed signal value in the test preparation signal is fixedly set to 0 or 1; Setting the unassigned values, signal input port values ​​and signal output port values ​​in the test preparation signal to X, where X is 0 or 1 or Z is a high impedance state; A plurality of assigned test-ready signals are set as the test-ready vector.

4. The method according to claim 1, characterized in that: The found test vectors include dummy input values, dummy output values, main input values ​​and main output values; The step of searching for a test vector according to a fixed format of the test vector, converting the found test vector to generate a plurality of test signals and outputting the signals comprises: Process and generate a plurality of shift signals according to the pseudo input value and the pseudo output value; Determining the type of the STIL file capture process according to the test protocol configuration file; Generate and output a plurality of capture signals according to the type of the STIL file capture process, the main input value and the main output value; A plurality of the shift signals and a plurality of the capture signals are set as the test signals.

5. The method according to claim 4, characterized in that: The processing and generating of a plurality of shift signals according to the pseudo input value and the pseudo output value comprises: Inputting the pseudo input values ​​into the scan chain in sequence according to the beats, and outputting the corresponding pseudo output values ​​in sequence according to the beats through the scan chain; Compare the dummy output value output by the scan chain with the dummy output value in the test vector in sequence, and output a comparison result; Setting the pseudo input value, the pseudo output value, the comparison result and a preset control signal as the shift signal; All the dummy input values ​​and the dummy output values ​​are looped, and a plurality of the shift signals are generated.

6. The method according to claim 4, characterized in that: The types of the STIL file capture process include: multi-clock capture, reset capture and on-chip clock capture; The generating and outputting a plurality of capture signals according to the type of the STIL file capture process, the main input value and the main output value comprises: If the STIL file capture process type is multi-clock capture, the enable signal is fixedly set to 0, the reset signal is fixedly set to 1, the test mode is fixedly set to 1, and all the main input values, all the main output values ​​and the fixed set values ​​are assigned to the capture signal according to the preset signal format; If the STIL file capture process type is reset capture, the enable signal is fixedly set to 1, the reset signal is fixedly set to 0, the test mode is fixedly set to 1, and all the main input values, all the main output values ​​and the fixed set values ​​are assigned to the capture signal according to the preset signal format; If the STIL file capture process type is on-chip clock capture, the enable signal is fixed to 0, the reset signal is fixed to 1, the test mode is fixed to 1, and according to the preset signal format, all the main input values, all the main output values ​​and the fixed set values ​​are assigned to the capture signal.

7. The method according to claim 1, characterized in that: The test bench file in Verilog format is generated and output according to the test protocol configuration file and the conversion process of the plurality of test signals, including: According to the test protocol configuration file, converting the main output port name for executing the test vector conversion into a hexadecimal character representation and generating a main output port name file; The test bench file in the Verilog format is generated and output according to the test protocol configuration file, the file name and file path of the main output port name file and the conversion process of several test signals.

8. A device for converting a STIL file to a test bench file, characterized in that: The device comprises: An original file acquisition module (301) is used to acquire and parse a STIL file, wherein the STIL file contains a test protocol configuration file; A keyword acquisition module (302), used to search for a pattern keyword in the STIL file, and determine whether the STIL file is valid according to the pattern keyword; A test vector conversion module (303) is used to search for a test vector according to a fixed format of the test vector if the STIL file is valid, convert the found test vector to generate a number of test signals and output them; A configuration file output module (304), used for outputting a test bench configuration file according to a process of converting a plurality of test signals; A test bench file output module (305) is used to generate and output a test bench file in Verilog format according to the test protocol configuration file and the conversion process of the plurality of test signals.

9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and execute the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: A computer program is stored which can be loaded by a processor and execute the method as claimed in any one of claims 1 to 7.

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