Execution method and device of test case in verification platform, equipment and storage medium

Abstract

The invention provides an execution method and device for a test case in a verification platform, equipment and a storage medium, and the method comprises the steps: obtaining a target test case constructed by an interpreted language, and starting the execution of the target test case on the verification platform; the target test case is a program for providing an excitation component for verification of the to-be-tested design file; in response to execution of the target test case, generating a test trigger instruction through the flow controller, and transmitting the test trigger instruction to a sequence control tool in the verification platform through the socket interface; a sequence control tool is used for analyzing the test trigger instruction, the starting and excitation sending sequence of an excitation assembly in the execution process of the target test case is controlled through an analysis result, an excitation execution result is obtained, and the sequence control tool is compiled through a compilation type language; and the excitation execution result is transmitted to the flow controller through the socket interface to be output. According to the application, multi-language compatibility is realized by adopting the socket interface.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method, device, equipment and storage medium for executing test cases in a verification platform. Background Art

[0002] The network-on-chip (NOC) is a key technology of multi-processor architecture. It is the interconnection path and communication network inside the processor, responsible for message transmission, and is the basis for the collaborative work of processors. At the same time, in order to ensure the operational stability of the network-on-chip, the design of the network-on-chip needs to be verified.

[0003] As a large-scale network-on-chip system, the verification environment of NOC relies on large-scale register transfer level (RTL) compilation and verification IP (VIP) compilation. Some environments may even use more than two large VIPs. This method requires constant refreshing of test case configurations and constant construction of test cases in the early test case debugging stage. The traditional method is to construct separately based on the VIP sequence, and then modify the configuration according to different scenario requirements, and then recompile and rerun.

[0004] However, when the test cases are unstable and need to be constantly refreshed, it takes a long time and results in low verification efficiency. Summary of the invention

[0005] The embodiments of the present application provide a method, apparatus, device and storage medium for executing test cases in a verification platform to solve the problems in the related art.

[0006] In a first aspect, an embodiment of the present application provides a method for executing a test case in a verification platform, the method comprising: Obtaining a target test case constructed in an interpreted language, and starting execution of the target test case on a verification platform; the target test case is a program that provides a stimulus component for verification of a design file to be tested; In response to the execution of the target test case, a test trigger instruction is generated by a flow controller, and the test trigger instruction is transmitted to a sequence control tool in the verification platform through a socket interface; The sequence control tool is used to parse the test trigger instruction, and the startup and stimulus sending sequence of the stimulus component during the execution of the target test case are controlled by the parsing result to obtain the stimulus execution result, wherein the sequence control tool is written in a compiled language; The stimulus execution result is transmitted to the flow controller through the socket interface for output to complete the execution of the target test case.

[0007] In a second aspect, an embodiment of the present application provides a device for executing a test case in a verification platform, the device comprising: An acquisition module is used to acquire a target test case constructed in an interpreted language and start the execution of the target test case on a verification platform; the target test case is a program that provides a stimulus component for the verification of the design file to be tested; A first transmission module, configured to generate a test trigger instruction through a flow controller in response to the execution of the target test case, and transmit the test trigger instruction to a sequence control tool in the verification platform through a socket interface; An execution module, used to parse the test trigger instruction through the sequence control tool, and control the startup of the stimulus component and the stimulus sending sequence during the execution of the target test case through the parsing result to obtain the stimulus execution result, wherein the sequence control tool is written in a compiled language; The second transmission module is used to transmit the stimulus execution result to the flow controller for output through the socket interface to complete the execution of the target test case.

[0008] In a third aspect, an embodiment of the present application further provides an electronic device, including a processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method of the first aspect.

[0009] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, which, when instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method of the first aspect.

[0010] In an embodiment of the present application, a target test case written in an interpreted language is obtained, and test case related information is sent to a verification platform through a socket interface. The verification platform determines the startup and stimulus sending order and executes the target test case to obtain the stimulus execution result. The stimulus execution result can also be fed back through the socket interface in reverse. In this way, intercommunication between interpreted languages ​​and compiled languages ​​is achieved through the socket interface, and multi-language compatibility is achieved. Due to multi-language compatibility, the time for constructing test cases is greatly reduced, thereby improving verification efficiency.

[0011] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0013] Figure 1 It is a step flow chart of a method for executing a test case in a verification platform provided in an embodiment of the present application.

[0014] Figure 2 It is a schematic diagram of an architecture for executing a test case provided in an embodiment of the present application.

[0015] Figure 3 It is a flowchart of the specific steps of a method for executing a test case in a verification platform provided in an embodiment of the present application.

[0016] Figure 4 It is a schematic diagram of the architecture of a compilation test case provided in an embodiment of the present application.

[0017] Figure 5 It is a schematic diagram of the data flow direction in a verification platform provided in an embodiment of the present application.

[0018] Figure 6 It is a block diagram of a test case execution device in a verification platform provided in an embodiment of the present application.

[0019] Figure 7 It is a block diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0021] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally a class, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three kinds of relationships can exist, for example, A and / or B can be represented: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the front and back associated objects are a kind of "or" relationship. In the embodiment of the present application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0022] In practical applications, although the multiple processor cores in a multi-core processor chip each execute their own code, data needs to be shared and synchronized between the processor cores. Therefore, the hardware structure of the multi-core processor must support efficient inter-core communication, and the performance of the on-chip communication structure will directly affect the performance of the processor.

[0023] Therefore, the network-on-chip (NOC) is a key technology of the multi-processor architecture. It is the interconnection path and communication network inside the processor, responsible for message transmission, and is the basis for the collaborative work of processors. The network-on-chip aims to solve the communication problem within the multi-core processor. The network-on-chip is an integrated circuit on a network-based communication subsystem. The network-on-chip is a packet switching network based on routers between systems-on-chip. The network-on-chip technology draws on the interconnection network structure of parallel computers, integrating a large number of computing resources and an on-chip communication network connecting these resources on a single chip. Each processor core has an independent router and its private cache, and is connected together through an on-chip communication network. The message communication mechanism is used between the processor cores, and the on-chip bus of the related technology is replaced by routers and packet switching technology to complete the communication task, thereby solving the various bottleneck problems caused by bus interconnection in the related technology.

[0024] Specifically, in the process of developing and designing on-chip networks, high-level languages ​​(such as Python) can be used to write on-chip network design files. In one implementation method, the on-chip network design files can be in the form of register transfer level (RTL). In digital circuit design, RTL is an abstract model of synchronous digital circuits. This model can describe the circuit structure based on the flow of digital signals between logic units such as hardware registers, memories, combinational logic devices and buses, as well as their logic algebraic operation.

[0025] The network on chip may include multiple hardware units, which may include: routing modules, access devices, consistency modules, processor cores, buffers, etc. Among them, the routing module is an important component of the network on chip, and the routing module is used to implement important functions in the network on chip such as routing calculation and data arbitration. In addition, the number of routing modules can be multiple, and multiple routing modules can be connected to each other. The routing module can also be connected to other access devices. For example, the access device connected to the injection port of the routing module may include external devices such as memory, graphics card, network card, etc., that is, through a rich selection of additional access devices, the function realization of the multi-core processor architecture is improved.

[0026] In related technologies, as the chip scale increases and the number of modules in the chip increases, the number of on-chip networks in the chip and the number of interfaces in each on-chip network increase significantly. The verification environment of NOC relies on large-scale RTL compilation and VIP compilation. Some environments may even use more than two large VIPs. This method requires constant refreshing of test case configurations and constant construction of test cases in the early test case debugging stage. The traditional method is to construct separately based on the VIP sequence, and then modify the configuration according to different scenario requirements, and then recompile and rerun.

[0027] However, when the test cases are unstable and need to be constantly refreshed, they need to be recompiled every time the configuration is changed. The VIP and RTL required for the NOC verification environment are often large in size and the compilation time is also long. At this time, the verification personnel spend most of their time waiting for compilation.

[0028] In order to solve the above problems, the present application provides a method, device, equipment and storage medium for executing test cases in a verification platform, which realizes the intercommunication between interpreted languages ​​and compiled languages ​​through a socket interface and realizes multi-language compatibility. Due to multi-language compatibility, the time for constructing test cases is greatly reduced, thereby improving verification efficiency.

[0029] The following is a detailed description of the method for executing test cases in the verification platform provided by this application.

[0030] Figure 1 is a flowchart of a method for executing a test case in a verification platform provided by an embodiment of the present application, such as Figure 1 As shown, the method may include the following steps.

[0031] Step 101: Obtain a target test case constructed in an interpreted language, and start executing the target test case on a verification platform.

[0032] It should be noted that an interpreted language is a programming language that interprets and executes the source code line by line through an interpreter when it is executed. The interpreter reads the source code, translates it into machine code (or intermediate code) line by line and executes it immediately without generating an executable file.

[0033] In the embodiment of the present application, the interpreted language may be Python, JavaScript, Ruby, Hypertext Preprocessor (PHP), etc.

[0034] In the embodiment of the present application, the target test case may be a program that provides a stimulus component for the verification of the design file under test. The stimulus component is used to randomly generate a stimulus signal (transaction) input into the design under test (DUT), and receive a response signal output by the DUT, thereby performing simulation behavior to test the function of the DUT.

[0035] In some embodiments, the design file to be tested may be a circuit design file to be tested corresponding to the DUT.

[0036] It should be noted that in the design field of the intellectual property module (IP) of integrated circuits, designers can use Verilog (a hardware description language) to write circuit designs and obtain design files of the circuit to be tested. The design files of the circuit to be tested can be used to describe the constituent units of the circuit, the interconnection relationships between the constituent units, and other contents.

[0037] In some embodiments, before step 101, the execution method of the test case in the above verification platform may also include: obtaining the circuit design file to be tested for testing, and building the verification platform based on the Universal Verification Methodology (UVM). Among them, UVM is a set of class libraries built in System Verilog language to implement the verification methodology based on coverage-driven excitation random constraints. UVM aims to unify and standardize the verification specifications of the industry.

[0038] In some embodiments, the design file of the circuit under test includes task descriptions of different functional modules in the chip under test and / or hardware definitions of each functional module.

[0039] In some embodiments, the verification platform initiating execution of the target test case may include: executing code of a target test script corresponding to the target test case.

[0040] Step 102: In response to the execution of the target test case, a test trigger instruction is generated by the flow controller, and the test trigger instruction is transmitted to the sequence control tool in the verification platform through the socket interface.

[0041] In the embodiment of the present application, the socket interface may be a Socket.

[0042] In the embodiment of the present application, the traffic controller (Traffic Control, TC) is used for the flow control of the Linux kernel. It uses queue rules to establish a queue for processing data packets and defines the way in which the data packets in the queue are sent, thereby realizing the control of the flow. The queue rules used by TC are divided into two categories, one is the classless queue rules and the other is the classified queue rules. The classless queue rules are relatively simple, while the classified queue rules have functions such as classification and filters, which enhance their flow control function.

[0043] In the embodiment of the present application, the test trigger instruction may be a trigger instruction by which the Socket can interact with the Python TC.

[0044] In some embodiments, the user can locate all parameters and sending timing information specified for running a test sequence, and the user needs to write code in Python coding format.

[0045] In the embodiment of the present application, the sequence control tool may be common_sequence in Verilog Intellectual Property, wherein the sequence control tool is used to generate complex stimuli and flexibly control stimuli parameters to generate complex stimuli.

[0046] It should be noted that in IP verification, various input stimuli need to be provided to the verified IP core to verify the correctness of its functions. The sequence mechanism can be used to generate a series of regular or random stimulus signal sequences. For example, when verifying a network protocol IP core, the sequence can generate a sequence of data packets that conform to a specific protocol format, including different addresses, data contents, and control signals, etc., to simulate network data transmission in a real environment. Through the sequence mechanism, various parameters of the stimulus can also be flexibly configured and modified. For example, the frequency, duty cycle, data width and other parameters of the stimulus signal can be dynamically adjusted to comprehensively test the response and stability of the IP core under different input conditions. Taking a high-speed analog-to-digital converter (ADC) IP core verification as an example, the sequence can generate analog signals of different frequencies and amplitudes as input to verify the conversion accuracy and speed of the ADC under various conditions.

[0047] In the embodiment of the present application, common_sequence may be obtained by inheriting base_sequence, and common_sequence integrates the transaction level modeling (TLM) communication interface of UVM.

[0048] For example, the Socket interface can interact with the Python TC, and the Python TC sends the packaged transaction bit stream to the receiving direction (Receive, RX) of the Socket client interface. The socket sending direction (Transmit, TX) can interact with the common_sequence through the TX interface to send the data to the common_sequence, thereby realizing the sending of the transaction stream.

[0049] Step 103: parse the test trigger instruction through the sequence control tool, and control the startup of the stimulus component and the stimulus sending sequence during the execution of the target test case through the parsing result to obtain the stimulus execution result.

[0050] In the embodiment of the present application, the sequence control tool is written in a compiled language.

[0051] It should be noted that compiled languages ​​exist in contrast to interpreted languages. Compiled languages ​​are programming languages ​​that require a compiler to convert source code into machine code (or intermediate code) before execution. The compiler translates the entire source code into target code at one time, generates an executable file, and then runs it directly on the target platform.

[0052] In the embodiment of the present application, the compiled language may be C language, C++, etc.

[0053] In some embodiments, step 103 may include: using common_sequence in the verification platform to parse the test trigger instruction to obtain the stimulus start and sending sequence.

[0054] In some embodiments, the verification stimulus is input into the verification platform and the design to be tested paths respectively according to the stimulus startup and sending order. In the path corresponding to the verification platform, the verification stimulus flows through the Reference model, and the first execution result of the Reference model is input into the Scoreboard; in the path corresponding to the design to be tested, the second execution result of the design to be tested is obtained, and the second execution result is input into the Scoreboard; in the Scoreboard, the stimulus execution result is generated according to the obtained first execution result and the second execution result.

[0055] Step 104: Transmit the stimulus execution result to the flow controller through the socket interface for output to complete the execution of the target test case.

[0056] In some embodiments, step 104 may include the following sub-steps.

[0057] Sub-step 1041: transmitting the incentive execution result to the flow controller through the socket interface, and outputting the incentive data stream related to the incentive execution result through the flow controller.

[0058] In some embodiments, step 104 may further include the following sub-steps: Sub-step 1042: output the stimulus data stream related to the stimulus execution result to the test case pool (PyCase case pool) through the flow controller.

[0059] For example, common_sequence is a sequence inherited from VIP. In some sequence scenarios, the integrated VIP can return a response. Similarly, in order to obtain this data, Python TC can also interact with Socket through common_sequence, receive the returned response, and complete the interaction with Socket TX and Python TC to return the response to Pyton TC for subsequent response interaction.

[0060] It should be noted that see Figure 2In the verification environment, you can specify a PyCase test case pool, which includes multiple tests. For example, in order to save the time cost of testing and reduce the number of test rounds, you can use smoke test (ST). Each test includes parameter configuration, random configuration and control of the sending order required for common_sequence to send stimulus. When the user runs the verification environment, it runs at the bottom of the compilation simulation tool (Verilog CompiledSimulator, VCS). When the user needs to run PyCase, the Python test case that the Socket interface needs to run interactively is specified in the command line. In this way, Python will interact with the Socket interface during the test case execution phase, and the Socket interface and common_sequence maintain communication and send stimulus.

[0061] In summary, in the embodiments of the present application, a target test case written in an interpreted language is obtained, and the test case related information is sent to a verification platform through a socket interface. The verification platform determines the startup and stimulus sending order and executes the target test case to obtain the stimulus execution result. The stimulus execution result can also be fed back through the socket interface in reverse. In this way, the intercommunication between the interpreted language and the compiled language is achieved through the socket interface, and multi-language compatibility is achieved. Due to multi-language compatibility, the time for constructing test cases is greatly reduced, thereby improving the verification efficiency.

[0062] Figure 3 is a flowchart of the specific steps of a method for executing a test case in a verification platform provided by an embodiment of the present application, such as Figure 3 As shown, the method may include the following steps.

[0063] Step 201: When modifying the parameters of a test case or constructing a test case, determine the configuration parameters of the test script after the modification.

[0064] In an embodiment of the present application, modifying the parameters of a test case or constructing a test case includes modifying the parameters of an existing test case or constructing a new test case.

[0065] In some embodiments, modifying the parameters of a test case or constructing a test case may include: modifying a Sequence Item in vip_common_sequence, wherein each test case is composed of a series of actions, and each action represents a state change or input event of the system.

[0066] In some embodiments, before step 201, the method for executing the test case in the above verification platform further includes the following sub-steps.

[0067] Sub-step A1: obtaining a preset designated writing format, wherein the designated writing format includes a Python encoding format.

[0068] Sub-step A2: Write the code of the target test script in a specified writing format according to the parameters and sending timing required by the running sequence control tool.

[0069] In the embodiment of the present application, the specified writing format may be a Python encoding format.

[0070] In an embodiment of the present application, the parameters and sending timing required for running the sequence control tool may include all parameters and sending timing information specified by the sequence running.

[0071] Exemplarily, sub-step A2 may include: writing the code of the target test script in the Python coding format according to all parameters and sending timing information specified by the sequence operation.

[0072] Step 202: Recompile the test script in the verification environment platform according to the modified configuration parameters to obtain the target test case.

[0073] In an embodiment of the present application, target test cases use different sequences to generate stimuli.

[0074] In some embodiments, after step 202, the execution method of the test case in the above verification platform may further include: storing the compiled target test case in the test case pool (PyCase). In this way, the subsequent operation directly loads the target test case, avoiding recompilation at each operation, reducing compilation time, increasing program startup speed, and improving program operation efficiency.

[0075] It should be noted that see Figure 4 The environment in the embodiment of the present application is divided into two parts. The part that does not need to be compiled includes PyCase and Socket interfaces, as well as the configuration function for configuring test cases; the part that needs to include common_sequence, DUT and verification environment. Figure 4 In the architecture, through common_sequence, various parameters of PyCase can be flexibly configured and modified. When the user needs to modify parameters or construct new test cases, he only needs to modify the parameters in Pycase or add Pycase, recompile the test script, and get the target test case without recompiling the entire environment. In this way, it communicates with Python through the dynamic link library and realizes platform isolation through the Socket interface while achieving multi-language compatibility.

[0076] In some embodiments, step 202 may include the following sub-steps.

[0077] Sub-step 2021: According to the modified configuration parameters, the test script is recompiled in the verification environment component according to the grammatical rules of the compiled language to obtain a binary file.

[0078] Sub-step 2022: Execute the interpreted language script and binary file to obtain the target test case.

[0079] Optionally, sub-step 2021 may include: obtaining a target test script according to the modified configuration parameters; searching for a corresponding library according to the language type of the compiled language script; and writing and compiling the target test script according to the documentation of the library to obtain a binary file.

[0080] Exemplarily, if the compiled language is C language, the corresponding library may be syck or lyaml, and the compiled language script is written and the target test script is compiled through the syck library or the lyaml library to obtain a binary file.

[0081] Step 203: Pack the parameter information and timing information required for sending the stimulus through the packing task function in the flow controller to obtain a test trigger instruction.

[0082] In an embodiment of the present application, the packing task function may be Pack_task.

[0083] In an embodiment of the present application, the packaging task function is used to package the parameter information and timing information required for sending incentives specified by the user.

[0084] Step 204: Send the test trigger instruction to the socket interface through the sending task function in the traffic controller.

[0085] In the embodiment of the present application, the sending task function may be Send_task.

[0086] In the embodiment of the present application, the sending task function is used to send the sending stimulus information bit stream specified by the user to the Socket interface.

[0087] Step 205: Transmit the data stream corresponding to the test trigger instruction to the sequence control tool in the verification platform through the socket interface.

[0088] The method of this step has been described in the aforementioned step 102 and will not be repeated here.

[0089] In some embodiments, step 205 may include the following sub-steps.

[0090] Sub-step 2051, transmitting the data stream to the transaction-level modeling communication interface in the verification environment platform through the socket interface; Sub-step 2052: Send the data stream to the sequence control tool through the transaction-level modeling communication interface.

[0091] In the embodiment of the present application, the transaction level modeling communication interface may be a TLM communication interface.

[0092] It should be noted that TLM is a language-independent standard that is often used for system modeling to accelerate the collaborative development of software and hardware. In chip development, it is often used in conjunction with System C for system design.

[0093] For example, see Figure 5 , the architecture in the embodiment of the present application includes a flow controller (Python TC), a socket interface (Socket interface), a transaction-level modeling communication interface (TLM communication interface), a sequence control tool (common_sequence) and a design under test (DUT). Among them, when the quantity is the sending direction (TX), the transmission of the data stream includes: the flow controller calls the Python interface through the C language, sends the data stream to the Socket interface, the Socket interface interacts with the TLM communication interface through the C language, the TLM communication interface interacts with the System Verilog, and sends the data to the sequence control tool, and the sequence control tool interacts with the design under test through the connection.

[0094] Optionally, the TLM communication interface includes a get_cfg task function, a get_rn_transaction function, and a send_rn_transaction function.

[0095] Exemplarily, sub-step 2052 may include: obtaining data from the TML communication interface through get_rn_transaction; in the case of obtaining transaction-related stimulus data (transaction), calling send_rn_transaction to parse the transaction and send it to the sequence control tool. A transaction is a basic unit of one or a group of database operations, and operations related to a transaction are either all executed successfully or all failed and returned.

[0096] Step 206: parse the test trigger instruction through the sequence control tool to obtain parsed data, where the parsed data includes the start-up of the stimulus component and the stimulus sending sequence during the execution of the target test case.

[0097] In the embodiment of the present application, the sequence control tool is written in a compiled language.

[0098] The method of this step has been described in the aforementioned step 103 and will not be repeated here.

[0099] In some embodiments, step 206 may include the following sub-steps.

[0100] Sub-step 2061: Acquire transaction data corresponding to the test trigger instruction from the transaction-level modeling communication interface through the acquisition task function in the sequence control tool.

[0101] Sub-step 2062: parse the transaction data to obtain parsed data through the parsing task function in the sequence control tool.

[0102] In the embodiment of the present application, the transaction-level modeling communication interface (TLM communication interface) improves the abstraction level of design and verification. It no longer focuses on the specific behavior of the signal level, such as clock cycles, high and low level changes of signals, etc., but models in units of transactions. For example, when verifying the communication between a processor and memory, TLM can abstract a memory read and write operation as a transaction without describing in detail the changes of address lines, data lines, and control lines in each clock cycle. This can greatly reduce the complexity of modeling and speed up design and verification.

[0103] Optionally, the TLM communication interface includes the get_cfg task function, get_rn_transaction function and send_rn_transaction function. Among them, the get_cfg task function is used to obtain the verification configuration given by the upper layer of the environment, get_rn_transaction is used to obtain data from TML as needed, and send_rn_transaction is used to parse the stimulus data (transaction) and send it.

[0104] Exemplarily, sub-step 2062 may include: receiving a response after the transaction is completed and writing it into the TML communication interface.

[0105] Step 207: input the parsed data into the design file to be tested to obtain the stimulus execution result.

[0106] In some embodiments, step 207 may include: inputting the parsed data into two paths, the verification platform and the design to be tested, respectively, wherein in the path corresponding to the verification platform, the verification stimulus flows through the Reference model, and the first execution result of the Reference model is input into the Scoreboard; in the path corresponding to the design to be tested, the second execution result of the design to be tested is obtained, and the second execution result is input into the Scoreboard; in the Scoreboard, the stimulus execution result is generated according to the obtained first execution result and the second execution result. .

[0107] Step 208: Obtain the stimulus execution result transmitted by the sequence control tool from the transaction-level modeling communication interface through the socket interface.

[0108] Optionally, step 208 may include: obtaining a success response or a failure response after the transaction is completed by common_sequence transmitted from the TML interface through the Socket interface. The success response includes confirmation information, data confirmation, operation result confirmation, etc.; the failure response includes error code and message, system failure information, data conflict information, etc.

[0109] Exemplarily, if a successful response is returned, the following situations are included.

[0110] 1. Confirmation information: Return a clear success indicator, for example, {"status":"success","message":"Transactioncompletedsuccessfully"}, indicating that the transaction has been completed successfully.

[0111] 2. Data confirmation: If the transaction involves reading or modifying data, relevant data results may be returned. For example, {"data":[{"id":123,"name":"JohnDoe","balance":1000.50}],"status":"success"}, which means that the relevant data records are successfully obtained.

[0112] 3. Operation result confirmation: If the operation is update, insert, etc., information such as the number of affected rows may be returned, for example, {"rows_affected":5,"status":"success"}, indicating that 5 records are affected by this transaction operation.

[0113] For example, if a failure response is returned, the following situations are included.

[0114] 1. Error code and message: Returns the specific error code and detailed error message to help locate and solve the problem. For example, {"status":"error","error_code":"TML-001","error_message":"Invalidtransactiondata"}, indicating that the failure was caused by invalid transaction data.

[0115] 2. System fault information: If there is a problem within the system, it may return, for example, {"status":"error","error_code":"SYS-500","error_message":"Internalservererror"} indicates that a failure occurred inside the server.

[0116] 3. Data conflict information: In concurrent operations, if data conflicts occur, it may return, for example, {"status":"error","error_code":"CONFLICT-409","error_message":"Dataconflictdetectedduringtransaction"}, indicating that data conflict was detected during transaction processing.

[0117] Step 209: Return the stimulus execution result to the flow controller through the socket interface.

[0118] In some embodiments, step 209 may include: transmitting the stimulus execution result to the flow controller via the socket interface, and outputting the stimulus data stream related to the stimulus execution result via the flow controller.

[0119] In some embodiments, after step 209, the method for executing test cases in the above verification platform may further include: outputting the stimulus data flow related to the stimulus execution result to the test case pool (PyCase) through the flow controller.

[0120] For example, see Figure 5 , the architecture in the embodiment of the present application includes a flow controller (Python TC), a socket interface (Socket interface), a transaction-level modeling communication interface (TLM communication interface), a sequence control tool (common_sequence) and a design under test (DUT). Among them, when the quantity is the receiving direction (RX), the transmission of the data stream includes: the design under test interacts with the sequence control tool through a connection, and transmits the stimulus execution result to the sequence control tool, the TLM communication interface interacts with System Verilog, and returns the data value to the TLM communication interface, and the Socket interface interacts with the TLM communication interface through the C language, and returns the stimulus execution result to the flow controller.

[0121] To sum up, in the embodiments of the present application, the compiled language and the interpreted language are interoperable through the socket interface, thereby realizing multi-language compatibility and platform isolation. Conversely, the data that the environment needs to sample can also be fed back to the test case pool through the socket interface; when the user needs to modify parameters or construct a new test case, he only needs to modify the parameters of the test case or add a new test case without recompiling the entire environment, which greatly reduces the compilation time and improves the verification efficiency.

[0122] Figure 6 It is a block diagram of a test case execution device in a verification platform provided in an embodiment of the present application. The device 600 includes the following modules.

[0123] The acquisition module 601 is used to acquire a target test case constructed in an interpreted language and start the execution of the target test case on a verification platform; the target test case is a program that provides a stimulus component for the verification of the design file to be tested.

[0124] The first transmission module 602 is used to generate a test trigger instruction through a flow controller in response to the execution of a target test case, and transmit the test trigger instruction to a sequence control tool in the verification platform through a socket interface.

[0125] The execution module 603 is used to parse the test trigger instruction through the sequence control tool, and control the startup of the stimulus component and the stimulus sending order during the execution of the target test case through the parsing result to obtain the stimulus execution result. The sequence control tool is written in a compiled language.

[0126] The second transmission module 604 is used to transmit the stimulus execution result to the flow controller for output through the socket interface to complete the execution of the target test case.

[0127] Optionally, the test case execution device 600 in the above verification platform also includes the following modules.

[0128] The first determination module is used to determine the configuration parameters of the test script after the modification when modifying the parameters of the test case or constructing the test case.

[0129] The compilation module is used to recompile the test script in the verification environment platform according to the modified configuration parameters to obtain the target test case, and the target test case uses different sequences to generate stimuli.

[0130] Optionally, the compilation module includes: a compilation sub-module, used to recompile the test script according to the grammatical rules of the compiled language in the verification environment component according to the modified configuration parameters to obtain a binary file, and a first execution sub-module, used to execute the interpreted language script and the binary file to obtain the target test case.

[0131] Optionally, the first transmission module 602 includes: a packing submodule, used to pack the parameter information and timing information required for sending the stimulus through the packing task function in the flow controller to obtain a test trigger instruction; a packing submodule, used to send the test trigger instruction to the socket interface through the sending task function in the flow controller; a transmission submodule, used to transmit the data stream corresponding to the test trigger instruction to the sequence control tool in the verification platform through the socket interface.

[0132] Optionally, the transmission submodule includes: a transmission unit, used to transmit the data stream to the transaction-level modeling communication interface in the verification environment platform through the socket interface; and a sending unit, used to send the data stream to the sequence control tool through the transaction-level modeling communication interface.

[0133] Optionally, the second transmission module 604 includes: an acquisition submodule, used to acquire the stimulus execution result transmitted by the sequence control tool from the transaction-level modeling communication interface through the socket interface; and a return submodule, used to return the stimulated execution result to the flow controller through the socket interface.

[0134] Optionally, the test case execution device 600 in the above verification platform also includes the following modules.

[0135] The format acquisition module is used to obtain the preset specified writing format, and the specified writing format includes the Python encoding format.

[0136] The writing module is used to write the code of the target test script in a specified writing format according to the parameters and sending timing required by the running sequence control tool.

[0137] Optionally, the execution module 603 includes: a parsing submodule, which is used to parse the test trigger instructions through a sequence control tool to obtain parsing data, and the parsing data includes the startup and stimulus sending sequence of the stimulus components during the execution of the target test case; and a second execution submodule, which is used to input the parsing data into the design file to be tested to obtain the stimulus execution result.

[0138] Optionally, the parsing submodule includes: an acquisition unit, used to obtain transaction data corresponding to the test trigger instruction from the transaction-level modeling communication interface through the acquisition task function in the sequence control tool; and a parsing unit, used to parse the transaction data to obtain parsed data through the parsing task function in the sequence control tool.

[0139] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0140] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0141] Regarding the device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0142] An embodiment of the present application provides an electronic device, comprising a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more processors to perform the methods described in one or more of the above embodiments.

[0143] The present application also provides an electronic device, see Figure 7 , the electronic device 700 may include one or more of the following components: a processing component 702 , a memory 704 , a power component 706 , a multimedia component 708 , an audio component 710 , an input / output (I / O) interface 712 , a sensor component 714 , and a communication component 716 .

[0144] The processing component 702 generally controls the overall operation of the electronic device 700, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 702 may include one or more processors 720 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 702 may include one or more modules to facilitate the interaction between the processing component 702 and other components. For example, the processing component 702 may include a multimedia module to facilitate the interaction between the multimedia component 708 and the processing component 702.

[0145] The memory 704 is used to store various types of data to support the operation of the electronic device 700. Examples of such data include instructions for any application or method operating on the electronic device 700, contact data, phone book data, messages, pictures, multimedia, etc. The memory 704 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0146] The power supply component 706 provides power to the various components of the electronic device 700. The power supply component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 700.

[0147] The multimedia component 708 includes an interface that provides an output interface between the electronic device 700 and the user. In some embodiments, the interface may include a liquid crystal display (LCD) and a touch panel (TP). If the interface includes a touch panel, the interface may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the boundaries of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 708 includes a front camera and / or a rear camera. When the electronic device 700 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0148] The audio component 710 is used to output and / or input audio signals. For example, the audio component 710 includes a microphone (MIC), and when the electronic device 700 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 704 or sent via the communication component 716. In some embodiments, the audio component 710 also includes a speaker for outputting audio signals.

[0149] The input / output I / O interface 712 provides an interface between the processing component 702 and the peripheral interface module, which may be a keyboard, a click wheel, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0150] The sensor assembly 714 includes one or more sensors for providing various aspects of status assessment for the electronic device 700. For example, the sensor assembly 714 can detect the open / closed state of the electronic device 700, the relative positioning of components, such as the display and keypad of the electronic device 700, and the sensor assembly 714 can also detect the position change of the electronic device 700 or a component of the electronic device 700, the presence or absence of user contact with the electronic device 700, the orientation or acceleration / deceleration of the electronic device 700, and the temperature change of the electronic device 700. The sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 714 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 714 may also include an acceleration sensor, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0151] The communication component 716 is used to facilitate wired or wireless communication between the electronic device 700 and other devices. The electronic device 700 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 7G or 7G), or a combination thereof. In an exemplary embodiment, the communication component 716 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 716 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0152] In an exemplary embodiment, the electronic device 700 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement a method for executing test cases in a verification platform provided in an embodiment of the present application.

[0153] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 704 including instructions, and the instructions can be executed by a processor 720 of an electronic device 700 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0154] An embodiment of the present application further provides a computer program product, including a computer program, which implements the method described in the above embodiment when executed by a processor.

[0155] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the application disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0156] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A method for executing a test case in a verification platform, characterized in that: The method comprises: Obtaining a target test case constructed in an interpreted language, and starting execution of the target test case on a verification platform; the target test case is a program that provides a stimulus component for verification of a design file to be tested; In response to the execution of the target test case, a test trigger instruction is generated by a flow controller, and the test trigger instruction is transmitted to a sequence control tool in the verification platform through a socket interface; The sequence control tool is used to parse the test trigger instruction, and the startup and stimulus sending sequence of the stimulus component during the execution of the target test case are controlled by the parsing result to obtain the stimulus execution result, wherein the sequence control tool is written in a compiled language; The stimulus execution result is transmitted to the flow controller through the socket interface for output to complete the execution of the target test case.

2. The method for executing test cases in a verification platform according to claim 1, characterized in that: The method further comprises: obtaining a target test case constructed in an interpreted language, and before the verification platform starts executing the target test case: When modifying the parameters of a test case or constructing a test case, determine the configuration parameters of the test script after the modification; According to the modified configuration parameters, the test script is recompiled in the verification environment platform to obtain a target test case, and the target test case generates stimulus using a different sequence.

3. The method for executing test cases in a verification platform according to claim 2, characterized in that: The step of recompiling the test script in the verification environment platform according to the modified configuration parameters to obtain the target test case includes: According to the modified configuration parameters, the test script is recompiled in the verification environment component according to the grammatical rules of the compiled language to obtain a binary file, The interpreted language script and the binary file are executed to obtain a target test case.

4. The method for executing test cases in a verification platform according to claim 1, characterized in that: The method of generating a test trigger instruction through a flow controller and transmitting the test trigger instruction to a sequence control tool in a verification platform through a socket interface includes: The parameter information and timing information required for sending the stimulus are packaged by the packaging task function in the flow controller to obtain the test trigger instruction; Sending the test trigger instruction to the socket interface through a sending task function in the traffic controller; The data stream corresponding to the test trigger instruction is transmitted to the sequence control tool in the verification platform through the socket interface.

5. The method for executing test cases in a verification platform according to claim 4, characterized in that: The method of transmitting the data stream corresponding to the test trigger instruction to the sequence control tool in the verification platform through the socket interface includes: Transmitting the data stream to a transaction-level modeling communication interface in a verification environment platform through a socket interface; The data stream is sent to the sequence control tool through the transaction level modeling communication interface.

6. The method for executing test cases in a verification platform according to claim 1, characterized in that: The step of transmitting the stimulus execution result to the flow controller for output through the socket interface includes: Acquiring, through the socket interface, a stimulus execution result transmitted by the sequence control tool from the transaction-level modeling communication interface; The stimulated execution result is returned to the flow controller through the socket interface.

7. The method for executing test cases in a verification platform according to claim 2, characterized in that: In the case of modifying the parameters of the test case or constructing the test case, before determining the configuration parameters of the modified test script, the method further includes: Obtain a preset specified writing format, wherein the specified writing format includes a Python encoding format; According to the parameters and sending timing required for running the sequence control tool, write the code of the target test script in accordance with the specified writing format.

8. The method for executing test cases in a verification platform according to claim 1, characterized in that: The test trigger instruction is parsed by the sequence control tool, and the startup and stimulus sending sequence of the stimulus component during the execution of the target test case are controlled by the parsing result to obtain the stimulus execution result, including: Parsing the test trigger instruction by the sequence control tool to obtain parsed data, wherein the parsed data includes the start-up and stimulus sending sequence of the stimulus component during the execution of the target test case; The parsed data is input into the design file to be tested to obtain the stimulus execution result.

9. The method for executing test cases in a verification platform according to claim 8, characterized in that: The step of parsing the test trigger instruction by the sequence control tool to obtain parsed data includes: Acquire the transaction data corresponding to the test trigger instruction from the transaction-level modeling communication interface through the acquisition task function in the sequence control tool; The transaction data is parsed to obtain parsed data through the parsing task function in the sequence control tool.

10. A device for executing test cases in a verification platform, characterized in that: The device comprises: An acquisition module is used to acquire a target test case constructed in an interpreted language and start the execution of the target test case on a verification platform; the target test case is a program that provides a stimulus component for the verification of the design file to be tested; A first transmission module, configured to generate a test trigger instruction through a flow controller in response to the execution of the target test case, and transmit the test trigger instruction to a sequence control tool in the verification platform through a socket interface; An execution module, used to parse the test trigger instruction through the sequence control tool, and control the startup of the stimulus component and the stimulus sending sequence during the execution of the target test case through the parsing result to obtain the stimulus execution result, wherein the sequence control tool is written in a compiled language; The second transmission module is used to transmit the stimulus execution result to the flow controller for output through the socket interface to complete the execution of the target test case.

11. An electronic device, characterized in that: include: processor; a memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method as claimed in any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that: When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the method as claimed in any one of claims 1 to 9.

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