Method and system for checking quality of standard intercellular spacing

Abstract

The invention provides a method and a system for checking standard cell interval quality in a design. The method includes providing a first standard cell. A cell environment of a first standard cell is determined, and a first feasible distance is determined between a first boundary of the first standard cell and a boundary of a first adjacent cell based on the cell environment. Based on the cell environment, a second feasible distance is determined between a second boundary of the first standard cell and a boundary of a second adjacent cell. A feasible interval is provided between the first standard cell and the second standard cell, and an evaluation of the feasible interval is made based on the first feasible distance, the second feasible distance, and the cell spacing of the first standard cell. An integrated circuit including a first standard cell responsive to the evaluation is fabricated. The invention relates to improving and optimizing standard cell design using the results of a quality inspection process.

Description

Technical Field

[0001] The invention relates to a method and a system for checking the quality of a standard cell compartment. Background Art

[0002] Typically, automated tools are used to assist semiconductor designers with manufacturing and circuit design, including converting the functional design of a circuit into a finished layout of the circuit. Integrated circuit (IC) automated design tools are used to convert circuit designs into circuit layouts for manufacturing. The process includes converting the behavioral description of the circuit into a functional description, which is then decomposed into logical functions and drawn into rows of cells using a standard cell library, which includes standard cells for predetermined logical functions, such as NAND, NOR, latches, and flip-flop functions. Standard cells may include transistors, diodes, resistors, inductors, capacitors, or other suitable devices, or a combination of one or more such devices formed in a substrate to perform a predetermined logical function. Automatic Placement and Routing (APR) methods and systems may be used to construct an IC layout in which selected standard cells are placed adjacent to each other in the IC layout. Once the rows of cells are mapped, synthesis is performed to convert the structural design into a physical layout, construct a clock tree to synchronize the structural elements, and optimize the design after layout. Some parts of the design and manufacturing process are often manual, such as checking the quality of the standard cells. Summary of the invention

[0003] A method for checking the quality of standard cell spacing according to an embodiment of the present invention includes: providing a first standard cell; determining a cell environment of the first standard cell; determining a first feasible distance between a first boundary of the first standard cell and a boundary of a first adjacent cell based on the cell environment; determining a second feasible distance between a second boundary of the first standard cell and a boundary of a second adjacent cell based on the cell environment; providing a feasible spacing between the first standard cell and the second standard cell; evaluating the feasible spacing based on the first feasible distance, the second feasible distance and the cell spacing of the first standard cell; and manufacturing an integrated circuit including the first standard cell in response to the evaluation.

[0004] A method for checking the quality of standard cell intervals according to an embodiment of the present invention comprises: providing a first standard cell; providing a plurality of additional standard cells; evaluating a plurality of feasible intervals between the first standard cell and the corresponding plurality of additional standard cells, comprising: determining a plurality of interval scores for each of the plurality of feasible intervals; determining an overall interval score based on the plurality of interval scores; and manufacturing an integrated circuit responsive to the overall interval score.

[0005] A system for inspecting the quality of standard cell spacing according to an embodiment of the present invention comprises: a processor; a memory, which can be accessed by the processor and stores instructions, and when executed by the processor, performs a method including evaluating a feasible spacing between a first standard cell and a second standard cell; wherein the feasible spacing is based on a first feasible distance between a first boundary of the first standard cell and a boundary of a first adjacent cell, a second feasible distance between a second boundary of the first standard cell and a boundary of a second adjacent cell, and a cell spacing of the first standard cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a block diagram schematically illustrating an example of a process system according to some embodiments.

[0008] Figure 2 is a schematic diagram illustrating an example IC design according to some embodiments and may include Figure 1 A diagram of the manufacturing process of a process system.

[0009] Figure 3 is a flow chart illustrating an example of a standard cell spacing quality inspection process according to some embodiments.

[0010] Figure 4 According to some embodiments, Figure 3 A block diagram of further aspects of the process shown in FIG.

[0011] Figure 5 According to some embodiments, Figure 3 A block diagram of further aspects of the process shown in FIG.

[0012] Figure 6 According to some embodiments, Figure 3 A block diagram of further aspects of the process shown in FIG.

[0013] Figure 7 According to some embodiments, Figure 3 A block diagram of further aspects of the process shown in FIG.

[0014] Figure 8 According to some embodiments, Figure 3 A block diagram of further aspects of the process shown in FIG.

[0015] Fig. 9 According to some embodiments, Figure 3A block diagram of further aspects of the process shown in FIG.

[0016] Fig.10 is a flow chart illustrating an example of a standard cell quality inspection process according to some embodiments.

[0017] Fig.11 According to some embodiments, Fig.10 A block diagram of further aspects of the process shown in FIG.

[0018] Fig.12 According to some embodiments, Fig.10 A block diagram of further aspects of the process shown in FIG.

[0019] Fig.13 According to some embodiments, Fig.10 A block diagram of further aspects of the process shown in FIG.

[0020] Fig.14 is a flow chart illustrating an example of a standard cell quality inspection process according to some embodiments.

[0021] Fig.15 According to some embodiments, Fig.14 A block diagram of further aspects of the process shown in FIG. DETAILED DESCRIPTION

[0022] The following disclosure provides a plurality of different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature is formed in direct contact with the second feature, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature may not be in direct contact with the second feature. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0023] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0024] Automation tools are often used to assist semiconductor designers with manufacturing and circuit design, including converting a functional design of a circuit into a finished layout of the circuit. IC designs often include standard cells or "intellectual property" (IP) blocks (used interchangeably in this article), which refer to reusable, custom-designed logic components, memory components, etc.

[0025] In the integrated circuit (IC) manufacturing process, many aspects are automated. However, some parts of the process are still manual, such as checking the quality of standard cells during design, optimization, physical implementation, and manufacturing processes for improving the power, performance, and area (PPA) of the IC. Such quality checks usually rely on human experience and manual inspection of standard cells. Although guidelines for standard cell quality checks can be developed, there is a lack of a systematic approach to check the quality of standard cells from the design platform to physical implementation and wafer manufacturing. In addition, standard cell quality issues may appear later in the process, such as during the physical implementation or wafer manufacturing steps, which may result in poor IC design quality return (QoR). For example, the lack of standard cell design quality review may result in increased area requirements and / or reduced performance (e.g., slower speed) in the circuit.

[0026] Therefore, the standard cell design process relies on human experience to implement the following design items, such as the size, location and connection of the cell; planning and connection of the middle process and back-end process (MEOL, BEOL); IO pin accessibility and the like. Usually, the standard cell to standard cell spacing is not considered in the design stage. There is a lack of systematic and well-defined checking mechanism to evaluate and compare the QoR between two cells in a given environment. In addition, although the spacing between standard cells may be important in the design process, it may be difficult to simulate the constraints between two cells for automated processes.

[0027] Aspects of the present disclosure relate to a standard cell level interval quality inspection method. Provide cell-to-cell interval inspection for designs in various environments, such as power delivery (PG) network structures, pre-placed cell locations, etc. A scoring system is used to represent cell quality. The cell design flow is used to incorporate a quality inspection process, including providing feedback on the QoR of the cell so that the cell design quality can be ensured before release. Further aspects relate to using the results of the quality inspection process to improve and optimize the standard cell design. Such a process can reduce the turnaround time of the cell design between the design and implementation of the cell. In addition, once the cell is optimized and passes the process verification, the standard cell design can be further optimized for items such as PPA (power, performance and area).

[0028] Figure 11 is a block diagram schematically illustrating an example of a computer system 100 according to some embodiments. In some embodiments, one or more operations and / or functions of the tools and / or systems described herein are implemented by a processor 101, which is programmed to perform such operations and / or functions. One or more of the memory 102 (including the kernel 114 and the user space 116), the network I / F 106, the storage 110, the I / O device 108, the hardware component 118, and the bus 104 are operable to receive instructions, data, design rules, netlists, layouts, models, and / or other parameters for the processor 101 to perform a process.

[0029] In some embodiments, one or more operations and / or functions of the tools and / or systems described herein are implemented by specially configured hardware (e.g., via one or more included application specific integrated circuits (ASICs)) separate from or in place of processor 101. Some embodiments combine more than one of the described operations and / or functions into a single ASIC (application specific integrated circuit).

[0030] In some embodiments, the operations and / or functions are implemented as functions of a program stored in a non-transitory computer-readable recording medium, such as storage 110 and / or memory 102. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM), memory cards, or other suitable non-transitory computer-readable recording media.

[0031] The computer system 100 may also include a manufacturing tool 150 for implementing the process and / or method stored in the storage 110, such as manufacturing an IC. For example, the design may be synthesized, wherein the behavior and / or function required by the design is converted into a functionally equivalent logic gate-level circuit description by matching the design with standard cells selected from a layout cell library. The synthesis result is functionally equivalent to the logic gate-level circuit description, such as a gate-level netlist. Based on the gate-level netlist, a photolithography mask may be generated, which is used to manufacture the integrated circuit through the manufacturing tool 150. According to some embodiments, further in combination Figure 2 (which is a block diagram of an IC manufacturing system 200) and an IC manufacturing process associated therewith, disclose aspects of device manufacturing. In some embodiments, based on the layout diagram, the manufacturing system 200 is used to manufacture at least one of the following: (A) one or more semiconductor masks, or (B) a component in a layer of at least one semiconductor integrated circuit.

[0032] Figure 2 is a block diagram of an IC manufacturing system 200 according to some embodiments. Figure 2In the present invention, the IC manufacturing system 200 includes entities such as a design room 220, a mask room 230, and an IC manufacturer / fabricator (fab) 250, which interact with each other in the design, development and manufacturing cycle and / or services related to the manufacture of IC devices 260. The entities in the system 200 are connected through a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an enterprise intranet, the Internet, etc. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design room 220, the mask room 230, and the IC manufacturer / fabricator 250 are owned by a single large company. In some embodiments, two or more of the design room 220, the mask room 230, and the IC manufacturer / fabricator 250 coexist in a common facility and use common resources.

[0033] The design office (or design team) 220 generates an IC design layout 222. The IC design layout 222 includes patterns of various geometric shapes or IC layouts designed specifically for the IC device 260. The geometric patterns correspond to patterns of metal, oxide or semiconductor layers, which constitute various components of the IC device 260 to be manufactured. Various layers are combined to form various IC features. For example, a portion of the IC design layout 222 includes various IC features, such as active areas, gate electrodes, source and drain, metal lines or through-holes for interconnecting between layers, and openings for bonding pads to be formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. The design office 220 implements a design process to form the IC design layout 222. The design process includes one or more of a logic design, a physical design, or a layout and routing. The IC design layout 222 is presented in one or more data files having geometric pattern information. For example, the IC design layout 222 can be represented in a GDSII file format or a DFII file format.

[0034] The mask chamber 230 includes data preparation 232 and mask manufacturing 244. The mask chamber 230 uses the IC design layout drawing 222 to manufacture one or more masks 245 to be used as various layers of the IC device 260 according to the IC design layout drawing 222. The mask chamber 230 performs mask data preparation 232, wherein the IC design layout drawing 222 is converted into a representative data file (RDF). The mask data preparation 232 provides the RDF to the mask manufacturing 244. The mask manufacturing 244 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 245 or a semiconductor wafer 253. The design layout drawing 222 is manipulated by the mask data preparation 232 to conform to the specific characteristics of the mask writer and / or the requirements of the IC manufacturer / fabricator 250. In Figure 2 In FIG. 2 , mask data preparation 232 and mask manufacturing 244 are shown as separate elements. In some embodiments, mask data preparation 232 and mask manufacturing 244 may be collectively referred to as mask data preparation.

[0035] In some embodiments, mask data preparation 232 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those caused by diffraction, interference, other process effects, etc. OPC adjusts IC design layout 222. In some embodiments, mask data preparation 232 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting mask, other suitable techniques, and the like or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0036] In some embodiments, mask data preparation 232 includes a mask rule checker (MRC) that checks the IC design layout 222 that has been through the OPC process using a set of mask creation rules, where the mask creation rules include certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC (mask rule checker) modifies the IC design layout 222 to compensate for the restrictions during mask fabrication 244, which may undo some of the modifications made by the OPC to satisfy the mask creation rules.

[0037] In some embodiments, mask data preparation 232 includes a lithography process check (LPC), which simulates the process that will be implemented by IC manufacturer / fabricator 250 to manufacture IC device 260. Based on IC design layout 222, LPC simulates such a process to create a simulated manufactured device, such as IC device 260. Processing parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other appropriate factors, and the like or combinations thereof. In some embodiments, after creating a simulated manufactured device through LPC, if the simulated device is not close enough in shape to meet the design rules, OPC and / or MRC are repeated to further refine the IC design layout 222.

[0038] It should be understood that the above description of mask data preparation 232 has been simplified for the purpose of clarity. In some embodiments, additional features are included in the data preparation 232, such as logic operations (LOPs), to modify the IC design layout 222 according to manufacturing rules. In addition, the processes applied to the IC design layout 222 during the data preparation 232 can be performed in a variety of different orders.

[0039] After mask data preparation 232 and during mask manufacturing 244, a mask 245 or a group of masks 245 are manufactured based on the modified IC design layout 222. In some embodiments, mask manufacturing 244 includes performing one or more photolithography exposures based on the IC design layout 222. In some embodiments, an electron beam (e-beam) or multiple electron beam mechanisms are used to form a pattern on a mask (photomask or reticle) 245 based on the modified IC design layout 222. The mask 245 can be formed using a variety of techniques. In some embodiments, the mask 245 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, is blocked by the opaque areas and penetrates the transparent areas, and the radiation beam is used to expose an image sensitive material layer (e.g., photoresist) that has been coated on the wafer. In one embodiment, a binary mask version of mask 245 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another embodiment, mask 245 is formed using an offset phase technique. In a phase-shifted mask (PSM) version of mask 245, each feature in a pattern formed on the phase-shifted mask is configured to have an appropriate phase difference to enhance resolution and imaging quality. In various embodiments, the offset mask phase can be an attenuated PSM or an alternating PSM. Masks produced by mask manufacturing 244 are used in various processes. For example, such masks are used in ion implantation processes to form various doped regions in semiconductor wafer 253, in etching processes to form various etched regions in semiconductor wafer 253, and / or in other suitable processes.

[0040] IC manufacturer / fab 250 includes wafer fabrication 252. IC manufacturer / fab 250 is an IC manufacturing company that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC manufacturer / fab 250 is a semiconductor foundry. For example, there may be a fabrication plant for front-end fabrication (FEOL fabrication) of multiple IC products, while a second fabrication plant may provide back-end fabrication (BEOL fabrication) for interconnection and packaging of IC products, and a third fabrication facility may provide other services for the wafer foundry.

[0041] IC manufacturer / fabricator 250 uses mask 245 manufactured by mask chamber 230 to manufacture IC device 260. Therefore, IC manufacturer / fabricator 250 at least indirectly uses IC design layout 222 to manufacture IC device 260. In some embodiments, semiconductor wafer 253 is manufactured by IC manufacturer / fabricator 250 using mask 245 to form IC device 260. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based at least indirectly on IC design layout 222. Semiconductor wafer 253 includes a silicon substrate or other suitable substrate with a material layer formed thereon. Semiconductor wafer 253 also includes one or more of various doped regions, dielectric features, multi-level interconnects, and the like (formed at subsequent manufacturing steps).

[0042] The disclosed embodiment also includes an IP or standard cell quality inspection process 300, which can be implemented by the computer system 100 as part of the design studio 220. An example of the first standard cell quality inspection process 300a is Figure 3 The quality inspection process 300a is part of a larger design quality inspection process discussed further below. Figure 3 The process 300a shown is related to checking the quality of the design as it relates to the cell-to-cell spacing of the standard cells in the design. As described above, the process 300a shown can be Figure 1 The computer system 100 shown in FIG. 1 is implemented as Figure 2 Part of the design room 220.

[0043] Process 300a includes providing a standard cell design at operation 310 and providing a design environment at operation 312, which may include items such as power distribution (i.e., power ground, PG) networks, pre-set cells, and cell components. A cell abstraction operation 314 for spacing quality checking uses the cells and design environment provided at operations 310 and 312. The cell abstraction provided at operation 314 is then used in a cell spacing quality checking operation 316, where inter-cell spacing is evaluated. The spacing evaluation provided by operation 316 is input to a cell quality score operation 318, where a spacing quality score is calculated, which can be compared to a threshold to determine whether the evaluated cell passes the quality check.

[0044] Figure 4 and Figure 5 Further illustrating aspects of the cell abstraction operation 314, a standard cell c 1 Various aspects at different platforms of operation 314. Unit abstraction operation 314 includes at platform 314a, unit c 1For example, the physical object may include a shape 320, an electrical interface 322 (such as a through hole and a metal line), a blockage 324, and the like.

[0045] The individual objects of the cell can be arranged along tracks 326, where a spacing 328 is defined as the distance between tracks 326. In some embodiments, the spacing 328 corresponds to the gate spacing of the IC process (contact poly pitch, CPP). In some embodiments, the spacing 328 corresponds to the metal one pitch of the IC process, which is the same as the polysilicon gate pitch of the IC process. In some embodiments, the spacing 328 corresponds to the metal one pitch of the IC process, which is different from the polysilicon gate pitch of the IC process. In some embodiments, the spacing 328 corresponds to a multiple of the metal one pitch of the IC process.

[0046] At platform 314b and platform 314c, according to environmental constraints (such as PG network, pre-placed unit location, etc.), in unit c 1 The available locations / solutions are marked on the top. Therefore, at platform 314b, in unit c 1 The PG position 330 is identified on the platform 314c, and based on the position of the physical objects modeled at the platform 314a (i.e., the shape 320, the electrical junction 322, the obstruction 324) together with the PG position 330 identified at the platform 314b, the available position 332 for the PG network 330 and the unavailable position 334 for the PG network 330 are identified on the platform 314c.

[0047] Figure 5 Shown from Figure 4 The platform 314c includes an available position 332 for the PG network 330 and an unavailable position 334 for the PG network 330. At the platform 314d, the unit c 1 A PG pattern 340 for the PG network is identified above, which is combined with the results of platform 314c to derive possible or feasible locations 342 for the PG network as shown in platform 314e.

[0048] Figure 6-Figure 8316 is an example of further aspects of the cell spacing quality check operation 316 according to some embodiments. Operation 316 focuses on evaluating the cell spacing (i.e., cell-to-cell spacing), which is usually not addressed in an objective and automated manner in the design process. Therefore, operation 316 includes an equation-based spacing quality check process that first transforms the distance of the first feasible position to the left and right boundaries of the adjacent cells into variables. Depending on the cell c 1 Various aspects of, for example, the identified feasible position 342 for the PG network 330, the distance d of the first feasible position to the left boundary 350 l and the distance d to the first feasible position of the right boundary 352 r .

[0049] In some embodiments, the following formula is used to evaluate the unit c 1 and another unit c i The cell-to-cell spacing between:

[0050]

[0051] where s is two units (i.e. Figure 7 The unit c shown in 1 and unit c 2 ) between the feasible intervals.

[0052] P is the cell pitch. Figure 7 Unit c 1 Identified instances

[0053] d 1 r From Unit 1 c 1 The distance from the right boundary of to the first feasible position, the right boundary is close to the first unit c 1 The neighboring unit on the right (i.e. Figure 7 The unit c shown in 2 ).

[0054] d 2 l From Unit 2 c 2 The distance from the left boundary of the first feasible position to the left boundary close to the second unit c 2 The neighboring unit on the left (i.e. the first unit c 1 ).

[0055] In some embodiments, the input to equation (1) (and other equations disclosed below) is input to, for example Figure 1The storage 110 and / or memory 102 of the system 100 shown in FIG. Such input may be provided by a user using an I / O device 108 or received via a network I / F (network interface) 106. Some of the input may be calculated by the processor 101 and stored in an appropriate memory.

[0056] If equation (1) is true, then s is a unit c 1 and unit c 2 The closer the result of equation (1) is to 0, the better the design quality is with respect to the cell-to-cell spacing. Moreover, this cell spacing quality inspection process 300a can be used as part of a larger scale quality inspection process to inspect a design including multiple standard cells.

[0057] It should be noted that d l and d r Will change depending on the orientation of the unit. Figure 8 Shows unit c 3 , where d l and d r They are 1CPP and 7CPP respectively. Fig. 9 Shows unit c 3 The reverse orientation (i.e., mirror image) of d l and d r On the contrary. When unit c 3 Oriented as Fig. 9 When shown, d l and d r They are 7CPP and 1CPP respectively.

[0058] exist Figure 3 At operation 318, cell level spacing quality operation 316 is used to determine a cell quality score. In some embodiments, the cell quality score of a given cell (e.g., cell c) in the IC design is calculated. 1 ) and other cells to determine the interval quality score for a given cell.

[0059] For example, Unit 1 c 1 The standard unit interval fraction g because it is connected to another unit c i Correlation can be determined according to formula (2):

[0060]

[0061] Therefore, the number of feasible intervals determined by equation (1) can be used in equation (2) to determine the first cell c 1 and another unit c i The interval quality score of the interval between .

[0062] Then the unit c can be determined according to formula (3): 1 The overall interval quality score S is because it is consistent with all other cells c in the design. i Related.

[0063]

[0064] In formula (3), the unit c 1 to n other units c i The interval quality score g i Add and divide by other units c i The total score S for a particular design (representing the cell-to-cell spacing quality score of the design's standard cells) can then be compared to a threshold value T to determine a quality check pass / fail.

[0065] Fig.10 is shown with Figure 2 FIG. 4 is a flow chart of another process 300 b associated with the standard cell quality inspection process 300 shown in FIG. Fig.10 The process 300b shown will Figure 3 The standard cell spacing quality inspection process 300a shown is incorporated into the standard cell design process. Fig.10 In the process 300b of FIG. 1 , each designed standard cell is checked against the design-specific environmental constraints before release. Therefore, a standard cell circuit design is provided at operation 360, and a layout design of the cell is provided at operation 362. The cell circuit design operation 360 and the layout design operation 362 may be combined with Figure 2 The design house 220 disclosed as part of the IC design is associated. At operation 364, a standard cell quality check process can be performed, wherein various quality checks are provided to the circuits and layouts provided by operations 360 and 362. Operation 364 of the quality check process can check functional items such as cell operation efficiency and accuracy, cell area utilization, and compliance with various design rules.

[0066] exist Fig.10 In process 300b, Figure 3 The cell spacing quality check process 300a is performed to evaluate the cell-to-cell spacing of the cells in the design provided at operation 360 and operation 362. Before release, each standard cell design provided in operation 360 and operation 362 is checked using design-specific environment constraints. As described above, in conjunction with process 300a, the design environment is set at Figure 3 The process 300a is shown at operation 312. Fig.11As shown, the design environment of the standard cell design 370 includes, for example, shapes 320, electrical junctions 322 such as vias and metal lines, stoppers 324, etc. Different types and styles of PG network components (including strips 372 or pillars 374) are considered, as well as various spacings and pitches for different PG components (e.g., 8-CPP or 4-CPP for VDD to VDD spacing).

[0067] exist Fig.12 , different locations (eg, design boundaries or hierarchies of a cell design) are considered for items such as metal lines and other electrical junctions 322, shapes 320, etc., which are considered relative to other cells 376 or components of other hierarchies 378. Fig.13 An example is shown in which various pre-placed cells are evaluated for cell design 370. For example, various pre-placed abutment scenarios or orientations may be considered. Fig.13 , two different pre-placed unit sizes and shapes can be considered at state 380 and state 382.

[0068] These design specific environment constraints can be used in the standard cell level spacing quality check process 300a to determine feasible boundary locations for input to equations (1) and (2) disclosed above. If the results in the cell spacing quality check process 300a meet the predetermined threshold in operation 366, the cell is released for design. If the threshold is not met in operation 366, the process is repeated and the design may be modified and optimized for cell to cell spacing. The optimized cell design can then be released in operation 368 for IC fabrication, for example, by Figure 2 As shown in the IC manufacturer / fabricator 250, the IC manufacturing operation 368 may be employed Figure 1 1 and 12. The manufacturing tool 150 and other components of the system 100 are shown in FIG.

[0069] According to a further aspect, the cell-to-cell spacing quality of an existing design may be evaluated to diagnose and improve quality issues of the existing design. Fig.14 Such a process 300c is shown, which is combined with the cell spacing quality check 300a. Operation 390 is provided with an existing design or wafer. For example, Fig.15 As shown, the cell spacing quality inspection process 300a may be used to analyze an existing design 410 or wafer 400 to identify and diagnose quality issues of the design 410. In some embodiments, defective or underperforming existing standard cell designs may be extracted to improve and enhance the designs.

[0070] At operation 392, environmental constraints are extracted from the design 410. Fig.15 In the extraction and design of the two standard cells c included in 410 1 With c 2 The environmental constraints 412 such as the associated electrical junction 322. These environmental constraints can be used to determine the unit c 1 and c 2 The feasible cell spacing of the design can be evaluated by inputting the information into equations (1)-(3) to evaluate the cell spacing quality. If the result of the cell spacing quality inspection process 300a meets the predetermined threshold at operation 394, the existing design is released for IC manufacturing at operation 398 (e.g. Figure 2 The IC manufacturer / fabricator 250 shown in FIG. 2 may manufacture the IC using Figure 1 1 and 12. If the quality requirements are not met at operation 394, then at operation 396, the evaluated standard cell design is improved.

[0071] Thus, the disclosed embodiments disclose processes and systems for checking and evaluating the quality of spacing between standard cells based on a design environment. Furthermore, such cell-to-cell spacing quality checks can be formed in an objective and automated manner, using a disclosed process flow for standard cell level design checks to ensure cell design quality before releasing the design and the process flow of cell design quality for existing designs or wafers. This helps to further improve factors such as PPA of existing designs. This can reduce standard cell design processing time and further improve performance (e.g., PPA) by ensuring that all standard cell designs meet the cell spacing standards.

[0072] In some embodiments, a method for checking the quality of standard cell spacing includes: providing a first standard cell; determining a cell environment of the first standard cell; determining a first feasible distance between a first boundary of the first standard cell and a boundary of a first adjacent cell based on the cell environment; determining a second feasible distance between a second boundary of the first standard cell and a boundary of a second adjacent cell based on the cell environment; providing a feasible spacing between the first standard cell and the second standard cell; evaluating the feasible spacing based on the first feasible distance, the second feasible distance and the cell spacing of the first standard cell; and manufacturing an integrated circuit including the first standard cell in response to the evaluation.

[0073] In some embodiments, the method further comprises modifying the design of the first standard cell based on the evaluation. In some embodiments, the method further comprises determining a standard cell spacing score of the first standard cell based on the evaluation. In some embodiments, if the standard cell spacing score exceeds a threshold, the integrated circuit is manufactured. In some embodiments, the method further comprises modeling a plurality of physical objects of the first standard cell, wherein the first feasible distance and the second feasible distance are further determined based on the modeling. In some embodiments, the plurality of physical objects comprises at least one of a shape, an electrical junction, a perforation, a metal line and / or an obstruction. In some embodiments, the cell environment comprises at least one of a power grid and / or a pre-placed cell location. In some embodiments, the feasible spacing is evaluated based on the following formula:

[0074]

[0075] Where s is the feasible spacing between the first standard cell and the second standard cell; P is the cell spacing; d 1 r is the first feasible distance; and d 2 l is the second feasible distance. In some embodiments, it also includes: providing multiple feasible intervals between the first standard cell and the corresponding multiple additional standard cells; evaluating the multiple feasible intervals; and manufacturing the integrated circuit including the first standard cell and the multiple additional standard cells based on the evaluation of the multiple feasible intervals. In some embodiments, it also includes: providing a circuit design; providing a layout design; and wherein the cell environment is based on the circuit design and the layout design. In some embodiments, it also includes: providing an existing wafer including the first standard cell; wherein the cell environment is extracted from the existing wafer.

[0076] In some embodiments, a method for inspecting the quality of standard cell spacing comprises: providing a first standard cell; providing a plurality of additional standard cells; evaluating a plurality of feasible spacings between the first standard cell and the corresponding plurality of additional standard cells, comprising: determining a plurality of spacing scores for each of the plurality of feasible spacings; determining an overall spacing score based on the plurality of spacing scores; and manufacturing an integrated circuit responsive to the overall spacing score.

[0077] In some embodiments, the evaluation of the plurality of feasible spacings comprises: determining a cell environment of the first standard cell; determining a first feasible distance between a first boundary of the first standard cell and a boundary of a first adjacent cell based on the cell environment; and determining a second feasible distance between a second boundary of the first standard cell and a boundary of a second adjacent cell based on the cell environment. In some embodiments, the evaluation of the plurality of feasible spacings is performed based on the first feasible distance, the second feasible distance, and the cell spacing of the first standard cell. In some embodiments, the evaluation further comprises modifying the design of the first standard cell based on the evaluation. In some embodiments, if the overall spacing score is below a threshold, the design of the first standard cell is improved.

[0078] In some embodiments, a system for inspecting the quality of standard cell spacing includes: a processor; a memory that can be accessed by the processor and stores instructions, which when executed by the processor, performs a method including evaluating a feasible spacing between a first standard cell and a second standard cell; wherein the feasible spacing is based on a first feasible distance between a first boundary of the first standard cell and a boundary of a first adjacent cell, a second feasible distance between a second boundary of the first standard cell and a boundary of a second adjacent cell, and a cell spacing of the first standard cell.

[0079] In some embodiments, performing the method further comprises: receiving a cell environment of the first standard cell, and determining the first feasible distance and the second feasible distance based on the cell environment. In some embodiments, wherein evaluating the feasible interval comprises calculating a standard cell interval score for the first standard cell. In some embodiments, performing the method further comprises: evaluating a plurality of feasible intervals between the first standard cell and a corresponding plurality of additional standard cells; calculating a plurality of standard cell interval scores for each of the plurality of feasible intervals corresponding to the evaluation; calculating an overall interval score based on the plurality of interval scores; and comparing the overall interval score to a threshold.

[0080] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and various changes, substitutions and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for checking the quality of a standard cell compartment, comprising: providing a first standard unit; determining a cell environment of the first standard cell; determining, based on the cell environment, a first feasible distance between a first boundary of the first standard cell and a boundary of a first neighboring cell; determining, based on the cell environment, a second feasible distance between a second boundary of the first standard cell and a boundary of a second neighboring cell; providing a feasible spacing between the first standard cell and the second standard cell; evaluating the feasible spacing based on the first feasible distance, the second feasible distance, and the cell spacing of the first standard cell; and An integrated circuit is fabricated including the first standard cell responsive to the evaluating. 2 . The method of claim 1 , further comprising modifying a design of the first standard cell based on the evaluating. 3 . The method of claim 1 , further comprising modeling a plurality of physical objects of the first standard cell, wherein the first feasible distance and the second feasible distance are determined further based on the modeling.

4. The method according to claim 1, wherein the feasible interval is evaluated based on the following formula: in s is the feasible interval between the first standard cell and the second standard cell; P is the unit spacing; d1 r is the first feasible distance; and d2 l is the second feasible distance.

5. A method for checking the quality of a standard cell compartment, comprising: providing a first standard unit; Provides multiple additional standard units; Evaluating a plurality of feasible spacings between the first standard cell and the corresponding plurality of additional standard cells comprises: determining a plurality of interval scores for each of the plurality of feasible intervals; determining an overall interval score based on the plurality of interval scores; and An integrated circuit is fabricated responsive to the overall spacing fraction.

6. The method of claim 5, wherein the evaluation of the plurality of feasible intervals comprises: determining a cell environment of the first standard cell; determining, based on the cell environment, a first feasible distance between a first boundary of the first standard cell and a boundary of a first neighboring cell; as well as Based on the cell environment, a second feasible distance is determined between a second boundary of the first standard cell and a boundary of a second neighboring cell. 7 . The method of claim 5 , further comprising modifying a design of the first standard cell based on the evaluating. The method of claim 5 , wherein if the overall spacing score is below a threshold, improving the design of the first standard cell.

9. A system for checking the quality of a standard cell compartment, comprising: processor; a memory accessible by the processor and storing instructions that, when executed by the processor, perform a method including, evaluating a feasible spacing between a first standard cell and a second standard cell; The feasible spacing is based on a first feasible distance between a first boundary of the first standard cell and a boundary of a first adjacent cell, a second feasible distance between a second boundary of the first standard cell and a boundary of a second adjacent cell, and a cell pitch of the first standard cell.

10. The system according to claim 9, performing the method further comprising: receiving a cell environment of the first standard cell, and The first feasible distance and the second feasible distance are determined based on the cell environment.

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