Behavior-level modeling method of analog circuit, electronic equipment and storage medium

Abstract

The invention provides a behavior-level modeling method of an analog circuit, electronic equipment and a storage medium. The behavior-level modeling method comprises the following steps: acquiring an equivalent circuit of an analog circuit; analyzing a function expression of a target node in the equivalent circuit; and performing hardware language conversion on the function expression to obtain a target digital model of the analog circuit. An analysis object during modeling is the equivalent circuit of the analog circuit, so that a digital model obtained by modeling the equivalent circuit can be suitable for various analog circuits, the reuse of verification platforms and use cases of similar power supply chips is facilitated, the development periods of the verification platforms and the use cases are reduced, and the development efficiency is improved. Meanwhile, a PID algorithm module and a chip-level verification platform assembly can be reused, and the chip verification period is efficiently shortened. And digital modeling is carried out on an analog circuit in the chip, so that the verification environment of the chip supports a UVM digital verification platform, verification programming languages and verification scenes are enriched, the complexity of the verification environment is reduced, and the configuration of the verification environment is simplified.

Description

Technical Field

[0001] The present application relates to the field of chip verification technology, and in particular to a behavior-level modeling method for analog circuits, an electronic device, and a storage medium. Background Art

[0002] As one of the largest market segments of analog chips, power chips are widely used in mobile phones, consumer electronics, industrial control, automotive electronics, artificial intelligence and other fields. With the continuous upgrading of demand, integration, core digitization and intelligence have become the development trend of the new generation of power management chips. Digital power can effectively solve the problems of fragmented power demand, difficult reuse and low design efficiency.

[0003] Digital power SOC includes digital control system and analog circuit system. For a large-scale complex digital-analog hybrid SOC power chip design, the bottleneck of the design cycle lies in the verification of hybrid simulation. The current mainstream hybrid simulation methods vcs+xa and vcs+finesim are inefficient, simulation cases take months, and debugging is difficult. The structure is complex and can only guarantee digital-analog connectivity and basic functions, and cannot verify space requirements, which makes chip design have a greater risk. The core of digital power lies in the PID algorithm. The correctness of the PID algorithm determines the function and performance of the chip. To verify the correctness of the PID algorithm, it is necessary to introduce the peripheral power level buck circuit and build a complete closed feedback loop system. The current mainstream verification method of this algorithm is to use modelsim+matlab joint simulation, which can only perform simple scene verification on the PID+buck circuit, but it is difficult to achieve chip-level simulation. Because no matter whether it is joint simulation or hybrid simulation verification, the verification scene is relatively simple and the verification process is complicated. It is impossible to perform blind spot and large-scale random verification on the loop PID algorithm, which is bound to affect the chip verification quality.

[0004] Therefore, it is necessary to provide a new behavior-level modeling method to solve the above problems. Summary of the invention

[0005] The main purpose of this application is to provide a behavioral-level modeling method for analog circuits, an electronic device, and a storage medium, which can at least solve the problems of low verification efficiency, high complexity of the verification environment, and single test scenario of power chips in related technologies.

[0006] To achieve the above-mentioned objectives, the first aspect of the present application provides a behavioral-level modeling method for an analog circuit, the method comprising: obtaining an equivalent circuit of the analog circuit; analyzing a function expression of a target node in the equivalent circuit based on a circuit analysis model; wherein the function expression comprises a current expression and a voltage expression; and performing hardware language conversion on the function expression to obtain a target digital model of the analog circuit.

[0007] The second aspect of the present application provides an electronic device, comprising: a memory and a processor, wherein the processor is used to execute a computer program stored in the memory, and when the processor executes the computer program, it implements each step of the behavioral level modeling method of the analog circuit provided in the first aspect of the present application.

[0008] The third aspect of the present application provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, each step of the behavioral level modeling method of the analog circuit provided in the first aspect of the present application is implemented.

[0009] As can be seen from the above, according to the behavioral modeling method, electronic device and storage medium of the analog circuit provided by the present application, the equivalent circuit of the analog circuit is obtained; the function expression of the target node in the equivalent circuit is analyzed based on the circuit analysis model; wherein the function expression includes a current expression and a voltage expression; the function expression is converted into a hardware language to obtain the target digital model of the analog circuit. Through the implementation of the present application, the equivalent circuit of the analog circuit is analyzed to obtain the current expression and the voltage expression of the target node, and then the current expression and the voltage expression are converted into a hardware language to obtain the digital model of the analog circuit. Since the object analyzed during modeling is the equivalent circuit of the analog circuit, modeling an equivalent circuit can be applied to a variety of analog circuits, which is convenient for the reuse of the verification platform and use cases of the same power supply chip, reducing the development cycle of the verification platform and use cases, and at the same time, the PID algorithm verification module and the chip-level verification platform component can be reused to efficiently promote the chip verification cycle. In addition, by digitally modeling the analog circuit in the power supply chip, the chip verification environment can support the UVM digital verification platform, which is conducive to enriching the verification programming language and verification scenario, simplifying the configuration and debugging of the verification environment, and improving the efficiency of the use case regression. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0011] Figure 1 A basic flow chart of a behavioral level modeling method for analog circuits provided in one embodiment of the present application;

[0012] Figure 2 A schematic diagram of an equivalent circuit of a buck circuit provided in one embodiment of the present application;

[0013] Figure 3 A schematic diagram of converting a Simulink model into a Verilog model to generate a Comsim module provided in one embodiment of the present application;

[0014] Figure 4 A waveform diagram of a first output characteristic curve provided by an embodiment of the present application;

[0015] Figure 5 A simulink simulation circuit schematic diagram of a buck equivalent circuit provided in one embodiment of the present application;

[0016] Figure 6 A simulink simulation circuit schematic diagram of a PID+buck equivalent circuit provided in one embodiment of the present application;

[0017] Figure 7 A waveform diagram of a third output characteristic curve and a fourth output characteristic curve provided in an embodiment of the present application;

[0018] Figure 8 A schematic diagram of the structure of an electronic device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0019] In order to make the purpose, features, and advantages of the invention of this application more obvious and easy to understand, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0020] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0021] In order to solve the problems of low efficiency of PID algorithm verification and chip-level verification of power chips in related technologies, high complexity of verification platform and single test scenario, an embodiment of the present application provides a behavioral level modeling method for analog circuits, such as Figure 1 A basic flow chart of a behavioral modeling method for an analog circuit provided in this embodiment, the behavioral modeling method for an analog circuit includes the following steps:

[0022] Step 101: Obtain an equivalent circuit of an analog circuit.

[0023] Specifically, in this embodiment, the circuit characteristics of the analog circuit can be analyzed, for example, according to the series-parallel relationship of the resistance, capacitance and reactance in the analog circuit, and the simplest circuit diagram can be drawn to obtain the equivalent circuit diagram of the analog circuit. Taking the analog circuit as a buck circuit as an example, the equivalent circuit diagram of the buck circuit is as follows: Figure 2 As shown in Figure 1, this equivalent circuit can be applied to various buck circuits or common RCL circuits.

[0024] Step 102: Analyze the function expression of the target node in the equivalent circuit based on the circuit analysis model.

[0025] Specifically, in this embodiment, after the equivalent circuit of the analog circuit is obtained, the current expression and the voltage expression of the target node in the equivalent circuit may be analyzed based on the circuit analysis model to obtain the function expression of the target node.

[0026] In some implementations of this embodiment, the analog circuit includes a buck circuit, and the function expression of the target node in the equivalent circuit is analyzed based on the circuit analysis model, including: analyzing the function expression of each node in the equivalent circuit based on the circuit analysis model; discretizing each function expression and jointly solving it to obtain the expression of the inductor current, the expression of the capacitor current and the expression of the output voltage in the equivalent circuit respectively.

[0027] Specifically, in this embodiment, in order to obtain the function expression of the target node, the mathematical expressions of the voltage and current of different nodes in the buck equivalent circuit can be analyzed based on the circuit analysis model, which includes the three major theories of circuit analysis, namely, the superposition law, Kirchhoff's law and the homogeneous law, and then the equation is established and solved according to the node relationship to obtain the function of the inductor current over time and the function of the capacitor current over time. In the process of joint solution, the idea of ​​calculus can be used to discretize and sum the voltage and current of the node, that is, to convert the integral into a differential and sum it, and finally obtain the current relationship between time t-1 and time t. After obtaining the capacitor current and the inductor current, the expression of the output voltage can be derived.

[0028] by Figure 2 Taking the equivalent circuit diagram of as an example, the analysis process of the function expression of the target node is explained. Figure 2 In the equivalent circuit, Vdc, PWM and RL are variables, and Vdc and RL should remain unchanged once they are given. Therefore, when analyzing the input-output relationship under the stable circuit state, only one input variable PWM needs to be considered, and the target is the change of the output voltage Vout. Therefore, the main line of modeling is to find the functional relationship between Vout and PWM: Vout = F(PWM). According to the circuit analysis theory, we can get:

[0029] Vout(t)=Ires(t)*RL

[0030] =(Iind(t)-Icap(t))*RL (1)

[0031]

[0032] According to the principle of circuit analysis, the following equation can be obtained:

[0033]

[0034] And V 1 =VDD, V 0 =VSS; so:

[0035]

[0036] For the convenience of description, Vin is used here to represent PWM.

[0037] Vin=(!PWM)?VDD:VSS;

[0038] Therefore: V 4 (t) = Vin - Iind (t) * (r + R p_ind ) (4)

[0039] Substituting equation (4) into equation (3) yields:

[0040]

[0041] Substituting into formula 1 and 2, we can calculate:

[0042]

[0043] Wherein, Vout(t) represents the output voltage, Ires(t) represents the current flowing through the resistor RL, Iind(t) represents the current flowing through the inductor L, Icap(t) represents the current flowing through the capacitor C, RL represents the resistance of the resistor RL, Ucap(t) represents the voltage across the capacitor C, V(t) represents the voltage across the resistor Rp_cap, C represents the capacitance of the capacitor C, R p_cap is the resistance of resistor Rp_cap, L is the inductance of inductor L, Uind(t) is the voltage across inductor L, V 4 (t) is the node voltage between the inductor L and the resistor Rp_ind, V 3 is the node voltage between resistor Rp_ind and resistor r2, V 2 is the node voltage between the resistor r1 and the switch tube Q1, V 1 is the node voltage between resistor r1 and the voltage source, V 0is the node voltage between the voltage source and the ground, r is the resistance value of resistor r1 or resistor r2, Sum_Iind(t) represents the integral The differential form of is used to represent the sum of the inductor current at time t, Sum_Iind(t-1) is used to represent the sum of the inductor current at time t-1, and Sum_Vdel(t) is The differential form is used to represent the sum of the voltages at time t, Sum_Vdel(t-1) represents the sum of the voltages at time t-1, DT is the infinitesimal in the differential expression, which is equivalent to the sampling interval in Verilog, ChargeA is the charge of the capacitor, and PWM is the control signal output by the PID algorithm for controlling the on and off of the switch tube. In this embodiment, according to circuit analysis theory such as the basic laws of KCL and KVL, the current and voltage expressions of each node are analyzed, the relationship between the expressions is established, and the joint solution is performed to obtain the current expression and voltage expression at the output node in the equivalent circuit, such as the expression of the inductor current, the capacitor current and the output voltage, wherein the integral idea is first used to introduce the function of the voltage and current to time, and then the differential idea is used to discretize the continuous signal to obtain the function expression that conforms to the characteristics of the hardware language. By discretizing the node voltages and currents of the circuit, the time domain integration of the current is converted into the cumulative summation of time domain segments, which solves the problem that the Verilog language does not support the modeling and simulation of analog voltage and analog current. At the same time, the discretization of current and voltage enables the VCS simulator to use voltage and current as data types supported by Verilog.

[0044] Step 103: convert the function expression into hardware language to obtain a target digital model of the analog circuit.

[0045] In some implementations of the present embodiment, the function expression is converted into a hardware language to obtain a target digital model of the analog circuit, including: converting the expression of the inductor current, the expression of the capacitor current and the expression of the output voltage into Verilog language to obtain a first digital model, a second digital model and a third digital model respectively; generating a target digital model of the analog circuit according to the first digital model, the second digital model and the third digital model.

[0046] Specifically, in this embodiment, after obtaining a function expression that conforms to the characteristics of the hardware language, the function expression can be mapped to a preset hardware language, thereby completing digital modeling. Figure 2 Taking the expressions of the inductor current, capacitor current and output voltage obtained from the equivalent circuit as an example, by converting the expression of the inductor current into Verilog language, the expression of the inductor current is:

[0047]

[0048] Then the expression of the inductor current can be described as: @(posedge CLK)I_ind<=((DT*(Vin-Vout)+(IND*I_ind)) / (IND+DT*Res1)); the expression of the capacitor current is converted into Verilog language, and the expression of the capacitor current is:

[0049]

[0050] The expression of capacitor current can be described as: @(posedge CLK)I_cap<=(((I_ind*RESL*CAP)-ChargeA) / (((RESL+Res2)*CAP)+DT)); the expression of capacitor charge can also be converted into Verilog language, and the corresponding description is: @(negedge CLK)ChargeA<=ChargeA+DT*I_cap; the actual simulation starts from time 0, so the initial values ​​of capacitance, inductance and charge are 0; and the output voltage expression can have many forms. When the output voltage expression is Vout(t)=Ucap(t)+V(t), it can be described as: Vout=ChargeA / CAP+I_cap*Res2.

[0051] Furthermore, in some implementations of the present embodiment, a target digital model of an analog circuit is generated based on the first digital model, the second digital model and the third digital model, including: performing bit type conversion on the third digital model to obtain a fourth digital model; and generating a target digital model of the analog circuit based on the first digital model, the second digital model and the fourth digital model.

[0052] Specifically, in this embodiment, since the output of the equivalent circuit is a real voltage, in order to facilitate the connection of the digital-analog interface, the real type can be converted to the bit type through real2bit, and the conversion of the output voltage vout real type to the bit type can be described as: EAP = $realtobits (Vout); then, each digital model after the Verilog hardware design language conversion can be used as the Verilog model of the analog circuit. After the Verilog model is completed, for similar buck circuits or common RCL circuits, after the circuit is equivalent, only R, L, and C in the Verilog model need to be replaced to realize its Verilog modeling.

[0053] In some other implementations of the present embodiment, the function expression is converted into a hardware language to obtain a target digital model of the analog circuit, including: converting the function expression into a hardware language to obtain an initial digital model of the analog circuit; simulating the initial digital model to obtain a simulation result; if it is determined according to the simulation result that the initial digital model meets preset modeling conditions, then the initial digital model is determined as the target digital model of the analog circuit.

[0054] Specifically, in this embodiment, in order to ensure that the Verilog model obtained by modeling can correctly express the characteristics of the analog circuit, the initial digital model obtained can also be simulated and verified to determine whether the initial digital model meets the modeling conditions such as accuracy and stability based on the simulation results. If so, the initial digital model is determined as the target digital model of the analog circuit.

[0055] Furthermore, in some implementations of the present embodiment, the initial digital model is simulated to obtain simulation results, including: constructing a first simulation circuit in a Simulink simulation environment based on the initial digital model; performing Simulink conversion on the first simulation circuit to obtain a Comsim module; and performing digital simulation on the Comsim module to obtain a first output characteristic curve of the first simulation circuit.

[0056] Furthermore, in some implementations of the present embodiment, the initial digital model is determined as the target digital model of the analog circuit, including: constructing a second simulation circuit in a simulink simulation environment based on the equivalent circuit; obtaining a second output characteristic curve generated by a target oscilloscope in the second simulation circuit; if the similarity between the first output characteristic curve and the second output characteristic curve is greater than a preset threshold, determining the initial digital model as the target digital model of the analog circuit.

[0057] Specifically, when the Verilog model of the analog circuit is functionally verified, the accuracy of the model function can be judged by comparing the Vout output curve characteristics of the analog circuit and the Verilog model. Usually, the analog circuit selects SPICE simulation, and the Verilog model selects VCS simulation. In order to make the verification process more intuitive, this embodiment selects MATLAB as the simulation tool, because MATLAB supports joint simulation and can convert the Verilog model into a Comsim block. At this time, the analog circuit and the Comsim block can select the same stimulus source and waveform file, and can perform simulation in the same simulation environment, and the output characteristic curve comparison is clearer. The steps to generate the comsim block of the verilog model are as follows: start matlab and call modelsim in the command window; set the HDL execution path; add the RTL that needs to be converted into the matlab module; compile the added RTL and correct the compilation parameters; specify the module name and simulation parameters for generating cosimulation; set all port types; set the clock cycle, reset duration, reset effective value and simulation unit, etc.; set the simulink simulator starting point; after completion, compile_hdl_design.m and launch_hdl_simulator.m and comsim modules will be generated, as shown in the box Figure 3 As shown. Build the simulink simulation environment for the generated comsim module, that is, Figure 3 Build a simulink simulation environment, add the same pwm signal generator to the input port for simulation, and get the vout output characteristic curve. The specific output characteristic curve is as follows Figure 4 At the same time, the simulation circuit schematic diagram of the equivalent circuit of the analog circuit is constructed in the simulink simulation environment, such as Figure 5 As shown, in the simulation circuit schematic diagram, multiple oscilloscopes are provided to obtain the voltage and current of each node. By obtaining the output characteristic curve generated by the oscilloscope at the output node, the real output characteristic curve of the analog circuit can be obtained, and the similarity between the output characteristic curve and the output characteristic curve simulated by the comsim module is judged. If the similarity is greater than the preset threshold, it means that the accuracy and reliability of the initial digital model are high, and the modeling conditions are met. The initial digital model can be determined as the target digital model of the analog circuit.

[0058] Furthermore, in some other implementations of the present embodiment, the initial digital model is simulated to obtain simulation results, including: constructing a first simulation circuit in a Simulink simulation environment based on the initial digital model; performing Simulink conversion on the first simulation circuit to obtain a Comsim module; constructing a third simulation circuit in a Simulink simulation environment based on the Comsim module and a preset loop control chip; and performing digital simulation on the third simulation circuit to obtain a third output characteristic curve of the third simulation circuit.

[0059] Furthermore, in some other implementations of the present embodiment, the initial digital model is determined as the target digital model of the analog circuit, including: constructing a second simulation circuit in a Simulink simulation environment based on the equivalent circuit; constructing a fourth simulation circuit in a Simulink simulation environment based on the second simulation circuit and the loop control chip; performing digital simulation on the fourth simulation circuit to obtain a fourth output characteristic curve of the fourth simulation circuit; if the similarity between the third output characteristic curve and the fourth output characteristic curve is greater than a preset threshold, determining the initial digital model as the target digital model of the analog circuit.

[0060] Specifically, in this embodiment, the accuracy of modeling can also be determined by comparing whether the closed-loop circuit characteristics of the analog circuit and the Verilog model under PID loop control are the same. Specifically, a Simulink simulation environment of the PID+Verilog model and a Simulink simulation environment of the equivalent circuit of the PID+analog circuit are set up. The simulation circuit diagram of the equivalent circuit of the PID+analog circuit in the Simulink simulation environment is as follows: Figure 6 As shown in Figure 2, the output characteristic curves of the two simulation circuits are obtained through simulation, such as Figure 7 As shown, Figure 7 Curve a in the figure is the output curve of the equivalent circuit of PID+analog circuit, and curve b is the output curve of PID+Verilog model. It can be seen from the figure that the analog circuit under PID loop control and the Verilog model are almost the same, which shows that the accuracy and reliability of the initial digital model are high and meet the modeling conditions. The initial digital model can be determined as the target digital model of the analog circuit.

[0061] In order to further reflect the effect of simulation efficiency after modeling the analog circuit, a UVM verification environment of PID RTL code + Verilog model can be built to obtain the simulation waveform of voltage conversion under typical switching frequency. At the same time, a VCS + XA digital-analog mixed simulation environment of PID netlist + SPICE netlist can be built to obtain the simulation waveform of voltage conversion under typical switching frequency. By comparing the structural complexity, excitation space size and debugging difficulty of the two simulation platforms, the superiority of simulation efficiency after modeling can be reflected.

[0062] In addition, by comparing the complexity, variability, debugging complexity, and simulation time of the same use case between different verification platform structures, such as the VCS pure digital simulation environment and the VCS+XA hybrid simulation environment, the necessity of modeling in chip verification can be explained. The following is the process of building and simulating the two verification platforms:

[0063] Among them, the VCS+UVM pure digital environment is built. According to the general verification environment process, the clock, reset, and Verilog models can be instantiated at the top level of the system. Real2bit is used to convert real numbers to bit types to facilitate digital-analog interface connection. The design RTL and simulation environment filelist file list are created. Different use case simulations can be realized by specifying the compilation source code, compiler, and compilation options through the makefile. The entire simulation takes 8 minutes.

[0064] To build a vcs+xa mixed digital-analog simulation environment, it is necessary to add the corresponding initialization vcsAD.init file to the VCS script file based on the vcs pure digital environment. In the AD.init file, it is necessary to specify the xa software through choose xa-hspice test.sp-c xa.cmd-o xa_mixsim / xa, and specify the spice module name and instance path and port matching method to be mixed. Call the a2d and d2a commands to complete the conversion of the digital-analog interface direction. The commands have different parameters for setting power supply, signal rise and fall time, voltage threshold, delay, conversion voltage and other characteristics. In the vcsAD.init file, call the initialization resistor rmapAD.init file. Since the conversion between digital and analog signals is based on the drive strength of Verilog, resistors of different resistance values ​​are used for equivalent. After completing the XA simulation environment, specify the sp script file in the XA environment in the vcsAD.init file. The sp file defines the working environment of the chip, such as process, power supply voltage, temperature, simulation accuracy, waveform format, transistor-level netlist, etc. In the vcsAD.init file, set the cmd file to configure the XA tool, which is mainly used to set the simulation speed, number of CPUs, logic level, voltage-to-logic conversion threshold, print information, etc. After the digital-analog platform is built, the same use case can only be simulated for 20us per day under the same resources.

[0065] Therefore, the behavioral modeling method of the analog circuit in the digital power chip provided by this embodiment, by performing Verilog behavioral modeling on the analog circuit, makes the chip-level verification platform simple in structure, efficient in simulation and highly reusable, and effectively solves the problems of poor reusability, difficult debugging, complex structure and poor controllability of the traditional digital-analog hybrid simulation platform or joint simulation platform. After modeling, the test stimulus is simple to generate, the test scenarios are diverse, the module and system verification platform structure is unified, and the debugging analysis is efficient and convenient, which greatly shortens the verification cycle of the system and PID algorithm module, reduces the verification risk, and improves the verification efficiency. In addition, the behavioral modeling method of the analog circuit in the digital power chip of this embodiment solves the timeliness problem of the development cycle of the digital power chip, which is conducive to the efficient discovery of the defects of the PID algorithm in the early stage and the effective solution of the recurrence of the return chip fault in the later stage. The modeling of the analog circuit introduces a high-speed clock, discretizes the node voltage and current of the circuit, and converts the time domain integral of the current into the cumulative summation of the time domain segment, which solves the problem that the Verilog language does not support the modeling and simulation difficulties of the analog voltage and current. At the same time, the discretization of current and voltage enables the VCS simulator to use voltage and current as data types supported by Verilog.

[0066] Figure 8 An electronic device provided in an embodiment of the present application can be used to implement the behavioral modeling method of the analog circuit in the aforementioned embodiment, mainly comprising:

[0067] The memory 801, the processor 802, and the computer program 803 stored in the memory 801 and executable on the processor 802, the memory 801 and the processor 802 are connected by communication. When the processor 802 executes the computer program 803, the method of the aforementioned embodiment is implemented. The number of processors may be one or more.

[0068] The memory 801 may be a high-speed random access memory (RAM) memory, or a non-volatile memory, such as a disk memory. The memory 801 is used to store executable program codes, and the processor 802 is coupled to the memory 801 .

[0069] Furthermore, the embodiment of the present application also provides a computer-readable storage medium, which may be disposed in the above-mentioned electronic device. The computer-readable storage medium may be the above-mentioned Figure 8 Memory in the illustrated embodiment.

[0070] The computer readable storage medium stores a computer program, and when the program is executed by the processor, the behavioral modeling method of the analog circuit in the aforementioned embodiment is implemented. Furthermore, the computer storable medium can also be a U disk, a mobile hard disk, a read-only memory (ROM), a RAM, a magnetic disk or an optical disk, and other media that can store program codes.

[0071] It should be noted that, for the above-mentioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described action sequence, because according to the present application, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0072] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0073] The above is a description of the behavioral-level modeling method, electronic device, and storage medium for analog circuits provided in this application. For technicians in this field, according to the ideas of the embodiments of this application, there may be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on this application.

Claims

1. A behavioral level modeling method for analog circuits, characterized in that: include: Obtaining an equivalent circuit of the analog circuit; Analyzing the function expression of the target node in the equivalent circuit based on the circuit analysis model; wherein the function expression includes a current expression and a voltage expression; The function expression is converted into a hardware language to obtain a target digital model of the analog circuit.

2. The behavioral level modeling method according to claim 1, characterized in that: The analog circuit includes a buck circuit, and the circuit analysis model-based analysis of a function expression of a target node in the equivalent circuit includes: Analyzing the function expression of each node in the equivalent circuit based on the circuit analysis model; The function expressions are discretized and jointly solved to obtain expressions of the inductor current, the capacitor current and the output voltage in the equivalent circuit.

3. The behavioral level modeling method according to claim 2, characterized in that: The step of converting the function expression into a hardware language to obtain a target digital model of the analog circuit includes: Convert the expression of the inductor current, the expression of the capacitor current and the expression of the output voltage into Verilog language respectively, and obtain a first digital model, a second digital model and a third digital model respectively; A target digital model of the analog circuit is generated according to the first digital model, the second digital model, and the third digital model.

4. The behavioral level modeling method according to claim 3, characterized in that: Generating a target digital model of the analog circuit according to the first digital model, the second digital model and the third digital model comprises: Performing bit conversion on the third digital model to obtain a fourth digital model; A target digital model of the analog circuit is generated according to the first digital model, the second digital model, and the fourth digital model.

5. The behavioral level modeling method according to claim 1, characterized in that: The step of converting the function expression into a hardware language to obtain a target digital model of the analog circuit includes: Converting the function expression into a hardware language to obtain an initial digital model of the analog circuit; Simulating the initial digital model to obtain simulation results; If it is determined according to the simulation result that the initial digital model meets the preset modeling condition, the initial digital model is determined as the target digital model of the analog circuit.

6. The behavioral level modeling method according to claim 5, characterized in that: The simulating the initial digital model to obtain a simulation result includes: According to the initial digital model, construct a first simulation circuit in a simulink simulation environment; Performing simulink conversion on the first simulation circuit to obtain a comsim module; The comsim module is digitally simulated to obtain a first output characteristic curve of the first simulation circuit.

7. The behavioral level modeling method according to claim 6, characterized in that: The step of determining the initial digital model as a target digital model of the analog circuit comprises: According to the equivalent circuit, construct a second simulation circuit in the simulink simulation environment; Acquire a second output characteristic curve generated by a target oscilloscope in the second simulation circuit; If the similarity between the first output characteristic curve and the second output characteristic curve is greater than a preset threshold, the initial digital model is determined as the target digital model of the analog circuit.

8. The behavioral level modeling method according to claim 5, characterized in that: The simulating the initial digital model to obtain a simulation result includes: According to the initial digital model, construct a first simulation circuit in a simulink simulation environment; Performing simulink conversion on the first simulation circuit to obtain a comsim module; According to the comsim module and the preset loop control chip, a third simulation circuit is constructed in the simulink simulation environment; Digital simulation is performed on the third simulation circuit to obtain a third output characteristic curve of the third simulation circuit.

9. The behavioral level modeling method according to claim 8, characterized in that: The step of determining the initial digital model as a target digital model of the analog circuit comprises: According to the equivalent circuit, construct a second simulation circuit in the simulink simulation environment; According to the second simulation circuit and the loop control chip, construct a fourth simulation circuit in a simulink simulation environment; Performing digital simulation on the fourth simulation circuit to obtain a fourth output characteristic curve of the fourth simulation circuit; If the similarity between the third output characteristic curve and the fourth output characteristic curve is greater than a preset threshold, the initial digital model is determined as the target digital model of the analog circuit.

10. An electronic device, characterized in that: The device comprises a memory and a processor, wherein: The processor is used to execute the computer program stored in the memory; When the processor executes the computer program, the processor implements the steps of the behavioral modeling method for analog circuits according to any one of claims 1 to 9.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps in the behavioral level modeling method of analog circuits as claimed in any one of claims 1 to 9 are implemented.

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