Automatic layout generation method

Abstract

The invention discloses an automatic layout generation method, which comprises the following steps of: firstly, aiming at a process library PDK specified by an analog circuit or a digital-analog hybrid circuit, generating a minimum analog unit ACell of each circuit component required by automatic layout by using a unit library compiler AellGen; secondly, replacing each parameterized unit Pcell in a schematic diagram established by using the parameterized units Pcell with a corresponding minimum simulation unit ACell, generating a corresponding circuit net list based on the currently obtained schematic diagram, and putting the ACell applied by the schematic diagram in the same schema to extract a GDS file; and finally, based on the circuit netlist, the GDS and the minimum simulation unit of each circuit component required by automatic layout of the circuit, performing final layout generation by using an automatic layout and wiring tool (pnr). The layout design method has the advantages that the layout design method can be used for layout design of an analog circuit or a digital-analog hybrid circuit, the layout area is small, manual intervention is not needed during layout design of the analog circuit or the digital-analog hybrid circuit, and the efficiency is high.

Description

Technical Field

[0001] The invention relates to a layout generation method, in particular to an automatic layout generation method. Background Art

[0002] In integrated circuit (IC) design, layout is one of the key steps to convert circuit design into physical layer implementation. With the rapid development of semiconductor technology, the complexity of IC design continues to increase, and the traditional manual layout design method can no longer meet the needs of modern IC design. In order to meet the needs of modern IC design, some automatic layout generation methods have been developed, which aim to improve design efficiency, shorten design cycle, and achieve the quality of manual layout.

[0003] There are two main existing automatic layout generation methods. The first automatic layout generation method is mainly based on Synopsys's ICC2 automatic layout and routing tool of Cadence Virtuoso Layout XL, which is specially used for analog and mixed analog and digital circuit layout and routing. The second automatic layout generation method is based on Innovus, a digital design implementation tool provided by Cadence Design Systems, which is specially used for automatic layout and routing of digital circuit layout.

[0004] The first automatic layout generation method mainly includes the following steps when realizing automatic layout generation: first, according to the target circuit schematic, define the placement target (such as reducing the area, optimizing the wiring space, etc.), and select the automatic placement function, automatically arrange the circuit elements according to the design rules, and automatically place each circuit element (cell) on the layout according to the design rules and placement targets. Secondly, set the layout parameters (such as layout length, layout width, etc.) and define the wiring rules (such as line width, line spacing, etc.); finally, according to the set layout parameters and the defined wiring rules, use the automatic wiring function to automatically generate the wiring path to connect the circuit elements. However, the first automatic layout generation method has the following problems: 1. For complex designs, inappropriate routing rule definitions may cause problems in subsequent steps, requiring additional manual inspection and correction; 2. Automatic placement of circuit components may not fully meet all design requirements, requiring further manual adjustment; 3. In high-density designs, automatic routing may cause signal congestion or poor routing paths, which cannot meet the accuracy and performance requirements of manual routing, and may require further manual optimization; 4. It simply implements layout and routing, and does not achieve timing optimization, power consumption optimization, and chip energy efficiency optimization, and cannot automatically optimize the layout area, which also requires further manual optimization. Therefore, the first automatic layout generation method often requires designers to perform manual optimization and adjustment in actual use to overcome the limitations of the automation function. The workload of manual adjustment and optimization is large and the efficiency is low. In general, the design of the digital-analog mixed circuit layout using the first automatic layout generation method still requires a lot of manual intervention.

[0005] The second automatic layout generation method mainly includes the following steps when realizing automatic layout generation: first, extract and generate a netlist from the schematic diagram of the target circuit, optimize according to the netlist, including area optimization, speed optimization, power consumption optimization, etc., then place the macrocells (such as memory, I / O cells) in the target circuit to the predefined position of the chip, then arrange standard cells (such as logic gates) on the chip according to design requirements, and finally perform global automatic routing to connect various macrocells and standard cells to ensure that signals can be transmitted, thereby realizing automatic layout generation. Although the second automatic layout generation method can provide fast layout and routing capabilities, support efficient processing of complex designs, and can achieve performance, power consumption and area optimization during the generation process, in actual use, it only needs to extract the netlist information in the schematic diagram of the target circuit, and can realize automatic layout layout and routing according to the netlist information, and the workload of manual adjustment and optimization is small and the efficiency is high, but it can only be applied to the automatic layout and routing of digital circuits, and cannot be used for the layout design of analog circuits and mixed digital and analog circuits. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a layout design method that can be used for analog circuits and mixed analog and digital circuits, and does not require manual intervention when performing layout design on analog circuits and mixed analog and digital circuits, and has a high efficiency automatic layout generation method.

[0007] The technical solution adopted by the present invention to solve the above technical problem is: an automatic layout generation method, comprising the following steps:

[0008] Step 1: For the process library PDK specified for the analog circuit or the mixed-analog circuit, first use the cell library compiler AcellGen to generate the minimum analog cell Acell of each circuit component required for the automatic layout of the analog circuit or the mixed-analog circuit;

[0009] Step 2: First, replace each parameterized unit Pcell in the schematic diagram of the analog circuit or the mixed analog circuit constructed by using the parameterized unit Pcell with the corresponding minimum analog unit Acell, and then generate the corresponding circuit netlist Netlist based on the currently obtained analog circuit or the mixed analog circuit schematic diagram. The circuit netlist Netlist contains the parameter information of each circuit component in the analog circuit or the mixed analog circuit and the connection relationship between each circuit component, and puts the minimum analog unit Acell used in the analog circuit or the mixed analog circuit schematic diagram in the same schematic to extract the GDS file. The GDS file records every detail of the chip layout, including the graphic shapes at different levels and the connection methods of circuit components;

[0010] Step 3: Based on the circuit netlist, GDS file and the minimum analog unit Acell of each circuit component required for the automatic layout of the analog circuit or the mixed analog circuit, use the automatic layout and routing tool pnr to generate the layout of the analog circuit or the mixed analog circuit.

[0011] Furthermore, the automatic placement and routing tool is a related script and calls the Innovus digital circuit automatic placement and routing tool of Cadence.

[0012] Compared with the prior art, the advantage of the present invention is that first, for the process library PDK specified for the analog circuit or the digital-analog mixed circuit, the cell library compiler AcellGen is used to generate the minimum analog unit Acell of the circuit components required for the automatic layout of the analog circuit or the digital-analog mixed circuit, so as to facilitate the subsequent use of automatic layout and routing tools to realize the automatic layout and routing of the analog circuit or the digital-analog mixed circuit. The minimum analog unit Acell is generated according to the process library PDK provided by the chip process manufacturer, and fully complies with the design rules of the chip process manufacturer, ensuring that the analog circuit or the digital-analog mixed circuit that is subsequently laid out and routed fully meets the manufacturing requirements of the process manufacturer; then the automatic layout and routing tool is used to implement the automatic layout and routing of the analog circuit or the digital-analog mixed circuit. Each parameterized unit Pcell in the schematic diagram of the analog circuit or mixed analog circuit constructed by the parameterized unit Pcell (the parameterized unit Pcell is used to represent those circuit components with variable parameters, such as transistors, resistors, capacitors, etc.) is replaced with the corresponding minimum analog unit Acell, and a corresponding circuit netlist is generated. The circuit netlist contains the parameter information of each circuit component in the analog circuit or mixed analog circuit and the connection relationship between each circuit component, and the minimum analog unit Acell used in the analog circuit or mixed analog circuit schematic diagram is placed in the same schematic to extract the GDS file. At this time, the root The information parameters provided by the circuit netlist are used as input for subsequent automatic layout and routing tools to guide the placement and routing of various circuit components. This can avoid problems in subsequent steps caused by inappropriate routing rule definitions in the automatic layout and routing tools, thereby reducing the manpower required for subsequent adjustments. Finally, based on the circuit netlist, GDS file, and the smallest analog unit Acell of each circuit component required for the automatic layout of analog circuits or mixed analog circuits, an automatic layout and routing tool (such as Cadence's Innovus digital circuit automatic layout and routing tool) is used to generate the final layout. The Innovus digital circuit automatic layout and routing tool The automatic layout and routing of the layout that can only generate digital circuits, the present invention combines it with Acell to realize the layout automation of analog circuits and mixed analog and digital circuits. The automatic layout and routing tool integrates an efficient algorithm, which can continuously optimize the layout during the generation process, accelerate the layout and routing process, and achieve the best pipeline layout, line length, utilization and PPA (performance, power consumption, area), so that the ideal analog circuit or mixed analog and digital circuit layout can be obtained without human intervention. Therefore, the present invention can be used for the layout design of analog circuits or mixed analog and digital circuits, and no human intervention is required when performing layout design on analog circuits or mixed analog and digital circuits, and the efficiency is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A flowchart of an automatic layout generation method of the present invention;

[0014] Figure 2Acell: Schematic diagram based on Pcell + different transistor parameters;

[0015] Figure 3 It is a schematic diagram of splicing multiple Acells;

[0016] Figure 4 Acell schematic diagram of NMOS;

[0017] Figure 5 This is the schematic diagram of the target secondary op amp;

[0018] Figure 6 This is a schematic diagram of the Acell layout;

[0019] Figure 7 Generate the layout for the Acell-based automatic layout (secondary op amp circuit). DETAILED DESCRIPTION

[0020] The present invention is further described in detail below with reference to the accompanying drawings.

[0021] Embodiment 1: Figure 1 As shown, an automatic layout generation method comprises the following steps:

[0022] Step 1: For the process library PDK specified for the analog circuit or the mixed-analog circuit, first use the cell library compiler AcellGen to generate the minimum analog cell Acell of each circuit component required for the automatic layout of the analog circuit or the mixed-analog circuit;

[0023] Step 2: First, replace each parameterized unit Pcell in the schematic diagram of the analog circuit or mixed analog circuit constructed using the parameterized unit Pcell for representing circuit components with variable parameters (such as transistors, resistors, capacitors, etc.) with the corresponding minimum analog unit Acell, and then generate the corresponding circuit netlist Netlist based on the currently obtained analog circuit or mixed analog circuit schematic diagram. The circuit netlist Netlist contains the parameter information of each circuit component in the analog circuit or mixed analog circuit and the connection relationship between each circuit component. And put the Acell used in the analog circuit or mixed analog circuit schematic diagram in the same schematic to extract the GDS file. The GDS file records every detail of the chip layout, including the graphic shapes at different levels and the connection methods of circuit components;

[0024] Step 3: Based on the circuit netlist, GDS file and the minimum analog unit Acell of each circuit component required for the automatic layout of the analog circuit or mixed analog circuit, use the automatic layout and routing tool (pnr) to call the Innovus digital circuit automatic layout and routing tool and related scripts to generate the layout of the analog circuit or mixed analog circuit.

[0025] In this embodiment, first, for the process library PDK specified for the analog circuit or the mixed analog circuit, the cell library compiler AcellGen is used to generate the minimum analog cell Acell of the circuit components required for the automatic layout of the analog circuit or the mixed analog circuit, so as to facilitate the subsequent use of the automatic layout and routing tool to realize the automatic layout and routing of the analog circuit or the mixed analog circuit. The minimum analog cell Acell is generated according to the process library PDK provided by the chip process manufacturer, and fully complies with the design rules of the chip process manufacturer, ensuring that the analog circuit or the mixed analog circuit subsequently laid out and routed fully meets the manufacturing requirements of the process manufacturer; then, each parameterized cell Pcell in the schematic diagram of the analog circuit or the mixed analog circuit constructed using the parameterized cell Pcell (the parameterized cell Pcell is used to represent those circuit components with variable parameters, such as transistors, resistors, capacitors, etc.) is replaced with the corresponding minimum analog cell Acell, and a corresponding circuit netlist is generated, which contains the parameter information of each circuit component in the analog circuit or the mixed analog circuit and the connection relationship between each circuit component. At this time, the information parameters provided by the circuit netlist are used as the subsequent automatic The automatic layout and routing tool is input to guide the placement and routing of each circuit component, so as to avoid problems in subsequent steps caused by inappropriate routing rule definitions in the automatic layout and routing tool, thereby reducing the manpower required for subsequent adjustments; the Acell used in the circuit schematic is placed in the same schematic to extract the GDS file. The GDS file records every detail of the chip layout, including the graphic shapes at different levels, the connection methods of circuit components, etc., to ensure that the final layout details are accurate; finally, based on the circuit netlist, GDS file, and the minimum analog unit Acell of each circuit component required for the automatic layout of analog circuits or mixed analog circuits, the automatic layout and routing tool (pnr) is used to generate the final layout. The automatic layout and routing tool integrates efficient algorithms and calls the Innovus digital circuit automatic layout and routing tool and related scripts during operation. It can continuously optimize the layout during the generation process, accelerate the layout and routing process, and achieve the best pipeline layout, line length, utilization and PPA (performance, power consumption, area), so that the ideal analog circuit or mixed analog circuit layout can be obtained without manual intervention.

[0026] Embodiment 2: This embodiment is basically the same as Embodiment 1, except that: in this embodiment, the automatic placement and routing tool is Cadence's Innovus digital circuit automatic placement and routing tool. Innovus provides full-process support from early layout planning to final sign-off to ensure that the design meets performance, power consumption and area requirements. It has high-performance algorithms to accelerate the placement and routing process, supports comprehensive optimization of area, timing and power consumption, and provides multi-mode and multi-corner analysis. Innovus also uses advanced global and detailed routing strategies, and can automatically fix problems such as timing violations in placement and routing.

[0027] In this embodiment, Cadence's Innovus digital circuit automatic layout and routing tool can only automatically layout and route digital circuits. We use Acell generated by AcellGen to enable analog circuits and mixed analog and digital circuits to be laid out and routed using Innovus. The present invention uses an automatic layout and routing tool (pnr) to call Innovus and use it together with related scripts to facilitate multiple runs to successfully verify the IC. The Innovus script can control steps from initial floor planning (Floorplanning) to detailed layout (Placement), clock tree synthesis (Clock Tree Synthesis, CTS), routing (Routing), timing analysis and optimization (Timing Analysis and Optimization) and power analysis and optimization (Power Analysis and Optimization), which greatly promotes performance improvement, timing consistency, compatibility, DRC results, power optimization, global routing, voltage drop impact, integrated environment, and automation and script support.

[0028] In order to verify the performance of the automatic layout generation method of the present invention, Figure 5 The secondary operational amplifier built with Pcell shown in the figure is used as the target circuit, and the method of the present invention is used to automatically generate the layout of the target circuit. We first use AcellGen to generate the corresponding Acell according to the PDK used by the target circuit and the circuit component parameters (such as MOS tube width and length), as shown in the figure. Figure 2 The figure shows a schematic diagram of one of the Acells. Figure 4 This is a schematic diagram of the Acell of NMOS; we will splice it later, the specific form is as follows Figure 3As shown. Then use the generated Acell to replace the Pcell in the circuit schematic, extract the Netlist information and put the Acell used in the circuit schematic in the same schematic to extract the GDS file. Finally, call the minimum analog unit Acell of each circuit component required for the circuit netlist, GDS file and circuit automatic layout, use the automatic layout and routing tool (pnr) to call the Innovus digital circuit automatic layout and routing tool and related scripts to generate the circuit layout. The layout diagram is shown in Figure 6 , and finally generate the layout as Figure 7 As shown, its area is 30% smaller than that of the Pcell-based manual layout.

[0029] In integrated circuit design, manual layout drawing is not only time-consuming, but also prone to errors, especially design rule checking (DRC) and layout and circuit Figure 1In the present invention, since the minimum analog unit Acell is generated according to the process library PDK provided by the chip process manufacturer, it fully complies with the design rules of the chip process manufacturer, ensuring that the analog circuit or digital-analog mixed circuit of the subsequent layout and routing fully meets the manufacturing requirements of the process factory, and the designer can focus more on the innovation and optimization of the design, rather than spending a lot of time on tedious manual drawing and error checking. This not only improves the accuracy and reliability of the design of analog circuits or digital-analog mixed circuits, but also shortens the design cycle and speeds up the time to market for the product. In the present invention, the extracted circuit netlist information can be used to ensure that the design follows the set rules and optimization goals, which has significant advantages over manual hand drawing. The automatic layout and routing tool quickly completes the layout and routing through high-performance algorithms, optimizes the design performance, and comprehensively considers the area, timing and power consumption to achieve the best design results. Ensure the reliability of the design under different processes and environments, and improve the signal integrity through advanced routing technology. In contrast, manual hand drawing may take longer, be less efficient, and be prone to errors. The automatic layout and routing tool pnr automatic repair function can solve complex timing problems, while manual hand drawing requires designers to constantly check and correct. In addition, it can be seamlessly integrated with other Cadence tools, further improving the design efficiency, while manual hand-drawing lacks this integration advantage. In general, it greatly surpasses the traditional manual hand-drawing method in terms of efficiency, accuracy and optimization capability. In the present invention, the smallest analog unit Acell of circuit components is introduced, and automatic layout layout and routing can be realized on analog circuits or mixed analog circuits, breaking through the defect that Innovus, a digital design implementation tool provided by Cadence Design Systems, can only realize the automatic layout layout and routing of digital circuit layouts, and can realize the automatic layout layout and routing of analog circuits or mixed analog circuits. Therefore, the present invention improves the accuracy of layout generation by directly extracting circuit netlist information during the layout generation process through these technical advantages. The generated Acell standard unit is used to realize the automatic layout and routing of analog circuits or mixed analog circuits using Innovus, breaking through the limitation that Innovus can only automatically generate digital circuit layouts, and in the generation process, the automatic layout and routing tool (pnr) will use high-performance algorithms to quickly complete the layout and routing, optimize the design performance, and comprehensively consider the area, timing and power consumption to achieve the best design results, which greatly reduces the subsequent required manpower. The automatic layout generation method of the present invention can realize the automatic and efficient generation of analog circuit and digital-analog mixed circuit layouts, and has broad application prospects in the field of automatic generation of analog circuits and digital-analog mixed circuits.

Claims

1. An automatic layout generation method, characterized in that The following steps are involved: Step 1: For the process library PDK specified for the analog circuit or the mixed-analog circuit, first use the cell library compiler AcellGen to generate the minimum analog cell Acell of each circuit component required for the automatic layout of the mixed-analog circuit; Step 2: First replace each parameterized unit Pcell in the schematic diagram of the analog circuit or mixed analog circuit constructed using the parameterized unit Pcell with the corresponding minimum analog unit Acell, and then generate the corresponding circuit netlist Netlist based on the current analog circuit or mixed analog circuit schematic diagram. The circuit netlist Netlist contains the parameter information of each circuit component in the analog circuit or mixed analog circuit and the connection relationship between each circuit component. And put the minimum analog unit Acell used in the analog circuit or mixed analog circuit schematic diagram in the same schematic to extract the GDS file. The GDS file records every detail of the chip layout, including the graphic shapes at different levels and the connection methods of circuit components; Step 3: Based on the circuit netlist, the minimum analog unit Acell of each circuit component required for the automatic layout of the analog circuit or the mixed analog circuit, and the GDS file, use the automatic layout and routing tool to generate the layout of the analog circuit or the mixed analog circuit.

2. According to claim 1, an automatic layout generation method is characterized in that The automatic placement and routing tool is a related script and calls the Innovus digital circuit automatic placement and routing tool of Cadence.

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