A method for placing flip-chip solder columns for superconducting quantum chips

Abstract

This invention discloses a method for placing flip-chip solder posts for superconducting quantum chips. This method, which belongs to the field of superconducting quantum chip design, meticulously processes the grids at the layout boundaries, within and around placed module units, and within already placed wires, marking special grid types and employing a secondary placement strategy. This method improves the flexibility and space utilization of flip-chip solder post placement while ensuring high efficiency and precision. This efficient, accurate, and flexible method can significantly improve chip design quality and production efficiency, filling the gap in existing commercial EDA tools, which currently lack fully automated flip-chip post placement capabilities.

Description

Technical Field

[0001] The present invention belongs to the field of superconducting quantum chip design, and more specifically, relates to a method for placing flip-chip solder columns of a superconducting quantum chip. Background Art

[0002] During the manufacturing process of superconducting quantum chips, flip-chip solder pillars are placed in unused areas to improve power integrity and the chip's mechanical strength. These solder pillars not only ensure reliable electrical connections within the chip but also enhance its mechanical strength and heat dissipation. Due to the complexity of chip design and its miniaturization, the number of flip-chip solder pillars is often enormous. The precision and efficiency of their placement directly impact the chip's overall performance and production costs. Therefore, efficiently and accurately placing flip-chip solder pillars in unused areas of the chip is a crucial factor influencing chip design and production quality.

[0003] During the placement of flip-chip solder pillars, there is a significant difference between traditional manual placement methods and modern electronic design automation (EDA) tool placement methods.

[0004] Manual placement of flip-chip solder pillars relies primarily on the designer's experience and manual operation. The advantage of this method is that the designer can flexibly adjust the placement of the flip-chip pillars based on actual conditions to meet complex and special layout requirements. However, manual placement also has many disadvantages:

[0005] 1. Slow speed: Since the columns need to be placed manually one by one, the manual placement speed is relatively slow. Especially when there are a large number of columns, the placement process is extremely time-consuming.

[0006] 2. Low precision: Manual operation inevitably involves human errors, and the placement of the inverted pillars may deviate, affecting the electrical performance and mechanical strength of the chip.

[0007] 3. Poor consistency: Different designers have different operating habits and experience levels, resulting in poor placement consistency. It is difficult to ensure that the inverted pillar placement of each chip is completely consistent.

[0008] 4. Low efficiency: Manual placement requires designers to repeatedly adjust and check, and the overall efficiency is low, which is difficult to meet the needs of large-scale production.

[0009] Compared with manual placement, the EDA tool placement method utilizes computer algorithms and automation technology to greatly improve the efficiency and accuracy of inverted pillar placement. Only the layout of the board and parameters such as the safe spacing for inverted pillar placement need to be input. The main advantages of the EDA tool placement method include:

[0010] 1. Fast speed: EDA tools can complete the placement of a large number of inverted pillars in a short period of time. Through algorithm optimization, the tool can accurately place thousands of inverted pillars in a few seconds.

[0011] 2. High precision: EDA tools can ensure the accurate position of each inverted column through precise calculation and control, significantly reducing human errors.

[0012] 3. Strong consistency: Automated tools can ensure that the placement results are completely consistent each time, without being affected by human factors, thereby improving the quality consistency of the chip.

[0013] 4. High flexibility: Modern EDA tools are highly flexible and can automatically adjust the placement of inverted pillars according to different layout requirements and design rules to meet the requirements of complex designs.

[0014] 5. Furthermore, EDA tools can incorporate various optimization strategies, such as using a gridding model to process the layout, flexibly adjusting the grid size, and marking the grid type, to improve the efficiency and rationality of inverted pillar placement. In contrast, manual placement often proves inadequate when faced with complex layouts and a large number of inverted pillars, making it difficult to ensure overall design quality and efficiency.

[0015] The technical challenges of flip-chip solder column placement primarily lie in balancing speed and accuracy, efficiently utilizing space within complex layouts, and ensuring flexibility and consistency in the placement process. Traditional manual placement methods, while flexible, are inefficient and subject to significant errors. While EDA tool placement methods are fast and highly accurate, they still present technical challenges when handling complex boundaries and irregular layouts. Summary of the Invention

[0016] In response to the above-mentioned defects or improvement needs of the prior art, the present invention provides a flip-chip solder column placement method for a superconducting quantum chip, which can improve the placement flexibility and space utilization while ensuring high efficiency and high precision.

[0017] To achieve the above objectives, according to a first aspect of the present invention, a method for placing flip-chip solder pillars of a superconducting quantum chip is provided, comprising:

[0018] S1, gridding the layout to be processed and marking the type of each grid according to its location;

[0019] Among them, the types of grids at the boundaries of the layout to be processed and the boundaries of the module units placed in the layout to be processed are all boundary grids; the types of grids at the boundaries of the placed lines and the grids within the placed module units in the layout to be processed are occupied grids; the types of grids whose distance from the boundary of the layout to be processed is less than the first safety distance and the types of grids whose distance from the boundary of the placed module units is not less than the second safety distance are all within the safety distance grids; the types of the remaining grids are all free grids;

[0020] S2, with the goal of maximizing the number of flip-chip solder columns that can be placed, scan each free grid G ​​row by row i , with G i As a reference, align the lower left corner vertex of the flip-chip solder column with G i After the lower left corner vertex of the flip-chip solder column is overlapped, it is determined whether the grids occupied by the flip-chip solder column are all free grids. If so, the corresponding horizontal placement can be performed, the placement position coordinates of the flip-chip solder column are recorded, and the grid type of the grid occupied by the flip-chip solder column is updated. If not, the grid type of the grid occupied by the flip-chip solder column is updated with G. i As a reference, align the lower left corner of the flip-chip solder column after tilting with G i After the lower left corner vertex of the grid coincides, it is determined whether the grids occupied by the tilted flip-chip solder column are all free grids. If so, the corresponding tilted placement can be performed, and the placement position coordinates and tilt angle of the flip-chip solder column are recorded, and the grid type of the grid occupied by the flip-chip solder column is determined. Otherwise, the grid is skipped until all free grids are scanned to obtain the coordinate set and tilt angle of the flip-chip solder column that can be placed.

[0021] According to a second aspect of the present invention, there is provided an electronic device comprising: a computer-readable storage medium and a processor;

[0022] The computer-readable storage medium is used to store executable instructions;

[0023] The processor is configured to read the executable instructions stored in the computer-readable storage medium and execute the method according to the first aspect.

[0024] According to a third aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to execute the method according to the first aspect.

[0025] According to a fourth aspect of the present invention, there is provided a computer program product comprising a computer program or instructions, which implement the method according to the first aspect when executed by a processor.

[0026] In general, the above technical solutions conceived by the present invention can achieve the following beneficial effects compared with the prior art:

[0027] This invention provides a method for placing flip-chip solder pillars for superconducting quantum chips. By meticulously processing the grids at the layout boundaries, within and around already placed module units, and within already placed wires, marking them as special grid types, and employing a secondary placement strategy, this method improves the flexibility and space utilization of flip-chip solder pillar placement while ensuring high efficiency and precision. This efficient, accurate, and flexible method significantly improves chip design quality and production efficiency, filling the gap in existing commercial EDA tools, which currently lack fully automated flip-chip layout optimization capabilities. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 A flow chart of a method for placing flip-chip solder pillars for a superconducting quantum chip provided by an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of a layout space after pre-processing the boundaries of the layout and the boundaries of placed module units provided in an embodiment of the present invention;

[0030] Figure 3 A schematic diagram of a layout space after pre-processing the internal grid of a module unit where components have been placed, provided by an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of the layout space after the inverted columns provided in an embodiment of the present invention are placed;

[0032] Figure 5 A schematic diagram of horizontal placement of an inverted column provided in an embodiment of the present invention;

[0033] Figure 6 A schematic diagram of the tilted placement of an inverted column provided in an embodiment of the present invention;

[0034] Figure 7 A schematic diagram of secondary placement provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

[0036] The embodiment of the present invention provides a method for placing flip-chip solder pillars of a superconducting quantum chip. The flip-chip placement process is as follows: Figure 1 Shown, including:

[0037] S1, gridding the layout to be processed and marking the type of each grid according to its location;

[0038] Among them, the types of grids at the boundaries of the layout to be processed and the boundaries of the module units placed in the layout to be processed are all boundary grids; the types of grids at the boundaries of the placed lines and the grids within the placed module units in the layout to be processed are occupied grids; the types of grids whose distance from the boundary of the layout to be processed is less than the first safety distance and the types of grids whose distance from the boundary of the placed module units is not less than the second safety distance are all within the safety distance grids; the types of the remaining grids are all free grids;

[0039] S2, with the goal of maximizing the number of flip-chip solder columns that can be placed, scan each free grid G ​​row by row i , with G i As a reference, align the lower left corner vertex of the flip-chip solder column with G i After the lower left corner vertex of the flip-chip solder column coincides, determine whether the grids occupied by the flip-chip solder column are all free grids. If so, they can be placed horizontally accordingly, record the placement position coordinates of the flip-chip solder column, and update the grid type of the grid occupied by the flip-chip solder column. If not, use G i As a reference, align the lower left corner of the flip-chip solder column after tilting with G i After the lower left corner vertex of the grid coincides, it is determined whether the grids occupied by the tilted flip-chip solder column are all free grids. If so, the corresponding tilted placement can be performed, the placement position coordinates and tilt angle of the flip-chip solder column are recorded, and the grid type of the grid occupied by the flip-chip solder column is updated. Otherwise, the grid is skipped until all free grids are scanned to obtain the coordinate set and tilt angle of the flip-chip solder column that can be placed.

[0040] First, the layout to be processed in the plan is divided into a series of equally sized grids. The grid size determines the number of grids in the control layout. Each grid type is then labeled. For example, a flag can be set for each grid to indicate the corresponding grid type. Different flags indicate whether the current grid type is a free grid, an occupied grid, a grid within a safe distance, or a free grid.

[0041] Specifically, the boundaries of the layout are processed, and the grids where the boundaries are located and the grids within the first safety distance from the boundaries are marked as corresponding types, which are used for boundary judgment in the subsequent placement process; the boundaries of the module units that have been placed in the layout are processed, and the grids where the unit boundaries are located and the grids within the safety distance are marked as corresponding types, which are used for boundary judgment in the subsequent placement process, such as Figure 2 As shown;

[0042] Process the grid inside the placed module unit and mark all the grids inside the unit as the corresponding type for grid type judgment in the subsequent placement process, such as Figure 3 As shown; wherein, preferably, in order to speed up the preprocessing process, a breadth-first traversal is used to process the grid inside the placed module unit.

[0043] Then, the flip-chip solder column placement work is performed in the placeable area in the layout (that is, the area where the free grid is located). Due to the irregular module boundaries in the layout, a single placement method may lead to space waste and fail to fully utilize the layout space. Therefore, a secondary placement method is adopted, that is, a secondary processing is performed on the placeable area, and two methods of placement are used, horizontally and tilted, respectively, in order to fully utilize the placement space. Among them, when scanning each row of free grids, priority is given to determining whether the flip-chip column can be placed horizontally. Finally, the placement coordinates are output according to the specified requirements. The layout space after the flip-chip column placement is completed is as follows Figure 4 shown.

[0044] Among them, by designing visualization tools, the current layout area information can be saved in bmp file format at different stages of the program processing process.

[0045] The method provided by the present invention is further described below by mathematical modeling. An abstract model is performed on the chip inverted pillar placement problem, and a corresponding basic mathematical model is established.

[0046] 1. Problem Modeling

[0047] 1.1 Input Definition

[0048] A flat layout, with dimensions W × H;

[0049] ·Inverted column size s×s;

[0050] The set of placed module units E = {e j}, each module unit is an irregular polygon, consisting of a vertex set {(x j1 ,y j1 ),(x j2 ,y j2 ),…,(x jn ,y jn )}The polygonal area formed by connecting the end to the end;

[0051] Network set W = {w k}, each network is a line w connected by multiple points in sequence k ={(x k1 ,y k1 ),(x k2 ,y k2 )…,(x kt ,y kt )}constitute;

[0052] The safety distance d1 between the inverted column and the layout boundary, and the safety distance d2 between the inverted column and the boundary of the placed component module unit;

[0053] Grid size g×g; to maximize the number of inverted pillars, the grid area is usually set smaller than the inverted pillar area. For example, the side length of an inverted pillar is generally 20 times the side length of the grid.

[0054] The rotation angle θ of the inverted column (θ∈{0,45}).

[0055] 1.2 Output Definition

[0056] The coordinate set of the inverted column placement S={(x1,y1),(x2,y2),....(x m ,y m )}

[0057] 1.3 Constraints

[0058] Inverted columns cannot overlap with existing components and networks.

[0059] A safe distance must be maintained between the inverted column and existing components and networks

[0060] The inverted column cannot exceed the boundaries of the plane layout

[0061] 1.4 Objective Function

[0062] Maximize the number of inverted columns placed m

[0063] 2. Mathematical Model

[0064] 2.1 Mesh division model

[0065] Divide the layout P into grids of equal size, each grid size is g×g, where g is used to control the number and size of grids and can be set according to actual conditions. The smaller the g value, the higher the calculation accuracy, but at the same time, the calculation efficiency must still be taken into account.

[0066] 2.2 Grid Logo

[0067] Each grid G i There is a flag bit b, which is used to indicate the state of the grid. The flag bit uses bit operations to accelerate the judgment. For example:

[0068] b=0: free grid

[0069] b=1: Boundary grid

[0070] b=2:grid within safety distance

[0071] b=3: Occupied grid

[0072] 2.3 Boundary Processing

[0073] The boundaries of the layout are processed, and the grids at the boundaries and the grids within the safety interval are marked as corresponding types b=1 and b=2 respectively.

[0074] 2.4 Component Processing

[0075] For each element e j , mark the grid it occupies and the grid within the safety distance as the corresponding type b j =3 and b j =2.

[0076] 2.5 Placement method

[0077] Two placement methods (tilted or horizontal) are used to place the pre-processed layout inverted.

[0078] For each placement method: For each free grid G i (ie b i =0), judge whether it meets the conditions for placing an inverted column.

[0079] If the conditions are met, the inverted column is placed in the grid and the corresponding flag is updated.

[0080] When scanning each row of free grids, the system first determines whether the column can be placed horizontally. If so, it is placed horizontally and the corresponding flag is updated. The position coordinates of the horizontal column are recorded. Otherwise, the system determines whether the column can be placed tilted. If so, it is placed tilted and the corresponding flag is updated. The position coordinates and tilt angle of the tilted column are recorded. Otherwise, the system skips the process until all free grids are scanned to obtain the coordinate set and tilt angle of the column. Accordingly, it can be understood that if a column does not have a tilt angle, the column is placed horizontally.

[0081] The results of using only the horizontal or tilted placement method and the use of both the horizontal and tilted placement methods proposed by the present invention are as follows: Figures 5-7 shown.

[0082] The method provided by the present invention can place as many inverted columns as possible by defining a specific placement process through grid division, marking grid type status, and scanning idle grids.

[0083] An embodiment of the present invention provides an electronic device, characterized by comprising: a computer-readable storage medium and a processor;

[0084] The computer-readable storage medium is used to store executable instructions;

[0085] The processor is configured to read the executable instructions stored in the computer-readable storage medium and execute the method described in any one of the above embodiments.

[0086] An embodiment of the present invention provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to execute the method described in any of the above embodiments.

[0087] An embodiment of the present invention provides a computer program product, including a computer program or instructions, characterized in that when the computer program or instructions are executed by a processor, the method described in any of the above embodiments is implemented.

[0088] It will be easily understood by those skilled in the art that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for placing flip-chip solder columns of a superconducting quantum chip, characterized in that: include: S1, gridding the layout to be processed and marking the type of each grid according to its location; Among them, the types of grids at the boundaries of the layout to be processed and the boundaries of the module units placed in the layout to be processed are all boundary grids; the types of grids at the boundaries of the placed lines and the grids within the placed module units in the layout to be processed are occupied grids; the types of grids whose distance from the boundary of the layout to be processed is less than the first safety distance and the types of grids whose distance from the boundary of the placed module units is not less than the second safety distance are all within the safety distance grids; the types of the remaining grids are all free grids; S2, with the goal of maximizing the number of flip-chip solder columns that can be placed, scan each free grid G ​​row by row i , with G i As a reference, align the lower left corner vertex of the flip-chip solder column with G i After the lower left corner vertex of the flip-chip solder column coincides, determine whether the grids occupied by the flip-chip solder column are all free grids. If so, they can be placed horizontally accordingly, record the placement position coordinates of the flip-chip solder column, and update the grid type of the grid occupied by the flip-chip solder column. If not, use G i As a reference, align the lower left corner of the flip-chip solder column after tilting with G i After the lower left corner vertex of the grid coincides, it is determined whether the grids occupied by the tilted flip-chip solder column are all free grids. If so, the corresponding tilted placement can be performed, the placement position coordinates and tilt angle of the flip-chip solder column are recorded, and the grid type of the grid occupied by the flip-chip solder column is updated. Otherwise, the grid is skipped until all free grids are scanned to obtain the coordinate set and tilt angle of the flip-chip solder column that can be placed.

2. The method according to claim 1, wherein The grids in the placed module units are traversed using a breadth-first traversal method to mark the grid types.

3. The method according to claim 1 or 2, wherein: In step S2, the angle of the inclined placement is 45 degrees.

4. The method according to claim 1, wherein The grid area is smaller than the area of ​​the flip-chip solder pillar.

5. An electronic device, characterized in that: include: Computer-readable storage media and processor; The computer-readable storage medium is used to store executable instructions; The processor is configured to read the executable instructions stored in the computer-readable storage medium and execute the method according to any one of claims 1 to 4.

6. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to execute the method according to any one of claims 1 to 4.

7. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the method according to any one of claims 1 to 4 is implemented.

Images