Intelligent design method for microwave chip circuit architecture

Abstract

The invention discloses an intelligent design method for a microwave chip circuit architecture. Comprising the steps of index input, netlist digitization, transistor automatic selection, matching network impedance point automatic selection, Smith chart automatic matching, matching network netlist automatic determination, netlist circuit structure automatic generation, direct current bias network netlist automatic determination, overall network netlist automatic determination, layout automatic conversion and theoretical and actual index comparison. And automatically generating a circuit diagram. According to the method, manual participation is not needed in the whole process, a user only needs to input indexes, the chip layout can be obtained, the design time of the microwave chip is shortened, and the method can be effectively applied to microwave chip circuit design.

Description

Technical Field

[0001] The present invention belongs to the field of microwave chip circuit design, and in particular relates to an intelligent design method for a microwave chip circuit architecture. Background Art

[0002] With the development of data analysis and the gradual shift of artificial intelligence technology from research to application, multidisciplinary integration has become a hot research topic in recent years. Radar systems at home and abroad are rapidly developing towards chip integration. Faced with radar and communication systems with diverse frequency bands, how to save chip design time and improve design efficiency has become the focus of research. Summary of the invention

[0003] The purpose of the present invention is to address the problems of high threshold, long design time and low design efficiency of existing microwave chip designs, and to provide an intelligent design method for microwave chip circuit architecture, computer equipment, computer-readable storage medium and computer program product, which can realize full-process automated design of microwave chips, effectively save chip design time and improve chip design efficiency.

[0004] In order to achieve the above object, one aspect of the present invention provides a method for intelligent design of microwave chip circuit architecture, comprising:

[0005] An indicator input step, receiving input indicators;

[0006] Netlist digitization step, extracting component connection relations, component values ​​and component types from the netlist file and forming an array;

[0007] The automatic transistor selection step uses the Monte Carlo tree search method, takes the input index as the basis for determining the key nodes of the tree, selects the gate width and gate voltage that meet the index, and completes the automatic transistor selection;

[0008] The step of automatically selecting impedance points of the matching network is to use the inter-stage DC capacitor as the dividing point of the cascade circuit into sub-circuits, set the left and right nodes of the capacitor as the starting points of the front and rear sub-circuits respectively, set the next inter-stage capacitor or the chip starting port as the end point, use the breadth-first algorithm to search all paths between the two points to form a sub-circuit network, calculate the input impedance or output impedance or minimum noise impedance of the sub-circuit network respectively, and complete the automatic selection of impedance points of the cascade circuit matching network;

[0009] The Smith chart automatic matching step adopts the Smith chart graphical method, takes the impedance point of the matching network as the starting point and the end point, takes the Q line of the matching network as the boundary condition of the impedance matching path, completes the path between the starting point and the end point, and realizes the automatic determination of the matching network netlist;

[0010] The step of automatically generating a netlisted circuit structure determines the DC bias according to the gate voltage and gate width selected in the transistor automatic selection step, and adds a network at the node of the circuit structure by parsing the netlist file of the circuit structure to generate the circuit structure, complete the automatic determination of the DC bias network netlist, and realize the automatic determination of the overall network netlist;

[0011] In the automatic layout conversion step, the netlist devices are randomly optimized, the random error values ​​are retained, and the randomly optimized netlist is gradient optimized. By comparing the generated error values ​​with the random error values, each device is iterated in turn to realize the conversion of all ideal devices to actual layout devices;

[0012] Theoretical and actual index comparison step, compare the actual simulation result with the input index, if the difference with the index value does not exceed the tolerance, then enter the circuit diagram automatic generation step, if the difference with the index value exceeds the tolerance, then return to the netlist digitization step;

[0013] The automatic circuit diagram generation step automatically converts the digital netlist into an intuitive graphical circuit diagram.

[0014] Another aspect of the present invention provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above method.

[0015] Another aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the above method when executed by a processor.

[0016] Another aspect of the present invention provides a computer program product, comprising a computer program, which implements the steps of the above method when executed by a processor.

[0017] The microwave chip circuit architecture intelligent design method, computer equipment, computer-readable storage medium and computer program product according to the above aspects of the present invention can realize the full-process automated design of microwave chips, effectively save chip design time and improve chip design efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings used in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work:

[0019] Figure 1 It is a flow chart of a method for intelligent design of microwave chip circuit architecture according to one embodiment of the present invention;

[0020] Figure 2 It is a structural diagram of a computer device according to one embodiment of the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] The embodiments of the present invention provide an intelligent design method for microwave chip circuit architecture. For microwave low-noise amplifiers, filters and other chips that are key components of the transceiver system, the data analysis software Python and the microwave simulation software ADS are used to realize the automatic design of the chip. The user only needs to input the parameter indicators of concern, and the chip layout can be generated without human intervention in the intermediate process.

[0023] like Figure 1 As shown, the intelligent design method of the microwave chip circuit architecture of the embodiment of the present invention includes the following steps: indicator input, netlist digitization, automatic transistor selection, automatic selection of matching network impedance points, automatic Smith chart matching, automatic generation of netlist circuit structure, automatic determination of DC bias network netlist, automatic determination of overall network netlist, automatic layout conversion, comparison of theoretical and actual indicators, and automatic generation of circuit diagram.

[0024] In the indicator input step, the data analysis software Python is used to receive user input indicators.

[0025] In the netlist digitization step, the input index, component connection relationship, component value and component type are digitized. In one embodiment, the component connection relationship, component value and component type are extracted from the netlist file and formed into an array.

[0026] In the automatic transistor selection step, the Monte Carlo Tree Search (MCTS) method is used to replace the traversal scanning of the transistor gate width and gate voltage to improve the efficiency of transistor selection. The design idea is to use the input index as the judgment basis of the MCTS key node, which can effectively narrow the range of all index requirements and filter out all transistor bias conditions that meet the index. Specifically, randomly extract values ​​from the limited range of gate width and gate voltage, combine the method of local parameter traversal, and use the gain, noise, current and P1dB indicators as the criteria of the tree key nodes for step-by-step screening and loop feedback to complete the automatic selection of transistors. In one embodiment, the gate width array is composed of [2,4,6,8], and the gate voltage array is composed of [25,50,75,100]. The computer randomly extracts values ​​from the two arrays, and uses the traversal loop statement to analyze the gain and other indicators to complete the screening of the gate width and gate voltage values ​​that meet the indicators.

[0027] In the matching network impedance point selection step, the complex cascade circuit is automatically disassembled into a collection of several simple sub-circuits. The design idea is to use the inter-stage DC capacitor as the dividing point of the cascade circuit sub-circuit, set the left and right nodes of the capacitor as the starting points of the front and back sub-circuits respectively, and set the next inter-stage capacitor or chip starting port as the end point. Use the breadth-first algorithm to search all paths between the two points to form a new sub-circuit network. Calculate the input impedance or output impedance or minimum noise impedance of the sub-circuit network respectively to complete the automatic selection of the impedance point of the cascade circuit matching network.

[0028] In the Smith chart automatic matching step, the Smith chart diagram method is used as a single-layer recursive logical relationship, dual-element matching is used as a recursive termination condition, and the intermediate impedance point in the matching process is used as a recursive return parameter. Its design idea can be summarized as taking the impedance point of the matching network as the starting point and the end point, and taking the equal Q line of the matching network as the boundary condition of the impedance matching path to complete the path realization between the starting point and the end point. The path information includes the type of component, the series and parallel form of the component, and the value of the component, so as to realize the automatic determination of the matching network netlist. In one embodiment, the starting point of the matching network is 50 ohms and the end point is 100 ohms. The equal Q line is constructed on the Smith chart. The area within the equal Q line is the feasible area of ​​the matching path. The matching from the starting point to the end point is completed by using series and parallel capacitors and inductors.

[0029] In the step of automatic generation of netlist circuit structure, a specific network structure is inserted at any node of the original circuit architecture to realize functions such as noise matching and impedance matching. The design idea is that the object of automatic generation of circuit architecture is a circuit network. From the perspective of the network outside, the original inserted node needs to be split into two nodes; inside the network, a new set of nodes, new connection relationships, and new device types and values ​​need to be generated. The network to be inserted can be described by the above three factors. Relying on the data analysis software Python, the key information in the netlist text file (such as the insertion node) is automatically read and written, and the netlist file of the circuit architecture is parsed to realize automatic addition of the network and automatic generation of the circuit structure. The gate voltage and gate width selected by the automatic transistor selection step determine the DC bias. The automatic generation technology of the netlist circuit structure is used to complete the automatic determination of the DC bias network netlist and realize the automatic determination of the overall network netlist.

[0030] In the automatic layout conversion step, the ideal device is automatically converted into the actual layout simulation device. The design idea is divided into two cases: the passive or low-noise class adopts the replacement order from front to back; the power amplifier class adopts the replacement order from back to front. First, starting from the first replacement device, all devices except the replacement device are prohibited from optimization. The inductor and capacitor layout database is searched by binary search to determine the initial value. On this basis, the random algorithm is used for optimization, and the optimized error value is retained; secondly, a temporary netlist file is generated, and the randomly optimized netlist is gradient optimized, and the error value generated is compared with the error value of random optimization. If it is better than the former, the temporary netlist file will overwrite the source netlist file; if it is worse than the former, the temporary netlist file will be deleted, and each conversion device will be iterated in turn, and finally all ideal devices will be converted into actual layout devices.

[0031] In the step of comparing theoretical and actual indicators, the data analysis software Python is used to make judgments by comparing the input indicators with the actual simulation results. If the range of the difference from the indicator value is within the acceptable range and does not exceed the tolerance, the circuit diagram automatic generation step is entered; if the range of the difference from the indicator value exceeds the tolerance, the step returns to the netlist digitization step and recalculates.

[0032] In the automatic generation of circuit diagrams, the calculated digital netlist is automatically converted into an intuitive graphical circuit diagram. The design idea is to use data processing software to analyze the netlist, extract component connection relationships and size information, generate a file format that meets the requirements of EDA software, and automatically convert it into an intuitive circuit diagram. This completes the realization process of intelligent design of microwave chip circuit architecture.

[0033] The intelligent design method of microwave chip circuit architecture of the embodiment of the present invention is suitable for microwave active and passive chip design. The design method does not require human participation throughout the process. The user only needs to input indicators to obtain the chip layout, which shortens the design time of the microwave chip and can be effectively used in microwave chip circuit design.

[0034] The embodiment of the present invention further provides a computer device, which may be a server, and its internal structure diagram may be as shown in FIG. Figure 2 As shown. The computer device includes a processor, a memory and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store operating parameter data of each framework. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the steps of the method of the embodiment of the present invention are implemented.

[0035] Those skilled in the art will understand that Figure 2 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0036] The embodiments of the present invention further provide a computer-readable storage medium having a computer program stored thereon, and the computer program, when executed by a processor, implements the steps of the method of the embodiments of the present invention.

[0037] The embodiments of the present invention further provide a computer program product, including a computer program, which implements the steps of the method of the embodiments of the present invention when executed by a processor.

[0038] The above description is only by way of illustration of certain exemplary embodiments of the present invention. It is undoubted that those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the above drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A method for intelligent design of microwave chip circuit architecture, characterized in that: include: An indicator input step, receiving input indicators; Netlist digitization step, extracting component connection relations, component values ​​and component types from the netlist file and forming an array; The automatic transistor selection step uses the Monte Carlo tree search method, takes the input index as the basis for determining the key nodes of the tree, selects the gate width and gate voltage that meet the index, and completes the automatic transistor selection; The step of automatically selecting impedance points of the matching network is to use the inter-stage DC capacitor as the dividing point of the cascade circuit into sub-circuits, set the left and right nodes of the capacitor as the starting points of the front and rear sub-circuits respectively, set the next inter-stage capacitor or the chip starting port as the end point, use the breadth-first algorithm to search all paths between the two points to form a sub-circuit network, calculate the input impedance or output impedance or minimum noise impedance of the sub-circuit network respectively, and complete the automatic selection of impedance points of the cascade circuit matching network; The Smith chart automatic matching step adopts the Smith chart graphical method, takes the impedance point of the matching network as the starting point and the end point, takes the Q line of the matching network as the boundary condition of the impedance matching path, completes the path between the starting point and the end point, and realizes the automatic determination of the matching network netlist; The step of automatically generating a netlisted circuit structure determines the DC bias according to the gate voltage and gate width selected in the transistor automatic selection step, and adds a network at the node of the circuit structure by parsing the netlist file of the circuit structure to generate the circuit structure, complete the automatic determination of the DC bias network netlist, and realize the automatic determination of the overall network netlist; In the automatic layout conversion step, the netlist devices are randomly optimized, the random error values ​​are retained, and the randomly optimized netlist is gradient optimized. By comparing the generated error values ​​with the random error values, each device is iterated in turn to realize the conversion of all ideal devices to actual layout devices; Theoretical and actual index comparison step, compare the actual simulation result with the input index, if the difference with the index value does not exceed the tolerance, then enter the circuit diagram automatic generation step, if the difference with the index value exceeds the tolerance, then return to the netlist digitization step; The automatic circuit diagram generation step automatically converts the digital netlist into an intuitive graphical circuit diagram.

2. The method according to claim 1, characterized in that In the automatic transistor selection step, values ​​are randomly extracted from the limited range of gate width and gate voltage, and the local parameter traversal method is adopted to use the input indicators as the criteria of the key nodes of the tree for step-by-step screening and cyclic feedback to complete the automatic transistor selection.

3. The method according to claim 1 or 2, characterized in that In the automatic layout conversion step, the initial value of the netlist device is determined by the binary method, and the random algorithm is used for optimization. The optimized random error value is retained, a temporary netlist file is generated, and the randomly optimized netlist is gradient optimized. The generated error value is compared with the random error value. If it is better than the random error value, the temporary netlist file overwrites the source netlist file; if it is worse than the random error value, the temporary netlist file is deleted, and each device is iterated in turn to realize the conversion of all ideal devices into actual layout devices.

4. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 3.

5. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

6. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 3 are implemented.

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