Core particle simulation platform design method and device, electronic equipment and storage medium

Abstract

The invention discloses a core particle simulation platform design method and device, electronic equipment and a storage medium, and relates to the technical field of integrated circuits, and the method comprises the steps: determining a first topological structure of a core particle simulation platform; the first topological structure comprises a controller and a plurality of core particle nodes; determining a second topological structure of the controller; the controller is used for realizing operation control on the core particle simulation platform; determining a third topological structure of each core particle node; each core particle node comprises a core particle assembly and an external assembly; configuring a plurality of core particle nodes to be tested in the core particle simulation platform; and controlling the plurality of to-be-tested core particle nodes to be tested by using the controller. Compared with a system structure simulator, the core particle simulation platform and the core particle simulation process have the advantages that hardware-level verification can be carried out, more accurate actual core particle behaviors can be obtained, higher running speed is achieved, and various types of core particles can be supported more easily; compared with a traditional FPGA verification platform building method, the method is simpler and more suitable for a core particle design mode.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a method, device, electronic device and storage medium for designing a core particle simulation platform. Background Art

[0002] Existing chiplet testing methods include using architecture simulators or traditional FPGA verification platforms. Architecture simulators usually use software to model system hardware, simulate the architecture's processors, storage systems, network transmission topology, etc., and verify the system's functions and performance. FPGA verification platforms can restore the chip's real usage scenarios as much as possible before tape-out, achieving the purpose of fully verifying the chip's functions.

[0003] However, it is difficult for architecture simulators or traditional FPGA verification platforms to simulate multiple cores, and the simulation efficiency is low. Summary of the invention

[0004] The main purpose of the embodiments of the present application is to provide a chip simulation platform design method, device, electronic device and storage medium to design a hardware platform for simulating multi-chip testing.

[0005] To achieve the above object, one aspect of an embodiment of the present application provides a method for designing a core particle simulation platform, the method comprising the following steps:

[0006] Determine a first topology structure of a core particle simulation platform; wherein the first topology structure includes a controller and a plurality of core particle nodes;

[0007] Determining a second topological structure of the controller; wherein the controller is used to implement operation control of the core particle simulation platform;

[0008] Determine a third topological structure of each of the core-grain nodes; wherein each of the core-grain nodes includes a core-grain component and an external component;

[0009] configuring a plurality of the core-grain nodes to be tested in the core-grain simulation platform;

[0010] The controller is used to control a plurality of the core particle nodes to be tested to perform simulation.

[0011] In some embodiments, determining the first topology of the core particle simulation platform comprises the following steps:

[0012] Determine the number and topological relationship of each of the core particle nodes;

[0013] determining the type and location of the controller;

[0014] Determining the spatial size and position of the storage chip of each of the core particles;

[0015] Determine the control signals and interconnection methods of each of the core particle nodes.

[0016] In some embodiments, the method further comprises the following steps:

[0017] The peripheral circuits of each of the core node are arranged in the first topology structure.

[0018] In some embodiments, determining the second topology of the controller comprises the following steps:

[0019] Determine the external path of the controller; wherein the external path includes a data path, a monitoring path, a reset path and a debugging path;

[0020] The data path is set as a first on-chip network; wherein the data path is used to connect each of the core grain nodes; transmit the executable files of each of the core grain nodes to the corresponding storage chip; after the core grain ends running, provide the controller with the data of the storage chip;

[0021] The monitoring path is set as a second on-chip network; wherein the monitoring path is used to obtain data of the monitoring module and transmit data of the virtual peripheral; the monitoring path is sent from the host computer to the controller via Ethernet, and then forwarded to the programmable logic through the controller, and the programmable logic is sent to each of the core grain nodes after protocol conversion of the second on-chip network;

[0022] The reset path is set to include a first reset path of the chiplet simulation platform and a second reset path of each chiplet node; wherein the controller uses corresponding reset signals to control the reset of multiple chiplet nodes and the reset of a single chiplet node through the first reset path and the second reset path respectively;

[0023] The debugging path is set to include a first debugging path of the hard-core processor and a second debugging path of the JTAG interface; wherein the debugging path is used to provide a burning and debugging path for each of the core grain nodes; the first debugging path is used to realize the transmission of the hardware bitstream file of each of the core grain nodes from Ethernet to the cache of the controller, and then the programmable logic converts the hardware bitstream file into a JTAG signal; the second debugging path is used to burn the hardware bitstream file through an external JTAG debugger.

[0024] In some embodiments, determining the third topological structure of each of the core-grain nodes, wherein each of the core-grain nodes includes a core-grain component and an external component, comprises the following steps:

[0025] Setting the type of the core particle component of each core particle node and the interface of each type;

[0026] Setting the type of the external components of each of the core grain nodes; wherein the external components include an interconnect component, an address mapping component, a monitoring component, a peripheral component and a reset component;

[0027] The interconnection component includes a first on-chip network router and a second on-chip network router; the first on-chip network router is connected to the data path of the core grain node, serves as an adaptation interface of the core grain component, and communicates with the core grain components in other adjacent core grain nodes; the second on-chip network router is used to transmit information of the monitoring component and the peripheral component to the controller;

[0028] The address mapping component is used to record the physical location identification ID of each of the core grain nodes and the mapping relationship between the physical location identification ID and the physical access address;

[0029] The monitoring component is used to monitor the operating status of each of the core grain nodes and the operating status of the core grain components;

[0030] The peripheral components include real peripherals and virtual peripherals; wherein the real peripherals are preset when the core particle simulation platform is designed; the virtual peripherals use the programmable logic resources in the FPGA to simulate the input and output of each core particle node;

[0031] The service component is used to connect to a reset path in the controller.

[0032] In some embodiments, configuring a plurality of the core-grain nodes to be tested in the core-grain simulation platform comprises the following steps:

[0033] Determine an address mapping table according to the position of each of the core grain nodes;

[0034] Selecting a core-grain component to be tested from each of the core-grain nodes and configuring an external component for the core-grain component;

[0035] Inserting a test probe into each of the configured core-grain nodes to generate a core-grain project;

[0036] Generate a hardware bitstream file according to the core grain project;

[0037] The hardware bitstream file is downloaded to the chip simulation platform for testing.

[0038] In some embodiments, the use of the controller to control the plurality of core particle nodes to be tested to perform simulation comprises the following steps:

[0039] Receiving a load program of each of the core particle nodes;

[0040] Loading the executable file corresponding to the load program into the storage chip corresponding to the core grain node through the controller;

[0041] Starting the executable file in each of the core grain nodes through a reset path of the controller;

[0042] Obtaining the running information of each of the core grain nodes when running the executable file;

[0043] After each of the core grain nodes finishes running the executable file, reading the execution result;

[0044] The operation information and the execution result are uploaded to a host computer so that the host computer can analyze the simulation results of each of the core particle nodes.

[0045] To achieve the above-mentioned purpose, another aspect of the embodiment of the present application provides a device for designing a core particle simulation platform, the device comprising:

[0046] A platform design unit, used to determine a first topology structure of a core particle simulation platform; wherein the first topology structure includes a controller and a plurality of core particle nodes;

[0047] A controller design unit, used to determine a second topological structure of the controller; wherein the controller is used to implement operation control of the core particle simulation platform;

[0048] A core grain design unit, used to determine a third topological structure of each of the core grain nodes; wherein each of the core grain nodes includes a core grain component and an external component;

[0049] A core particle configuration unit, used for configuring a plurality of core particle nodes to be tested in the core particle simulation platform;

[0050] The core particle simulation unit is used to control the plurality of core particle nodes to be tested to perform simulation using the controller.

[0051] To achieve the above objective, another aspect of an embodiment of the present application provides an electronic device, the electronic device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the above method when executing the computer program.

[0052] To achieve the above objective, another aspect of an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program implements the above method when executed by a processor.

[0053] The embodiments of the present application include at least the following beneficial effects:

[0054] The present application can determine the first topology of the core particle simulation platform; wherein the first topology includes a controller and multiple core particle nodes; determine the second topology of the controller; wherein the controller is used to realize the operation control of the core particle simulation platform; determine the third topology of each core particle node; wherein each core particle node includes a core particle component and an external component; configure multiple core particle nodes to be tested in the core particle simulation platform; use the controller to control the multiple core particle nodes to be tested for testing. Compared with the architecture simulator, the core particle simulation platform and simulation process of the present application can perform hardware-level verification, obtain more accurate actual core particle behavior, have a higher operating speed than the architecture simulator, and are more likely to support various types of core particles; compared with the traditional FPGA verification platform construction method, it is simpler and more suitable for the design mode of core particles. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0056] Figure 1 A schematic diagram of a process flow of a core particle simulation platform design method provided in an embodiment of the present application;

[0057] Figure 2 A hardware design flow chart of the core particle simulation platform provided in the embodiment of the present application;

[0058] Figure 3 A hardware topology diagram of an exemplary core particle simulation platform provided in an embodiment of the present application;

[0059] Figure 4 A topological structure diagram of a controller provided in an embodiment of the present application;

[0060] Figure 5 A schematic diagram of the data path and monitoring path connection method provided in the embodiment of the present application;

[0061] Figure 6 A structural diagram of a core particle node provided in an embodiment of the present application;

[0062] Figure 7 A flow chart for generating and downloading a multi-chip engineering project provided in an embodiment of the present application;

[0063] Figure 8 A control flow chart of the core particle operation provided in the embodiment of the present application;

[0064] Fig. 9A schematic diagram of the structure of a core particle simulation platform design device provided in an embodiment of the present application;

[0065] Fig.10 A schematic diagram of the hardware structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0067] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0068] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0069] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0070] Before describing the embodiments of the present application in detail, the related technologies involved in the embodiments of the present application are first described as follows:

[0071] With the continuous evolution of semiconductor process nodes, transistors are shrinking to the point of approaching physical limits, and the pursuit of economic efficiency "Moore's Law" is slowing down. The R&D cost and complexity of chips under advanced processes have increased significantly, and the development difficulty of advanced technology node system-on-chip (SoC) has also increased significantly, bringing challenges in terms of yield, cost, and development cycle, forcing people to seek more cost-effective technical routes to meet the industry's growing demand for chip performance, which can achieve larger chip sizes, break through the current manufacturing area limitations, and promote the continuous improvement of chip integration and computing power. The chiplet heterogeneous integration technology has promoted the development of multi-chip packaging and can effectively continue Moore's Law. The principle of the chiplet is to decompose the original complex SoC chip according to different computing units or functional units from the design time, and then select the most suitable process to manufacture each unit, and then interconnect these modular bare chips through advanced packaging technology, such as using a silicon interposer. Finally, the chiplets with different functions and different processes are packaged into a SoC chip. This technology effectively solves the problems of chip R&D in terms of cost, scale, cycle, etc. In addition, due to the use of advanced packaging technologies such as 2.5D and 3D, the chiplets achieve on-chip interconnection and have amazing performance in terms of integration, power consumption, delay, operating frequency, etc.

[0072] The core particle system is a new design model that involves a combination of multiple independent small chips with different functions and different architectures, and needs to consider the communication and collaboration between multiple core particles. This design model requires detailed verification and design space exploration of the core particle system before manufacturing to ensure that the system can meet the functional performance requirements.

[0073] The technical problems to be solved by this application are:

[0074] Existing chiplet testing methods include using architecture simulators or traditional FPGA verification platforms.

[0075] Architecture simulators usually use software to model system hardware, simulate the architecture's processors, storage systems, network transmission topologies, etc., and verify the system's functions and performance. (1) However, simulators are not based on real hardware. They rely on software to simulate hardware characteristics such as circuits and clock frequencies. In order to achieve simplicity and fast execution of performance models, developers often abstract some detailed features, which may not be able to fully simulate real hardware behavior, resulting in deviations between simulator results and actual hardware behavior. (2) Architecture simulators also have the problem of slow simulation speed, especially when cycle-accurate simulation models are used to get closer to real hardware. This is a very time-consuming process. The coregrain system uses multiple coregrains to splice together, which can achieve a larger chip scale. As the scale of the coregrain system increases, the running time of using a simulator to model the entire coregrain system becomes unacceptable and cannot meet the research and design requirements of the coregrain system. (3) Simulators for coregrain systems are not yet mature and still face many problems. In order to simulate the coregrain system, it is necessary to integrate multiple different types of simulators, such as processor simulators of multiple different architectures, interconnect simulators, and storage models, which involves complex interconnection and synchronization issues between simulators.

[0076] Using RTL simulation is also a verification method, but it also faces the problem of slow simulation speed and long simulation time. FPGA prototype verification technology is used to verify integrated circuits for special applications by porting RTL to FPGA. FPGA prototype verification technology can restore the actual use scenario of the chip as much as possible before tape-out, so as to fully verify the chip function.

[0077] (1) Traditional FPGA verification platforms are mainly oriented towards large-scale SOC design, and they strive to fit the entire SOC into one FPGA chip as much as possible, so they tend to use a small number of large-capacity FPGAs. A single large-capacity FPGA may be more expensive than multiple small-capacity FPGAs, and the supply is unstable. At the same time, when a large SOC requires multiple FPGA chips to accommodate it, it is necessary to design a complex logic partitioning strategy, and after the logic partitioning, it is necessary to carefully consider the impact of interconnection delay on chip functions. This leads to the high overall cost of traditional FPGA prototype verification platforms and their tools.

[0078] The core particle is based on the concept of splitting a large chip into small chips. A single small FPGA can accommodate a complete single core particle design without considering complicated circuit division. In addition, the communication delay between core particles is usually considered to require multiple core particle cycles to complete, so longer communication delays are allowed between FPGAs. Therefore, a large number of small FPGA platforms are more suitable for core particle simulation.

[0079] (2) Traditional FPGA verification platforms are not designed for chiplet systems. Chiplet combinations may use larger topologies, more peripherals, and more flexible storage models. Traditional FPGA verification platforms require manual creation of chiplet external components and manual splicing of multiple chiplets into a complete chiplet system, lacking fast combination and verification methods.

[0080] This application aims to propose a design method for a core particle simulation platform based on multiple FPGAs, which effectively guides the design of the core particle simulation platform. The core particle simulation platform and simulation process designed using this method can perform hardware-level verification compared to the simulator, obtain more accurate actual core particle behavior, have a higher running speed than the core particle simulator, and are more likely to support various types of core particles. This solution is simpler than the traditional FPGA verification platform construction method and is more suitable for the core particle design model. At the same time, the method proposes a hardware and software design solution for the core particle simulation platform, provides complete hardware and software support for core particle simulation, supports flexible core particle and external design, supports rapid embedding of core particles into the simulation platform to build a core particle system, and supports hardware and software level monitoring and effective data interaction during core particle operation.

[0081] Therefore, the embodiments of the present application provide a method, device, electronic device and storage medium for designing a core particle simulation platform. The technical solution of the present application includes: determining a first topological structure of the core particle simulation platform; wherein the first topological structure includes a controller and a plurality of core particle nodes; determining a second topological structure of the controller; wherein the controller is used to realize the operation control of the core particle simulation platform; determining a third topological structure of each core particle node; wherein each core particle node includes a core particle component and an external component; configuring a plurality of core particle nodes to be tested in the core particle simulation platform; and using the controller to control the plurality of core particle nodes to be tested for testing. Compared with the architecture simulator, the core particle simulation platform and simulation process of the present application can perform hardware-level verification, obtain more accurate actual core particle behavior, have a higher operating speed than the architecture simulator, and are more likely to support various types of core particles; compared with the traditional FPGA verification platform construction method, it is simpler and more suitable for the design mode of core particles.

[0082] The embodiment of the present application provides a method for designing a core particle simulation platform, which relates to the field of integrated circuit technology. The method for designing a core particle simulation platform provided in the embodiment of the present application can be applied to a terminal, a server, or a software running in a terminal or a server. In some embodiments, the terminal can be a smart phone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, and a car terminal, etc., but is not limited to this; the server side can be configured as an independent physical server, or a server cluster or distributed system composed of multiple physical servers, and can also be configured as a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms. The server can also be a node server in a blockchain network; the software can be an application that implements a method for designing a core particle simulation platform, etc., but is not limited to the above forms.

[0083] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments, in which tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media including storage devices.

[0084] An embodiment of the present application provides a method for designing a chiplet simulation platform, through which a hardware platform that is more suitable for chiplet simulation can be designed; this method can achieve flexible chiplet combination and external design, support rapid embedding of chiplets into a simulation platform to build a chiplet system, support monitoring of the software and hardware levels during chiplet operation and effective data interaction, and more effectively support early design space exploration of the chiplet system.

[0085] Specifically, the methods of the embodiments of the present application include a chip simulation platform hardware design method, which describes a hardware carrier design method suitable for chip operation; a controller design method, in which the controller is responsible for the control of the hardware platform, host computer interaction, and signal monitoring during the chip operation process; a single chip node design method, which describes the component design requirements outside the chip component, and the chip component and external components constitute a complete chip engineering method; a multi-chip combination generation and download method, which describes how to generate the system engineering required for multiple chiplets and the download method of multi-chip bitstreams; a chip operation control method, which describes the loading and operation strategy of the chip internal load program, as well as the software monitoring method of the operation process, etc.

[0086] Reference Figure 1 The embodiment of the present application provides a method for designing a core particle simulation platform. The method may include but is not limited to S100 to S140, which are as follows:

[0087] S100: Determine a first topology structure of a core particle simulation platform; wherein the first topology structure includes a controller and a plurality of core particle nodes.

[0088] Furthermore, S100 may include:

[0089] S101: Determine the number and topological relationship of each of the core particle nodes;

[0090] S102: Determine the type and location of the controller;

[0091] S103: Determine the space size and position of the storage chip of each core particle;

[0092] S104: Determine the control signal and interconnection mode of each of the core particle nodes.

[0093] Specifically, in the chiplet simulation platform design method of this embodiment, it is necessary to first design its hardware platform. The hardware design process of the chiplet simulation platform is as follows: Figure 2 As shown. The core particle simulation platform hardware uses a method of simulating core particles with multiple small-capacity FPGAs. Each FPGA can accommodate a single core particle. The interconnection delay between FPGAs can tolerate multiple cycles. Each FPGA can be considered as a core particle simulation node. The core particle simulation platform built by this method can perform hardware-level verification compared to simulators and obtain more accurate actual core particle behaviors. Compared with the traditional FPGA verification platform construction method, it is simpler and more suitable for the design mode of core particles.

[0094] Specifically, the hardware design method of the core particle simulation platform can be summarized as follows: Figure 2 process. Figure 3 A hardware topology diagram of a core particle simulation platform exemplarily provided in this embodiment. Figure 2 The specific steps include:

[0095] (1) Define the number and topology of core particle simulation nodes. The core particle simulation node topology needs to consider the maximum number of core particles that can be simulated and the physical location layout of the core particles. In order to make the platform compatible with a larger number of core particles, the scalability of the platform generally needs to be considered. Each core particle simulation node needs to be set with its own unique physical location identification ID. As shown in the example, the core particle simulation node is designed as a 4x4 array topology, which can simulate most of the core particle layout methods; the peripheral core particle simulation node is designed with a fiber optic interface (the expansion interface in the figure), which can realize the interconnection and expansion of multiple core particle simulation platforms. Each core particle simulation node is set with a unique location identification ID, which is realized by a multi-bit input bias resistor (not shown in the figure).

[0096] (2) Determine the controller type and location. The core particle simulation platform requires a controller as the process control of the platform and the communication with the host computer. The controller needs to be responsible for the core particle node project loading, core particle operation startup, process monitoring, result output, etc. of the core particle simulation platform. The type and location of the controller need to be determined during the hardware design process. The controller is more suitable for using a heterogeneous processor that includes a hard-core SOC processor part and a programmable logic part. The controller in the example is located in the lower right corner of the platform.

[0097] (3) Define the storage size and physical location of the storage chip. In a multi-chip combination, the storage chip location needs to consider the possible memory location in the actual chip system. The storage chip can be considered as a chip or a peripheral unit. In the example, an external storage chip is configured for each chip simulation node, such as Figure 2 Therefore, each chiplet simulation node can simulate a single memory chiplet, or the DDR can be considered as the mounted storage of each chiplet (such as 3D stacking), or the peripheral DDR can be considered as a storage peripheral outside the chiplet.

[0098] (4) Design the control signals of the chiplet simulation nodes and the interconnection between the nodes. The control signals and interconnection between the chiplet simulation nodes need to meet the communication between the chiplet components, the communication between the controller and the chiplet simulation nodes, the global reset, and the burning and debugging interface of each chiplet simulation node.

[0099] The interconnection between the chip simulation node and the adjacent nodes requires two paths. The data path is responsible for the communication between the chip components, and the monitoring path is responsible for the communication with the controller. These two paths are usually implemented as two independent on-chip networks. The hardware can use a serial bus (such as SerDes) or a parallel bus. The data path between the chip components needs to evaluate the difference between the communication delay between the chip simulation nodes (real hardware delay) and the actual communication delay of the chip (expected delay). It is generally believed that the delay between chiplets is slower than the operating frequency within the chiplet, so if the real delay is less than the required chip communication delay, a delay unit can be inserted in the node engineering for regulation; if the real delay is greater than the required chip communication delay, consider reducing the operating frequency of the chip simulation node and reducing the speed of the simulation.

[0100] In addition, each chip analog node requires a JTAG path to connect to the controller. The debug path can be selected in the form of a daisy chain, or if the topology is too large, each row can be selected as a daisy chain, and each row has a debugger interface connected to the controller.

[0101] The chip analog node requires two reset signals, which are responsible for the reset of the chip analog node and the reset of the chip component. All chip analog nodes can share two multiplexed signals, which are output by the controller.

[0102] Furthermore, S100 may also include:

[0103] S105: Setting peripheral circuits of each of the core node in the first topology structure.

[0104] Specifically, this embodiment can design core grain simulation node peripherals. The peripherals should meet the requirements of node operation, such as clock modules and FLASH peripherals required for FPGA curing. The peripherals need to provide common general peripherals for the core grain system, such as GPIO, which can be provided by real peripherals or replaced by virtual peripherals simulated by programmable logic in the core grain simulation node project.

[0105] S110: Determine a second topology structure of the controller; wherein the controller is used to implement operation control of the core particle simulation platform.

[0106] Specifically, through a single controller, the hardware bitstream file and the executable file of the core grain simulation platform can be downloaded, the operation control of the core grain simulation platform can be realized, and the data of the core grain simulation platform can be transmitted and monitored during operation. The controller uses a heterogeneous processor with a hard-core SOC processor part and a programmable logic part, which is compatible with the development convenience of the hard-core processor and the interface expansion of the programmable logic, such as the use of Xilinx's ZYNQ series chips. The hard-core SOC processor is responsible for communicating with the host computer through the Ethernet high-speed bus, and the programmable part is responsible for functions such as data conversion and path selection. The controller's external channels include data channels, monitoring channels, reset channels and debugging channels. The following describes the role of each channel and its implementation method in the controller.

[0107] Furthermore, S110 may include S111 to S115:

[0108] S111: Determine the external path of the controller; wherein the external path includes a data path, a monitoring path, a reset path and a debugging path;

[0109] S112: Setting the data path as a first on-chip network; wherein the data path is used to connect each of the core grain nodes; transmitting the executable files of each of the core grain nodes to the corresponding storage chip; and providing the data of the storage chip to the controller after the core grain ends operation;

[0110] S113: Setting the monitoring path as a second on-chip network; wherein the monitoring path is used to obtain data of the monitoring module and transmit data of the virtual peripheral; the monitoring path is sent from the host computer to the controller via Ethernet, and then forwarded to the programmable logic via the controller, and the programmable logic is sent to each of the core grain nodes after protocol conversion of the second on-chip network;

[0111] S114: Setting the reset path to include a first reset path of the chiplet simulation platform and a second reset path of each chiplet node; wherein the controller uses corresponding reset signals to control the reset of multiple chiplet nodes and the reset of a single chiplet node through the first reset path and the second reset path respectively;

[0112] S115: The debugging path is set to include a first debugging path of the hard-core processor and a second debugging path of the JTAG interface; wherein the debugging path is used to provide a burning and debugging path for each of the core grain nodes; the first debugging path is used to realize the transmission of the hardware bitstream file of each of the core grain nodes from Ethernet to the cache of the controller, and then the programmable logic converts the hardware bitstream file into a JTAG signal; the second debugging path is used to burn the hardware bitstream file through an external JTAG debugger.

[0113] For example, refer to Figure 4 , this embodiment provides a topological structure diagram of a controller. Specifically, the steps of designing the external path of the controller may include:

[0114] (1) The data path connects the data path of the multi-chip combination (multiple analog chip nodes). The data path is responsible for transmitting the executable files of the multi-chip combination to the corresponding storage location. After the chip finishes running, the data in the memory is read through the data path. This path is only valid before and after the chip runs, and is closed at other times. Since the data path needs to be connected to all chip simulation nodes, it can be considered to be implemented through an on-chip network during design, such as Figure 5 As shown, Figure 5 The diagram is a diagram of the connection between the data path and the monitoring path. Figure 5 The R in the figure stands for the on-chip network router. The on-chip network router of the multi-chip combination is defined in the chip node project. During the use of the data path, the data of the host computer reaches the storage unit of the control system through Ethernet, and then forwarded to the programmable logic through the control system. The programmable logic is converted to the on-chip network protocol and sent to the multi-chip combination. Similarly, the data from the multi-chip combination is converted to the storage unit of the controller after the protocol conversion, and then the controller notifies the host computer to read.

[0115] (2) Monitoring channel: The monitoring channel obtains the data of the monitoring module in the core particle project and transmits the data of the virtual peripheral. This channel is sent from the host computer to the control system via Ethernet, and then forwarded to the programmable logic through the control system. The programmable logic is sent to the multi-core combination after protocol conversion. Since the monitoring channel needs to be connected to all core particle simulation nodes, it can be considered to be implemented through the on-chip network during design. In order not to affect the communication between core particle components, a set of on-chip networks is used separately, such as Figure 4 As shown, a multi-chip combined NoC router is defined in the chip node project.

[0116] (3) Reset path: The reset path is divided into core grain project reset and core grain component reset. The controller uses two reset signals to control the reset of the global core grain node project and the global core grain component respectively. This signal can be directly given by the control system of the hard core processor.

[0117] (4) The debug path is responsible for providing a burning and debugging path for each analog node. The data of the debug path can be divided into two sources. Source one is the hard-core processor. The hardware bitstream file of the node is transmitted from Ethernet to the cache in the controller, and then converted into JTAG signals by the programmable logic. This path is easier to implement multiple node burning in conjunction with the host computer. Source two is the JTAG adapter. The bitstream file is burned through an external JTAG debugger. This path can debug the FPGA hardware more directly. In a multi-chip combination, the debug path can be selected in the form of a daisy chain, or if the topology is too large, each row can be selected as a daisy chain, so that each row will have a JTAG signal connected to the controller. The input and output of the debug path data are connected through a multiplexer and a demultiplexer. The control signals of the multiplexer and demultiplexer are provided by the control system in the hard-core processor.

[0118] S120: Determine a third topological structure of each of the core-grain nodes; wherein each of the core-grain nodes includes a core-grain component and an external component.

[0119] Specifically, a single-chip node is composed of a complete chip engineering consisting of a chip component and an external component, and the method realizes the generation of a single-chip platform. The method includes the design of interactive components between chiplets, a flexible peripheral support solution, and a control and monitoring method for chiplets. Since the combination of chip components and external components in this process is relatively fixed, it is more suitable to make configuration software to complete the operation. The configuration software needs to complete functions such as selecting the source of chip components, selecting the chip interface type, configuring router parameters and peripheral types, etc.

[0120] Further, S120 may include S121-S122:

[0121] S121: Setting the type of the core particle component of each core particle node and the interface of each type;

[0122] S122: Setting the type of the external component of each of the core grain nodes; wherein the external component includes an interconnect component, an address mapping component, a monitoring component, a peripheral component and a reset component;

[0123] The interconnection component includes a first on-chip network router and a second on-chip network router; the first on-chip network router is connected to the data path of the core grain node, serves as an adaptation interface of the core grain component, and communicates with the core grain components in other adjacent core grain nodes; the second on-chip network router is used to transmit information of the monitoring component and the peripheral component to the controller;

[0124] The address mapping component is used to record the physical location identification ID of each of the core grain nodes and the mapping relationship between the physical location identification ID and the physical access address;

[0125] The monitoring component is used to monitor the operating status of each of the core grain nodes and the operating status of the core grain components;

[0126] The peripheral components include real peripherals and virtual peripherals; wherein the real peripherals are preset when the core particle simulation platform is designed; the virtual peripherals use the programmable logic resources in the FPGA to simulate the input and output of each core particle node;

[0127] The service component is used to connect to a reset path in the controller.

[0128] Reference Figure 6 , the single core node project includes the following components:

[0129] (1) Core-grain component. The core-grain component is the core-grain to be simulated, which is provided by the user of the core-grain simulation platform. The core-grain component interface needs to comply with certain standard protocol interfaces, such as using a CHI interface with cache consistency function, or using the same on-chip network interface as the simulation platform. The configuration software selects the source of the core-grain component and the interface protocol used by the core-grain component.

[0130] (2) Interconnection components. Interconnection components are generally implemented by on-chip network routers. Interconnection components mainly use two on-chip network routers, one of which is connected to the data path of the core particle simulation node. As the adaptation interface of the core particle component, it is responsible for communicating with the core particle components in other adjacent nodes. Usually, the amount of data processed by this router is large. The router has certain configurability. The routing algorithm, bandwidth, delay and other parameters of the interconnection are selected through the configuration software, which will make the core particle simulation platform more flexible. Another router transmits information such as monitoring components and peripheral components to the controller. This router can use a fixed structure. Interconnection components generally need to consider how to adapt to real hardware, such as converting on-chip network data into SerDes signals to adapt to the serial path between nodes.

[0131] (3) System address mapping component. Each chip node in the system needs to be assigned a unique node ID, which is the physical location identification ID of the chip simulation node. During the use of the interconnection component, the address mapping table of the system address mapping component needs to be obtained. Through this table, the physical access address of the chip component is converted into the target physical location ID, and the local node ID and target node ID information are provided for the on-chip network data packet, and then the interface protocol is converted into the on-chip network protocol. The monitoring path also needs to obtain the local node ID and the location of the controller from the system address mapping component. The address mapping table must fully describe the entire system address space, and all chip simulation nodes must maintain the same address mapping table.

[0132] (4) Monitoring component. The monitoring component can monitor the operating status of the core particle node hardware, such as the temperature and power supply voltage of the FPGA where the node is located; the monitoring module can also monitor the real-time status of the core particle component, such as the number of core particle operation cycles. The data of the monitoring component is connected to the controller through the monitoring chip network channel, and is processed by the controller or forwarded to the host computer.

[0133] (5) Peripheral components. Peripheral components are set according to the needs of the core particles, including real peripherals, which are preset by the core particles when simulating the hardware platform design; virtual peripherals, which use the programmable logic resources in the FPGA to simulate the input and output of the core particles. The configuration software provides general peripheral modules, which can also be designed by the user. Virtual peripherals can parse the instruction sequence issued by the controller into peripheral input signals, such as simulating GPIO input signals; or package the peripheral outputs and transmit them to the controller, such as outputting through a virtual serial port. Virtual peripherals are also connected to the controller through the monitoring chip network channel.

[0134] (6) Reset component. The reset path is divided into core grain node engineering reset and core grain component reset. The core grain node engineering reset resets all components in the node, and the core grain component reset is only connected to the reset pin of the core grain component. The reset signal is globally controlled by the controller.

[0135] S130: configuring a plurality of the core-grain nodes to be tested in the core-grain simulation platform.

[0136] Furthermore, S130 may include S131 to S135:

[0137] S131: Determine an address mapping table according to the position of each of the core grain nodes;

[0138] S132: Select a core-grain component to be tested from each of the core-grain nodes and configure an external component for the core-grain component;

[0139] S133: inserting a test probe into each of the configured core-grain nodes to generate a core-grain project;

[0140] S134: Generate a hardware bitstream file according to the core grain project;

[0141] S135: Download the hardware bitstream file to the chip simulation platform for testing.

[0142] Specifically, the multi-chip project generation and download process is as follows Figure 7 As shown, the method realizes the configuration and generation of multiple core grain nodes, as well as how to insert hardware probes during the generation process and hardware debugging during operation. The method can also realize the automatic download of executable files of multiple core grain nodes through Ethernet. The method can insert hardware probes in a single core grain node and configure the controller to debug the hardware of the core grain node during operation.

[0143] Specifically, this embodiment includes:

[0144] (1) Define the system address mapping table according to the chiplet location. This step requires determining the chiplet location based on the required chiplet quantity and topology. The system address mapping table is obtained from the actual chiplet location, the address range to which the chiplet belongs, and the address range of the storage chip. The memory access address is mapped to the chiplet location identification ID. All chiplet node projects share the same table, which is stored in the system address mapping component in each chiplet node project.

[0145] (2) Select core particle components and configure peripheral components. Select the core particle component source and configure the parameters of the core particle external components according to the configurable options provided by the configuration software. For details, please refer to the core particle node engineering design method.

[0146] (3) Integrate the single chip node project and insert the test probe. After the chip external components are configured, the configuration software can integrate the chip components and external components. Then, the test probe can be inserted into the project through EDA tools, such as the ILA tool provided by Xilinx. Finally, a complete chip project is generated.

[0147] (4) EDA tools generate hardware bitstream files. After a single core node project is compiled, synthesized, and implemented using EDA tools, a hardware bitstream file that can be downloaded will be generated. Depending on the number of cores, the above steps need to be performed separately to generate hardware bitstream files for multiple core nodes.

[0148] (5) Multi-core node project download. The core project download method can be through Ethernet. The host computer sends multiple hardware bitstream files to the controller and automatically selects nodes and burns hardware bitstream files by controlling the debug path. It can also be manually downloaded through the JTAG adapter provided by the controller.

[0149] (6) Real-time hardware debugging: After all hardware bitstream files are downloaded successfully, all core nodes are globally reset. The FPGA hardware can then be debugged during runtime through the JTAG interface provided by the controller. The specific node selection for debugging is controlled by the controller.

[0150] S140: Using the controller to control the plurality of core particle nodes to be tested to perform simulation.

[0151] Furthermore, S140 may include S141 to S146:

[0152] S141: receiving a load program of each of the core grain nodes;

[0153] S142: Loading the executable file corresponding to the load program into the storage chip corresponding to the core grain node through the controller;

[0154] S143: starting the executable file in each of the core grain nodes through the reset path of the controller;

[0155] S144: Acquire the operation information of each of the core grain nodes when running the executable file;

[0156] S145: After each of the core grain nodes finishes running the executable file, reading the execution result;

[0157] S146: Upload the operation information and the execution result to a host computer so that the host computer can analyze the simulation results of each of the core particle nodes.

[0158] Specifically, the control process of the core particle operation is as follows Figure 8 As shown. This embodiment proposes a writing idea for multiple core load programs and a communication method between core load programs. The method provides how to load multiple program executable files into corresponding storage locations through data paths, and provides a software monitoring strategy when the core is running. After the operation is completed, the operation data of the core can be further obtained. It can be specifically divided into the following steps:

[0159] (1) Write and compile the load program for multiple cores. The writing and compilation of the multi-core load program is completed on the host computer side. Different compilation tool chains may be used to compile separately according to the instruction set architecture of the core. When writing a program, it communicates with other nodes through addresses, and messages can be passed to different core nodes by referring to the address mapping table. When compiling a program, it is necessary to define the starting address and size of the program code memory area of ​​the program, such as by modifying the link script during the compilation process. If multiple cores cannot share a program, the program code memory areas of multiple cores cannot conflict. Multiple cores can also share the same program code and perform different operations by reading the location identification ID.

[0160] (2) Loading the multi-core load program into the core-core platform storage system. According to the core-core program space location mentioned above, the executable file is serially loaded into the corresponding core-core storage space. This operation is performed by the host computer loading the core-core executable file into the controller, and the controller then loads the executable file into the corresponding storage location through the data path. During this process, the reset path of the controller keeps each core-core component in a reset non-operating state.

[0161] (3) Start the core particle operation. After all the load program executable files are transferred to the corresponding locations, the core particle components can be started through the reset path of the controller. After startup, multiple core particle components run in parallel, execute corresponding core particle tasks, and generate data interaction.

[0162] (4) Operation process monitoring. During the operation of the core particle component, the core particle operation process can be monitored to a certain extent according to the configured core particle peripheral components, such as monitoring the number of cycles of the core particle operation. During this process, the core particle can send output information to the controller and the host computer through the virtual peripheral, or receive input information from the controller through the virtual peripheral. During the operation, the core particle can also write the data it wants to record into the storage space, and read it after the core particle operation ends.

[0163] (5) The core particle operation ends. After each core particle has completed its operation, it can send an end signal to inform the controller and the host computer. This process can be implemented by virtual peripherals.

[0164] (6) Reading the execution results of the core particles. When all the core particles have finished running, the execution results of the core particles can be read, such as exporting the storage space data through the data path of the controller.

[0165] (7) Analysis of core particle simulation results: The core particle simulation results are analyzed based on the process monitoring signals and virtual peripheral information during the execution of the core particle task, as well as the exported data after the core particle operation ends.

[0166] In summary, the multi-FPGA-based core particle simulation platform design method provided by this application effectively guides the design of the core particle simulation platform. The core particle simulation platform and simulation process designed using this method can perform hardware-level verification compared to the simulator, obtain more accurate actual core particle behavior, have a higher operating speed than the core particle simulator, and are more likely to support various types of core particles. This method is simpler than the traditional FPGA verification platform construction method and is more suitable for the core particle design model. At the same time, the method proposes a hardware and software design solution for the core particle simulation platform, provides complete hardware and software support for core particle simulation, supports flexible core particle and external design, supports rapid embedding of core particles into the simulation platform to build a core particle system, and supports monitoring and effective data interaction at the hardware and software levels during core particle operation.

[0167] The key technical solutions of some embodiments of the present application are as follows:

[0168] 1. Hardware design method of core-grain simulation platform.

[0169] The core particle simulation platform hardware uses a method of simulating core particles with multiple small-capacity FPGAs. Each FPGA can accommodate a single core particle, and the interconnection delay between FPGAs can tolerate multiple cycles. Each FPGA can be considered as a core particle simulation node. The core particle simulation platform built by this method can perform hardware-level verification compared to simulators and obtain more accurate actual core particle behavior; it is simpler than the traditional FPGA verification platform construction method and is more suitable for the design mode of core particles.

[0170] 2. Controller design method.

[0171] Through a single controller, the hardware bitstream file of the core-grain platform and the executable file of the core-grain load program can be downloaded, the operation control of the core-grain platform can be realized, and data can be transferred and monitored during the operation of the core-grain platform. The controller uses a heterogeneous processor with a hard-core SOC processor part and a programmable logic part. The hard-core SOC processor is responsible for communicating with the host computer through the Ethernet high-speed bus, and the programmable part is responsible for data conversion and path selection. The external channels of the controller include data channel, control channel, reset channel and debug channel.

[0172] 3. Single-core node design method.

[0173] The single-chip node is a complete chip engineering composed of chip components and external components. This method realizes the generation of a single-chip platform. The method includes the design of interactive components between chiplets, flexible peripheral support solutions, and chip control and monitoring methods. Since the combination of chip components and external components in this process is relatively fixed, it is more suitable to make configuration software to complete the operation. The configuration software needs to complete the functions of selecting the source of chip components, selecting the chip interface type, configuring router parameters and peripheral types, etc.

[0174] 4. Multi-core combination generation and downloading method.

[0175] The multi-core engineering generation and downloading method realizes the configuration and generation of multiple core-grain nodes, as well as how to insert hardware probes during the generation process and hardware debugging during operation. The method can also realize the automatic download of executable files of multiple core-grain nodes through Ethernet. The method can insert hardware probes in a single core-grain node and configure the controller to debug the hardware of the core-grain node during operation.

[0176] 5. Core particle operation control method.

[0177] The control method of core-grain operation proposes the idea of ​​writing multiple core-grain load programs and the communication method between core-grain load programs. The method provides how to load multiple program executable files into corresponding storage locations through data paths, and provides a software monitoring strategy when the core-grain is running. After the operation is completed, the operation data of the core-grain can be further obtained.

[0178] Some embodiments of the present application have the following beneficial effects:

[0179] 1. Hardware design method of core-grain simulation platform.

[0180] Technical solution: Provide design instructions for hardware carrier design methods suitable for core particle operation.

[0181] Beneficial effects: By using multiple small-capacity FPGAs to simulate core particles, each FPGA can accommodate a single core particle, and the interconnection delay of the FPGA can tolerate multiple cycles. The core particle simulation platform built by this method has a higher running speed than the core particle simulator and is easier to support various types of core particles. It is simpler than the traditional FPGA verification platform construction method and more suitable for the design mode of core particles.

[0182] 2. Controller design method.

[0183] Technical solution: Use heterogeneous processors to implement, the host computer communicates with the controller through Ethernet, and the controller controls the chiplet platform. The interaction path between the controller and the chiplet platform includes data path, monitoring path, reset path and debugging path.

[0184] Beneficial effects: The controller adopts heterogeneous processor design, which is compatible with the fast development of hard-core processors and the interface expansion of programmable logic. Through a single controller, the hardware bitstream file of the core-grain platform and the executable file of the core-grain load program can be downloaded, the operation of the core-grain platform can be controlled, and the core-grain platform can be controlled and monitored during operation.

[0185] 3. Single-core node design method.

[0186] Technical solution: This design method configures external components for the core component, including interconnect components, system address mapping components, monitoring components, peripheral components, reset components, etc. After the configuration is completed, a complete single core project is generated. This process can be executed by the configuration software.

[0187] Beneficial effects: The method provides design ideas for core particle nodes and realizes the generation of a single core particle platform. The method includes the design of interactive components between core particles, a flexible peripheral support solution, and a control and monitoring method for core particles. The method can be completed by configuration software, and the parameters of peripheral components can be configured. Through the configuration software, the generation of a single core particle platform can be quickly realized.

[0188] 4. Multi-core combination generation and downloading method.

[0189] Technical solution: This method describes the steps of generating and downloading a multi-chip combination, as well as how to insert a hardware probe during the generation process and the hardware debugging method of the multi-chip combination during operation.

[0190] Beneficial effects: The method realizes the configuration and generation of multiple core-grain nodes. The method can realize the automatic download of multiple core-grain platform executable files through Ethernet. The method can insert hardware probes in a single core-grain project and configure the controller to debug the core-grain hardware during operation.

[0191] 5. Core particle operation control method.

[0192] Technical solution: This method describes the loading and running strategy of the core particle internal program, as well as the running process monitoring method.

[0193] Beneficial effects: The method proposes a method for writing multiple core-grain load programs and a method for communication between core-grain load programs. The method provides how to load multiple program executable files into corresponding storage locations through data paths, and provides a software monitoring strategy when the core-grain is running. After the operation is completed, the operation data of the core-grain can be further obtained.

[0194] Reference Fig. 9 The embodiment of the present application further provides a device for designing a core particle simulation platform, which can implement the above-mentioned method for designing a core particle simulation platform, and the device includes:

[0195] A platform design unit, used to determine a first topology structure of a core particle simulation platform; wherein the first topology structure includes a controller and a plurality of core particle nodes;

[0196] A controller design unit, used to determine a second topological structure of the controller; wherein the controller is used to implement operation control of the core particle simulation platform;

[0197] A core grain design unit, used to determine a third topological structure of each of the core grain nodes; wherein each of the core grain nodes includes a core grain component and an external component;

[0198] A core particle configuration unit, used for configuring a plurality of core particle nodes to be tested in the core particle simulation platform;

[0199] The core particle simulation unit is used to control the plurality of core particle nodes to be tested to perform simulation using the controller.

[0200] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0201] The embodiment of the present application also provides an electronic device, the electronic device includes a memory and a processor, the memory stores a computer program, and the processor implements the above-mentioned chiplet simulation platform design method when executing the computer program. The electronic device can be any smart terminal including a tablet computer, a car computer, etc.

[0202] It can be understood that the contents of the above method embodiments are all applicable to the present device embodiments, the functions specifically implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0203] See also Fig.10 , Fig.10 The hardware structure of an electronic device of another embodiment is illustrated, and the electronic device includes:

[0204] The processor 1001 may be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application;

[0205] The memory 1002 can be implemented in the form of a read-only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory 1002 can store an operating system and other application programs. When the technical solution provided in the embodiment of this specification is implemented by software or firmware, the relevant program code is stored in the memory 1002, and the processor 1001 calls and executes a chip simulation platform design method of the embodiment of this application;

[0206] Input / output interface 1003, used to implement information input and output;

[0207] The communication interface 1004 is used to realize the communication interaction between the device and other devices. The communication can be realized through a wired manner (such as USB, network cable, etc.) or a wireless manner (such as mobile network, WIFI, Bluetooth, etc.);

[0208] A bus 1005 , which transmits information between various components of the device (e.g., the processor 1001 , the memory 1002 , the input / output interface 1003 , and the communication interface 1004 );

[0209] The processor 1001 , the memory 1002 , the input / output interface 1003 and the communication interface 1004 are connected to each other in communication within the device via the bus 1005 .

[0210] An embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the above-mentioned core particle simulation platform design method is implemented.

[0211] It can be understood that the contents of the above method embodiments are all applicable to the present storage medium embodiments, the functions specifically implemented by the present storage medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0212] The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0213] The embodiments described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0214] Those skilled in the art will appreciate that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0215] The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0216] Those skilled in the art will appreciate that all or some of the steps in the methods disclosed above, and the functional modules / units in the systems and devices may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0217] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0218] It should be understood that in the present application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0219] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0220] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0221] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0222] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM), disk or optical disk and other media that can store programs.

[0223] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. A method for designing a core particle simulation platform, characterized in that: The method comprises the following steps: Determine a first topology structure of a core particle simulation platform; wherein the first topology structure includes a controller and a plurality of core particle nodes; Determining a second topological structure of the controller; wherein the controller is used to implement operation control of the core particle simulation platform; Determine a third topological structure of each of the core-grain nodes; wherein each of the core-grain nodes includes a core-grain component and an external component; configuring a plurality of the core-grain nodes to be tested in the core-grain simulation platform; The controller is used to control a plurality of the core particle nodes to be tested to perform simulation.

2. A method for designing a core particle simulation platform according to claim 1, characterized in that: Determining the first topological structure of the core particle simulation platform comprises the following steps: Determine the number and topological relationship of each of the core particle nodes; determining the type and location of the controller; Determining the spatial size and position of the storage chip of each of the core particles; Determine the control signals and interconnection methods of each of the core particle nodes.

3. A method for designing a core particle simulation platform according to claim 2, characterized in that: The method further comprises the following steps: The peripheral circuits of each of the core node are arranged in the first topology structure.

4. A method for designing a core particle simulation platform according to claim 1, characterized in that: Determining the second topology of the controller comprises the following steps: Determine the external path of the controller; wherein the external path includes a data path, a monitoring path, a reset path and a debugging path; The data path is set as a first on-chip network; wherein the data path is used to connect each of the core grain nodes; transmit the executable files of each of the core grain nodes to the corresponding storage chip; after the core grain ends running, provide the controller with the data of the storage chip; The monitoring path is set as a second on-chip network; wherein the monitoring path is used to obtain data of the monitoring module and transmit data of the virtual peripheral; the monitoring path is sent from the host computer to the controller via Ethernet, and then forwarded to the programmable logic through the controller, and the programmable logic is sent to each of the core grain nodes after protocol conversion of the second on-chip network; The reset path is set to include a first reset path of the chiplet simulation platform and a second reset path of each chiplet node; wherein the controller uses corresponding reset signals to control the reset of multiple chiplet nodes and the reset of a single chiplet node through the first reset path and the second reset path respectively; The debugging path is set to include a first debugging path of the hard-core processor and a second debugging path of the JTAG interface; wherein the debugging path is used to provide a burning and debugging path for each of the core grain nodes; the first debugging path is used to realize the transmission of the hardware bitstream file of each of the core grain nodes from Ethernet to the cache of the controller, and then the programmable logic converts the hardware bitstream file into a JTAG signal; the second debugging path is used to burn the hardware bitstream file through an external JTAG debugger.

5. A method for designing a core particle simulation platform according to claim 1, characterized in that: The determining of the third topological structure of each of the core-grain nodes, wherein each of the core-grain nodes includes a core-grain component and an external component, comprises the following steps: Setting the type of the core particle component of each core particle node and the interface of each type; Setting the type of the external components of each of the core grain nodes; wherein the external components include an interconnect component, an address mapping component, a monitoring component, a peripheral component and a reset component; The interconnection component includes a first on-chip network router and a second on-chip network router; the first on-chip network router is connected to the data path of the core grain node, serves as an adaptation interface of the core grain component, and communicates with the core grain components in other adjacent core grain nodes; the second on-chip network router is used to transmit information of the monitoring component and the peripheral component to the controller; The address mapping component is used to record the physical location identification ID of each of the core grain nodes and the mapping relationship between the physical location identification ID and the physical access address; The monitoring component is used to monitor the operating status of each of the core grain nodes and the operating status of the core grain components; The peripheral components include real peripherals and virtual peripherals; wherein the real peripherals are preset when the core particle simulation platform is designed; the virtual peripherals use the programmable logic resources in the FPGA to simulate the input and output of each core particle node; The service component is used to connect to a reset path in the controller.

6. A method for designing a core particle simulation platform according to claim 1, characterized in that: The step of configuring a plurality of the core-grain nodes to be tested in the core-grain simulation platform comprises the following steps: Determine an address mapping table according to the position of each of the core grain nodes; Selecting a core-grain component to be tested from each of the core-grain nodes and configuring an external component for the core-grain component; Inserting a test probe into each of the configured core-grain nodes to generate a core-grain project; Generate a hardware bitstream file according to the core grain project; The hardware bitstream file is downloaded to the chip simulation platform for testing.

7. A method for designing a core particle simulation platform according to any one of claims 1 to 6, characterized in that: The use of the controller to control the plurality of core grain nodes to be tested to perform simulation comprises the following steps: Receiving a load program of each of the core particle nodes; Loading the executable file corresponding to the load program into the storage chip corresponding to the core grain node through the controller; Starting the executable file in each of the core grain nodes through a reset path of the controller; Obtaining the running information of each of the core grain nodes when running the executable file; After each of the core grain nodes finishes running the executable file, reading the execution result; The operation information and the execution result are uploaded to a host computer so that the host computer can analyze the simulation results of each of the core particle nodes.

8. A core particle simulation platform design device, characterized in that: The device comprises: A platform design unit, configured to determine a first topology structure of a core particle simulation platform; wherein the first topology structure includes a controller and a plurality of core particle nodes; A controller design unit, used to determine a second topological structure of the controller; wherein the controller is used to implement operation control of the core particle simulation platform; A core grain design unit, used to determine a third topological structure of each of the core grain nodes; wherein each of the core grain nodes includes a core grain component and an external component; A core particle configuration unit, used for configuring a plurality of core particle nodes to be tested in the core particle simulation platform; The core particle simulation unit is used to control the plurality of core particle nodes to be tested to perform simulation using the controller.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method according to any one of claims 1 to 7 is implemented.

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