Time domain parallel WTA circuit and control method thereof

Abstract

The invention provides a time domain parallel WTA circuit and a control method thereof, and relates to the field of integrated circuits. The WTA circuit comprises switch control circuits, a reset latch circuit and a common suppression circuit, wherein the number of the switch control circuits is the same as that of output neurons; a single-channel control signal generated by the reset latch circuit and a common suppression signal generated by the suppression circuit are respectively used for controlling the switch control circuit to realize a WTA mechanism; and when the output signal reaches the output end, the neuron which reaches the output end first keeps normal output, and the other neuron channels are closed until the control signal is reset. According to the method, the correctness of the WTA decision can be ensured under the condition that the time intervals of different output signals are relatively small, and meanwhile, the output of the winning party is not influenced, so that the high speed and the accuracy of time coding information are effectively improved, and the noise robustness and the stability of a nervous system are improved. And meanwhile, a parallel structure and a common suppression circuit mode are adopted, so that the integration density of the chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a time domain parallel WTA circuit and a control method thereof. Background Art

[0002] The concept of Winner-Takes-All (WTA) was originally inspired by biology, that is, when multiple neurons are connected to the same target neuron at the same time, only the neuron with the highest activation value will produce an output, and the output of other neurons will be suppressed in the brain. WTA technology plays a key role in many fields, especially in applications that require fast and parallel processing of a large number of signals. With the development of brain-like computing, the implementation of WTA at the hardware level has become particularly important. WTA circuits are often used to determine the most active or important input signals in the network, which helps to optimize the transmission and processing of information, reduce network power consumption and improve computing efficiency.

[0003] WTA circuits have a variety of comparison domains and structures. For WTA circuits in voltage or current domains with parallel structures, since they are based on analog circuits, DC current and additional external bias voltage are required, which occupies a large area and has a slow response speed; due to the analog calculation using parallel structures, the increase in the number of neurons will lead to a sharp decrease in circuit accuracy. In order to solve the problem of parallel structures, some scholars have proposed WTA circuits based on binary tree structures. In the binary tree structure, each pair of inputs competes with each other in the first stage to identify the one with higher voltage or current. Then, the local winner in the first stage participates in the next round of competition until the global winner is found. Due to the inherent characteristics of the binary tree, power consumption and silicon area will increase significantly as the number of inputs increases. In addition, the binary tree-based WTA also requires back-propagation logic to find the index of the winner, which requires additional power consumption, silicon area, and delay. Summary of the invention

[0004] Purpose of the invention: In view of the above problems raised by the prior art, the present invention proposes a time domain parallel WTA circuit, and further proposes a control method for the WTA circuit, which ensures the correctness of the WTA decision when the time intervals between different output signals are small, and ensures that the output of the winning party is not affected.

[0005] In order to achieve the above technical objectives, the technical solutions adopted by the present invention are as follows: A time domain parallel WTA circuit includes: a switch control circuit, a reset latch circuit and a shared inhibition circuit having the same number as the output neurons. The switch control circuit includes a first control terminal and a second control terminal; The first control terminal is connected to a first control signal, which is a common inhibition signal. The first control signal ensures that after the WTA circuit makes a decision, the channels from input to output of the remaining neurons are closed except for the earliest arriving neuron channel; The second control terminal is connected to the output terminal of the reset latch circuit to generate a second control signal, wherein the second control signal is a single-channel control signal, and the second control signal ensures that the neuron channel that generates the output earliest is not affected and can still generate the correct output; The reset latch circuit includes a high-level latch circuit, a low-level latch circuit and a second reset circuit; wherein the high-level and low-level latch circuits are used to latch the second control signal; the second reset circuit resets the second control signal to an initial state; the reset latch circuit outputs the second control signal and the input signal of the suppression circuit respectively; The inhibition circuit includes an inhibition signal latch circuit and a first reset circuit, wherein the first reset circuit resets the first control signal to an initial state; the inhibition signal latch circuit latches the first control signal; the inhibition circuit input end is connected to the reset latch circuit control signal output end of all neurons participating in the competition, and participates in controlling the on and off of the neuron competition channel by outputting the first control signal.

[0006] In a further embodiment, the switch control circuit includes a P-type transistor P1 and N-type transistors N1, N2, and N3; The drain of the P-type transistor P1 is connected to the drains of the N-type transistors N1 and N2 as the output signal of the switch control circuit, the source of the P-type transistor P1 is connected to the positive power supply, the sources of the N-type transistors N1 and N2 are connected to the drain of the N-type transistor N3, and the source of the N-type transistor N3 is grounded; The gates of the P-type transistor P1 and the N-type transistor N3 are connected to the input signal, the gate of the N-type transistor N1 is connected to the second control signal output terminal of the reset latch circuit, and the gate of the N-type transistor N2 is connected to the first control signal output terminal of the suppression circuit.

[0007] In a further embodiment, the low-level latch circuit includes an inverter INV1, a P-type transistor P2, and N-type transistors N4 and N5; The source of the P-type transistor P2 is connected to the positive power supply, the drain of P2 is connected to the drain of the N-type transistor N4 and the input end of the inverter INV1, the output end of the inverter INV1 is connected to the gate of the N-type transistor N5, the drain of the N-type transistor N5 is connected to the source of the N-type transistor N4, the source of the N-type transistor N5 is grounded, and the gates of the N-type transistor N4 and the P-type transistor P2 are connected to the output signal of the switch control circuit; When the input signal is at a low level, the second control signal is at a low level, and the low level is stored through the low level latch circuit.

[0008] In a further embodiment, the high-level latch circuit includes P-type transistors P3 and P4 and an N-type transistor N7; The gate of the N-type transistor N7 is connected to the drain of the P-type transistor P4, the source of the N-type transistor N7 is grounded, the source of the P-type transistor P4 is connected to the drain of the P-type transistor P3, the source of the P-type transistor P3 is connected to the positive power supply, the gate of the P-type transistor P3 is connected to the drain of the N-type transistor N7, the drain of the N-type transistor N7 is also connected to the input end of the suppression circuit, and the gate of the P-type transistor P4 is connected to the output signal of the switch control circuit; When the input signal is at a high level, the second control signal is at a high level, and the high level is stored through the high level latch circuit.

[0009] In a further embodiment, the inhibit signal latch circuit includes inverters INV2 and INV3 connected end to end; In one WTA decision cycle, the first control signal changes from high to low only once, and the high and low levels are latched by inverters INV2 and INV3 connected end to end; the second control signal changes from low to high only once, and the high and low levels are latched by the reset storage circuit of claim 1.

[0010] In a further embodiment, the first reset circuit includes a P-type transistor P5, the source of the P-type transistor P5 is connected to a positive power supply, the drain is connected to a first control signal, and the gate is connected to a clock signal CLK; when the clock signal CLK is at a low level, the first control signal is reset to a high level, and at this time all neuron signals participating in the competition can be correctly reflected at the output end.

[0011] In a further embodiment, the second reset circuit includes an N-type transistor N6, the drain of which is connected to the second control signal, the source is grounded, and the gate is connected to the opposite signal CLKB of the clock signal; when the clock signal CLK is at a high level, the second control signal is reset to a low level, and all single channels of neurons participating in the competition are closed.

[0012] Based on the structure of the time domain parallel WTA circuit disclosed above, the present invention also proposes a control method of the time domain parallel WTA circuit, which specifically includes the following process: (1) Reset stage: When the clock signal CLK is at a low level and the opposite signal CLKB of the clock signal is at a high level, the P-type transistor P5 is turned on, the first control signal Vinh is at a high level, the N-type transistor N6 is turned on, and the second control signal Vc2 is at a low level, so that the N-type transistor N1 is turned on, N2 is turned off, N5 is turned on, N7 is turned off, and the P-type transistor P3 is turned off; the input signal reaches the output end through the inverter composed of the P-type transistor P1, the N-type transistor N1, and the N-type transistor N3. In this stage, the single-channel privilege disappears, and the input of all neurons can be reflected at the output end; (2) Quiescent stage: At this time, all input signals Vin are at a low level, P-type transistor P1 is turned on, and the output signal Vout is connected to VDD through P-type transistor P1; P-type transistor P2 is turned off, N-type transistor N4 is turned on, and the second control signal Vc2 is reset to a low level. A high level is input to the gate of N-type transistor N5 through inverter INV1, and N-type transistor N5 is turned on. Inverter INV1, N-type transistor N5, and N-type transistor N4 form positive feedback to keep the second control signal Vc2 at a low level; N-type transistor N7 is turned off, Vinh is reset to a high level, P-type transistor P3 is turned off, Vout is at a high level, and P-type transistor P4 is turned off. In this stage, the second control signal Vc2 is latched to ensure the closure of the single-channel privilege, preparing for the subsequent competition stage; (3) Competition stage: When one of the competing neurons receives a high level first, the input signal Vin is high, the initial first control signal Vinh is high, the second control signal Vc2 is low, the N-type transistors N3 and N2 are turned on, the output signal Vout is low, the P-type transistor P2 is turned on, the N-type transistor N4 is turned off, the positive feedback of the second control signal Vc2 locks '0' and is automatically disconnected, Vc2 becomes high, the N-type transistor N7 is turned on, the first control signal Vinh is low, the P-type transistors P3 and P4 are turned on, and the N-type transistors N7, P-type transistors P3, and P-type transistors P4 form positive feedback to save '1'; since Vinh is a common inhibition signal, for other competing neurons, Vinh and Vc2 are both low, and the path from Vin to Vout is cut off; for the neuron that receives a high level first, Vc2 is high at this time, and the change of Vin can still be reflected in Vout, thereby realizing the winner-takes-all WTA mechanism.

[0013] Beneficial effects: The present invention proposes a time domain parallel WTA circuit and a control method thereof, which ensures the correctness of WTA decision-making when the time intervals between different output signals are small, and ensures that the output of the winning party is not affected. The present invention can effectively improve the high speed and accuracy of time-coded information through digital logic circuit control, overcome the influence of charge leakage by introducing positive feedback, and improve the stability and robustness of the nervous system. At the same time, the present invention adopts a parallel structure and a shared suppression circuit, which is conducive to improving the integration density of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 1 is a schematic diagram of a parallel structure WTA circuit structure in an embodiment.

[0015] Figure 2 is a WTA circuit in the embodiment.

[0016] Figure 31 is a diagram showing changes of the single-channel control signal and the common inhibition signal of the WTA circuit in three different stages in the embodiment.

[0017] Figure 4 This is the output pulse curve of the WTA circuit in the embodiment under the competition of three neurons. DETAILED DESCRIPTION

[0018] In the following description, a large number of specific details are provided to provide a more thorough understanding of the present invention. However, it is apparent to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features well known in the art are not described.

[0019] The purpose of this embodiment is to provide a WTA learning mechanism circuit with small area, high precision, low power consumption and high speed. The WTA circuit of this embodiment is composed of N switch control circuits, N reset latch circuits and a shared inhibition circuit, where the number N is the number of neurons participating in the competition.

[0020] Figure 1 The figure shows a schematic diagram of the parallel structure WTA circuit structure in which multiple neurons participate in competition. Multiple neuron channels are connected in parallel. When the neurons are in a resting state, the switch control circuits of all neurons are in an open state due to the high level of the common inhibition signal Vinh, and Vc2 is a low level. When one of the competing neurons receives a high level first, the common inhibition signal Vinh is pulled down, and the Vc2 of its own channel is increased. The neuron channel remains open, and the lagging neuron channel becomes closed due to the low level of the common inhibition signal Vc1 and the single-channel control signal Vc2, and the output end no longer reflects the input changes.

[0021] Figure 2 FIG. 2 shows a specific WTA implementation circuit in this embodiment. Figure 2 As shown, the WTA circuit consists of three parts: a switch control circuit, a reset latch circuit and an inhibition circuit. The switch control circuit includes a first control terminal and a second control terminal, wherein the first control terminal is connected to a first control signal, the first control signal is a common inhibition circuit output signal, and the first control signal ensures that after the WTA circuit makes a decision, the channels from input to output of the remaining neurons except for the earliest arriving neuron channel are closed. The second control terminal is connected to the output terminal of the reset latch circuit to generate a second control signal, and the second control signal is a single-channel control signal. The second control signal ensures that the neuron channel that generates the output earliest is not affected and can still generate the correct output. Specifically, referring to Figure 2In the left part, the switch control circuit is composed of a P-type transistor P1, and N-type transistors N1, N2, and N3. The drain of the P-type transistor P1 is connected to the drains of the N-type transistors N1 and N2 as the output signal of the switch control circuit, the source of the P-type transistor P1 is connected to the positive power supply, the sources of the N-type transistors N1 and N2 are connected to the drain of the N-type transistor N3, and the source of the N-type transistor N3 is grounded. The gates of the P-type transistor P1 and the N-type transistor N3 are connected to the input signal, the gate of the N-type transistor N1 is connected to the second control signal output terminal of the reset latch circuit, and the gate of the N-type transistor N2 is connected to the first control signal output terminal of the suppression circuit.

[0022] The reset latch circuit is composed of a high-level latch circuit, a low-level latch circuit and a second reset circuit. The high-level and low-level latch circuits are used to latch the second control signal; the second reset circuit resets the second control signal to the initial state; and the reset latch circuit outputs the second control signal and the input signal of the suppression circuit respectively. Specifically, refer to Figure 2 In the middle part, the low-level latch circuit includes an inverter INV1, a P-type transistor P2, and N-type transistors N4 and N5. The source of the P-type transistor P2 is connected to the positive power supply, the drain of P2 is connected to the drain of the N-type transistor N4, and the input of the inverter INV1, the output of the inverter INV1 is connected to the gate of the N-type transistor N5, the drain of the N-type transistor N5 is connected to the source of the N-type transistor N4, the source of the N-type transistor N5 is grounded, and the gates of the N-type transistor N4 and the P-type transistor P2 are connected to the output signal of the switch control circuit. The high-level latch circuit includes P-type transistors P3, P4, and an N-type transistor N7. The gate of N-type transistor N7 is connected to the drain of P-type transistor P4, the source of N-type transistor N7 is grounded, the source of P-type transistor P4 is connected to the drain of P-type transistor P3, the source of P-type transistor P3 is connected to the positive power supply, the gate of P-type transistor P3 is connected to the drain of N-type transistor N7, the drain of N-type transistor N7 is also connected to the input end of the suppression circuit, and the gate of P-type transistor P4 is connected to the output signal of the switch control circuit. The second reset circuit includes N-type transistor N6, the drain of N-type transistor N6 is connected to the second control signal, the source is grounded, and the gate is connected to the opposite signal CLKB of the clock signal; when the clock signal CLK is high, the second control signal is reset to a low level, and at this time, all the single channels of neurons participating in the competition are closed.

[0023] The suppression circuit is composed of a suppression signal latch circuit and a first reset circuit. The first reset circuit resets the first control signal to an initial state; the suppression signal latch circuit latches the first control signal; the suppression circuit input end is connected to the reset latch circuit control signal output end of all neurons participating in the competition, and participates in controlling the on and off of the neuron competition channel by outputting the first control signal. Specifically, refer to Figure 2Right part: The inhibition signal latch circuit includes inverters INV2 and INV3 connected end to end; in one WTA decision cycle, the first control signal changes from high to low only once, and the high and low levels are latched by inverters INV2 and INV3 connected end to end. The second control signal also changes from low to high only once, and the high and low levels are latched by the reset storage circuit described in claim 1. The first reset circuit includes a P-type transistor P5, the source of the P-type transistor P5 is connected to the positive power supply, the drain is connected to the first control signal, and the gate is connected to the clock signal CLK; when the clock signal CLK is at a low level, the first control signal is reset to a high level, and at this time, all the competing neuron signals can be correctly reflected at the output end.

[0024] The specific working status of the WTA circuit is as follows: (1) Reset stage: When the clock signal CLK is at a low level and the opposite signal CLKB of the clock signal is at a high level, the P-type transistor P5 is turned on, the first control signal Vinh is at a high level, the N-type transistor N6 is turned on, and the second control signal Vc2 is at a low level, so that the N-type transistor N1 is turned on, N2 is turned off, N5 is turned on, N7 is turned off, and the P-type transistor P3 is turned off; the input signal reaches the output end through the inverter composed of the P-type transistor P1, the N-type transistor N1, and the N-type transistor N3. In this stage, the single-channel privilege disappears, and the input of all neurons can be reflected at the output end; (2) Quiescent stage: At this time, all input signals Vin are at a low level, P-type transistor P1 is turned on, and the output signal Vout is connected to VDD through P-type transistor P1; P-type transistor P2 is turned off, N-type transistor N4 is turned on, and the second control signal Vc2 is reset to a low level. A high level is input to the gate of N-type transistor N5 through inverter INV1, and N-type transistor N5 is turned on. Inverter INV1, N-type transistor N5, and N-type transistor N4 form positive feedback to keep the second control signal Vc2 at a low level; N-type transistor N7 is turned off, Vinh is reset to a high level, P-type transistor P3 is turned off, Vout is at a high level, and P-type transistor P4 is turned off. In this stage, the second control signal Vc2 is latched to ensure the closure of the single-channel privilege, preparing for the subsequent competition stage; (3) Competition stage: When one of the competing neurons receives a high level first, the input signal Vin is high, the initial first control signal Vinh is high, the second control signal Vc2 is low, the N-type transistors N3 and N2 are turned on, the output signal Vout is low, the P-type transistor P2 is turned on, the N-type transistor N4 is turned off, the positive feedback of the second control signal Vc2 locks '0' and is automatically disconnected, Vc2 becomes high, the N-type transistor N7 is turned on, the first control signal Vinh is low, the P-type transistors P3 and P4 are turned on, and the N-type transistors N7, P-type transistors P3, and P-type transistors P4 form positive feedback to save '1'; since Vinh is a common inhibition signal, for other competing neurons, Vinh and Vc2 are both low, and the path from Vin to Vout is cut off; for the neuron that receives a high level first, Vc2 is high at this time, and the change of Vin can still be reflected in Vout.

[0025] Figure 3 The figure shows the changing curves of the first control signal and the second control signal at different stages. When working in the reset stage, CLK is at a low level, the first control signal Vinh is reset to a high level, and the second control signals Vc20, Vc21, and Vc22 are reset to a low level (taking three neurons as an example); when CLK changes from a low level to a high level, and the neurons are not excited, the circuit works in a resting stage, and the first control signal and the second control signal are maintained in the reset stage state because of their respective latch circuits; when the first neuron generates a high level first, the circuit works in a competitive state, the common inhibition signal Vinh becomes a low level, the single-channel control signal Vc20 of channel 0 becomes a high level, and the single-channel control signals of the remaining channels remain at a low level, thereby realizing the WTA mechanism.

[0026] Figure 4 It is shown that when the three neurons compete for the first time, Vin0 receives a high level at 6 ns, Vin1 at 6.5 ns, and Vin2 at 7 ns. Vin0 wins and generates a spike signal, inhibiting the excitation of the other two neurons. The other two excitation times of Vin0 are 8 ns and 10 ns, respectively. It can be seen that Vo0 can reflect the change of Vin0. No matter how the subsequent input of Vin1 and Vin2 changes, their respective outputs remain unchanged and remain at a high level. Taking the scheme as an example, the neuron WTA learning mechanism of the present invention can be accurate to 0.5 ns.

[0027] In summary, the present invention adopts a time domain WTA circuit with a parallel structure. The time domain parallel WTA circuit has significant advantages. By converting the input size difference in the voltage or current domain into a time difference in the time domain and using time information to encode the strength of the input signal, it is easier to integrate with a digital integrated circuit and avoid complex analog signal processing components; by accurately measuring the time interval to improve the accuracy of signal processing, quickly respond to input signal changes, and be robust to noise and interference; the parallel structure overcomes the disadvantage of the tree structure occupying a large area. On this basis, the present invention uses multiple latch structures to effectively overcome the possible charge leakage problem during the circuit operation process, improve the accuracy of WTA decision-making, and have high reliability.

[0028] Although the steps in this embodiment are arranged with numbers, they are not used to limit the order of the steps. Unless the order of the steps is clearly stated or the execution of a certain step requires other steps as a basis, the relative order of the steps can be adjusted. It is understood that the term "and / or" used in this article involves and covers any and all possible combinations of one or more of the associated listed items.

[0029] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A time domain parallel WTA circuit, characterized in that: It includes switch control circuits, reset latch circuits and a shared inhibition circuit, which are the same in number as the output neurons; The switch control circuit includes a first control terminal and a second control terminal; The first control terminal is connected to a first control signal, the first control signal is a common inhibition signal, and the first control signal ensures that after the WTA circuit makes a decision, the channels from input to output of the remaining neurons except for the earliest arriving neuron channel are closed; The second control terminal is connected to the output terminal of the reset latch circuit to generate a second control signal, wherein the second control signal is a single-channel control signal, and the second control signal ensures that the neuron channel that generates the output earliest is not affected and can still generate the correct output; The reset latch circuit includes a high-level latch circuit, a low-level latch circuit and a second reset circuit; wherein the high-level and low-level latch circuits are used to latch the second control signal; the second reset circuit resets the second control signal to an initial state; the reset latch circuit outputs the second control signal and the input signal of the suppression circuit respectively; The inhibition circuit includes an inhibition signal latch circuit and a first reset circuit, wherein the first reset circuit resets the first control signal to an initial state; the inhibition signal latch circuit latches the first control signal; the inhibition circuit input end is connected to the reset latch circuit control signal output end of all neurons participating in the competition, and participates in controlling the on and off of the neuron competition channel by outputting the first control signal.

2. The time domain parallel WTA circuit according to claim 1, characterized in that: The switch control circuit includes a P-type transistor P1 and N-type transistors N1, N2, N3; The drain of the P-type transistor P1 is connected to the drains of the N-type transistors N1 and N2 as the output signal of the switch control circuit, the source of the P-type transistor P1 is connected to the positive power supply, the sources of the N-type transistors N1 and N2 are connected to the drain of the N-type transistor N3, and the source of the N-type transistor N3 is grounded; The gates of the P-type transistor P1 and the N-type transistor N3 are connected to the input signal, the gate of the N-type transistor N1 is connected to the second control signal output terminal of the reset latch circuit, and the gate of the N-type transistor N2 is connected to the first control signal output terminal of the suppression circuit.

3. The time domain parallel WTA circuit according to claim 1, characterized in that: The low-level latch circuit includes an inverter INV1, a P-type transistor P2, and N-type transistors N4 and N5; The source of the P-type transistor P2 is connected to the positive power supply, the drain of P2 is connected to the drain of the N-type transistor N4 and the input end of the inverter INV1, the output end of the inverter INV1 is connected to the gate of the N-type transistor N5, the drain of the N-type transistor N5 is connected to the source of the N-type transistor N4, the source of the N-type transistor N5 is grounded, and the gates of the N-type transistor N4 and the P-type transistor P2 are connected to the output signal of the switch control circuit; When the input signal is at a low level, the second control signal is at a low level, and the low level is stored through the low level latch circuit.

4. The time domain parallel WTA circuit according to claim 1, characterized in that: The high-level latch circuit includes P-type transistors P3 and P4 and an N-type transistor N7; The gate of the N-type transistor N7 is connected to the drain of the P-type transistor P4, the source of the N-type transistor N7 is grounded, the source of the P-type transistor P4 is connected to the drain of the P-type transistor P3, the source of the P-type transistor P3 is connected to the positive power supply, the gate of the P-type transistor P3 is connected to the drain of the N-type transistor N7, the drain of the N-type transistor N7 is also connected to the input end of the suppression circuit, and the gate of the P-type transistor P4 is connected to the output signal of the switch control circuit; When the input signal is at a high level, the second control signal is at a high level, and the high level is stored through the high level latch circuit.

5. The time domain parallel WTA circuit according to claim 1, characterized in that: The inhibition signal latch circuit includes inverters INV2 and INV3 connected end to end; In one WTA decision cycle, the first control signal changes from high to low only once, and the high and low levels are latched by inverters INV2 and INV3 connected end to end; the second control signal changes from low to high only once, and the high and low levels are latched by the reset storage circuit described in claim 1.

6. The time domain parallel WTA circuit according to claim 1, characterized in that: The first reset circuit includes a P-type transistor P5, a source of the P-type transistor P5 is connected to a positive power supply, a drain is connected to a first control signal, and a gate is connected to a clock signal CLK; when the clock signal CLK is at a low level, the first control signal is reset to a high level, and at this time all neuron signals participating in the competition can be correctly reflected at the output end.

7. The time domain parallel WTA circuit according to claim 1, characterized in that: The second reset circuit includes an N-type transistor N6, the drain of which is connected to the second control signal, the source is grounded, and the gate is connected to the opposite signal CLKB of the clock signal; when the clock signal CLK is at a high level, the second control signal is reset to a low level, and all single channels of neurons participating in the competition are closed.

8. The control method of the time domain parallel WTA circuit according to any one of claims 1 to 7, characterized in that: The steps include: (1) Reset stage: When the clock signal CLK is at a low level and the opposite signal CLKB of the clock signal is at a high level, the P-type transistor P5 is turned on, the first control signal Vinh is at a high level, the N-type transistor N6 is turned on, and the second control signal Vc2 is at a low level, so that the N-type transistor N1 is turned on, N2 is turned off, N5 is turned on, N7 is turned off, and the P-type transistor P3 is turned off; the input signal reaches the output end through the inverter composed of the P-type transistor P1, the N-type transistor N1, and the N-type transistor N3. The single-channel privilege disappears in the reset stage, and the input of all neurons can be reflected at the output end; (2) Quiescent stage: At this time, all input signals Vin are at a low level, P-type transistor P1 is turned on, and the output signal Vout is connected to VDD through P-type transistor P1; P-type transistor P2 is turned off, N-type transistor N4 is turned on, and the second control signal Vc2 is reset to a low level. A high level is input to the gate of N-type transistor N5 through inverter INV1, and N-type transistor N5 is turned on. Inverter INV1, N-type transistor N5, and N-type transistor N4 form positive feedback to keep the second control signal Vc2 at a low level; N-type transistor N7 is turned off, Vinh is reset to a high level, P-type transistor P3 is turned off, Vout is at a high level, and P-type transistor P4 is turned off. In the quiescent stage, the second control signal Vc2 is latched to ensure the closure of the single-channel privilege, preparing for the subsequent competition stage; (3) Competition stage: When one of the competing neurons receives a high level first, the input signal Vin is high, the initial first control signal Vinh is high, the second control signal Vc2 is low, the N-type transistors N3 and N2 are turned on, the output signal Vout is low, the P-type transistor P2 is turned on, the N-type transistor N4 is turned off, the positive feedback of the second control signal Vc2 locks '0' and is automatically disconnected, Vc2 becomes high, the N-type transistor N7 is turned on, the first control signal Vinh is low, the P-type transistors P3 and P4 are turned on, and the N-type transistor N7, the P-type transistor P3, and the P-type transistor P4 form a positive feedback to save '1'; since Vinh is a common inhibition signal, for other competing neurons, Vinh and Vc2 are both low, and the path from Vin to Vout is cut off; for the neuron that receives a high level first, Vc2 is high at this time, and the change of Vin can still be reflected in Vout, thereby realizing the WTA mechanism.

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