Time domain parallel wta circuit and its control method

Abstract

The application provides a time domain parallel WTA circuit and a control method thereof, and relates to the field of integrated circuits.The WTA circuit comprises the same number of switch control circuits as output neurons, a reset latch circuit and a shared inhibition circuit; the switch control circuit is controlled to realize the WTA mechanism by generating a single-channel control signal through the reset latch circuit and generating a shared inhibition signal through the inhibition circuit; when the output signal reaches the output end, the neuron that reaches the output end first keeps its normal output, and the channels of the remaining neurons are closed until the reset control signal.The application can ensure the correctness of the WTA decision under the condition that the time interval of different output signals is small, ensure the output of the winning side is not affected, effectively improve the high speed and accuracy of time coding information, and improve the noise robustness and stability of the nervous system.Meanwhile, the application adopts the parallel structure and the shared inhibition circuit mode, which is beneficial to improving the integration density of the chip.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a time-domain parallel WTA circuit and a control method thereof. BACKGROUND

[0002] The concept of Winner-Takes-All (WTA) is originally inspired from biology, where when multiple neurons are connected to the same target neuron, only the neuron with the highest activation value will produce an output, and the outputs of other neurons are inhibited in the brain. WTA technology plays a key role in many fields, especially in applications that require fast and parallel processing of large amounts of signals. With the development of brain-like computing, the implementation of WTA at the hardware level becomes particularly important. WTA circuits are often used to determine the most active or most important input signal in a network, which helps to optimize the transmission and processing of information, reduce network power consumption and improve computing efficiency.

[0003] There are various comparison domains and structures for WTA circuits. For WTA circuits using parallel structures in voltage or current domains, due to the use of analog circuits, direct current and additional external bias voltage are required, which occupies a large area and has slow reaction speed. Due to the use of parallel structure analog computing, the increase in the number of neurons will cause the accuracy of the circuit to decrease sharply. In order to solve the problem of parallel structure, some scholars have proposed a WTA circuit based on binary tree structure. In the binary tree structure, each pair of inputs competes with each other in the first stage to identify the one with higher voltage or current. Then, the local winners of the first stage participate in the next round of competition until the global winner is found. Due to the inherent characteristics of the binary tree, as the number of inputs increases, the power consumption and silicon area will increase significantly. In addition, the WTA based on binary tree also needs backpropagation logic to find the index of the winner, which requires additional power consumption, silicon area and delay. SUMMARY

[0004] The present application proposes a time-domain parallel WTA circuit to solve the above problems in the prior art, and further proposes a control method for the WTA circuit, which ensures the correctness of WTA decision-making when the time interval of different output signals is small, and ensures that the output of the winning side is not affected.

[0005] To achieve the above technical purposes, the technical solutions adopted by the present application are as follows:

[0006] A time-domain parallel WTA circuit, comprising: a number of switch control circuits equal to the number of output neurons, a reset latch circuit, and a shared inhibition circuit. Wherein:

[0007] The switch control circuit comprises a first control end and a second control end;

[0008] The first control terminal is connected with a first control signal, and the first control signal is a common inhibition signal. The first control signal ensures that, after decision by the WTA circuit, the channels of the neurons other than the earliest-arriving neuron are closed from input to output.

[0009] The second control terminal is connected with an output terminal of a reset latch circuit to generate a second control signal. The second control signal is a single-channel control signal. The second control signal ensures that the channel of the neuron that generates the earliest output is not affected and can still generate correct output.

[0010] The reset latch circuit includes a high-level latch circuit, a low-level latch circuit, and a second reset circuit. The high-level and low-level latch circuits are used to latch the second control signal. The second reset circuit resets the second control signal to an initial state. The reset latch circuit outputs the second control signal and an input signal of the inhibition circuit.

[0011] The inhibition circuit includes an inhibition signal latch circuit and a first reset circuit. The first reset circuit resets the first control signal to an initial state. The inhibition signal latch circuit latches the first control signal. The input terminal of the inhibition circuit is connected with the control signal output terminals of the reset latch circuits of all the neurons participating in competition, and outputs the first control signal to participate in the control of the on-off of the neuron competition channel.

[0012] In a further embodiment, the switch control circuit includes a P-type transistor P1 and N-type transistors N1, N2, and N3.

[0013] The drain of the P-type transistor P1 and the drains of the N-type transistors N1 and N2 are connected as output signals of the switch control circuit. The source of the P-type transistor P1 is connected with a positive power supply. The sources of the N-type transistors N1 and N2 are connected with the drain of the N-type transistor N3. The source of the N-type transistor N3 is connected with a ground.

[0014] The gates of the P-type transistor P1 and the N-type transistor N3 are connected with an input signal. The gate of the N-type transistor N1 is connected with the second control signal output terminal of the reset latch circuit. The gate of the N-type transistor N2 is connected with the first control signal output terminal of the inhibition circuit.

[0015] In a further embodiment, the low-level latch circuit includes an inverter INV1, a P-type transistor P2, and N-type transistors N4 and N5.

[0016] The source of the P-type transistor P2 is connected with a positive power supply. The drain of P2 is connected with the drain of the N-type transistor N4 and the input terminal of the inverter INV1. The output terminal of the inverter INV1 is connected with the gate of the N-type transistor N5. The drain of the N-type transistor N5 is connected with the source of the N-type transistor N4. The source of the N-type transistor N5 is connected with a ground. The gates of the N-type transistor N4 and the P-type transistor P2 are connected with the output signal of the switch control circuit.

[0017] When the input signal is low, the second control signal is low, and the low level is saved through the low level latch circuit.

[0018] In a further embodiment, the high level latch circuit comprises P-type transistors P3 and P4 and N-type transistor N7.

[0019] The gate of the N-type transistor N7 is connected to the drain of the P-type transistor P4, the source of the N-type transistor N7 is grounded, the source of the P-type transistor P4 is connected to the drain of the P-type transistor P3, the source of the P-type transistor P3 is connected to a positive power supply, the gate of the P-type transistor P3 is connected to the drain of the N-type transistor N7, the drain of the N-type transistor N7 is connected to the input of the inhibition circuit, and the gate of the P-type transistor P4 is connected to the output signal of the switch control circuit.

[0020] When the input signal is high, the second control signal is high, and the high level is saved through the high level latch circuit.

[0021] In a further embodiment, the inhibition signal latch circuit comprises inverters INV2 and INV3 connected in series.

[0022] In one WTA decision cycle, the first control signal changes from high to low only once, and the high and low levels are latched through the inverters INV2 and INV3 connected in series. The second control signal changes from low to high only once, and the high and low levels are latched through the reset circuit of claim 1.

[0023] In a further embodiment, the first reset circuit comprises a P-type transistor P5, the source of the P-type transistor P5 is connected to a positive power supply, the drain is connected to the first control signal, and the gate is connected to a clock signal CLK. When the clock signal CLK is low, the first control signal is reset to high, and at this time all the neuron signals participating in the competition can be correctly reflected on the output end.

[0024] In a further embodiment, the second reset circuit comprises an N-type transistor N6, the drain of the N-type transistor N6 is connected to the second control signal, the source is grounded, and the gate is connected to the inverse signal CLKB of the clock signal. When the clock signal CLK is high, the second control signal is reset to low, and at this time all the neuron single channels participating in the competition are closed.

[0025] Based on the structure of the time domain parallel WTA circuit disclosed above, the present application further proposes a control method of the time domain parallel WTA circuit, which specifically comprises the following processes:

[0026] (1) Reset stage: when the clock signal CLK is low and the opposite signal of the clock signal CLKB is high, the P-type transistor P5 is turned on, the first control signal Vinh is high, the N-type transistor N6 is turned on, and the second control signal Vc2 is low, so that the N-type transistor N1 is turned on, the N2 is turned off, the N5 is turned on, the N7 is turned off, and the P-type transistor P3 is turned off; the input signal reaches the output end through the inverter composed of the P-type transistor P1, the N-type transistor N1 and the N-type transistor N3, and in this stage, the single-channel privilege disappears, and the input of all neurons can be reflected on the output end;

[0027] (2) Resting stage: at this time, all input signals Vin are low, the P-type transistor P1 is turned on, and the output signal Vout is connected with VDD through the P-type transistor P1; the P-type transistor P2 is turned off, the N-type transistor N4 is turned on, the second control signal Vc2 is in the reset state of low level, the high level is input to the gate of the N-type transistor N5 through the inverter INV1, the N-type transistor N5 is turned on, the inverter INV1, the N-type transistor N5 and the N-type transistor N4 constitute positive feedback to keep the second control signal Vc2 at low level; the N-type transistor N7 is turned off, the Vinh is in the reset state of high level, the P-type transistor P3 is turned off, the Vout is high, and the P-type transistor P4 is turned off; in this stage, the second control signal Vc2 is latched to ensure the closing of the single-channel privilege, and to prepare for the subsequent competition stage;

[0028] (3) Competition stage: when one of the neurons participating in the competition accepts a high level first, the input signal Vin is high, the initial first control signal Vinh is high, the second control signal Vc2 is low, the N-type transistors N3 and N2 are turned on, the output signal Vout is low, the P-type transistor P2 is turned on, the N-type transistor N4 is turned off, the positive feedback of the second control signal Vc2 latched to '0' is automatically disconnected, Vc2 becomes high, the N-type transistor N7 is turned on, the first control signal Vinh is low, the P-type transistors P3 and P4 are turned on, and the N-type transistor N7, the P-type transistor P3 and the P-type transistor P4 constitute a positive feedback to save '1'; since Vinh is a common inhibition signal, for other competing neurons, Vinh and Vc2 are low, and the path from Vin to Vout is cut off; for the neuron that accepts a high level first, Vc2 is high at this time, and the change of Vin can still be reflected on Vout, thereby realizing the winner-takes-all (WTA) mechanism.

[0029] Beneficial effects: the present application proposes a time domain parallel WTA circuit and its control method, which ensures the correctness of WTA decision in the case of small time interval of different output signals, and ensures that the output of the winning side is not affected. The present application can effectively improve the speed and accuracy of time encoding information through digital logic circuit control method, and overcome the influence of charge leakage by introducing positive feedback, thereby improving the stability and robustness of the nervous system. At the same time, the present application adopts parallel structure and shared inhibition circuit, which is beneficial to improve the integration density of chip. BRIEF DESCRIPTION OF DRAWINGS

[0030] Figure 1 The figure is a parallel structure WTA circuit structure diagram in the embodiment.

[0031] Figure 2 The figure is a WTA circuit in the embodiment.

[0032] Figure 3 The figure is the change of single channel control signal and shared inhibition signal of WTA circuit in the embodiment in three different stages.

[0033] Figure 4 The figure is the output pulse curve of WTA circuit in the embodiment under the competition of three neurons. DETAILED DESCRIPTION

[0034] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present application. However, it is obvious to those skilled in the art that the present application can be implemented without one or more of these details. In other examples, some technical features known in the art are not described in order not to obscure the present application.

[0035] The purpose of the present embodiment is to provide a WTA learning mechanism circuit with small area, high precision, low power consumption and high speed. The WTA circuit of the present embodiment is composed of N switch control circuits, N reset latch circuits and a shared inhibition circuit. The number N is the number of neurons participating in the competition.

[0036] Figure 1 The figure is a parallel structure WTA circuit structure diagram with multiple neurons participating in the competition. Multiple neuron channels are connected in parallel. When the neurons are in a resting state, the switch control circuits of all neurons are in an open state at this time due to the high level of shared inhibition signal Vinh, and Vc2 is at a low level. When one of the neurons participating in the competition receives a high level first, the shared inhibition signal Vinh is pulled down, the Vc2 of the self channel is raised, and the neuron channel remains in an open state. The lagging neuron channel becomes closed due to the low levels of shared inhibition signal Vc1 and single channel control signal Vc2, and the output end no longer reflects the change of input.

[0037] Figure 2 The diagram shows a specific WTA implementation circuit in this embodiment. For example... Figure 2 As shown, the WTA circuit consists of three parts: a switch control circuit, a reset latch circuit, and a suppression circuit. The switch control circuit includes a first control terminal and a second control terminal. The first control terminal is connected to a first control signal, which is a shared output signal of the suppression circuit. This first control signal ensures that after the WTA circuit makes its decision, the input-to-output channels of all neurons except the earliest arriving neuron are closed. The second control terminal is connected to the output of the reset latch circuit to generate a second control signal. This second control signal is a single-channel control signal, ensuring that the earliest output neuron channel remains unaffected and can still produce a correct output. Specifically, refer to... Figure 2 The left part, the switch control circuit, consists of P-type transistor P1 and N-type transistors N1, N2, and N3. The drain of P-type transistor P1 is connected to the drains of N-type transistors N1 and N2 as the output signal of the switch control circuit. The source of P-type transistor P1 is connected to the positive power supply. The sources of N-type transistors N1 and N2 are connected to the drain of N-type transistor N3, and the source of N-type transistor N3 is grounded. The gates of P-type transistor P1 and N-type transistor N3 are connected to the input signals. The gate of N-type transistor N1 is connected to the second control signal output terminal of the reset latch circuit, and the gate of N-type transistor N2 is connected to the first control signal output terminal of the suppression circuit.

[0038] The reset latch circuit consists of three parts: a high-level latch circuit, a low-level latch circuit, and a second reset circuit. The high-level and low-level latch circuits latch the second control signal; the second reset circuit resets the second control signal to its initial state; and the reset latch circuit outputs both the second control signal and the input signal to the suppression circuit. Specifically, refer to... Figure 2The intermediate part, low level latch circuit contains inverter INV1, P-type transistor P2 and N-type transistor N4, N5. The source of P-type transistor P2 is connected to positive power supply, the drain of P2 is connected to the drain of N-type transistor N4, and the input of inverter INV1, the output of inverter INV1 is connected to the gate of N-type transistor N5, the drain of N-type transistor N5 is connected to the source of N-type transistor N4, the source of N-type transistor N5 is connected to ground, and the gates of N-type transistor N4 and P-type transistor P2 are connected to the output signal of switch control circuit. The high level latch circuit contains P-type transistor P3, P4 and N-type transistor N7. The gate of N-type transistor N7 is connected to the drain of P-type transistor P4, the source of N-type transistor N7 is connected to ground, the source of P-type transistor P4 is connected to the drain of P-type transistor P3, the source of P-type transistor P3 is connected to positive power supply, the gate of P-type transistor P3 is connected to the drain of N-type transistor N7, the drain of N-type transistor N7 is connected to the input of inhibition circuit, and the gate of P-type transistor P4 is connected to the output signal of switch control circuit. The second reset circuit contains N-type transistor N6, the drain of N-type transistor N6 is connected to the second control signal, the source is connected to ground, and the gate is connected to the opposite signal CLKB of clock signal. When the clock signal CLK is high, the second control signal is reset to low, at this time, all the single channels of neurons participating in competition are closed.

[0039] The inhibition circuit is composed of inhibition signal latch circuit and first reset circuit. The first reset circuit resets the first control signal to the initial state; the inhibition signal latch circuit latches the first control signal; the input of the inhibition circuit is connected to the control signal output end of the reset latch circuit of all neurons participating in competition, and controls the on-off of the competition channel of neurons through the output of the first control signal. Specifically, referring to Figure 2 The right part: the inhibition signal latch circuit includes inverters INV2 and INV3 connected in head-to-tail; in a WTA decision cycle, the first control signal changes from high to low only once, and the high and low levels are latched through the inverters INV2 and INV3 connected in head-to-tail. The second control signal changes from low to high only once, and the high and low levels are latched through the reset circuit claimed in claim 1. The first reset circuit includes P-type transistor P5, the source of P-type transistor P5 is connected to positive power supply, the drain is connected to the first control signal, and the gate is connected to the clock signal CLK; when the clock signal CLK is low, the first control signal is reset to high, at this time, all the signals of neurons participating in competition can be correctly reflected on the output end.

[0040] The specific working state of the WTA circuit is as follows:

[0041] (1) Reset stage: when the clock signal CLK is low and the opposite signal of the clock signal CLKB is high, the P-type transistor P5 is turned on, the first control signal Vinh is high, the N-type transistor N6 is turned on, and the second control signal Vc2 is low, so that the N-type transistor N1 is turned on, the N2 is turned off, the N5 is turned on, the N7 is turned off, and the P-type transistor P3 is turned off; the input signal reaches the output end through the inverter composed of the P-type transistor P1, the N-type transistor N1 and the N-type transistor N3, and the single-channel privilege disappears in this stage, and the input of all neurons can be reflected on the output end;

[0042] (2) Resting stage: at this time, all input signals Vin are low, the P-type transistor P1 is turned on, and the output signal Vout is connected with VDD through the P-type transistor P1; the P-type transistor P2 is turned off, the N-type transistor N4 is turned on, the second control signal Vc2 is in the reset state of low level, the high level is input to the gate of the N-type transistor N5 through the inverter INV1, the N-type transistor N5 is turned on, the inverter INV1, the N-type transistor N5 and the N-type transistor N4 constitute positive feedback to keep the second control signal Vc2 at low level; the N-type transistor N7 is turned off, the Vinh is in the reset state of high level, the P-type transistor P3 is turned off, the Vout is high, and the P-type transistor P4 is turned off; in this stage, the second control signal Vc2 is latched to ensure the closing of the single-channel privilege, and the subsequent competition stage is prepared;

[0043] (3) Competition stage: when one of the neurons participating in the competition accepts a high level first, the input signal Vin is high, the initial first control signal Vinh is high, the second control signal Vc2 is low, the N-type transistors N3 and N2 are turned on, the output signal Vout is low, the P-type transistor P2 is turned on, the N-type transistor N4 is turned off, the positive feedback of the second control signal Vc2 latched to '0' is automatically disconnected, Vc2 becomes high, the N-type transistor N7 is turned on, the first control signal Vinh is low, the P-type transistors P3 and P4 are turned on, and the N-type transistor N7, the P-type transistor P3 and the P-type transistor P4 constitute positive feedback to save '1'; since Vinh is a common inhibition signal, for other competing neurons, Vinh and Vc2 are low, and the path from Vin to Vout is cut off; for the neuron that accepts a high level first, Vc2 is high at this time, and the change of Vin can still be reflected on Vout.

[0044] Figure 3The first control signal and the second control signal are shown in different stages. When working in the reset stage, the first control signal Vinh is reset to the high level, and the second control signal Vc20, Vc21 and Vc22 is reset to the low level (taking three neurons as an example) when CLK is low. When CLK changes from low to high, and the neurons are not excited, the circuit works in the resting stage, and the first control signal and the second control signal are maintained in the state of the reset stage because the respective latch circuits are maintained in the state of the reset stage. When the first neuron produces a high level first, the circuit works in the competition state, the common inhibition signal Vinh becomes low, the single-channel control signal Vc20 of channel 0 becomes high, and the single-channel control signals of the remaining channels remain low, so that the control method realizes the WTA mechanism.

[0045] Figure 4 When the three neurons compete for the first time, Vin0 receives a high level at 6 ns, Vin1 receives a high level at 6.5 ns, and Vin2 receives a high level at 7 ns, respectively, and Vin0 wins to produce a spike signal, and inhibits the excitation of the other two neurons. The other two excitation times of Vin0 are 8 ns and 10 ns, respectively. It can be seen that Vo0 can reflect the change of Vin0, and the outputs of Vin1 and Vin2 remain unchanged at the high level regardless of the subsequent input change. Taking the scheme as an example, the neuron WTA learning mechanism of the application can be accurate to 0.5 ns.

[0046] In summary of the above embodiments, the application adopts a time domain WTA circuit with a parallel structure. The time domain parallel WTA circuit has the following advantages. The size difference of the input in the voltage or current domain is converted into the time difference in the time domain, the strength of the input signal is encoded by using time information, the circuit is more easily integrated with a digital integrated circuit, and complex analog signal processing elements are avoided. The accuracy of signal processing is improved by accurately measuring the time interval, the input signal change is quickly responded, and the robustness to noise and interference is high. The parallel structure overcomes the defect of large area occupied by the tree structure. On this basis, the application uses a plurality of latch structures to effectively overcome the possible charge leakage problem in the working process of the circuit, improve the correctness of the WTA decision, and has high reliability.

[0047] The steps in the embodiment are arranged by using labels, but are not used to limit the sequence of the steps. Unless the sequence of the steps is explicitly described or the execution of a step needs other steps as a basis, the relative sequence of the steps can be adjusted. It can be understood that the term “and / or” used in the present application relates to and covers any and all possible combinations of one or more of the associated listed items.

[0048] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; and although the present application has been described in detail with reference to the foregoing embodiments, it should be appreciated by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A time domain parallel WTA circuit, characterized by, The switch control circuit, the reset latch circuit and the shared inhibition circuit are the same as the number of output neurons; The switch control circuit comprises a first control end and a second control end; The first control end is connected with a first control signal, and the first control signal is a shared inhibition signal. The second control end is connected with an output end of the reset latch circuit to generate a second control signal, and the second control signal is a single-channel control signal. The high-level latch circuit is used for latching the second control signal. The second reset circuit resets the second control signal to an initial state.

2. The time domain parallel WTA circuit of claim 1, wherein, The reset latch circuit outputs the second control signal and the input signal of the inhibition circuit. The inhibition circuit comprises an inhibition signal latch circuit and a first reset circuit. The P-type transistor P1 and the N-type transistors N1, N2 and N3 are included in the switch control circuit.

3. The time domain parallel WTA circuit of claim 1, wherein, The drain of the P-type transistor P1 is connected with the drains of the N-type transistors N1 and N2 as the output signal of the switch control circuit. The source of the P-type transistor P1 is connected with a positive power supply. The source of the N-type transistor N3 is connected with a ground.

4. The time domain parallel WTA circuit of claim 1, wherein, The gates of the P-type transistor P1 and the N-type transistor N3 are connected with an input signal. The gate of the N-type transistor N1 is connected with a second control signal output end of the reset latch circuit. The gate of the N-type transistor N2 is connected with a first control signal output end of the inhibition circuit. The low-level latch circuit comprises an inverter INV1, a P-type transistor P2 and N-type transistors N4 and N5. The source of the P-type transistor P2 is connected with a positive power supply. The drain of the P-type transistor P2 is connected with the drain of the N-type transistor N4 and the input end of the inverter INV1. The output end of the inverter INV1 is connected with the gate of the N-type transistor N5. The drain of the N-type transistor N5 is connected with the source of the N-type transistor N4. The source of the N-type transistor N5 is connected with a ground. The gates of the N-type transistor N4 and the P-type transistor P2 are connected with the output signal of the switch control circuit. When the input signal is a low level, the second control signal is a low level, and the low level is saved through the low-level latch circuit. The high-level latch circuit comprises a P-type transistor P3, a P-type transistor P4 and a N-type transistor N7. The gate of the N-type transistor N7 is connected to the drain of the P-type transistor P4, the source of the N-type transistor N7 is connected to ground, the source of the P-type transistor P4 is connected to the drain of the P-type transistor P3, the source of the P-type transistor P3 is connected to a positive power supply, the gate of the P-type transistor P3 is connected to the drain of the N-type transistor N7, the drain of the N-type transistor N7 is connected to an input terminal of an inhibiting circuit, and the gate of the P-type transistor P4 is connected to an output signal of a switch control circuit. When the input signal is a high level, the second control signal is a high level, and the high level is saved through a high level latch circuit.

5. The time domain parallel WTA circuit of claim 1, wherein, The inhibiting signal latch circuit comprises inverters INV2 and INV3 connected in a head-to-tail manner. In one WTA decision cycle, the first control signal changes from high to low only once, and the high and low levels are latched through the inverters INV2 and INV3 connected in a head-to-tail manner; the second control signal changes from low to high only once, and the high and low levels are latched through the reset latch circuit.

6. The time domain parallel WTA circuit of claim 1, wherein, The first reset circuit comprises a P-type transistor P5, the source of the P-type transistor P5 is connected to a positive power supply, the drain is connected to the first control signal, and the gate is connected to a clock signal CLK; when the clock signal CLK is a low level, the first control signal is reset to a high level, at this time, all the neuron signals participating in the competition can be correctly reflected on the output terminal.

7. The time domain parallel WTA circuit of claim 1, wherein, The second reset circuit comprises an N-type transistor N6, the drain of the N-type transistor N6 is connected to the second control signal, the source is connected to ground, and the gate is connected to an inverse signal CLKB of the clock signal; when the clock signal CLK is a high level, the second control signal is reset to a low level, at this time, all the neuron single channels participating in the competition are closed.

8. The method of claim 1 to 7, wherein, The method comprises the following steps: (1) a reset stage: when the clock signal CLK is a low level and the inverse signal CLKB of the clock signal is a high level, the P-type transistor P5 is turned on, the first control signal Vinh is a high level, the N-type transistor N6 is turned on, the second control signal Vc2 is a low level, so that the N-type transistor N1 is turned on, the N2 is turned off, the N5 is turned on, the N7 is turned off, and the P-type transistor P3 is turned off; the input signal reaches the output terminal through the inverter composed of the P-type transistor P1, the N-type transistor N1 and the N-type transistor N3, the single channel privilege disappears in the reset stage, and the input of all neurons can be reflected on the output terminal; (2) a resting stage: at this time, all the input signals Vin are low levels, the P-type transistor P1 is turned on, and the output signal Vout is connected to the P-type transistor P1 and the VDD; the P-type transistor P2 is turned off, the N-type transistor N4 is turned on, the second control signal Vc2 is in a reset state of a low level, a high level is input to the gate of the N-type transistor N5 through the inverter INV1, the N-type transistor N5 is turned on, the inverter INV1, the N-type transistor N5 and the N-type transistor N4 constitute a positive feedback to make the second control signal Vc2 maintain at a low level; the N-type transistor N7 is turned off, the Vinh is in a reset state of a high level, the P-type transistor P3 is turned off, the Vout is a high level, the P-type transistor P4 is turned off, and the resting stage ensures the closing of the single channel privilege through the latching of the second control signal Vc2 to prepare for the subsequent competition stage. (3) Competition phase: when one of the competing neurons receives the high level first, the input signal Vin is high level, the initial first control signal Vinh is high level, the second control signal Vc2 is low level, the N-type transistor N3 and N2 are turned on, the output signal Vout is low level, the P-type transistor P2 is turned on, the N-type transistor N4 is cut off, the positive feedback of the second control signal Vc2 locking '0' is automatically disconnected, Vc2 becomes high level, the N-type transistor N7 is turned on, the first control signal Vinh is low level, the P-type transistor P3 and P4 are turned on, the N-type transistor N7, the P-type transistor P3 and the P-type transistor P4 constitute a positive feedback to save '1'; since Vinh is a common inhibition signal, for other competing neurons, Vinh and Vc2 are low level, the path from Vin to Vout is cut off; for the neuron that receives the high level first, Vc2 is high level at this time, the change of Vin can still be reflected in Vout, thereby realizing the WTA mechanism.

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