Storage unit, memory and preparation method thereof, and electronic equipment

Abstract

The invention relates to a storage unit, a memory and a preparation method thereof, and electronic equipment, relates to the technical field of storage, and aims to improve the performance and reliability of the storage unit and the memory. The memory cell includes a write transistor and a read transistor. The write transistor includes a first gate, a first source drain, and a second source drain. The read transistor includes a second gate, a third source drain, and a fourth source drain. The first grid electrode is electrically connected with the writing word line, the first source drain electrode is electrically connected with the writing bit line, and the second source drain electrode is electrically connected with the second grid electrode. The reading transistor further comprises a third grid electrode which is arranged on one side of the connecting part between the second source drain electrode and the second grid electrode in an insulating mode. Wherein the third grid electrode is electrically connected with the read word line, the fourth source drain electrode is electrically connected with the read bit line, and the third source drain electrode is electrically connected with the common source electrode line.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a storage unit, a memory and a preparation method thereof, and an electronic device. Background Art

[0002] With the development of communication technology and digital technology, people continue to pursue products with lower power consumption, lighter weight and better performance. Memory is easy to have higher integration density and larger storage capacity, and has gradually become one of the important research directions in the current storage field. For example, in the example of dynamic random access memory using 2T0C storage cells, it is easy to face problems such as read current multipath and read current crowding when reading data, which has an adverse effect on the performance of dynamic random access memory. Summary of the invention

[0003] Based on this, the embodiments of the present disclosure provide a storage unit, a memory and a method for preparing the same, and an electronic device, which are beneficial to improving the performance and reliability of the storage unit and the memory.

[0004] According to some embodiments, the present disclosure provides a storage unit on one hand, including: a write transistor and a read transistor; the write transistor includes a first gate, a first source and a drain, and a second source and a drain; the read transistor includes a second gate, a third source and a drain, and a fourth source and a drain; the first gate is electrically connected to a write word line, the first source and the drain are electrically connected to a write bit line, and the second source and the drain are electrically connected to the second gate. The read transistor also includes: a third gate, which is insulated and arranged on one side of the connection portion between the second source and the drain and the second gate; the third gate is electrically connected to the read word line, the fourth source and the drain are electrically connected to the read bit line, and the third source and the drain are electrically connected to the common source line.

[0005] According to some embodiments, the read bit line and the write bit line are arranged in parallel and spaced apart and extend along a first direction. The write transistor and the read transistor are arranged side by side in a second direction and are arranged in the space between the read bit line and the write bit line; the second direction intersects the first direction. The common source line surrounds the peripheral side of the read transistor and extends in a direction away from the read transistor. The center line of the common source line extends along the second direction.

[0006] According to some embodiments, the write transistor includes a first semiconductor layer; the read transistor includes a second semiconductor layer. The first gate and the write word line extend along a third direction; the third direction intersects both the first direction and the second direction. The first semiconductor layer is disposed around the periphery of the first gate, and the center line of the first semiconductor layer extends along the third direction; the portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source and drain, and the portion of the first semiconductor layer in contact with the second gate and located on the side of the first gate away from the first source and drain is the second source and drain. The second gate extends along the second direction, including: a first portion electrically connected to the second source and drain, and a second portion located on the side of the first portion away from the second source and drain and electrically connected to the first portion. The second semiconductor layer is disposed around the periphery of the second portion and on the side of the second portion away from the first portion. The center line of the second semiconductor layer extends along the second direction. The portion of the second semiconductor layer disposed around the periphery of the second portion and connected to the common source line is the third source and drain; the portion of the second semiconductor layer located on the side of the second portion away from the first portion is the fourth source and drain.

[0007] According to some embodiments, the third gate extends along a third direction. The third gate is insulated and disposed on one side of the first portion in the first direction.

[0008] According to some embodiments, the write transistor further includes a first gate dielectric layer; the read transistor further includes: a second gate dielectric layer and a third gate dielectric layer connected to each other. The first gate dielectric layer is located between the first gate and the first semiconductor layer. The second gate dielectric layer is located between the second portion and the second semiconductor layer. The third gate dielectric layer is disposed around the third gate and is connected to both the second gate dielectric layer and the second gate.

[0009] According to some embodiments, the write word line is multiplexed as the read word line during the data reading phase. The first gate is multiplexed as the third gate during the data reading phase.

[0010] According to some embodiments, a size of the first portion in the first direction is larger than a size of the second portion in the first direction, and a size of the first portion in the second direction is smaller than a size of the second portion in the second direction.

[0011] According to some embodiments, the write transistor further includes a first gate dielectric layer. The read transistor further includes: a second gate dielectric layer and a third gate dielectric layer connected to each other. The first gate dielectric layer is located between the first gate and the first semiconductor layer. The second gate dielectric layer is located between the second portion and the second semiconductor layer. The third gate dielectric layer is located between the first portion and the second semiconductor layer.

[0012] According to some embodiments, a size of the first semiconductor layer in the first direction is larger than a maximum size of the second gate in the first direction.

[0013] According to some embodiments, the present disclosure further provides a memory on the other hand, comprising one or more storage units as described in any one of the aforementioned embodiments.

[0014] According to some embodiments, the present disclosure further provides a data reading and writing method, which is applied to a memory as described in any of the above embodiments; the connection between the second source and drain of the write transistor and the second gate of the read transistor is a storage node of the storage unit. The data reading and writing method includes:

[0015] In the data writing phase, in response to a write command, the write bit line provides a data voltage to the write transistor; the write word line controls the write transistor to turn on, and the storage node is discharged to a stable state to write data corresponding to the data voltage.

[0016] In the data reading stage, in response to the read command, the read word line in the selected memory cell is set to a normal potential, and the read word line in the unselected memory cell is set to a low potential, so that the third gate connected to the read word line set to a low potential attracts more positive charges from the channel of the read transistor, and the read transistor in the unselected memory cell is in an electrically blocked state.

[0017] According to some embodiments, the write word line is multiplexed as the read word line in the data reading phase; the first gate is multiplexed as the third gate in the data reading phase.

[0018] In the data reading stage, in response to the read command, the read word line in the selected memory cell is set to a normal potential, and the read word line in the unselected memory cell is set to a low potential, so that the first gate connected to the read word line set to a low potential attracts more positive charges from the channel of the read transistor, and the read transistor in the unselected memory cell is in an electrically blocked state.

[0019] According to some embodiments, the present disclosure further provides a method for preparing a memory, comprising the following steps:

[0020] Depositing a first conductive material layer and an insulating material layer in sequence on the wafer to form a stacked structure;

[0021] forming read bit lines and write bit lines which are arranged in parallel and spaced apart and extend along a first direction;

[0022] A read transistor and a write transistor are formed in the interval between the read bit line and the write bit line and are arranged side by side in the second direction; the write transistor includes a first gate, a first source and a drain, and a second source and a drain; the read transistor includes a second gate, a third gate, a third source and a drain, and a fourth source and a drain; wherein the first source and the drain are electrically connected to the write bit line, the second source and the drain are electrically connected to the second gate, and the fourth source and the drain are electrically connected to the read bit line; the third gate is insulated and arranged on one side of the connection portion between the second source and the drain and the second gate; the first direction and the second direction intersect, and the first direction and the second direction are both parallel to the surface of the wafer;

[0023] forming a write word line electrically connected to the first gate;

[0024] forming a read word line electrically connected to the third gate;

[0025] A common source line electrically connected to the third source and drain is formed.

[0026] According to some embodiments, forming read bit lines and write bit lines arranged in parallel and extending in a first direction, and forming read transistors and write transistors arranged side by side in a second direction in the intervals between the read bit lines and the write bit lines, includes the following steps:

[0027] Forming a first conductive material layer and patterning the first conductive material layer to form a read bit line and a write bit line that are arranged in parallel and spaced apart, and a virtual gate located between and connecting the read bit line and the write bit line; wherein the read bit line and the write bit line extend along a first direction, and the virtual gate extends along a second direction;

[0028] Filling dielectric material on two opposite sides of the virtual gate in the first direction;

[0029] Etching the dummy gate and dielectric material in a first target area of ​​the dummy gate close to the write bit line to form an etching hole;

[0030] Based on the etching hole, the dummy gate is selectively etched along the second direction by wet etching to remove the retained dummy gate to form a receiving groove; the receiving groove exposes the corresponding side wall of the read bit line;

[0031] Depositing a semiconductor material layer, a gate dielectric material layer and a second conductive material layer in sequence on the inner wall of the receiving groove by an atomic layer deposition process;

[0032] The semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the etching hole are removed, so that the remaining gate dielectric material layer constitutes a second gate dielectric layer, and the remaining second conductive material layer constitutes a second gate electrode; and the semiconductor material layer in the second target area near the etching hole is removed, so that the remaining semiconductor material layer constitutes a second semiconductor layer, and the side wall of the second gate dielectric layer is exposed;

[0033] Removing the semiconductor material layer in the second target area near the etching hole, so that the remaining semiconductor material layer constitutes a second semiconductor layer and exposes the side wall of the second gate dielectric layer;

[0034] Etching dielectric material outside the side wall of the second gate exposed in the first direction to form a receiving hole; the receiving hole exposes the side wall of the second gate dielectric layer and the second semiconductor layer away from the read bit line;

[0035] forming a third gate dielectric layer and a third gate electrode in sequence in the receiving hole;

[0036] A first semiconductor layer, a first gate dielectric layer and a first gate electrode are sequentially formed on the hole wall of the etched hole to obtain a write transistor.

[0037] The portion of the second semiconductor layer surrounding the second gate and connected to the common source line is the third source and drain, and the portion of the second semiconductor layer located on the side of the second gate away from the first gate is the fourth source and drain. The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source and drain, and the portion of the first semiconductor layer extending along the first direction and located on the side of the first gate away from the first source and drain is the second source and drain. The write word line is formed synchronously with the first gate. The read word line is formed synchronously with the third gate.

[0038] According to some embodiments, the write word line is multiplexed as the read word line in the data reading stage, and the first gate is multiplexed as the third gate in the data reading stage. Forming read bit lines and write bit lines arranged in parallel and extending along a first direction, and forming read transistors and write transistors arranged side by side in a second direction in the interval between the read bit lines and the write bit lines, includes the following steps:

[0039] Forming a first conductive material layer, and patterning the first conductive material layer to form a read bit line and a virtual write bit line that are arranged in parallel and spaced apart, and a virtual gate located between the read bit line and the virtual write bit line and connected to the read bit line and the virtual write bit line; wherein the read bit line and the virtual write bit line extend along a first direction, and the virtual gate extends along a second direction;

[0040] Filling dielectric material on two opposite sides of the virtual gate in the first direction;

[0041] Etching the dummy gate and dielectric material in a first target area of ​​the dummy gate close to the dummy write bit line to form an etching hole;

[0042] Based on the etching hole, the dummy write bit line and the retained dummy gate are removed to form an accommodation space including the etching hole; the accommodation space exposes the corresponding side wall of the read bit line;

[0043] Depositing a semiconductor material layer, a gate dielectric material layer, and a second conductive material layer in sequence in the accommodating space;

[0044] removing the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the first target region, as well as the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the third target region and the fourth target region on both sides of the first target region along the second direction, so that the retained semiconductor material layer constitutes the second semiconductor layer, the retained gate dielectric material layer constitutes the second gate dielectric layer, the second conductive material layer retained on the side of the third target region close to the read bit line is the second part of the second gate, and the second conductive material layer retained on the side of the fourth target region away from the read bit line is the write bit line;

[0045] forming a third gate dielectric layer on the sidewalls of the second semiconductor layer and the second gate dielectric layer away from the read bit line;

[0046] Forming a first portion of a second gate at a second portion of the third target region and a sidewall of the third gate dielectric layer away from the read bit line;

[0047] A first semiconductor layer, a first gate dielectric layer and a first gate electrode are sequentially formed by etching a hole wall between the first portion and the write bit line to obtain a write transistor.

[0048] The portion of the second semiconductor layer surrounding the second portion and connected to the common source line is the third source and drain, and the portion of the second semiconductor layer located on the side of the second portion away from the first portion is the fourth source and drain. The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source and drain, and the portion of the first semiconductor layer extending along the first direction and located on the side of the first gate away from the first source and drain is the second source and drain. The write word line is formed synchronously with the first gate.

[0049] According to some embodiments, based on the etching hole, the virtual write bit line and the retained virtual gate are removed to form an accommodation space, which also includes: performing a wet etching process along the second direction and the first direction on the virtual write bit line and the retained virtual gate to form an accommodation space.

[0050] According to some embodiments, the present disclosure further provides an electronic device on another aspect, including: one or more memories as described in the aforementioned embodiments.

[0051] The embodiments of the present disclosure may or at least have the following advantages:

[0052] In some embodiments of the present disclosure, a third gate is added to the read transistor of the memory cell, and the third gate is insulated and arranged on one side of the connection portion (i.e., the storage node) between the second source and drain of the write transistor and the second gate of the read transistor, and the third gate is electrically connected to the read word line. In this way, when performing a read operation, the read word line in the selected memory cell is set to a normal potential, and the read word line in the unselected memory cell is set to a low potential. The third gate connected to the low potential read word line can attract more positive charges from the channel of the read transistor to ensure that the read transistor of the unselected memory cell is in an electrically blocked state, thereby solving the multi-path problem caused by the read current bypassing multiple storage nodes due to the storage nodes of multiple read transistors corresponding to the same read word line during the read operation, and avoiding the voltage drop problem caused to the target read bit line when leakage current flows out of different read bit lines under the control of the same read word line, and avoiding the problem of interference between different memory cells, thereby helping to improve the performance and reliability of the memory cell and the memory.

[0053] In addition, in some embodiments of the present disclosure, the third source and drain of the read transistor are electrically connected to the common source line, which is beneficial for connecting corresponding adjacent multiple memory cells into a piece through the common source line to solve the problem of current crowding and optimize the structure of the memory.

[0054] In some other embodiments of the present disclosure, the write word line is multiplexed as the read word line in the data reading stage, and the first gate of the write transistor is multiplexed as the third gate of the read transistor in the data reading stage, which is beneficial to further simplify the structure and process of the storage unit and the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without creative work.

[0056] Figure 1 A schematic diagram of the structure of a storage unit provided in some embodiments of the present disclosure;

[0057] Figure 2 for Figure 1 A schematic cross-sectional view of a structure shown on section M1;

[0058] Figure 3 A schematic diagram of an equivalent circuit of a storage unit provided in some embodiments of the present disclosure;

[0059] Figure 4 A schematic diagram of the structure of another storage unit provided in some embodiments of the present disclosure;

[0060] Figure 5 for Figure 4 A schematic cross-sectional view of a structure shown on section M1;

[0061] Figure 6 A schematic flow chart of a method for manufacturing a memory provided in some embodiments;

[0062] Figure 7 A schematic diagram of a process for forming a read transistor and a write transistor in a method for manufacturing a memory provided in some embodiments;

[0063] Figure 8 A schematic cross-sectional view of a structure obtained in step S20 in a method for manufacturing a memory provided in some embodiments;

[0064] Fig. 9 is a schematic cross-sectional view of a structure obtained in step S31 in a method for manufacturing a memory provided in some embodiments;

[0065] Fig.10 is a schematic cross-sectional view of a structure obtained in step S32 in a method for manufacturing a memory provided in some embodiments;

[0066] Fig.11 is a schematic cross-sectional view of a structure obtained in step S33 in a method for manufacturing a memory provided in some embodiments;

[0067] Fig.12 is a schematic cross-sectional view of a structure obtained in step S34 in a method for manufacturing a memory provided in some embodiments;

[0068] Fig.13 is a schematic cross-sectional view of a structure obtained in step S35 in a method for manufacturing a memory provided in some embodiments;

[0069] Fig.14 is a schematic cross-sectional view of a structure obtained in step S36 in a method for manufacturing a memory provided in some embodiments;

[0070] Fig.15 is a schematic cross-sectional view of a structure obtained in step S37 in a method for manufacturing a memory provided in some embodiments;

[0071] Fig.16 A schematic cross-sectional view of a structure obtained in step S50 in a method for manufacturing a memory provided in some embodiments;

[0072] Fig.17 A schematic cross-sectional view of a structure obtained in step S60 in a method for manufacturing a memory provided in some embodiments;

[0073] Fig.18 Another schematic diagram of a process for forming a read transistor and a write transistor in a method for manufacturing a memory provided in some embodiments;

[0074] Fig.19 A cross-sectional schematic diagram of another structure obtained in step S20 in a method for manufacturing a memory provided in some embodiments;

[0075] Fig. 20 is a cross-sectional schematic diagram of a structure obtained in step S31' in a method for manufacturing a memory provided in some embodiments;

[0076] Fig.21 is a cross-sectional schematic diagram of a structure obtained in step S32' in a method for manufacturing a memory provided in some embodiments;

[0077] Fig. 22 is a schematic cross-sectional view of a structure obtained in step S33' in a method for manufacturing a memory provided in some embodiments;

[0078] Fig.23 is a schematic cross-sectional view of a structure obtained in step S34' in a method for manufacturing a memory provided in some embodiments;

[0079] Fig.24 is a cross-sectional schematic diagram of a structure obtained in step S35' in a method for manufacturing a memory provided in some embodiments;

[0080] Fig.25 is a cross-sectional schematic diagram of a structure obtained in step S36' in a method for manufacturing a memory provided in some embodiments;

[0081] Fig.26 is a schematic cross-sectional view of a structure obtained in step S37' in a method for manufacturing a memory provided in some embodiments;

[0082] Fig. 27 A cross-sectional schematic diagram of another structure obtained in step S50 in a method for manufacturing a memory provided in some embodiments;

[0083] Fig.28 It is a cross-sectional schematic diagram of another structure obtained in step S60 in a method for manufacturing a memory provided in some embodiments.

[0084] Reference numerals:

[0085] 11-first gate electrode; 12-first source and drain electrode; 13-second source and drain electrode; 14-first semiconductor layer; 15-first gate dielectric layer;

[0086] 21 - second gate electrode; 22 - third source and drain electrode; 23 - fourth source and drain electrode; 24 - second semiconductor layer; 25 - second gate dielectric layer;

[0087] 31- a third gate; 32- a third gate dielectric layer;

[0088] 1-semiconductor material layer; 2-gate dielectric material layer; 3-second conductive material layer;

[0089] T W -Write transistor; T R - read transistor; WL1- write word line; WL2- read word line; BL1- write bit line; VBL1- virtual write bit line; BL2- read bit line; SL- common source line; A- first part; B- second part; K1- etched hole; K2- accommodation hole; V G -virtual gate; C1-accommodation groove; C2-accommodation space; L1-dielectric material; L2-insulating material. DETAILED DESCRIPTION

[0090] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. Embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0091] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0092] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0093] It is understood that the terms "first", "second", "third", "fourth", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first transistor may be referred to as a second transistor, and similarly, a second transistor may be referred to as a first transistor. Both the first transistor and the second transistor are transistors, but they are not the same transistor.

[0094] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0095] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0096] As used herein, a "deposition" process includes, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0097] At present, a variety of 3D dynamic random access memories are widely studied. Among them, the 3D dynamic random access memory with a 2T0C structure. The principle is to use a write transistor to control the write operation. The gate of the write transistor is connected to the write word line. After the write word line is set high, a certain voltage is input through the write bit line connected to the source and drain of the write transistor. This tube usually uses a wide bandgap oxide semiconductor to ensure that a small amount of charge can be locked in the gate of the read transistor and the wire connected to it as a storage node after being turned off. Then the data is read based on the read word line and read bit line connected to the source and drain of the read transistor. However, the 3D dynamic random access memory with a 2T0C structure is prone to problems such as read current multi-path and read current crowding when reading data, which has an adverse effect on the performance of the dynamic random access memory.

[0098] Based on this, the embodiments of the present disclosure provide a storage unit, a memory and a method for preparing the same, and an electronic device, which can help improve the performance and reliability of the storage unit and the memory.

[0099] See also Figure 1 to Figure 3 , some embodiments of the present disclosure provide a storage unit, comprising: a write transistor T W and read transistor T R ;Write transistor T W The read transistor T includes a first gate 11, a first source and drain 12, and a second source and drain 13. R The first gate 11 is electrically connected to the write word line WL1, the first source and drain 12 is electrically connected to the write bit line BL1, and the second source and drain 13 is electrically connected to the second gate 21. R It also includes: a third gate 31, which is insulated and arranged on one side of the connection portion between the second source and drain 13 and the second gate 21; wherein the third gate 31 is electrically connected to the read word line WL2, the fourth source and drain 23 is electrically connected to the read bit line BL2, and the third source and drain 22 is electrically connected to the common source line SL.

[0100] In the embodiment of the present disclosure, by using the read transistor T R A third gate 31 is added inside and the third gate 31 is insulated and arranged on the write transistor T W The second source-drain 13 and the read transistor T RThe third gate 31 is electrically connected to the connection portion (i.e., storage node) between the second gate 21 and the third gate 31. In this way, when performing a read operation, the read word line WL2 in the selected storage cell is set to a normal potential, and the read word line WL2 in the unselected storage cell is set to a low potential. The third gate 31 connected to the low potential read word line WL2 can transfer more positive charges from the read transistor T R The channel attracts away the read transistor T of the unselected memory cell. R The same read word line WL2 is electrically disconnected, thereby solving the problem of controlling multiple read transistors T R The multi-path problem caused by the read current bypassing multiple storage nodes can be avoided, and the voltage drop problem on the target read bit line BL2 caused by leakage current flowing out of different read bit lines BL2 under the control of the same read word line WL2 can be avoided, as well as the interference problem between different storage cells, thereby helping to improve the performance and reliability of the storage cells and the memory.

[0101] In addition, in the embodiment of the present disclosure, the read transistor T R The third source-drain 22 is electrically connected to the common source line SL, which is beneficial for connecting corresponding adjacent multiple memory cells into a piece through the common source line SL to solve the problem of current crowding and optimize the structure of the memory.

[0102] For example, the write word line WL1 and the first gate 11 can be formed synchronously. The read word line WL2 and the third gate 31 can be formed synchronously. For example, the write word line WL1 and the first gate 11 can be an integrated structure formed synchronously using a synchronous process. The read word line WL2 and the third gate 31 can be an integrated structure formed synchronously using a synchronous process.

[0103] In some embodiments, see Figure 1 and Figure 2 The read bit line BL2 and the write bit line BL1 are arranged in parallel and spaced apart, and extend along a first direction (eg, X direction). The write transistor T W and read transistor T R The common source line SL surrounds the read transistor T and is arranged in a second direction (eg, Y direction) and is disposed in the interval between the read bit line BL2 and the write bit line BL1; the second direction (eg, Y direction) intersects the first direction (eg, X direction). R The peripheral side of the transistor T R The surrounding center line of the common source line SL extends along the second direction (for example, the Y direction); the third direction (for example, the Z direction) intersects with the first direction (for example, the X direction) and the second direction (for example, the Y direction).

[0104] In some embodiments, see Figure 2, write transistor T W The first semiconductor layer 14 is included. The read transistor T R The second semiconductor layer 24 is included. The first gate 11 and the write word line WL1 extend along a third direction (e.g., Z direction). The first semiconductor layer 14 is disposed around the periphery of the first gate 11, and the center line of the first semiconductor layer 14 extends along the third direction (e.g., Z direction). The portion of the first semiconductor layer 14 extending along the first direction (e.g., X direction) and electrically connected to the write bit line BL1 is the first source and drain 12, and the portion of the first semiconductor layer 14 contacting the second gate 21 and located on the side of the first gate 11 away from the first source and drain 12 is the second source and drain 13. The second gate 21 extends along the second direction (e.g., Y direction), and includes: a first portion A electrically connected to the second source and drain 13, and a second portion B located on the side of the first portion A away from the second source and drain 13 and electrically connected to the first portion A. The second semiconductor layer 24 is disposed around the periphery of the second portion B and on the side of the second portion B away from the first portion A. The center line of the second semiconductor layer 24 extends along the second direction (e.g., Y direction). The portion of the second semiconductor layer 24 surrounding the second portion B and connected to the common source line SL is the third source and drain 22. The portion of the second semiconductor layer 24 located on the side of the second portion B away from the first portion A is the fourth source and drain 23.

[0105] In some embodiments, the third gate 31 extends along a third direction (eg, Z direction). The third gate 31 is insulated and disposed on one side of the first portion A in the first direction (eg, X direction).

[0106] In some embodiments, the write transistor T W The first gate dielectric layer 15 is also included. The read transistor T R The present invention also includes: a second gate dielectric layer 25 and a third gate dielectric layer 32 connected to each other. The first gate dielectric layer 15 is located between the first gate 11 and the first semiconductor layer 14. The second gate dielectric layer 25 is located between the second portion B and the second semiconductor layer 24. The third gate dielectric layer 32 is disposed around the third gate 31 and is connected to the second gate dielectric layer 25 and the second gate 21.

[0107] In some embodiments, see Figure 3 The first gate 11 is electrically connected to the write word line WL1, the first source and drain 12 is electrically connected to the write bit line BL1, and the second source and drain 13 is electrically connected to the second gate 21. The third gate 31 is electrically connected to the read word line WL2, the fourth source and drain 23 is electrically connected to the read bit line BL2, and the third source and drain 22 is electrically connected to the common source line SL.

[0108] In some other embodiments, see Figure 4 and Figure 5The write word line WL1 is multiplexed as the read word line WL2 during the data reading phase. The first gate 11 is multiplexed as the third gate 31 during the data reading phase.

[0109] In the embodiment of the present disclosure, the write word line WL1 is multiplexed as the read word line WL2 in the data reading phase, and the write transistor T W The first gate 11 is multiplexed as a read transistor T in the data reading phase. R The third gate 31 is beneficial to further simplify the structure and process of the storage unit and the memory.

[0110] In some embodiments, see Figure 5 , the size of the first part A in the first direction (for example, the X direction) is larger than the size of the second part B in the first direction (for example, the X direction). The size of the first part A in the second direction (for example, the Y direction) is smaller than the size of the second part B in the second direction (for example, the Y direction).

[0111] In the embodiment of the present disclosure, the size of the first portion A in the first direction (e.g., X direction) is larger than the size of the second portion B in the first direction (e.g., X direction), and the size of the first portion A in the second direction (e.g., Y direction) is smaller than the size of the second portion B in the second direction (e.g., Y direction). R With the write transistor T W The contact portion of the read transistor T is wider. R的 The channel is narrower, so that the write word line WL1 has stronger control over the read word line WL2.

[0112] In some embodiments, the write transistor T W The first gate dielectric layer 15 is also included. The read transistor T R The device further comprises: a second gate dielectric layer 25 and a third gate dielectric layer 32 connected to each other. The first gate dielectric layer 15 is located between the first gate 11 and the first semiconductor layer 14. The second gate dielectric layer 25 is located between the second portion B and the second semiconductor layer 24. The third gate dielectric layer 32 is located between the first portion A and the second semiconductor layer 24.

[0113] In some embodiments, a dimension of the first semiconductor layer 14 in the first direction (eg, the X direction) is greater than a maximum dimension of the second gate 21 in the first direction (eg, the X direction).

[0114] In some embodiments, the present disclosure further provides a memory, including one or more storage units as in any one of the above embodiments. The memory also has the technical advantages of the above storage units, which will not be described in detail here.

[0115] Some embodiments of the present disclosure also provide a data reading and writing method, which is applied to a memory as described in any of the above embodiments. The data reading and writing method also has the technical advantages of the above memory, which will not be described in detail here. W The second source-drain 13 and the read transistor T R The connection portion of the second gate 21 is a storage node of the storage unit. The data reading and writing method includes:

[0116] S1: In the data writing phase, in response to the write command, the write bit line BL1 is connected to the write transistor T W Provides data voltage; write word line WL1 controls write transistor T W The storage node is turned on and discharged to a stable state to write the data corresponding to the data voltage.

[0117] S2: In the data reading stage, in response to the read command, the read word line WL2 in the selected memory cell is set to a normal potential, and the read word line WL2 in the unselected memory cell is set to a low potential, so that the third gate 31 connected to the read word line WL2 at the low potential transfers more positive charges from the read transistor T R The channel attracts away the read transistor T in the unselected memory cell. R It is in an electrically disconnected state.

[0118] In some other embodiments, the write word line WL1 is multiplexed as the read word line WL2 during the data reading phase. The first gate 11 is multiplexed as the third gate 31 during the data reading phase.

[0119] In the data reading stage, in response to the read command, the read word line WL2 in the selected memory cell is set to a normal potential, and the read word line WL2 in the unselected memory cell is set to a low potential, so that the first gate 11 connected to the read word line WL2 at the low potential transfers more positive charges from the read transistor T R The channel attracts away the read transistor T in the unselected memory cell. R It is in an electrically disconnected state.

[0120] Some embodiments of the present disclosure also provide a method for preparing a memory, which is used to prepare the memory in some of the above embodiments. The manufacturing method also has the technical advantages of the above memory.

[0121] See also Figure 6 Combined with Figure 1 to Figure 3 It is understood that the manufacturing method includes the following steps.

[0122] S10: depositing a first conductive material layer and an insulating material layer in sequence on the wafer to form a stacked structure.

[0123] S20: forming read bit lines and write bit lines that are arranged in parallel and spaced apart and extend along a first direction.

[0124] S30: A read transistor and a write transistor are formed in the gap between the read bit line and the write bit line and are arranged side by side in the second direction; the write transistor includes a first gate, a first source and a drain, and a second source and a drain; the read transistor includes a second gate, a third gate, a third source and a drain, and a fourth source and a drain; wherein the first source and the drain are electrically connected to the write bit line, the second source and the drain are electrically connected to the second gate, and the fourth source and the drain are electrically connected to the read bit line; the third gate is insulated and arranged on one side of the connection portion between the second source and the drain and the second gate; the first direction intersects with the second direction, and the first direction and the second direction are both parallel to the wafer surface.

[0125] S40: forming a write word line electrically connected to the first gate.

[0126] S50: forming a read word line electrically connected to the third gate.

[0127] S60: forming a common source line electrically connected to the third source and drain.

[0128] In some embodiments, step S20 forms read bit lines and write bit lines that are arranged in parallel and spaced apart and extend along a first direction, including: forming a first conductive material layer, and patterning the first conductive material layer to form read bit lines and write bit lines that are arranged in parallel and spaced apart, and a virtual gate located between the read bit lines and the write bit lines and connecting the read bit lines and the write bit lines; wherein the read bit lines and the write bit lines extend along the first direction, and the virtual gate extends along the second direction.

[0129] In some embodiments, see Figure 7 Step S30 forms a read transistor and a write transistor arranged side by side in a second direction in the interval between the read bit line and the write bit line, comprising the following steps:

[0130] S31: filling dielectric material on two opposite sides of the dummy gate in the first direction.

[0131] S32: etching the dummy gate and dielectric material in a first target region of the dummy gate close to the write bit line to form an etching hole.

[0132] S33: Based on the etching hole, the retained dummy gate is removed to form a receiving groove; the receiving groove exposes the corresponding side wall of the read bit line.

[0133] S34: depositing a semiconductor material layer, a gate dielectric material layer, and a second conductive material layer in sequence on the inner wall of the receiving groove.

[0134] S35: removing the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the etching hole, so that the retained gate dielectric material layer constitutes a second gate dielectric layer, and the retained second conductive material layer constitutes a second gate; and removing the semiconductor material layer in the second target area near the etching hole, so that the retained semiconductor material layer constitutes a second semiconductor layer, and exposing the side wall of the second gate dielectric layer.

[0135] S36: etching dielectric material outside the side wall of the second gate dielectric layer exposed on one side in the first direction to form an accommodation hole; the accommodation hole exposes the side wall of the second semiconductor layer away from the read bit line.

[0136] S37: forming a third gate dielectric layer and a third gate electrode in sequence in the receiving hole.

[0137] S38: forming a first semiconductor layer, a first gate dielectric layer and a first gate electrode in sequence on the hole wall of the etched hole to obtain a write transistor.

[0138] In order to more clearly illustrate the methods for preparing the memory in some of the above embodiments, the following embodiments exemplarily provide some possible specific implementations of some steps.

[0139] In step S20, refer to Figure 8 , forming a first conductive material layer (not shown), and patterning the first conductive material layer to form a read bit line BL2 and a write bit line BL1 arranged in parallel and spaced apart, and a virtual gate V located between the read bit line BL2 and the write bit line BL1 and connecting the read bit line BL2 and the write bit line BL1 G Wherein, the read bit line BL2 and the write bit line BL1 extend along a first direction (eg, X direction), and the virtual gate V G Extending along a second direction (eg, the Y direction).

[0140] Here, it should be particularly noted that in the three-dimensional stacked structure, the first semiconductor layers corresponding to different first conductive material layers are separated. That is, multiple first conductive material layers and multiple sacrificial layers are alternately stacked, and the sacrificial layers are removed as required to obtain the first semiconductor layers of each write transistor by subsequent lateral etching of the first semiconductor material layer.

[0141] Illustratively, the first conductive material layer includes a metal layer, such as a metal tungsten layer.

[0142] Illustratively, the sacrificial layer includes, but is not limited to, a silicon nitride layer.

[0143] Here, each first conductive material layer and each sacrificial layer may be formed by a deposition process, respectively.

[0144] In step S31, refer to Fig. 9 , at the virtual gate V GThe dielectric material L1 is filled on two opposite sides in a first direction (eg, X direction).

[0145] By way of example, the dielectric material L1 includes, but is not limited to, silicon oxide.

[0146] Here, the dielectric material L1 may be formed by a deposition process. After the dielectric material L1 is formed by the deposition process, a chemical mechanical polishing (CMP) process may be used to grind the upper surface of the dielectric material L1 to ensure that the upper surface of the dielectric material L1 is flat.

[0147] In step S32, refer to Fig.10 , at the virtual gate V G A dummy gate V is etched in the first target area near the write bit line BL1. G and dielectric material L1 to form an etched hole K1.

[0148] Here, the etching hole K1 may be formed by dry etching.

[0149] In step S33, refer to Fig.11 Based on the etched hole K1, the virtual gate V is selectively etched along the second direction (eg, the Y direction) by wet etching. G , remove the retained dummy gate V G , forming a receiving groove C1; the receiving groove C1 exposes the corresponding side wall of the read bit line BL2.

[0150] Here, wet etching can be used to remove the retained virtual gate V G , forming a receiving groove C1.

[0151] In step S34, refer to Fig.12 , a semiconductor material layer 1 , a gate dielectric material layer 2 , and a second conductive material layer 3 are sequentially deposited on the inner wall of the receiving groove C1 by an atomic layer deposition process.

[0152] Here, an atomic layer deposition (ALD) process may be used to sequentially deposit the semiconductor material layer 1 , the gate dielectric material layer 2 , and the second conductive material layer 3 .

[0153] By way of example, the semiconductor material layer 1 includes but is not limited to a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0154] For example, the gate dielectric material layer 2 includes but is not limited to a HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, where the high dielectric constant K is, for example, greater than 3.9.

[0155] By way of example, the material of the second conductive material layer 3 includes, but is not limited to, metal tungsten.

[0156] In step S35, refer to Fig.13 , remove the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the etching hole K1, so that the retained gate dielectric material layer 2 constitutes the second gate dielectric layer 25, and the retained second conductive material layer 3 constitutes the second gate 21; and remove the semiconductor material layer 1 in the second target area near the etching hole K1, so that the retained semiconductor material layer 1 constitutes the second semiconductor layer 24, and the side wall of the second gate dielectric layer 25 is exposed.

[0157] Here, after removing the semiconductor material layer 1 in the second target region near the etching hole K1 , the insulating material L2 needs to be backfilled.

[0158] Illustratively, the insulating material L2 includes, but is not limited to, silicon oxide.

[0159] For example, step S35 further includes: backfilling the second conductive material layer 3 in the area of ​​the etched hole K1 close to the write bit line BL1 .

[0160] In step S36, refer to Fig.14 The dielectric material is etched outside the side wall of the second gate 21 exposed in the first direction (eg, X direction) to form an accommodation hole K2; the accommodation hole K2 exposes the side walls of the second gate dielectric layer 25 and the second semiconductor layer 24 away from the read bit line BL2.

[0161] Here, the receiving hole K2 and the etching hole K1 are spaced apart along the second direction (eg, the Y direction).

[0162] By way of example, the etching hole K2 may be formed by dry etching.

[0163] In step S37, refer to Fig.15 , a third gate dielectric layer 32 and a third gate 31 are sequentially formed in the accommodating hole K2.

[0164] For example, the third gate dielectric layer 32 includes but is not limited to a HK (high-K) dielectric layer. The HK dielectric layer refers to a dielectric layer with a high dielectric constant K, and the high dielectric constant K is, for example, greater than 3.9. The material of the third gate 31 includes but is not limited to metal tungsten.

[0165] In step S38, refer to Fig.16 The first semiconductor layer 14, the first gate dielectric layer 15 and the first gate electrode 11 are sequentially formed on the hole wall of the etching hole K1 to obtain the write transistor T W .

[0166] For example, the first semiconductor layer 14 includes but is not limited to a metal oxide semiconductor layer, such as an IGZO layer. The first gate dielectric layer 15 includes but is not limited to a HK dielectric layer. The material of the first gate 11 includes but is not limited to metal tungsten.

[0167] Please continue reading Fig.16 Understand, write transistor T W The transistor includes a first gate 11, a first source and drain 12, and a second source and drain 13; the read transistor includes a second gate 21, a third gate 31, a third source and drain 22, and a fourth source and drain 23; wherein the first source and drain 12 are electrically connected to the write bit line BL1, the second source and drain 13 are electrically connected to the second gate 21, and the fourth source and drain 23 are electrically connected to the read bit line BL2; the third gate 31 is insulated and arranged on one side of the connection between the second source and drain 13 and the second gate 21. The portion of the second semiconductor layer 24 located on the side of the second gate 21 away from the first gate 11 is the fourth source and drain 23. The portion of the first semiconductor layer 14 extending along the first direction (for example, the X direction) and electrically connected to the write bit line BL1 is the first source and drain 12, and the portion of the first semiconductor layer 14 extending along the first direction (for example, the X direction) and located on the side of the first gate 11 away from the first source and drain 12 is the second source and drain 13.

[0168] In step S40, refer to Fig.16 , forming a write word line WL1 electrically connected to the first gate 11.

[0169] Here, the write word line WL1 is formed synchronously with the first gate electrode 11 .

[0170] In step S50, please continue to refer to Fig.16 , forming a read word line WL2 electrically connected to the third gate 31.

[0171] Here, the read word line WL2 is formed synchronously with the third gate 31 .

[0172] In step S60, refer to Fig.17 , forming a common source line SL electrically connected to the third source and drain 22.

[0173] Here, the common source line SL includes, but is not limited to, metal tungsten.

[0174] For example, forming the common source line SL electrically connected to the third source and drain 22 includes: firstly etching the dielectric material L1 to expose the peripheral side of the second semiconductor layer 24 , and then backfilling the material to form the common source line SL.

[0175] The portion of the second semiconductor layer 24 surrounding the second gate 21 and connected to the common source line SL is the third source and drain 22 .

[0176] In some other embodiments, the write word line WL1 is multiplexed as the read word line WL2 in the data reading phase, and the first gate 11 is multiplexed as the third gate 31 in the data reading phase.

[0177] Accordingly, in some other embodiments, forming the read bit lines and write bit lines arranged in parallel and spaced apart and extending along the first direction in step S20 includes: forming a first conductive material layer, and patterning the first conductive material layer, forming the read bit lines and dummy write bit lines arranged in parallel and spaced apart, and a dummy gate V located between the read bit lines and the dummy write bit lines and connecting the read bit lines and the dummy write bit lines. G Wherein, the read bit line and the virtual write bit line extend along the first direction, and the virtual gate V G Extending along a second direction (eg, the Y direction).

[0178] Accordingly, in other embodiments, please refer to Fig.18 Combined with Figure 4 , Figure 5 It is understood that step S30 of forming a read transistor and a write transistor arranged side by side in the second direction in the interval between the read bit line and the write bit line may further include the following steps:

[0179] S31': filling dielectric material on two opposite sides of the virtual gate in the first direction;

[0180] S32': etching the virtual gate and the dielectric material in a first target area of ​​the virtual gate close to the virtual write bit line to form an etching hole;

[0181] S33': based on the etching hole, removing the virtual write bit line and the retained virtual gate to form an accommodation space including the etching hole; the accommodation space exposes the corresponding side wall of the read bit line;

[0182] S34': depositing a semiconductor material layer, a gate dielectric material layer and a second conductive material layer in sequence in the accommodating space;

[0183] S35': removing the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the first target region, as well as the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer in the third target region and the fourth target region on both sides of the first target region along the second direction, so that the retained semiconductor material layer constitutes the second semiconductor layer, the retained gate dielectric material layer constitutes the second gate dielectric layer, the second conductive material layer retained on the side of the third target region close to the read bit line is the second part of the second gate, and the second conductive material layer retained on the side of the fourth target region away from the read bit line is the write bit line;

[0184] S36': forming a third gate dielectric layer on the sidewalls of the second semiconductor layer and the second gate dielectric layer away from the read bit line;

[0185] S37′: forming a first portion of a second gate at a second portion of the third target region and a sidewall of the third gate dielectric layer away from the read bit line;

[0186] S38': etching the hole wall between the first portion and the write bit line to sequentially form a first semiconductor layer, a first gate dielectric layer and a first gate to obtain a write transistor.

[0187] Also, in order to more clearly illustrate the methods for preparing the memory in some of the above embodiments, some of the following embodiments exemplarily provide some possible specific implementations of some steps.

[0188] In step S20, refer to Fig.19 , forming a read bit line BL2 and a write bit line BL1 arranged in parallel and spaced apart and extending in a first direction (e.g., X direction) includes: forming a first conductive material layer (not shown), and patterning the first conductive material layer to form a read bit line BL2 and a virtual write bit line VBL1 arranged in parallel and spaced apart, and a virtual gate V located between the read bit line BL2 and the virtual write bit line VBL1 and connecting the read bit line BL2 and the virtual write bit line VBL1 G Wherein, the read bit line BL2 and the virtual write bit line VBL1 extend along a first direction (eg, X direction), and the virtual gate V G Extending along a second direction (eg, the Y direction).

[0189] Here, it should be particularly noted that in the three-dimensional stacked structure, the first semiconductor layers corresponding to different first conductive material layers are separated. That is, multiple first conductive material layers and multiple sacrificial layers are alternately stacked, and the sacrificial layers are removed as required to obtain the first semiconductor layers of each write transistor by subsequent lateral etching of the first semiconductor material layer.

[0190] Illustratively, the first conductive material layer includes a metal layer, such as a metal tungsten layer.

[0191] Illustratively, the sacrificial layer includes, but is not limited to, a silicon nitride layer.

[0192] Here, each first conductive material layer and each sacrificial layer may be formed by a deposition process, respectively.

[0193] In step S31', refer to Fig. 20 , at the virtual gate V G The dielectric material L1 is filled on two opposite sides in a first direction (eg, X direction).

[0194] By way of example, the dielectric material L1 includes, but is not limited to, silicon oxide.

[0195] Here, the dielectric material L1 may be formed by a deposition process. Moreover, after the dielectric material L1 is formed by the deposition process, a chemical mechanical polishing (CMP) process may be used to grind the upper surface of the dielectric material L1 to ensure that the upper surface of the dielectric material L1 is flat.

[0196] In step S32', refer to Fig.21 , at the virtual gate V G The first target area near the virtual write bit line VBL1 is etched with a virtual gate V G and dielectric material L1 to form an etched hole K1.

[0197] Here, the etching hole K1 may be formed by dry etching.

[0198] In step S33', refer to Fig. 22 , based on the etching hole K1, remove the virtual write bit line VBL1 and the retained virtual gate V G , forming an accommodating space C2 including the etching hole K1; the accommodating space exposes the corresponding side wall of the read bit line BL2.

[0199] For example, based on the etching hole K1, the virtual write bit line VBL1 and the retained virtual gate V G , forming an accommodation space C2, and further comprising: a virtual write bit line VBL1 and a reserved virtual gate V G A wet etching process is performed along the second direction (eg, the Y direction) and the first direction (eg, the X direction) to form the accommodating space C2.

[0200] In step S34', refer to Fig.23 , a semiconductor material layer 1, a gate dielectric material layer 2 and a second conductive material layer 3 are sequentially deposited in the accommodating space C2.

[0201] By way of example, the semiconductor material layer 1 includes but is not limited to a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0202] By way of example, the gate dielectric material layer 2 includes but is not limited to a HK dielectric layer.

[0203] By way of example, the material of the second conductive material layer 3 includes, but is not limited to, metal tungsten.

[0204] Here, the semiconductor material layer 1 , the gate dielectric material layer 2 , and the second conductive material layer 3 may be deposited in sequence using an ALD process.

[0205] In step S35', refer to Fig.24, remove the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the first target area, as well as the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the third target area and the fourth target area on both sides of the first target area adjacent to each other along the second direction (for example, the Y direction), so that the retained semiconductor material layer 1 constitutes the second semiconductor layer 24, the retained gate dielectric material layer 2 constitutes the second gate dielectric layer 25, the second conductive material layer 3 retained on the side of the third target area close to the read bit line is the second part B of the second gate 21, and the second conductive material layer 3 retained on the side of the fourth target area away from the read bit line BL2 is the write bit line BL1.

[0206] Here, dry etching can be used to first remove the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the first target area, and then wet etching can be used to remove the semiconductor material layer 1, the gate dielectric material layer 2 and the second conductive material layer 3 in the third target area and the fourth target area along the second direction (for example, the Y direction). The second conductive material layer 3 retained in the third target area close to the read bit line is the second part B of the second gate 21, and the second conductive material layer 3 retained in the fourth target area away from the read bit line BL2 is the write bit line BL1.

[0207] In step S36', refer to Fig.25 A third gate dielectric layer 32 is formed on the sidewalls of the second semiconductor layer 24 and the second gate dielectric layer 25 away from the read bit line BL2.

[0208] By way of example, the third gate dielectric layer 32 includes, but is not limited to, a HK dielectric layer.

[0209] In step S37', refer to Fig.26 A first portion A of the second gate 21 is formed in the second portion B of the third target region and on the sidewall of the third gate dielectric layer 32 away from the read bit line BL2 .

[0210] Here, while forming the first portion A of the second gate 21 , the second conductive material layer 3 is backfilled in the fourth target region.

[0211] In step S38', refer to Fig. 27 The hole wall of the hole K1 is etched between the first portion A and the write bit line BL1 to sequentially form a first semiconductor layer 14, a first gate dielectric layer 15 and a first gate electrode 11 to obtain a write transistor T W .

[0212] By way of example, the first semiconductor layer 14 includes but is not limited to a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0213] By way of example, the first gate dielectric layer 15 includes, but is not limited to, a HK dielectric layer.

[0214] By way of example, the material of the first gate 11 includes, but is not limited to, metal tungsten.

[0215] Here, the first semiconductor layer 14 , the first gate dielectric layer 15 and the first gate 11 may be deposited in sequence by using an ALD process.

[0216] Please continue reading Fig. 27 Understand, write transistor T W The transistor includes a first gate 11, a first source and drain 12, and a second source and drain 13; the read transistor includes a second gate 21, a third gate 31, a third source and drain 22, and a fourth source and drain 23; wherein the first source and drain 12 are electrically connected to the write bit line BL1, the second source and drain 13 are electrically connected to the second gate 21, and the fourth source and drain 23 are electrically connected to the read bit line BL2; the third gate 31 is insulated and arranged on one side of the connection between the second source and drain 13 and the second gate 21. The portion of the second semiconductor layer 24 located on the side of the second portion B away from the first portion A is the fourth source and drain 23. The portion of the first semiconductor layer 14 extending along the first direction (for example, the X direction) and electrically connected to the write bit line BL1 is the first source and drain 12, and the portion of the first semiconductor layer 14 extending along the first direction (for example, the X direction) and located on the side of the first gate 11 away from the first source and drain 12 is the second source and drain 13.

[0217] In step S40, refer to Fig. 27 , forming a write word line WL1 electrically connected to the first gate 11.

[0218] Here, the write word line WL1 is formed synchronously with the first gate electrode 11 .

[0219] In step S50, please continue to refer to Fig. 27 , forming a read word line WL2 electrically connected to the third gate 31.

[0220] Here, the write word line WL1 is multiplexed as the read word line WL2 in the data reading phase, and the first gate 11 is multiplexed as the third gate 31 in the data reading phase. The read word line WL2 and the third gate 31 are formed synchronously.

[0221] In step S60, refer to Fig.28 , forming a common source line SL electrically connected to the third source and drain 22.

[0222] Here, the common source line SL includes, but is not limited to, metal tungsten.

[0223] For example, forming the common source line SL electrically connected to the third source and drain 22 includes: firstly etching the dielectric material L1 to expose the peripheral side of the second semiconductor layer 24 , and then backfilling the material to form the common source line SL.

[0224] The portion of the second semiconductor layer 24 surrounding the second portion B and connected to the common source line SL is the third source and drain 22 .

[0225] Some embodiments of the present disclosure also provide an electronic device, including: one or more memories as described in the above embodiments. For example, data storage devices, photocopiers, network devices, household appliances, instruments, mobile phones, computers and other devices with data storage functions. The electronic device may include a housing and a circuit board arranged in the housing, a memory or a data read-write circuit integrated on the circuit board. The structure of the memory can refer to the relevant description in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in the embodiments of the present disclosure.

[0226] In some embodiments, the memory may be coupled to an external control device such as a processor or an actuator. The processor is coupled to the memory, and the processor can control the read and write operations of the memory.

[0227] In some embodiments, the memory is 3D dynamic random access memory.

[0228] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0229] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A storage unit, characterized in that: include: A write transistor and a read transistor; the write transistor comprises a first gate, a first source and a drain, and a second source and a drain; the read transistor comprises a second gate, a third source and a drain, and a fourth source and a drain; the first gate is electrically connected to a write word line, the first source and the drain are electrically connected to a write bit line, and the second source and the drain are electrically connected to the second gate; Wherein, the read transistor further comprises: a third gate, insulated and arranged on one side of a connection portion between the second source and drain and the second gate; The third gate is electrically connected to a read word line, the fourth source and drain are electrically connected to a read bit line, and the third source and drain are electrically connected to a common source line.

2. The storage unit according to claim 1, characterized in that The read bit lines and the write bit lines are arranged in parallel and spaced apart, and extend along a first direction; The write transistor and the read transistor are arranged side by side in a second direction and are disposed in a space between the read bit line and the write bit line; The second direction intersects the first direction; The common source line surrounds the peripheral side of the read transistor and extends in a direction away from the read transistor; the surrounding center line of the common source line extends along the second direction.

3. The storage unit according to claim 2, characterized in that The write transistor includes a first semiconductor layer; the read transistor includes a second semiconductor layer; The first gate and the write word line extend along a third direction; the third direction intersects both the first direction and the second direction; The first semiconductor layer is disposed around the first gate, and the center line of the first semiconductor layer extends along the third direction; the portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source and drain, and the portion of the first semiconductor layer contacting the second gate and located on the side of the first gate away from the first source and drain is the second source and drain; The second gate extends along the second direction and includes: a first portion electrically connected to the second source and drain, and a second portion located at a side of the first portion away from the second source and drain and electrically connected to the first portion; The second semiconductor layer is arranged around the periphery of the second part and on the side of the second part away from the first part; the center line of the second semiconductor layer extends along the second direction; the part of the second semiconductor layer arranged around the periphery of the second part and connected to the common source line is the third source and drain; the part of the second semiconductor layer located on the side of the second part away from the first part is the fourth source and drain.

4. The storage unit according to claim 3, characterized in that The third gate extends along the third direction; The third gate insulation is disposed on one side of the first portion in the first direction.

5. The storage unit according to claim 4, characterized in that The write transistor further includes a first gate dielectric layer; the read transistor further includes: a second gate dielectric layer and a third gate dielectric layer connected to each other; wherein, The first gate dielectric layer is located between the first gate and the first semiconductor layer; The second gate dielectric layer is located between the second portion and the second semiconductor layer; The third gate dielectric layer is disposed around the third gate electrode and is connected to both the second gate dielectric layer and the second gate electrode.

6. The storage unit according to claim 3, characterized in that: The write word line is multiplexed as the read word line during a data reading phase; the first gate is multiplexed as the third gate during the data reading phase.

7. The storage unit according to claim 6, characterized in that The size of the first portion in the first direction is greater than the size of the second portion in the first direction; A size of the first portion in the second direction is smaller than a size of the second portion in the second direction.

8. The storage unit according to claim 6, characterized in that The write transistor further includes a first gate dielectric layer; the read transistor further includes: a second gate dielectric layer and a third gate dielectric layer connected to each other; wherein, The first gate dielectric layer is located between the first gate and the first semiconductor layer; The second gate dielectric layer is located between the second portion and the second semiconductor layer; The third gate dielectric layer is located between the first portion and the second semiconductor layer.

9. The storage unit according to claim 4 or 6, characterized in that: A size of the first semiconductor layer in the first direction is greater than a maximum size of the second gate in the first direction.

10. A memory, characterized in that: include: One or more storage units as claimed in any one of claims 1 to 9.

11. A data reading and writing method, characterized in that: Applied to the memory as claimed in claim 10; the connection portion between the second source and drain of the write transistor and the second gate of the read transistor is a storage node of the storage unit; the data reading and writing method comprises: In the data writing phase, in response to a write command, the write bit line provides a data voltage to the write transistor; the write word line controls the write transistor to be turned on, and the storage node is discharged to a stable state to write data corresponding to the data voltage; In the data reading stage, in response to the read command, the read word line in the selected storage cell is set to a normal potential, and the read word line in the unselected storage cell is set to a low potential, so that the third gate connected to the read word line set to a low potential attracts more positive charges from the channel of the read transistor, and the read transistor in the unselected storage cell is in an electrically non-conductive state.

12. The data reading and writing method according to claim 11, characterized in that: The write word line is multiplexed as the read word line during the data reading phase; the first gate is multiplexed as the third gate during the data reading phase; In the data reading stage, in response to the read command, the read word line in the selected storage cell is set to a normal potential, and the read word line in the unselected storage cell is set to a low potential, so that the first gate connected to the read word line set to a low potential attracts more positive charges from the channel of the read transistor, and the read transistor in the unselected storage cell is in an electrically blocked state.

13. A method for preparing a memory, characterized in that: include: Depositing a first conductive material layer and an insulating material layer on the wafer in sequence to form a stacked structure; forming read bit lines and write bit lines which are arranged in parallel and spaced apart and extend along a first direction; A read transistor and a write transistor arranged side by side in a second direction are formed in the interval between the read bit line and the write bit line; the write transistor includes a first gate, a first source and a drain, and a second source and a drain; the read transistor includes a second gate, a third gate, a third source and a drain, and a fourth source and a drain; wherein the first source and the drain are electrically connected to the write bit line, the second source and the drain are electrically connected to the second gate, and the fourth source and the drain are electrically connected to the read bit line; the third gate is insulated and arranged on one side of the connection portion between the second source and the drain and the second gate; the first direction and the second direction intersect, and the first direction and the second direction are both parallel to the surface of the wafer; forming a write word line electrically connected to the first gate; forming a read word line electrically connected to the third gate; A common source line electrically connected to the third source and drain is formed.

14. The method for preparing a memory according to claim 13, characterized in that: The method comprises forming read bit lines and write bit lines arranged in parallel and spaced apart and extending in a first direction, and forming read transistors and write transistors arranged side by side in a second direction in the space between the read bit lines and the write bit lines, comprising: Patterning the first conductive material layer to form the read bit line and the write bit line that are arranged in parallel and spaced apart, and a virtual gate located between and connecting the read bit line and the write bit line; wherein the read bit line and the write bit line extend along the first direction, and the virtual gate extends along the second direction; Filling dielectric material on two opposite sides of the virtual gate in the first direction; Etching the dummy gate and the dielectric material in a first target area of ​​the dummy gate close to the write bit line to form an etching hole; Based on the etching hole, the dummy gate is selectively etched along the second direction by wet etching to remove the retained dummy gate to form a receiving groove; the receiving groove exposes the corresponding side wall of the read bit line; Depositing a semiconductor material layer, a gate dielectric material layer and a second conductive material layer in sequence on the inner wall of the containing groove by an atomic layer deposition process; Removing the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the etching hole, so that the remaining gate dielectric material layer constitutes a second gate dielectric layer, and the remaining second conductive material layer constitutes the second gate; and removing the semiconductor material layer in a second target area close to the etching hole, so that the remaining semiconductor material layer constitutes a second semiconductor layer, and exposing the sidewall of the second gate dielectric layer; The dielectric material is etched outside the side wall of the second gate exposed in the first direction to form a receiving hole; the receiving hole exposes the side wall of the second gate dielectric layer and the second semiconductor layer away from the read bit line; forming a third gate dielectric layer and the third gate in the receiving hole in sequence; Sequentially forming a first semiconductor layer, a first gate dielectric layer and the first gate on the hole wall of the etched hole to obtain the write transistor; The portion of the second semiconductor layer surrounding the second gate and connected to the common source line is the third source and drain; the portion of the second semiconductor layer located on the side of the second gate away from the first gate is the fourth source and drain; The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source and drain, and the portion of the first semiconductor layer extending along the first direction and located on the side of the first gate away from the first source and drain is the second source and drain; The write word line is formed synchronously with the first gate; The read word line is formed synchronously with the third gate.

15. The method for preparing a memory according to claim 13, characterized in that: The write word line is multiplexed as the read word line in a data reading phase, and the first gate is multiplexed as the third gate in the data reading phase; The method comprises forming read bit lines and write bit lines arranged in parallel and spaced apart and extending in a first direction, and forming read transistors and write transistors arranged side by side in a second direction in the space between the read bit lines and the write bit lines, comprising: Forming a first conductive material layer, and patterning the first conductive material layer to form the read bit line and the virtual write bit line arranged in parallel and spaced apart, and a virtual gate located between the read bit line and the virtual write bit line and connecting the read bit line and the virtual write bit line; wherein the read bit line and the virtual write bit line extend along the first direction, and the virtual gate extends along the second direction; Filling dielectric material on two opposite sides of the virtual gate in the first direction; Etching the virtual gate and the dielectric material at a first target area of ​​the virtual gate close to the virtual write bit line to form an etching hole; Based on the etched hole, the dummy write bit line and the retained dummy gate are removed to form an accommodation space including the etched hole; the accommodation space exposes the corresponding side wall of the read bit line; Depositing a semiconductor material layer, a gate dielectric material layer and a second conductive material layer in the accommodating space in sequence; removing the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the first target region, as well as the semiconductor material layer, the gate dielectric material layer and the second conductive material layer in the third target region and the fourth target region on both sides of the first target region along the second direction, so that the retained semiconductor material layer constitutes a second semiconductor layer, the retained gate dielectric material layer constitutes a second gate dielectric layer, the second conductive material layer retained in the third target region close to the read bit line is the second part of the second gate, and the second conductive material layer retained in the fourth target region away from the read bit line is the write bit line; forming a third gate dielectric layer on the sidewalls of the second semiconductor layer and the second gate dielectric layer away from the read bit line; forming a first portion of the second gate in the third target region at the second portion and a sidewall of the third gate dielectric layer away from the read bit line; Sequentially forming a first semiconductor layer, a first gate dielectric layer and the first gate on the hole wall of the etched hole between the first portion and the write bit line to obtain the write transistor; The portion of the second semiconductor layer surrounding the second portion and connected to the common source line is the third source and drain; the portion of the second semiconductor layer located on the side of the second portion away from the first portion is the fourth source and drain; The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source and drain, and the portion of the first semiconductor layer extending along the first direction and located on the side of the first gate away from the first source and drain is the second source and drain; The write word line is formed synchronously with the first gate.

16. The method for preparing a memory according to claim 15, characterized in that: The method of removing the dummy write bit line and the retained dummy gate based on the etched hole to form an accommodation space further includes: A wet etching process is performed on the dummy write bit line and the retained dummy gate along the second direction and the first direction to form the accommodation space.

17. An electronic device, characterized in that: include: One or more memories as claimed in claim 10.

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