Power management method for ultra-high-speed SD memory card and design circuit thereof

Abstract

The invention provides a power management method for an ultra-high-speed SD (Secure Digital) memory card and a design circuit of the ultra-high-speed SD memory card, and the output voltage of an LDO (Low Dropout Regulator) is determined by changing the ratio of divider resistors on a feedback pin based on the fact that the voltage of the feedback pin of the LDO is a constant value. In the process that a chip integrated with an SD controller serves as a host to initialize the SD card, after the host confirms that the SD card is an ultra-high-speed card supporting 1.8 V, a gate end of an NMOS (N-channel metal oxide semiconductor) is controlled by outputting a control signal, a divider resistor on a feedback pin of an LDO (low dropout regulator) is controlled to be connected with other resistors in parallel according to the switching characteristic of the NMOS, and the two resistors are connected in parallel, so that the SD card is initialized. According to the principle that the parallel resistance value is smaller than the value of any one resistor, the output voltage of the LDO is changed by changing the ratio of the divider resistors on the feedback pin of the LDO, and the power supply of the SD memory card supporting the UHS-I is switched from 3.3 V to 1.8 V. The output of the LDO is changed from 3.3 V to 1.8 V, and only the high and low levels of one GPIO need to be controlled in the switching process. The method is easy to implement and low in cost, and the problems of level mismatching and reverse leakage of LDO output from high voltage to low voltage between power supplies do not exist.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a power management method for an ultra-high-speed SD memory card and a design circuit thereof. Background Art

[0002] In the prior art, the SD memory card is a new generation of memory device based on semiconductor flash memory. Due to its small size, fast data transmission speed, hot-swappable and other excellent features, it is widely used in portable devices such as digital cameras, tablet computers and multimedia players. In August 1999, Toshiba, SanDisk and Panasonic jointly launched the SD card, which eliminated the MMC and became the most frequently used memory card in digital cameras today. With the development of small portable devices such as mobile phones, the small-sized micro SD card was launched. Today, it has become the standard memory card for surveillance cameras, drones, and sports cameras. Only SD cards and micro SD cards are left on the market with SD specifications. The standard of SD memory cards has changed several times over the past two decades. When the SD standard reached V3.0.1, UHS-I was proposed, and its peak bandwidth reached 104MB / s (under SDR104 mode). Most of the SD memory cards on the market are UHS-I cards. The higher the signal transmission speed, the lower the voltage swing is required. The SD physical layer protocol specification stipulates that the UHS-I card must use a 1.8V signal level in SDR50 and SDR104 modes. The initialization process of the SD card is: after power-on, the SD card is first at a 3.3V signal level, but when the host sends a command through the CMD bus to negotiate with the SD card and confirms that it supports UHS-I, it switches the voltage to 1.8V. Then, the host configures the bus width 4bit and the drive strength and frequency to complete the bus configuration. Therefore, in the process of the host (SD card controller chip) initializing the SD card, in addition to using a 3.3V signal level, the IO of the SD bus also needs to reduce the IO signal level standard from 3.3V to 1.8V after negotiating to UHS-I. For the host (SD card controller chip), in addition to adjusting the signal level threshold of the SD bus IO during the initialization phase, it is also necessary to control the IO power supply voltage from 3.3V to 1.8V.

[0003] The currently known high-end and high-cost solution is to use PMU (power management chip) to provide power for the integrated SD card controller chip. The PMU (power management chip) is programmed with a default output power of 3.3V. When the integrated SD card controller chip as the host recognizes the SD card as an ultra-high-speed card, it controls the PMU through PMBUS (power management bus, usually I2C bus) to dynamically adjust the power output to 1.8V, providing power with varying levels for its own power supply and the pull-up power supply of the card's IO.

[0004] In the prior art, there is also a low-cost solution, for example, the low-cost solution adopted by Beijing Ingenic Integrated Circuit Co., Ltd. (hereinafter referred to as Ingenic): using a PMOS as a 3.3V power switch and an LDO with an output of 1.8V to form a 3.3V and 1.8V level switch. The control signal of this LDO and PMOS is the same signal. It is known that the default pull-down resistor realizes low-level control of PMOS conduction and LDO is turned off to provide 3.3V for the pull-up power supply of the SD card controller chip and the SD card IO. When the SD card controller chip identifies that the SD card is a high-speed card during the initialization process, the output control signal is high-level controlled, the PMOS is turned off, and the LDO is turned on to provide 1.8V for the pull-up power supply of the SD card controller chip and the SD card IO, thereby realizing dynamic switching of the signal level.

[0005] However, most of the current PMUs require product customization, which is costly, takes a long time to develop, and has too high a threshold for users. The problem with the lower-cost PMOS and LDO solutions is that when some LDOs are in the disabled state, if there is voltage on the output pin, there may be a risk of internal leakage of the LDO, increasing the total power consumption of the system. If a diode is added to prevent reverse leakage of the LDO output, the diode voltage drop will be different under different load currents. For example, 10mA may cause a 300mV voltage drop of the diode, so that the 1.8V power supply output of the LDO becomes 1.5V after passing through the diode to supply IO, which does not meet the level requirements. If the output is fixed at 2.1V directly through the LDO, when the current is less than 10uA, the diode has almost no voltage drop, which will also cause overvoltage of the power supply. Therefore, this lower-cost solution has the risk of leakage or voltage instability caused by voltage changes with current.

[0006] In addition, commonly used technical terms include:

[0007] UHS-I card: an ultra-high-speed SD card. UHS-I cards are available in two types: UHS50 (data bandwidth up to 50MB / s) and UHS104 (data bandwidth up to 104MB / s). SDR50: UHS-I card operation mode, single-edge sampling can reach up to 100MHz, data bandwidth up to 50MB / s. SDR104: UHS-I card operation mode, single-edge sampling can reach up to 208MHz, data bandwidth up to 104MB / s.

[0008] PMOS: The actual structure and conduction conditions of PMOS, such as Figure 1As shown in the figure, when the voltage from the gate terminal (pin 1) to the source terminal (pin 2) of the PMOS is positive, the source terminal (pin 2) to the drain terminal (pin 3) of the PMOS is not conducting. When the voltage from the gate terminal (pin 1) to the source terminal (pin 2) of the PMOS is negative (less than the conduction condition voltage), the source terminal (pin 2) to the drain terminal (pin 3) of the PMOS is conducting. Taking WPM3401 as an example, the on-resistance from the source terminal (pin 2) to the drain terminal (pin 3) is 46mΩ@VGS=-4.5V.

[0009] NMOS: The actual structure and conduction conditions of NMOS, such as Figure 2 As shown in the figure, when the voltage from the gate terminal (pin 1) to the source terminal (pin 3) of the NMOS is less than the minimum conduction condition, the drain terminal (pin 2) to the source terminal (pin 3) of the NMOS is not conducting. When the voltage from the gate terminal (pin 1) to the source terminal (pin 3) of the NMOS is a positive voltage (greater than the conduction condition voltage), the drain terminal (pin 2) to the source terminal (pin 3) of the NMOS is conducting. Taking WNM3013 as an example, the conduction voltage threshold V GSth The minimum value is 0.8V, the maximum value is 1.5V, and the on-resistance from the drain end (pin 2) to the source end (pin 3) is 1.9Ω@VGS=2.5V.

[0010] LDO: Low Dropout Regulator, is a low voltage difference linear regulator, which belongs to linear power supply. Its characteristics are low cost, simple peripheral circuit design and small output ripple.

[0011] GPIO: General-purpose input / output, short for general-purpose input / output, whose pins can be used by chip users for input, output or other special functions. For input, the pin potential is determined by reading a register; for output, the pin outputs a high or low potential by writing to a register. Generally, most of the pins of processor chips, including chips with integrated SD controllers, are GPIOs. By connecting GPIO pins to external hardware devices, the processor chip can communicate with the outside, control external hardware, or collect external hardware data. Summary of the invention

[0012] In order to solve the above problems, the purpose of this application is to determine the output voltage of the LDO by changing the ratio of the voltage-dividing resistor on the feedback pin based on the fact that the voltage of the LDO feedback pin is a constant value. During the process of the host (SD controller chip) initializing the SD card, when the host confirms that the SD card is an ultra-high-speed card that supports the 1.8V signal level standard, it controls the gate end of the NMOS by outputting a control signal, and uses the NMOS switch characteristics to control a voltage-dividing resistor on the feedback pin of the LDO in parallel with other resistors. According to the principle that the two resistors are connected in parallel and the parallel resistance is smaller than the value of any one resistor, the ratio of the voltage-dividing resistor on the LDO feedback pin is changed to change the output voltage of the LDO, thereby realizing the switching of the power supply of the SD memory card supporting UHS-I from 3.3V to 1.8V. The LDO output changes from 3.3V to 1.8V, and the entire switching process can be achieved by only requiring the host to control the level output of a GPIO pin as a control signal connected to the gate end of the NMOS.

[0013] Specifically, the present invention provides a method for managing power supply of an ultra-high-speed SD memory card, the method comprising the following steps:

[0014] S1, during the SD card initialization process, the SD controller chip as a host outputs a control signal to control the gate end of NMOS Q1, and the drain end of the NMOS is connected in series with a resistor R3 and then connected to the power output end of the LDO, and the source end of the NMOS is connected to the feedback pin of the LDO, forming a circuit in which NMOS Q1 and the resistor R3 are connected in parallel with the voltage divider resistor R1;

[0015] S2, by default, the control signal is low level and NMOS is not turned on, which is equivalent to no resistor R3 connected in parallel with R1, so the voltage divider resistor ratio on the LDO feedback pin is resistor R1 to resistor R2; S3, when NMOS is turned on, resistor R3 is connected in parallel with R1, at this time, the voltage divider resistor ratio on the LDO feedback pin is the resistance value of resistors R1 and R3 connected in parallel to resistor R2, because R1 and R3 are connected in parallel, and the parallel resistance is smaller than the resistance of R1, so after NMOS is turned on, the voltage divider resistor ratio on the LDO feedback pin becomes smaller, and because the feedback pin voltage of LDO is a constant value, the output voltage of LDO becomes smaller;

[0016] S4, and by calculating the voltage divider resistor ratio on the feedback pin and selecting the appropriate voltage divider resistor value, the output voltage can be changed from 3.3V level output to 1.8V level power supply switching circuit.

[0017] The step S2 further comprises:

[0018] When NMOS is not conducting, the power switching circuit design is equivalent to the circuit without resistor R3, VFB is the feedback voltage of LDO, R1 and R2 are voltage divider resistors used to adjust the voltage, V OUT is the output voltage of the LDO, and the expression of the LDO output voltage is:

[0019]

[0020] When the default state control signal is low level and NMOS is not conducting, the output voltage V OUT =3.3V, then through formula (1) we can get:

[0021]

[0022]

[0023] The step S3 further comprises:

[0024] When NMOS is turned on, the power switching circuit is designed to connect the equivalent resistor R3 in parallel with R1. After R1 is connected in parallel with R3, the resistance value of the parallel connection is The expression of the LDO output voltage is:

[0025]

[0026] The SD controller chip acts as a host and outputs a high-level control signal to control the NMOS to turn on. The output voltage V OUT =1.8V, then through formula (3) we can get:

[0027]

[0028]

[0029]

[0030] After combining equations (2) and (4), We get the system of equations:

[0031]

[0032] The step S4 further comprises:

[0033] The relationship between R1, R2 and R3 is obtained from step S3, and is applied to a specific power switching design circuit through the equation group to obtain a suitable resistance value:

[0034] Assuming that the adjustable feedback voltage of the LDO is 0.6V, we can obtain

[0035] The relationship between the resistors can be obtained. Assuming that the resistance value of R1 is 150KΩ, the resistance value of R2 is 33.33KΩ with two decimal places, and the resistance value of R3 is 120KΩ. That is, in the initial default state, the control signal is low-level and NMOS is not turned on. Under the action of the voltage divider resistors R1 and R2, the LDO output is 3.3V. Once the control signal is high-level and NMOS is turned on, R3 is connected in parallel with R1, and the output of LDO becomes 1.8V.

[0036] Assuming that the LDO adjustable feedback voltage is 0.8V, through equation (5), we get:

[0037]

[0038] The relationship between the resistors can be obtained. Similarly, assuming that the resistance value of R1 is 150KΩ, then R2 is 47.5KΩ and R3 is 100KΩ. Therefore, in the initial default state, the control signal is low-level and NMOS is not turned on. Under the action of the voltage divider resistors R1 and R2, the LDO output is 3.3V. Once the control signal is high-level and NMOS is turned on, R3 is connected in parallel with R1, and the output of LDO becomes 1.8V.

[0039] The method changes the ratio of the voltage-dividing resistors on the LDO feedback pin to change the output voltage of the LDO, thereby switching the power supply of the SD memory card supporting UHS-I from 3.3V to 1.8V.

[0040] The LDO output changes from 3.3V to 1.8V. In the method, the entire switching process can be achieved by controlling the high and low levels of a GPIO, that is, the SD controller chip acts as a host, and any idle GPIO is configured as an output control signal, which is connected to the gate end of the NMOS. The default control signal is low, the NMOS is not turned on, and the LDO default output voltage is 3.3V; when the SD controller is used as a host to initialize the SD card and recognizes that the SD card is an ultra-high-speed card, the GPIO is controlled to output a high level as a control signal, and the NMOS is controlled to be turned on, so that the LDO output voltage changes from 3.3V to 1.8V.

[0041] The present application also relates to a circuit designed for power management of an ultra-high-speed SD memory card, the circuit being applied to any of the above-mentioned methods, the circuit comprising:

[0042] The power chip LDO sets the FB pin as its feedback pin, and sets the OUT pin as the LDO power output VDDIO_SD to power the pull-up resistor of the SD bus, and also powers the IO power domain power input pin of the SD bus of the SD controller chip. In the process of the SD controller chip initializing the SD card as a host, set VSD18_EN as the control signal output by the host. The default initial state is low level 0V, which controls the gate end of NMOS Q1. The source end of Q1 is connected to the feedback pin FB of the power chip LDO. At this time, the voltage V from the gate end to the source end of Q1 is GS =-V FB It is less than the minimum conduction condition of NMOS Q1, so Q1 is not conducting. The output voltage of LDO depends on the ratio of its voltage divider resistors R1 and R2. At this time, VOUT is:

[0043] Once the SD controller chip as the host confirms that the SD card is a 1.8V ultra-high-speed card, it outputs the control signal VSD18_EN to a high level of 3.3V. At this time, the gate voltage of Q1 is equal to the source voltage V GS =3.3-V FB , which is greater than the conduction condition of NMOS Q1, so Q1 is turned on, and the drain end of Q1 is connected to one end of resistor R3, and the other end of R3 is connected to the voltage divider resistor and V OUT connected, R3 and R1 are connected in parallel; at this time, V OUT :

[0044]

[0045]

[0046]

[0047] When the SD controller chip acts as a host to initialize the SD card, the VDDIO_SD power supply voltage is switched from 3.3V to 1.8V.

[0048] The voltage V of the feedback pin FB of the power chip LDO FB is 0.6V.

[0049] The NMOS includes WNM3013,

[0050] When V GS =-V FB =-0.6V is less than the minimum conduction condition of NMOS Q1, Q1 is not conducting, and its conduction voltage threshold V GSth The minimum value is 0.8V, and the output voltage of LDO VOUT :

[0051]

[0052] When V GS =3.3-V FB =2.7V is greater than the conduction condition of NMOS Q1, Q1 is turned on, and its conduction voltage threshold V GSth The maximum value is 1.5V. At this time, V OUT :

[0053]

[0054] Therefore, the advantages of the present application are: compared with the customized PMU solution of the prior art, the solution of the present application is simple to implement and low-cost, and the IO power supply of the host and the SD card is always powered by the same LDO output. Compared with the low-cost solution of the prior art, there is no level mismatch and possible reverse leakage problem from the 3.3V high voltage to the 1.8V low voltage LDO output between the power supplies. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of this application, and do not constitute a limitation of the present invention.

[0056] Figure 1 It is a schematic diagram of the actual structure and conduction conditions of PMOS in the prior art.

[0057] Figure 2 It is a schematic diagram of the actual structure and conduction conditions of NMOS in the prior art.

[0058] Figure 3 It is a schematic diagram of the power circuit switching design of this application.

[0059] Figure 4 It is an equivalent schematic diagram of the power switching circuit design when the NMOS is not conducting.

[0060] Figure 5 It is the equivalent schematic diagram of the power switching circuit design when the NMOS is turned on.

[0061] Figure 6 It is a schematic diagram of the SD card power switching design application circuit of this application.

[0062] Figure 7 This is the actual circuit for the SD card power design application of the Ingenic X2000 chip in the embodiment of this application.

[0063] Figure 8 It is a flow chart of the present application method. DETAILED DESCRIPTION

[0064] In order to more clearly understand the technical content and advantages of the present invention, the present invention is now further described in detail in conjunction with the accompanying drawings.

[0065] The present application proposes a method for managing the power supply of an ultra-high-speed SD memory card and a design circuit thereof. The present invention is based on the working principle that the voltage of the feedback pin of the LDO is a constant value and the ratio of the voltage-dividing resistors on the feedback pin determines the output voltage of the LDO. The voltage-dividing resistor on the feedback pin of the LDO is controlled to be connected in parallel with a resistor through an NMOS switch characteristic. According to the principle that the two resistors are connected in parallel and the parallel resistance is smaller than the value of any one resistor, the ratio of the voltage-dividing resistors on the feedback pin of the LDO is changed to control the output voltage of the LDO, thereby realizing the switching of the power supply of the SD memory card supporting UHS-I.

[0066] The power switching design diagram is as follows Figure 3 As shown, during the SD card initialization process, the host (SD controller chip) outputs a control signal to control the gate end of NMOS Q1, and the drain end of this NMOS is connected in series with a resistor R3 and then connected to the power output end of the LDO. The source end of the NMOS is connected to the feedback pin of the LDO, forming a circuit in which NMOS Q1 and R3 are connected in parallel with the voltage divider resistor R1.

[0067] By default, the control signal is low level, and the NMOS is not turned on, which is equivalent to no resistor R3 connected in parallel with R1. The equivalent circuit diagram of the power switching circuit design is as follows: Figure 4 As shown, the voltage divider resistor ratio on the LDO feedback pin is resistor R1 to resistor R2;

[0068] When NMOS is turned on, the equivalent circuit diagram of the power switching circuit design is as follows Figure 5 As shown, resistor R3 is connected in parallel with R1. At this time, the voltage-dividing resistor ratio on the feedback pin of the LDO is the resistance value of the resistors R1 and R3 connected in parallel to the resistor R2. Because the two resistors R1 and R3 are connected in parallel, the parallel resistance is smaller than the resistance of R1. Therefore, after the NMOS is turned on, the voltage-dividing resistor ratio on the feedback pin of the LDO becomes smaller. Because the feedback pin voltage of the LDO is a constant value, the output voltage of the LDO becomes smaller.

[0069] By calculating the voltage divider resistor ratio on the feedback pin and selecting the appropriate voltage divider resistor value, the output voltage can be changed from a 3.3V level output to a 1.8V level power supply switching circuit.

[0070] When NMOS is not conducting, the equivalent schematic diagram of the power switching circuit design is as follows Figure 4 As shown. FB is the feedback voltage of LDO, R1 and R2 are voltage divider resistors used to adjust the voltage, V OUTis the output voltage of the LDO.

[0071] Figure 4 The expression of LDO output voltage is as follows:

[0072] The default control signal is low level, when NMOS is not conducting, the output voltage V OUT =3.3V, then put it into equation (1) and we get:

[0073]

[0074]

[0075] When NMOS is turned on, the equivalent schematic diagram of the power switching circuit design is as follows Figure 5 As shown. When R1 is connected in parallel with R3, the resistance value of the parallel connection is like Figure 5 The expression of the LDO output voltage shown is formula (3):

[0076]

[0077] The host output control signal is high level to control NMOS conduction, the output voltage V OUT =1.8V, then inserting formula (3) will lead to formula (4):

[0078]

[0079]

[0080]

[0081] After solving the simultaneous equations The relationship between R1, R2 and R3 is obtained. Through the above equations, it is applied to the specific power switching design circuit, such as Figure 6 As shown, just take the appropriate resistance value.

[0082] As shown in the following two specific embodiments, different LDO design applications are demonstrated: Example 1: Assuming that the adjustable feedback voltage of the LDO is 0.6V, through formula (5), we get

[0083]

[0084] The relationship between the resistors can be obtained. Assuming that the resistance value of R1 is 150KΩ, the resistance value of R2 is about 33.33KΩ, and the resistance value of R3 is 120KΩ. That is, in the initial default state, the control signal is low-level and NMOS is not turned on. Under the action of the voltage divider resistors R1 and R2, the LDO output is about 3.3V. Once the control signal is high-level and NMOS is turned on, R3 is connected in parallel with R1, and the output of LDO becomes 1.8V.

[0085] Example 2: Assuming that the LDO adjustable feedback voltage is 0.8V, through equation (5), we get:

[0086]

[0087] The relationship between the resistors can be known. Similarly, assuming that the resistance value of R1 is 150KΩ, then R2 is 47.5KΩ and R3 is 100KΩ. Therefore, in the initial default state, the control signal is low-level and NMOS is not turned on. Under the action of the voltage divider resistors R1 and R2, the LDO output is about 3.3V. Once the control signal is high-level and NMOS is turned on, R3 is connected in parallel with R1, and the output of LDO becomes 1.8V.

[0088] The above design method has been verified in the design of many Ingenic platforms that support UHS-I chips. For example, on the Ingenic Halley development platform, the SD card power design application circuit of the Ingenic X2000 chip is shown in the figure below. Figure 7 As shown. In the figure, U2B is a power chip LDO, and its 15th pin LDOFB is used as a feedback pin with a voltage of 0.6V. Its 16th pin is used as the LDO power output VDDIO_SD to supply power to the pull-up resistor of the SD bus, and also supplies power to U1B, which is the IO power domain power input pin VDDIO33_SD of the SD bus of Ingenic's processor chip X2000. In the process of X2000 initializing the SD card as a host, VSD18_EN is used as the control signal output by the host. The default initial state is low level 0V, which controls the gate end of NMOS Q1. The source end of Q1 is connected to the 15th pin LDOFB of U2B. At this time, the voltage V from the gate end to the source end of NMOS Q1 is GS =-0.6V, V GS It means that the gate voltage minus the source voltage is less than the minimum conduction condition of NMOS Q1 (the conduction voltage threshold V GSth The minimum value is 0.8V), so Q1 is not conducting. The output voltage of LDO depends on the ratio of its voltage divider resistors R1 and R2.

[0089]

[0090] Once the host confirms that the SD card is a 1.8V ultra-high-speed card, it outputs the control signal VSD18_EN to a high level of 3.3V. At this time, the gate voltage of Q1 is equal to the source voltage V GS =2.7V is greater than the conduction condition of NMOS Q1 (the conduction voltage threshold V GSth The maximum value is 1.5V), so Q1 is turned on, and the drain end of Q1 is connected to one end of resistor R3, and the other end of R3 is connected to the voltage divider resistor and V OUT connected to realize parallel connection of R3 and R1; at this time

[0091]

[0092] When X2000 is used as host to initialize the SD card, the VDDIO_SD power supply voltage is switched from 3.3V to 1.8V.

[0093] In summary, if Figure 8 As shown, the method for managing the power supply of the ultra-high-speed SD memory card involved in this application includes the following steps:

[0094] S1, during the SD card initialization process, the SD controller chip as a host outputs a control signal to control the gate end of NMOS Q1, and the drain end of the NMOS is connected in series with a resistor R3 and then connected to the power output end of the LDO, and the source end of the NMOS is connected to the feedback pin of the LDO, forming a circuit in which NMOS Q1 and the resistor R3 are connected in parallel with the voltage divider resistor R1;

[0095] S2, by default, the control signal is low level and NMOS is not turned on, which is equivalent to no resistor R3 connected in parallel with R1, so the voltage divider resistor ratio on the LDO feedback pin is resistor R1 to resistor R2; S3, when NMOS is turned on, resistor R3 is connected in parallel with R1, at this time, the voltage divider resistor ratio on the LDO feedback pin is the resistance value of resistors R1 and R3 connected in parallel to resistor R2, because R1 and R3 are connected in parallel, and the parallel resistance is smaller than the resistance of R1, so after NMOS is turned on, the voltage divider resistor ratio on the LDO feedback pin becomes smaller, and because the feedback pin voltage of LDO is a constant value, the output voltage of LDO becomes smaller;

[0096] S4, and by calculating the voltage divider resistor ratio on the feedback pin and selecting the appropriate voltage divider resistor value, the output voltage can be changed from 3.3V level output to 1.8V level power supply switching circuit.

[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for managing power supply of an ultra-high-speed SD memory card, characterized in that: The method comprises the following steps: S1, during the SD card initialization process, the SD controller chip as a host outputs a control signal to control the gate end of NMOS Q1, and the drain end of the NMOS is connected in series with a resistor R3 and then connected to the power output end of the LDO, and the source end of the NMOS is connected to the feedback pin of the LDO, forming a circuit in which NMOS Q1 and the resistor R3 are connected in parallel with the voltage divider resistor R1; S2, by default, the control signal is low level and the NMOS is not turned on, which is equivalent to no resistor R3 connected in parallel with R1, so the voltage divider resistor ratio on the LDO feedback pin is resistor R1 to resistor R2; S3, and when NMOS is turned on, resistor R3 is connected in parallel with R1. At this time, the voltage-dividing resistor ratio on the feedback pin of LDO is the resistance value of the resistor R1 and R3 connected in parallel to the resistor R2. Because the two resistors R1 and R3 are connected in parallel, the parallel resistance is smaller than the resistance value of R1. Therefore, after NMOS is turned on, the voltage-dividing resistor ratio on the feedback pin of LDO becomes smaller. Since the feedback pin voltage of LDO is a constant value, the output voltage of LDO becomes smaller. S4, and by calculating the voltage divider resistor ratio on the feedback pin and selecting the appropriate voltage divider resistor value, the output voltage can be changed from 3.3V level output to 1.8V level power supply switching circuit.

2. A method for managing power supply of an ultra-high-speed SD memory card according to claim 1, characterized in that: The step S2 further comprises: When NMOS is not conducting, the power switching circuit design is equivalent to the circuit without resistor R3, V FB is the feedback voltage of LDO, R1 and R2 are voltage divider resistors used to adjust the voltage, V OUT is the output voltage of the LDO, and the expression of the LDO output voltage is: When the default state control signal is low level and NMOS is not conducting, the output voltage V OUT =3.3V, then through formula (1) we can get:

3. A method for managing power supply of an ultra-high-speed SD memory card according to claim 2, characterized in that: The step S3 further comprises: When NMOS is turned on, the power switching circuit is designed to connect the equivalent resistor R3 in parallel with R1. After R1 is connected in parallel with R3, the resistance value of the parallel connection is The expression of the LDO output is: The SD controller chip acts as a host and outputs a high-level control signal to control the NMOS to turn on. The output voltage V OUT =1.8V, then through formula (3) we can get: After combining equations (2) and (4), We get the system of equations:

4. A method for managing power supply of an ultra-high-speed SD memory card according to claim 3, characterized in that: The step S4 further comprises: The relationship between R1, R2 and R3 is obtained from step S3, and is applied to a specific power switching design circuit through the equation group to obtain a suitable resistance value: Assume that the LDO adjustable feedback voltage V FB When it is 0.6V, through formula (5), we get The relationship between the resistors can be obtained. Assuming that the resistance value of R1 is 150KΩ, the resistance value of R2 is 33.33KΩ with two decimal places, and the resistance value of R3 is 120KΩ. That is, in the initial default state, the control signal is low-level and NMOS is not turned on. Under the action of the voltage divider resistors R1 and R2, the LDO output is 3.3V. Once the control signal is high-level and NMOS is turned on, R3 is connected in parallel with R1, and the output of LDO becomes 1.8V. Assuming that the LDO adjustable feedback voltage is 0.8V, through equation (5), we get: The relationship between the resistors can be obtained. Similarly, assuming that the resistance value of R1 is 150KΩ, then R2 is 47.5KΩ and R3 is 100KΩ. Therefore, in the initial default state, the control signal is low-level and NMOS is not turned on. Under the action of the voltage divider resistors R1 and R2, the LDO output is 3.3V. Once the control signal is high-level and NMOS is turned on, R3 is connected in parallel with R1, and the output of LDO becomes 1.8V.

5. The method for managing power supply of an ultra-high-speed SD memory card according to claim 1, characterized in that: The method changes the ratio of the voltage-dividing resistors on the LDO feedback pin to change the output voltage of the LDO, thereby switching the power supply of the SD memory card supporting UHS-I from 3.3V to 1.8V.

6. The method for managing power supply of an ultra-high-speed SD memory card according to claim 1, characterized in that: The LDO output changes from 3.3V to 1.8V. In the method, the entire switching process can be achieved by controlling the high and low levels of a GPIO, that is, the SD controller chip acts as a host, and configures any idle GPIO as an output control signal, which is connected to the gate end of the NMOS; the default control signal is a low level, the NMOS is not turned on, and the LDO default output voltage is 3.3V; when the SD controller acts as a host to initialize the SD card and identifies that the SD card is an ultra-high-speed card, the GPIO is controlled to output a high level as a control signal, and the NMOS is controlled to be turned on, so that the LDO output voltage changes from 3.3V to 1.8V.

7. A circuit design for power management of ultra-high-speed SD memory card, characterized in that: The circuit is applied to the method described in any one of claims 1 to 6, and the circuit comprises: The power chip LDO sets the FB pin as its feedback pin, and sets the OUT pin as the LDO power output VDDIO_SD to power the pull-up resistor of the SD bus, and also powers the IO power domain power input pin of the SD bus of the SD controller chip. In the process of the SD controller chip initializing the SD card as a host, set VSD18_EN as the control signal output by the host. The default initial state is low level 0V, which controls the gate end of NMOS Q1. The source end of Q1 is connected to the feedback pin FB of the power chip LDO. At this time, the voltage V from the gate end to the source end of Q1 is GS =-V FB , which is less than the minimum conduction condition of NMOS Q1, so Q1 is not conducting. The output voltage of LDO depends on the ratio of its voltage divider resistors R1 and R2. At this time, VOUT is: Once the SD controller chip as the host confirms that the SD card is a 1.8V ultra-high-speed card, it outputs the control signal VSD18_EN to a high level of 3.3V. At this time, the voltage V GS =3.3-V FB , which is greater than the conduction condition of NMOS Q1, so Q1 is turned on, and the drain end of Q1 is connected to one end of resistor R3, and the other end of R3 is connected to the voltage divider resistor and V OUT connected, R3 and R1 are connected in parallel; at this time, V OUT : When the SD controller chip acts as a host to initialize the SD card, the VDDIO_SD power supply voltage is switched from 3.3V to 1.8V.

8. The circuit for designing power management for ultra-high-speed SD memory cards according to claim 7, characterized in that: The voltage V of the pin FB of the power chip LDO FB is 0.6V.

9. The circuit for designing power management for ultra-high-speed SD memory cards according to claim 8, characterized in that: The NMOS includes WNM3013, When V GS =-V FB =-0.6V is less than the minimum conduction condition of NMOS Q1, Q1 is not conducting, and its conduction voltage threshold V GSth The minimum value is 0.8V, and the output voltage of LDO V OUT : When V GS =3.3-V FB =2.7V is greater than the conduction condition of NMOS Q1, Q1 is turned on, and its conduction voltage threshold V GSth The maximum value is 1.5V. At this time, V OUT :

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