Memory unit, memory device, memory unit, and operating method of

Abstract

The invention discloses a memory cell, a memory device, a memory cell, and an operation method of the memory device. The memory cell includes: a memory; the gating device comprises a gating layer, the gating layer comprises at least two sub-gating layers and a threshold voltage adjusting layer, the threshold voltages of the at least two sub-gating layers are different, so that the gating device has different opening states under different threshold voltage conditions, the at least two sub-gating layers are arranged on the two sides of the threshold voltage adjusting layer in the first direction respectively, and the threshold voltage adjusting layer is arranged on the threshold voltage adjusting layer in the second direction. The threshold voltage adjusting layer may selectively adjust a threshold voltage of at least one of the at least two sub-gate layers. Therefore, the gate has at least two different threshold voltages, the gate has different opening states under different threshold voltage conditions, and the different opening states of the gate can control the memory to execute different operations, so that misoperation of the memory under the different opening states of the gate can be avoided; therefore, the operation reliability of the storage unit can be ensured.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a storage unit, a storage device, and an operating method of the storage unit and the storage device. Background Art

[0002] The new memory includes a selector and a memory. The selector requires a higher voltage to start the operation each time the memory performs a read or write operation. The existing new memory commonly uses a 1T1M, 1S1M or 1D1M array structure, where T is a transistor, S is a selector, D is a diode, and M is a memory. Different voltages are applied to both ends of a selector to start the read or write operation.

[0003] In the related art, when the threshold voltage of the read operation is large, the memory has the risk of being written by mistake. In addition, a large voltage will reduce the service life of the gate tube, and a large current will cause the gate tube to generate large power consumption. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, one object of the present invention is to provide a storage unit that can ensure the reliability of operation.

[0005] The present invention further provides an operating method of a storage unit.

[0006] The present invention further provides a storage device.

[0007] The present invention further provides an operating method of a storage device.

[0008] A memory cell according to an embodiment of the present invention comprises: a memory, wherein a first end of the memory is suitable for being electrically connected to a word line driving circuit; a gate, wherein the gate comprises a first electrode layer, a gate layer, and a second electrode layer, wherein the first electrode layer is arranged on a first side of the gate layer in a first direction, and the second electrode layer is arranged on a second side of the gate layer in the first direction opposite to the first side, wherein one of the first electrode layer and the second electrode layer is suitable for being electrically connected to a bit line driving circuit, and the other is suitable for being electrically connected to a second end of the memory; the gate layer comprises at least two sub-gate layers and a threshold voltage adjustment layer, wherein the threshold voltages of at least two of the sub-gate layers are different, so that the gate has different turn-on states under different threshold voltage conditions, and wherein at least two of the sub-gate layers are respectively arranged on both sides of the threshold voltage adjustment layer in the first direction, and wherein the threshold voltage adjustment layer can selectively adjust the threshold voltage of at least one of the at least two sub-gate layers.

[0009] Therefore, by setting the gate to have at least two different threshold voltages, and the gate to have different on states under different threshold voltage conditions, the different on states of the gate can control the memory to perform different operations, thereby avoiding the memory from erroneous operation under different on states of the gate, thereby ensuring the operational reliability of the storage unit.

[0010] According to some embodiments of the present invention, the gating layer includes a first gating layer and a second gating layer, the first gating layer and the second gating layer are respectively arranged on both sides of the threshold voltage adjustment layer in a first direction, and the threshold voltages of the first gating layer and the second gating layer are different.

[0011] According to some embodiments of the present invention, the threshold voltage of the first selection layer is set to V1th, and the threshold voltage of the second selection layer is set to V2th, V1th and V2th satisfy the relationship: V1th<V2th, and the threshold voltage adjustment layer is suitable for adjusting the threshold voltage of the second selection layer.

[0012] According to some embodiments of the present invention, V1th and V2th satisfy the relationship: 0.2V≤V1th≤1.0V, 0.6V≤V2th≤1.8V.

[0013] According to some embodiments of the present invention, the thickness of the threshold voltage adjustment layer in the first direction is smaller than the thickness of the first gating layer in the first direction, and the thickness of the threshold voltage adjustment layer in the first direction is smaller than the thickness of the second gating layer in the first direction.

[0014] According to some embodiments of the present invention, the thickness of the threshold voltage adjustment layer in the first direction is set to D, and D satisfies the relationship: 0<D<10nm.

[0015] According to some embodiments of the present invention, the material of the threshold voltage adjustment layer includes at least one of silicon dioxide, titanium dioxide, tantalum pentoxide, tungsten trioxide, hafnium dioxide and zirconium dioxide.

[0016] According to some embodiments of the present invention, the first gating layer and / or the second gating layer includes at least one of a bidirectional threshold switch layer, a diode layer, and a converter layer of a metal-insulator-metal structure.

[0017] According to some embodiments of the present invention, the switching layer material of the first gating layer and / or the second gating layer includes: at least one of niobium oxide and vanadium oxide.

[0018] According to some embodiments of the present invention, the first gating layer, and / or the second gating layer, and / or the threshold voltage adjustment layer are made by at least one of chemical vapor deposition, physical vapor deposition and atomic layer deposition.

[0019] According to some embodiments of the present invention, the memory includes at least one of a resistive memory, a phase change memory, a magnetic random access memory and a ferroelectric memory.

[0020] A method for operating a memory cell according to the present invention is suitable for the memory cell described above, comprising the following steps: setting the voltage difference between a word line driving circuit and a bit line driving circuit respectively connected to two ends of the memory cell to Vsel, setting the Vsel to satisfy the relationship: V1th≤Vsel, so as to control the gate of the memory cell to enter a first on state, and perform a read operation on the memory of the memory cell; wherein the threshold voltage of the first on state of the gate is V1th.

[0021] According to some embodiments of the present invention, the gate includes at least a first gate layer and a second gate layer, and the Vsel is set to satisfy the relationship: V1th≤Vsel<V2th, the first gate layer of the storage cell is controlled to be turned on, and the second gate layer of the storage cell is controlled to be turned off, and a read operation is performed on the memory of the storage cell; wherein the threshold voltage of the first gate layer of the storage cell is V1th, and the threshold voltage of the second gate layer of the storage cell is V2th.

[0022] A method for operating a memory cell according to the present invention is suitable for the memory cell described above, comprising the following steps: setting the voltage difference between a word line driving circuit and a bit line driving circuit respectively connected to the two ends of the memory cell to Vsel, setting the Vsel to satisfy the relationship: V2th≤Vsel, so as to control the gate of the memory cell to enter a second on state, and perform a write operation on the memory of the memory cell; wherein the threshold voltage of the second on state of the gate is V2th.

[0023] According to some embodiments of the present invention, the gate includes at least a first gate layer and a second gate layer, and the Vsel is set to satisfy the relationship: V1th≤Vsel and V2th≤Vsel, so as to control the first gate layer and the second gate layer of the storage cell to be turned on, and perform a write operation on the memory of the storage cell; wherein the threshold voltage of the first gate layer of the storage cell is V1th, the threshold voltage of the second gate layer of the storage cell is V2th, and V1th<V2th.

[0024] According to some embodiments of the present invention, the step of performing a write operation on the memory of the storage unit also includes: when a write 1 operation is performed on the memory, Vsel satisfies the relationship: Vsel=Vset, wherein the threshold voltage of the memory for writing 1 is Vset; when a write 0 operation is performed on the memory, Vsel satisfies the relationship: Vsel=Vreset, wherein the threshold voltage of the memory for writing 0 is Vreset.

[0025] A storage device according to an embodiment of the present invention comprises: a front-end driving circuit, the front-end driving circuit comprising a bit line driving circuit and a word line driving circuit; a storage array, the storage array comprising a plurality of storage cells according to any one of claims 1 to 11, a first end of the memory of the storage cell being electrically connected to the word line driving circuit, a first end of the gate of the storage cell being electrically connected to the bit line driving circuit, and a second end of the gate being suitable for being electrically connected to a second end of the memory.

[0026] An operating method for a storage device according to the present invention is suitable for the storage device described above, comprising the following steps: the threshold voltage of the on state of the gate of the storage cell is V1th, the voltage difference between the word line driving circuit and the bit line driving circuit respectively connected to the two ends of the target storage cell in the storage device is set to Vsel, and the voltage difference between the word line driving circuit and the bit line driving circuit respectively connected to the two ends of the non-target storage cell in the storage device is set to Vunsel; Vsel is set to satisfy the relationship: V1th≤Vsel, the gate of the target storage cell is controlled to be turned on, and a read operation or a write operation is performed on the memory of the target storage cell; Vunsel is set to satisfy the relationship: Vunsel<V1th, and the gate of the non-target storage cell is controlled to be turned off.

[0027] According to some embodiments of the present invention, the gate includes at least a first gate layer and a second gate layer; Vsel is set to satisfy the relationship: V1th≤Vsel<V2th, the first gate layer of the target storage unit is controlled to be turned on, the second gate layer of the target storage unit is controlled to be turned off, and a read operation is performed on the memory of the target storage unit; or, Vsel is set to satisfy the relationship: V2th≤Vsel, the first gate layer and the second gate layer of the target storage unit are controlled to be turned on, and a write operation is performed on the memory of the target storage unit; Vunsel is set to satisfy the relationship: Vunsel<V1th, the first gate layer and the second gate layer of the non-target storage unit are controlled to be turned off; wherein the threshold voltage of the first gate layer of the storage unit is V1th, the threshold voltage of the second gate layer of the storage unit is V2th, and V1th and V2th satisfy the relationship: V1th<V2th.

[0028] According to some embodiments of the present invention, the step of performing a write operation on the memory of the target memory cell also includes: when a write 1 operation is performed on the target memory cell, Vsel satisfies the relationship: Vsel=Vset, wherein the threshold voltage of the target memory cell for performing write 1 is Vset; when a write 0 operation is performed on the target memory cell, Vsel satisfies the relationship: Vsel=reset, wherein the threshold voltage of the target memory cell for performing write 0 is Vreset.

[0029] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a schematic diagram of a storage device according to an embodiment of the present invention; Figure 2 is a schematic diagram of a storage unit according to an embodiment of the present invention; Figure 3 is a schematic diagram of a gate according to an embodiment of the present invention; Figure 4 Schematic diagram of characteristic voltage-current curve of a memory cell according to an embodiment of the present invention.

[0031] Reference numerals: 100. Storage device; 10. Front-end drive circuit; 11. Bit line drive circuit; 12. Word line drive circuit; 20. Storage array; 21. Storage cell; 211. Memory; 212. Selector; 2121. First electrode layer; 2122. Second electrode layer; 2123. Select layer; 21231. First select layer; 21232. Second select layer; 21233. Threshold voltage adjustment layer. DETAILED DESCRIPTION

[0032] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0033] In the prior art, the new memory adopts the 1S1M (1-bit single-layer unit cross array) method, which includes a gate tube and a memory, and has the advantages of high density, low sneak current, low cost, and CMOS (complementary metal oxide semiconductor technology) compatibility. However, the gate tube in 1S1M requires a higher voltage for on switch operation each time reading and writing. This operation mode will cause the following problems in the array: a larger current is generated, thereby generating a larger power consumption; a larger voltage will reduce the service life of the memory; during the reading operation, if the gate tube is connected to a larger threshold voltage, the memory will be at risk of being written incorrectly. To this end, an embodiment of the present invention proposes a storage device with a gate having multiple operation intervals, that is, the reading and writing of the storage device can be performed at different threshold voltages.

[0034] Reference below Figure 1-Figure 4 The storage unit 21 according to an embodiment of the present invention is described.

[0035] Combination Figure 1-Figure 3 As shown, the memory cell 21 according to an embodiment of the present invention may mainly include: a memory 211 and a gate 212, wherein the first end of the memory 211 is suitable for being electrically connected to the word line driving circuit 12, the gate 212 includes a first electrode layer 2121, a gate layer 2123 and a second electrode layer 2122, the first electrode layer 2121 is arranged on a first side of the gate layer 2123 in a first direction, the second electrode layer 2122 is arranged on a second side of the gate layer 2123 in the first direction opposite to the first side, one of the first electrode layer 2121 and the second electrode layer 2122 is suitable for being electrically connected to the bit line driving circuit 11, and the other is suitable for being electrically connected to the second end of the memory 211.

[0036] Specifically, one of the first electrode layer 2121 and the second electrode layer 2122 is suitable for being electrically connected to the bit line driving circuit 11, and the other is suitable for being electrically connected to the second end of the memory 211, the first end of the memory 211 is suitable for being electrically connected to the word line driving circuit 12, and the first electrode layer 2121 and the second electrode layer 2122 are arranged on opposite sides of the selection layer 2123 in the first direction. In this way, the first electrode layer 2121, the selection layer, the second electrode layer 2122 and the memory 211 in the memory cell 21 can be connected together between the word line driving circuit 12 and the bit line driving circuit 11, so as to apply a voltage to both ends of the memory cell 21, thereby ensuring the circuit connectivity inside the memory cell 21.

[0037] In the embodiment of the present invention, the materials of the first electrode layer 2121 and the second electrode layer 2122 include but are not limited to tin, platinum, ruthenium, iridium, gold, and protactinium. It should be noted that the first electrode layer 2121 and the second electrode layer 2122 can be made of the same material, or the first electrode layer 2121 and the second electrode layer 2122 can be made of different materials.

[0038] Furthermore, the selection layer 2123 includes at least two sub-selection layers 2123 and a threshold voltage adjustment layer 21233, wherein the threshold voltages of at least two sub-selection layers 2123 are different, so that at least two sub-selection layers 2123 can be selectively turned on separately under different voltage adjustments, so that the selector 212 has different turn-on states under different threshold voltage conditions, and further, the memory 211 can be accurately operated under different threshold voltage conditions, thereby ensuring the operational reliability of the storage unit 21.

[0039] Normally, when the voltage on the gating layer 2123 is lower than its threshold voltage, the gating layer 2123 remains in a closed state, and the memory 211 does not perform a read or write operation. When the voltage on the gating layer 2123 is equal to or greater than its threshold voltage, the gating layer 2123 is converted from a closed state to an open state, and when the gating layer 2123 is turned on, the memory 211 can be controlled to perform a read or write operation. In addition, the gating layer 2123 includes at least two sub-gating layers 2123 with different threshold voltages, so that when the gating layer 2123 is under different threshold voltage conditions, the at least two sub-gating layers 2123 can respectively control the memory 211 to perform a read operation or a write operation.

[0040] Further, the threshold voltage adjustment layer 21233 is located between the first direction of at least two sub-selection layers 2123, and the threshold voltage adjustment layer 21233 can adjust the threshold voltage of the word select layer 2123 of at least one of the two sub-selection layers 2123, so that the threshold voltages of at least two sub-selection layers 2123 in the select layer 2123 can be different, so that the two sub-selection layers 2123 can be guaranteed to control the gate 212 to be turned on under different threshold voltage conditions, and the gate 212 can be made to control the memory 211 to perform different operations after being turned on under different threshold voltage conditions. In this way, the operation independence of different operations on the memory 211 can be guaranteed, and the memory 211 can be prevented from erroneously operating under different turn-on states of the gate 212, thereby ensuring the operational reliability of the storage unit 21.

[0041] Combination Figure 3As shown, the selection layer 2123 includes at least a first selection layer 21231 and a second selection layer 21232. The first selection layer 21231 and the second selection layer 21232 are respectively arranged on both sides of the first direction of the threshold voltage adjustment layer 21233. The threshold voltage of the first selection layer 21231 and the threshold voltage of the second selection layer 21232 are different. In this way, the first selection layer 21231 and the second selection layer 21232 in the storage unit 21 can be turned on at different threshold voltages. When the first selection layer 21231 and the second selection layer 21232 respectively control the memory 211 to perform different operations, different voltages can be applied between the word line driving circuit 12 and the bit line driving circuit 11 connected to the two ends of the memory cell 21 to control the memory 211 to perform different operations, thereby enabling the memory cell 21 to perform different operations. Moreover, under the action of the first selection layer 21231, the threshold voltage adjustment layer 21233 and the second selection layer 21232, the operation independence of different operations on the memory cell 21 can be guaranteed.

[0042] According to an embodiment of the present invention, the threshold voltage of the first selection layer 21231 is set to V1th, and the threshold voltage of the second selection layer 21232 is set to V2th, and V1th and V2th satisfy the relationship: V1th<V2th. Specifically, in an embodiment of the present invention, the threshold voltage of the first selection layer 21231 is set to be lower than the threshold voltage of the second selection layer 21232, so that the selection layer 2123 of the memory cell 21 can have different threshold voltages. When the voltage on the memory cell 21 is lower than the threshold voltage of the first selection layer 21231, the first selection layer 21231 and the second selection layer 21232 are both kept in a closed state. When the voltage on the memory cell 21 is between the threshold voltage of the first selection layer 21231 and the threshold voltage of the second selection layer 21232, the open state of the memory 211 is that the first selection layer 21231 is in an open state and the second selection layer 21232 is in a closed state. When the voltage on the memory cell 21 exceeds the threshold voltage of the second selection layer 21232, the memory 211 is turned on in the state that both the first selection layer 21231 and the second selection layer 21232 are turned on. In this way, the selection device 212 of the memory cell 21 can have different turn-on states under different threshold voltage conditions, and thus the memory 211 can be controlled to perform different operations under different threshold voltage conditions.

[0043] According to an embodiment of the present invention, V1th and V2th satisfy the relationship: 0.2V≤V1th≤1.0V, 0.6V≤V2th≤1.8V. Specifically, because in an embodiment of the present invention, the first selection layer 21231 and the second selection layer 21232 are respectively responsible for the storage unit 21 to perform different operations, the threshold voltage of the first selection layer 21231 is set to be different from the threshold voltage of the second selection layer 21232.

[0044] In an embodiment of the present invention, the threshold voltage of the first selection layer 21231 is set between 0.2V and 1.0V.

[0045] According to some embodiments of the present invention, the threshold voltage of the first gating layer 21231 is set to be not less than the first parameter value. If the threshold voltage of the first gating layer 21231 is less than the first parameter value, the threshold voltage of the first gating layer 21231 is too small, which may easily cause the first gating layer 21231 to be short-circuited. To prevent the first gating layer 21231 from being short-circuited, the threshold voltage of the first gating layer 21231 needs to be set to be not less than the first parameter value, wherein the first parameter value includes but is not limited to 0.15V, 0.2V and 0.25V.

[0046] According to other embodiments of the present invention, the threshold voltage of the first gating layer 21231 is set not to exceed the second parameter value. If the threshold voltage of the first gating layer 21231 exceeds the second parameter value, the difference between the threshold voltage of the second gating layer 21232 and the threshold voltage of the first gating layer 21231 will be too small, and there is a risk of erroneous writing to the memory 211. In order to ensure the operational reliability of the memory cell 21, it is necessary to set the threshold voltage of the first gating layer 21231 not to exceed the second parameter value, wherein the second parameter value includes but is not limited to 0.9V, 0.95V and 1.0V.

[0047] In an embodiment of the present invention, the threshold voltage of the second selection layer 21232 is set between 0.6V and 1.8V.

[0048] According to some embodiments of the present invention, the threshold voltage of the second gating layer 21232 is set to be not less than the third parameter value. If the threshold voltage of the second gating layer 21232 is less than the third parameter value, the difference between the threshold voltage of the second gating layer 21232 and the threshold voltage of the second gating layer 21232 will be too small, and the memory 211 is at risk of being mistakenly written. In order to ensure the operational reliability of the memory cell 21, it is necessary to set the threshold voltage of the second gating layer 21232 to be not less than the third parameter value, wherein the third parameter value includes but is not limited to 0.5V, 0.6V and 0.7V.

[0049] According to other embodiments of the present invention, the threshold voltage of the second gating layer 21232 is set not to exceed the fourth parameter value. If the threshold voltage of the second gating layer 21232 exceeds the fourth parameter value, the current in the second gating layer 21232 will be too large, which will increase the power consumption of the gate 212. In order to reduce the power consumption of the gate 212, it is necessary to set the threshold voltage of the second gating layer 21232 not to exceed the fourth parameter value, wherein the fourth parameter value includes but is not limited to 1.7V, 1.8V and 1.9V.

[0050] Preferably, the threshold voltage of the first selection layer 21231 in the embodiment of the present invention can be 0.5V, and the threshold voltage of the second selection layer 21232 in the embodiment of the present invention can be 1.5V. In this way, the difference between the threshold voltage of the second selection layer 21232 and the threshold voltage of the first selection layer 21231 can be set to 1.0V.

[0051] According to some embodiments of the present invention, Figure 3 As shown, the thickness of the threshold voltage adjustment layer 21233 in the first direction is less than the thickness of the first selection layer 21231 in the first direction, and the thickness of the threshold voltage adjustment layer 21233 in the first direction is less than the thickness of the second selection layer 21232 in the first direction. In an embodiment of the present invention, the thickness of the threshold voltage adjustment layer 21233 is adjustable. By changing the threshold voltage adjustment layer 21233, the threshold voltage of one of the first electrode layer 2121 and the second electrode layer 2122 can be selectively adjusted.

[0052] According to an embodiment of the present invention, the thickness of the threshold voltage adjustment layer 21233 in the first direction is set to D, and D satisfies the relationship: 0<D<10nm. Specifically, the thickness of the threshold voltage adjustment layer 21233 in the first direction is set to be not less than the fifth parameter value, so that the first electrode layer 2121 and the second electrode layer 2122 are arranged on both sides of the threshold voltage adjustment layer 21233 in the first direction, so that the threshold voltage adjustment layer 21233 can selectively adjust the threshold voltage of one of the first electrode layer 2121 and the second electrode layer 2122. In an embodiment of the present invention, the fifth parameter value is 0.

[0053] Further, the thickness of the threshold voltage adjustment layer 21233 in the first direction is set not to exceed the sixth parameter value, so that the threshold voltage adjustment layer 21233 can be prevented from selectively adjusting the threshold voltage of one of the first electrode layer 2121 and the second electrode layer 2122 to be too large, and the opening voltage of the gate 212 can be prevented from being too large, resulting in excessive power consumption of the gate 212. In this way, the thickness of the threshold voltage adjustment layer 21233 in the first direction needs to be set not to exceed the sixth parameter value. In the embodiment of the present invention, the sixth parameter value includes but is not limited to 9.5nm, 10nm and 10.5nm.

[0054] According to an embodiment of the present invention, the material of the threshold voltage adjustment layer 21233 includes at least one of silicon dioxide, titanium dioxide, tantalum pentoxide, tungsten trioxide, hafnium dioxide and zirconium dioxide. Specifically, metal oxide materials such as silicon dioxide, titanium dioxide, tantalum pentoxide, tungsten trioxide, hafnium dioxide and zirconium dioxide all have semiconductor properties and nonlinear volt-ampere properties.

[0055] Among them, the semiconductor properties make metal oxides have a higher resistivity at room temperature, and their conductivity can be changed under specific conditions, so that these metal oxides can play a role in voltage regulation in the circuit. In the case of overvoltage, metal oxides such as silicon dioxide, titanium dioxide, tantalum pentoxide, tungsten trioxide, hafnium dioxide and zirconium dioxide can limit the voltage by adjusting their own resistance.

[0056] Furthermore, the nonlinear volt-ampere characteristic can make the metal oxide present a high resistance state within the normal operating voltage range. When the voltage exceeds a certain threshold, the resistance of the metal oxide will drop rapidly, allowing a larger current to pass through. Thus, in the embodiment of the present invention, at least one of silicon dioxide, titanium dioxide, tantalum pentoxide, tungsten trioxide, hafnium dioxide and zirconium dioxide is used as the material for the threshold voltage adjustment layer 21233. By changing the material and thickness of the threshold voltage adjustment layer 21233, the tunneling voltage of the selection layer 2123 can be controlled. In this way, on the one hand, the threshold voltage of the second selection layer 21232 can be controlled to make the difference between the threshold voltage of the second electrode layer 2122 and the threshold voltage of the first electrode layer 2121 larger. On the other hand, the threshold voltage adjustment layer 21233 can act as a resistor to adjust the size of the low current area. Figure 4 As shown, the threshold voltage of the second gate layer 21232 can be adjusted from Vth2' to Vth2, wherein Vth2'<Vth2.

[0057] In this way, on the one hand, when the voltage between the word line driving circuit 12 and the bit line driving circuit 11 connected to the two ends of the storage cell 21 is between the threshold voltage of the first electrode layer 2121 and the threshold voltage of the second electrode layer 2122, even if there are some fluctuations in the voltage between the word line driving circuit 12 and the bit line driving circuit 11 connected to the two ends of the storage cell 21, it can still be ensured that the voltage on the selection layer 2123 is between the threshold voltage of the first electrode layer 2121 and the threshold voltage of the second electrode layer 2122, thereby ensuring that the memory 211 will not be mistakenly written, thereby ensuring the reliability of the storage cell 21 in performing operations.

[0058] According to some embodiments of the present invention, the first gating layer 21231 includes any one of a bidirectional threshold switch layer, a diode layer, and a converter layer of a metal-insulator-metal structure. Specifically, the bidirectional threshold switch layer can determine whether to turn on or off according to the level of the input signal, and it has two different thresholds. The use of the bidirectional threshold switch layer in the present invention can accurately control the opening and closing of the first gating layer 21231, thereby facilitating the improvement of the reliability of the first gating layer 21231 controlling the memory 211 to perform operations. Furthermore, the diode layer has unidirectional conductivity and can be used as a switch. In addition, some converter layers of a metal-insulator-metal structure can also be used as switches.

[0059] According to some other embodiments of the present invention, the second gating layer 21232 includes any one of a bidirectional threshold switch layer, a diode layer, and a converter layer of a metal-insulator-metal structure. Specifically, the bidirectional threshold switch layer can determine whether to turn on or off according to the level of the input signal, and it has two different thresholds. The use of the bidirectional threshold switch layer in the present invention can accurately control the opening and closing of the second gating layer 21232, thereby facilitating the improvement of the reliability of the second gating layer 21232 controlling the memory 211 to perform operations. Furthermore, the diode layer has unidirectional conductivity and can be used as a switch. In addition, some converter layers of a metal-insulator-metal structure can also be used as switches.

[0060] According to some embodiments of the present invention, the switching layer material of the first gating layer 21231 includes at least one of niobium oxide and vanadium oxide.

[0061] According to some other embodiments of the present invention, the switching layer material of the second gating layer 21232 includes at least one of niobium oxide and vanadium oxide.

[0062] According to some further embodiments of the present invention, the switching layer material of the first gating layer 21231 includes at least one of niobium oxide and vanadium oxide, and the switching layer material of the second gating layer 21232 includes at least one of niobium oxide and vanadium oxide.

[0063] Specifically, niobium oxide and vanadium oxide, as excellent switching layer materials, have the advantages of high on-off ratio, fast switching speed, good durability, low power consumption, easy integration, stable physical and chemical properties, and versatility.

[0064] It should be noted that the constituent materials of the first gating layer 21231 and the constituent materials of the second gating layer 21232 may be the same or different. Preferably, the first gating layer 21231 is a gating material layer with a lower threshold transition, and the second gating layer 21232 is a gating material layer with a higher threshold transition.

[0065] In the embodiment of the present invention, the first gating layer 21231 determines the voltage-current characteristics of the low current region and the magnitude of the threshold voltage of the first gating layer 21231. The second gating layer 21232 determines the voltage-current characteristics of the write current region and the magnitude of the threshold voltage of the second gating layer 21232. The threshold voltage adjustment layer 21233 can adjust the magnitude of the threshold voltage of the second gating layer 21232.

[0066] According to some embodiments of the present invention, the first gating layer 21231 is made by at least one of chemical vapor deposition, physical vapor deposition and atomic layer deposition.

[0067] According to some other embodiments of the present invention, the second gating layer 21232 is made by at least one of chemical vapor deposition, physical vapor deposition and atomic layer deposition.

[0068] According to some further embodiments of the present invention, the threshold voltage adjustment layer 21233 is made by at least one of chemical vapor deposition, physical vapor deposition and atomic layer deposition.

[0069] According to an embodiment of the present invention, the memory 211 includes at least one of a resistive memory, a phase change memory, a magnetic random access memory and a ferroelectric memory, that is, the memory unit 21 in the embodiment of the present invention is suitable for matching any one of the resistive memory, the phase change memory, the magnetic random access memory and the ferroelectric memory. The first gating layer 21231 and the second gating layer 21232 are respectively responsible for reading and writing operations, so that after setting the threshold voltages of the first gating layer 21231 and the second gating layer 21232 to be different, any one of the resistive memory, the phase change memory, the magnetic random access memory and the ferroelectric memory can perform corresponding operations under different voltage conditions, so that the operational reliability of any one of the resistive memory, the phase change memory, the magnetic random access memory and the ferroelectric memory can be improved.

[0070] According to an embodiment of the present invention, the storage unit 21 is configured with an operation method of the storage unit 21. The operation method of the storage unit 21 comprises the following steps: The voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the storage unit 21 is set to Vsel, and Vsel is set to satisfy the relationship: V1th≤Vsel, so as to control the selector 212 of the storage unit 21 to enter the first turn-on state, and perform a read operation on the memory 211 of the storage unit 21; wherein the threshold voltage of the first turn-on state of the selector 212 is V1th.

[0071] Specifically, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the storage unit 21 is set to be at least V1th, so that the gate 212 of the storage unit 21 can enter the first open state. When the gate 212 of the storage unit 21 enters the first open state, a read operation can be performed on the memory 211 of the storage unit 21, and V1th is the threshold voltage when the gate 212 enters the first open state.

[0072] Furthermore, the selection layer 2123 in the selector 212 includes at least a first selection layer 21231 and a second selection layer 21232, and Vsel is set to satisfy the relationship: V1th≤Vsel<V2th, the first selection layer 21231 of the storage unit 21 is controlled to be turned on, and the second selection layer 21232 of the storage unit 21 is controlled to be turned off, and a read operation is performed on the memory 211 of the storage unit 21; wherein the threshold voltage of the first selection layer 21231 of the storage unit 21 is V1th, and the threshold voltage of the second selection layer 21232 of the storage unit 21 is V2th.

[0073] Specifically, in the embodiment of the present invention, the selection layer 2123 in the selector 212 of the memory cell 21 includes at least a first selection layer 21231 and a second selection layer 21232, wherein the first selection layer 21231 performs a read operation on the memory 211 of the memory cell 21, and the second selection layer 21232 performs a write operation on the memory 211 of the memory cell 21. When the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the memory cell 21 is set to be at least the threshold voltage of the first selection layer 21231 and does not exceed the threshold voltage of the second selection layer 21232, the first selection layer 21231 is in an on state, and the second selection layer 21232 remains in a closed state, so that the first selection layer 21231 can control the memory 211 of the memory cell 21 to perform a read operation, but will not perform a write operation.

[0074] In the embodiment of the present invention, the operating method of the storage unit 21 can not only ensure the reliability of the storage unit 21 in performing the read operation, but also ensure that the second selection layer 21232 will not be mistakenly turned on, which can reduce the power consumption of the gate 212 and is conducive to extending the service life of the gate 212.

[0075] According to an embodiment of the present invention, the storage unit 21 is configured with an operation method of the storage unit 21. The operation method of the storage unit 21 comprises the following steps: The voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the storage unit 21 is set to Vsel, and Vsel is set to satisfy the relationship: V2th≤Vsel, so as to control the selector 212 of the storage unit 21 to enter the second turn-on state, and perform a write operation on the memory 211 of the storage unit 21; wherein the threshold voltage of the second turn-on state of the selector 212 is V2th.

[0076] Specifically, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the memory cell 21 is set to be at least V2th, so that the gate 212 in the memory cell 21 can enter the second open state. When the gate 212 of the memory cell 21 enters the second open state, the memory cell 21 can perform a write operation, wherein V2th is a threshold voltage when the gate 212 enters the second open state.

[0077] Furthermore, the selection layer 2123 in the selector 212 of the storage unit 21 includes at least a first selection layer 21231 and a second selection layer 21232, and Vsel is set to satisfy the relationship: V1th≤Vsel and V2th≤Vsel, so that the first selection layer 21231 and the second selection layer 21232 of the storage unit 21 can be controlled to be turned on to perform a write operation on the memory of the storage unit 21; wherein the threshold voltage of the first selection layer 21231 of the storage unit 21 is V1th, and the threshold voltage of the second selection layer 21232 of the storage unit 21 is V2th, and V1th<V2th.

[0078] Specifically, in the embodiment of the present invention, the gating layer 2123 in the gating device 212 of the memory cell 21 includes at least a first gating layer 21231 and a second gating layer 21232, wherein the first gating layer 21231 controls the memory of the memory cell 21 to perform a read operation, and the second gating layer 21232 controls the memory of the memory cell 21 to perform a write operation. When the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the memory cell 21 is set to be at least the threshold voltage of the second gating layer 21232.

[0079] In an embodiment of the present invention, the threshold voltage of the first selection layer 21231 is less than the threshold voltage of the second selection layer 21232. At this time, the first selection layer 21231 and the second selection layer 21232 are both in an on state, so that the second selection layer 21232 can control the memory of the storage unit 21 to perform a write operation. During this process, the opening of the first selection layer 21231 will not affect the write operation of the storage unit 21.

[0080] According to an embodiment of the present invention, the step of performing a write operation on the memory of the storage unit 21 further includes: When a write 1 operation is performed on the memory, Vsel satisfies the relationship: Vsel=Vset, where the threshold voltage of the memory for performing a write 1 is Vset; When a write-0 operation is performed on the memory, Vsel satisfies the relationship: Vsel=Vreset, where the threshold voltage of the memory for performing a write-0 operation is Vreset.

[0081] Specifically, in an embodiment of the present invention, the memory of the storage unit 21 performs a write operation including performing a write 1 operation and performing a write 0 operation. The threshold voltage when the memory performs a write 1 operation is different from the threshold voltage when the memory performs a write 0 operation. Therefore, when performing different write operations on the memory, different voltages need to be applied to both ends of the storage unit 21.

[0082] When the memory performs write 1, it is necessary to set the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the memory cell 21 as the threshold voltage of the memory of the memory cell 21 for performing write 1, wherein the threshold voltage of the memory of the memory cell 21 for performing write 1 operation is Vset. When the memory performs write 0, it is necessary to set the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the memory cell 21 as the threshold voltage of the memory of the memory cell 21 for performing write 0, wherein the threshold voltage of the memory of the memory cell 21 for performing write 0 operation is Vreset.

[0083] According to an embodiment of the present invention, the storage device 100 includes a front-end driving circuit 10 and a storage array 20, wherein the front-end driving circuit 10 includes a bit line driving circuit 11 and a word line driving circuit 12, and the word line driving circuit 12 and the bit line driving circuit 11 can be used to connect voltage to apply voltage to both ends of the storage device 100.

[0084] Furthermore, the memory array 20 includes a plurality of memory cells 21, a first end of a memory 211 of the memory cell 21 is connected to a word line driving circuit 12, a first end of a selector 212 of the memory cell 21 is electrically connected to a bit line driving circuit 11, and a second end of the selector 212 is suitable for being electrically connected to a second end of a memory 211 of the memory cell 211.

[0085] Specifically, among the multiple memory cells 21 in the memory array 20, the first end of the memory 211 of each memory cell 21 is at the same voltage as the word line driving circuit 12, the first end of the selector 212 of each memory cell 21 is at the same voltage as the bit line driving circuit 11, and the second end of the selector 212 in each memory cell 21 is electrically connected to the second end of the memory 211. In this way, the memory 211 and the selector 212 of the multiple memory cells 21 in the memory array 20 can be connected between the word line driving circuit 12 and the bit line driving circuit 11, so that when voltage is applied to the word line driving circuit 12 and the bit line driving circuit 11 connected to the two ends of the memory device 100, the circuit connectivity of the multiple memory cells 21 in the memory device 100 can be guaranteed.

[0086] According to an embodiment of the present invention, the storage device 100 is provided with an operating method of the storage device 100. The operating method of the storage device 100 comprises the following steps: The threshold voltage of the on state of the gate 212 of the memory cell 21 is V1th, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 in the memory device 100 is set to Vsel, and the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target memory cell 21 in the memory device 100 is set to Vunsel; Vsel is set to satisfy the relationship: V1th≤Vsel, the gate 212 of the target storage unit 21 is controlled to be turned on, and a read operation or a write operation is performed on the memory 211 of the target storage unit 21; Vunsel is set to satisfy the relationship: Vunsel<V1th, and the gate 212 of the non-target memory cell 21 is controlled to be closed.

[0087] Specifically, there are multiple storage cells 21 in the storage array 20, wherein the target storage cell 21 is a cell to be operated in the storage array 20, that is, a storage cell 21 on which a read or write operation is to be performed, and the non-target storage cell 21 is a cell on which no operation is to be performed, that is, a storage cell 21 on which neither a read operation nor a write operation is to be performed.

[0088] In the embodiment of the present invention, the target storage unit 21 includes but is not limited to one or more storage units 21 in the storage array 20 at a time.

[0089] Furthermore, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 in the memory device 100 is set to be at least the threshold voltage when the selection layer 2123 in the selector 212 of the memory cell 21 enters the turned-on state, so that the target memory cell 21 in the memory device 100 can be controlled to perform a read or write operation, wherein the threshold voltage when the selection layer 2123 in the selector 212 of the memory cell 21 enters the turned-on state is V1th.

[0090] Furthermore, the voltage between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target memory cell 21 in the memory device 100 is set to be lower than the threshold voltage when the selection layer 2123 in the selector 212 of the memory cell 21 enters the on state, so that the non-target memory cell 21 in the memory device 100 can be controlled to remain in the off state.

[0091] With such a configuration, the target storage unit 21 in the storage device 100 can perform a read or write operation, while the non-target storage unit 21 in the storage device 100 does not perform the operation. This ensures that the storage device 100 only performs a read or write operation on the memory 211 of the target storage unit 21, thereby ensuring the accuracy and reliability of the operation performed by the storage device 100.

[0092] Further, the gating layer 2123 in the gating device 212 of the storage unit 21 at least includes a first gating layer 21231 and a second gating layer 21232, and Vsel is set to satisfy the relationship: V1th≤Vsel<V2th, the first gating layer 21231 of the target storage unit 21 is controlled to be turned on, and the second gating layer 21232 of the target storage unit 21 is controlled to be turned off, and a read operation is performed on the memory 211 of the target storage unit 21; or, Vsel is set to satisfy the relationship: V2th≤Vsel, and the first gating layer 21231 of the target storage unit 21 is controlled to be turned off. Layer 21231 and the second selection layer 21232 are both turned on, and a write operation is performed on the memory 211 of the target storage unit 21; Vunsel is set to satisfy the relationship: Vunsel<V1th, and the first selection layer 21231 and the second selection layer 21232 of the non-target storage unit 21 are controlled to be closed; wherein, the threshold voltage of the first selection layer 21231 of the storage unit 21 is V1th, and the threshold voltage of the second selection layer 21232 of the storage unit 21 is V2th, and V1th and V2th satisfy the relationship: V1th<V2th.

[0093] Specifically, the selection layer 2123 in the selector 212 of multiple memory cells 21 of the memory device 100 includes at least a first selection layer 21231 and a second selection layer 21232, wherein the first selection layer 21231 controls the memory cell 21 to perform a read operation, and the second selection layer 21232 controls the memory cell 21 to perform a write operation.

[0094] When the target memory cell 21 performs a read operation, it is necessary to set the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 in the storage device 100 to be at least the threshold voltage of the first selection layer 21231 and less than the threshold voltage of the second selection layer 21232. In this way, the first selection layer 21231 in the target memory cell 21 can be controlled to be turned on, and the second selection layer 21232 in the target memory cell 21 can be controlled to be turned off, so as to control the memory 211 of the target memory cell 21 in the storage device 100 to perform a read operation.

[0095] Or the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 in the storage device 100 is set to be at least the threshold voltage of the second selection layer 21232, so that the first selection layer 21231 and the second selection layer 21232 of the target memory cell 21 can be turned on to perform a write operation on the memory 211 of the target memory cell 21.

[0096] During this process, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target memory cell 21 in the memory device 100 is set to be smaller than the threshold voltage of the first selection layer 21231. In this way, the first selection layer 21231 and the second selection layer 21232 of the non-target memory cell 21 in the memory device 100 can be turned off, which can prevent the memory device 100 from performing operations on the non-target memory cell 21, thereby ensuring the operating reliability of the memory device 100.

[0097] According to an embodiment of the present invention, the step of performing a write operation on the memory 211 of the target storage unit 21 further includes: When a write 1 operation is performed on the target memory cell 21, Vsel satisfies the relationship: Vsel=Vset, wherein the threshold voltage of the target memory cell 21 for performing a write 1 operation is Vset; When a write-0 operation is performed on the target memory cell 21 , Vsel satisfies the relationship: Vsel=Vreset, wherein the threshold voltage of the target memory cell 21 for performing a write-0 operation is Vreset.

[0098] Specifically, in an embodiment of the present invention, the write operation of the target storage unit 21 includes a write 1 operation and a write 0 operation, and the threshold voltage of the memory 211 of the target storage unit 21 when performing the write 1 operation is different from the threshold voltage when performing the write 0 operation.

[0099] When a write 1 operation is performed on the memory 211 of the target memory cell 21, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 needs to be set to the threshold voltage for the target memory cell 21 to perform write 1, that is, Vset. When a write 0 operation is performed on the memory 211 of the target memory cell 21, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21 needs to be set to the threshold voltage for the target memory cell 21 to perform write 0, that is, Vreset.

[0100] In the prior art, the storage device is mainly a cell structure composed of a gate and a memory (1S1M) to form a cell (storage cell 21). The gate has a fixed threshold voltage Vth. The threshold voltage of the write operation of the memory is set to Vwrite. Then Vth and Vwrite need to satisfy the relationship: the size of Vth needs to be greater than 1 / 3 Vwirte. For example, if the operating voltage of the memory is 3.6V, then the gate 212Vth needs to be set greater than 1.2V, otherwise it will cause errors in the array when selecting bits. And when Vth>1.2V, there is a large current in the gate, resulting in higher power consumption of the gate. In addition, frequent power-on exceeding 1.2V not only has an adverse effect on the life of the gate, but also at a read voltage exceeding 1.2V, the memory is at risk of erroneous write operations.

[0101] The manner in which the storage device 100 according to the embodiment of the present invention performs read and write operations is described in detail below.

[0102] When the first end of the memory 211 is electrically connected to the word line driving circuit 12, and the first end of the selector 212 is electrically connected to the bit line driving circuit 11, the voltage of the word line driving circuit 12 connected to the target memory cell 21 is set to Vwl_sel, and the voltage of the bit line driving circuit 11 connected to the target memory cell 21 is set to Vbl_sel, then the difference between Vwl_sel and Vbl_sel is the voltage difference Vsel between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target memory cell 21.

[0103] Correspondingly, the voltage of the word line driving circuit 12 connected to the non-target memory cell 21 is set to Vwl_unsel, and the voltage of the bit line driving circuit 11 connected to the non-target memory cell 21 is set to Vbl_unsel. The difference between Vwl_unsel and Vbl_unsel is the voltage difference Vunsel between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target memory cell 21.

[0104] In the embodiment of the present invention, set represents a write 1 operation in a write operation, and reset represents a write 0 operation in a write operation. The write operation of the memory 211 includes a write 1 operation and a write 0 operation. It can be understood that Vset represents the threshold voltage of the memory device 100 performing a write 1 operation on the memory 211 of the memory cell 21, and Vreset represents the threshold voltage of the memory device 100 performing a write 0 operation on the memory 211 of the memory cell 21.

[0105] According to the embodiment of the present invention, the first selection layer 21231 is responsible for controlling the read operation of the memory device 100 , and the second selection layer 21232 is responsible for controlling the write operation of the memory device 100 .

[0106] When the storage device 100 performs a read operation, Vbl_sel=0.8V, Vbl_unsel=0.4V, Vwl_sel=0V, Vwl_unsel=0.4V are set, so that the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the non-target storage unit 21 is 0, and Vunsel satisfies the relationship: Vunsel<V1th. The voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected to the two ends of the target storage unit 21 is 0.8V, and Vsel satisfies the relationship: V1th≤Vsel.

[0107] At this time, the first gating layer 21231 in the target memory cell 21 is turned on, and the second gating layer 21232 remains turned off. Only the memory 211 of the target memory cell 21 in the storage device 100 performs a read operation, and the state of the memory 211 in the target memory cell 21 can be read as 0 or 1. In the non-target memory cell 21, the first gating layer 21231 and the second gating layer 21232 are both in a turned-off state.

[0108] When the storage device 100 performs a write 1 operation, Vbl_sel=2.0V, Vbl_unsel=1.0Vset, Vwl_sel=0, Vwl_unsel=1.0Vset, so that the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected at both ends of the non-target storage unit 21 is ensured to be not greater than the threshold voltage of the second selection layer 21232, so that the second selection layer 21232 of the non-target storage unit 21 is turned off, and it can be ensured that the memory 211 in the non-target storage unit 21 does not perform a write 1 operation. In the target storage unit 21, the voltage difference between the word line driving circuit 12 and the bit line driving circuit 11 respectively connected at both ends thereof is greater than the threshold voltage of the second selection layer 21232, so that the second selection layer 21232 of the target storage unit 21 is turned on, and then the memory 211 of the target storage unit 21 can perform a write 1 operation.

[0109] Likewise, the write 0 operation is the same as the write 1 operation, and it is only necessary to swap the voltages of Vbl_sel and Vwl_sel.

[0110] According to an embodiment of the present invention, the gate 212 of the memory cell 21 of the memory device 100 includes at least two sub-selection layers 2123, and the threshold voltages of the at least two sub-selection layers 2123 are different, which can reduce the risk of the memory 211 being subjected to an erroneous write operation. When the memory device 100 performs a read operation, the voltage is low, and only the first selection layer 21231 responsible for the read operation is turned on, while the second selection layer 21232 responsible for the write operation is not turned on, thereby reducing the read power consumption of the memory device 100. In addition, when the storage device 100 performs a write operation, the voltage of the target storage unit 21 needs to be greater than the threshold voltage of the second selection layer 21232, so as to ensure that there is a smaller voltage divider on the selection layer 212, and most of the voltage falls on the memory 211, and the second selection layer 21232 is turned on. At this time, the first selection layer 21231 can also be turned on, but it does not affect the write operation, and when the first selection layer 21231 is turned on, it can be used as a small resistor in the circuit, which is beneficial to reduce the circuit current and reduce the overall power consumption of the storage device 100.

[0111] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "circumferential", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0112] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0113] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A storage unit, characterized in that: include: A memory (211), wherein a first end of the memory (211) is suitable for being electrically connected to a word line driving circuit (12); A gate (212), the gate (212) comprising a first electrode layer (2121), a gate layer (2123) and a second electrode layer (2122), the first electrode layer (2121) being arranged on a first side of the gate layer (2123) in a first direction, the second electrode layer (2122) being arranged on a second side of the gate layer (2123) in the first direction opposite to the first side, one of the first electrode layer (2121) and the second electrode layer (2122) being suitable for being electrically connected to a bit line driving circuit (11), and the other being suitable for being electrically connected to a second end of the memory (211); The gating layer (2123) comprises at least two sub-gating layers (2123) and a threshold voltage adjustment layer (21233); the threshold voltages of at least two of the sub-gating layers (2123) are different, so that the gate (212) has different opening states under different threshold voltage conditions; at least two of the sub-gating layers (2123) are respectively arranged on both sides of the threshold voltage adjustment layer (21233) in a first direction; and the threshold voltage adjustment layer (21233) can selectively adjust the threshold voltage of at least one of the at least two sub-gating layers (2123).

2. The storage unit according to claim 1, characterized in that The gating layer (2123) comprises a first gating layer (21231) and a second gating layer (21232), wherein the first gating layer (21231) and the second gating layer (21232) are respectively arranged on both sides of a first direction of the threshold voltage adjustment layer (21233), and the threshold voltages of the first gating layer (21231) and the second gating layer (21232) are different.

3. The storage unit according to claim 2, characterized in that The threshold voltage of the first selection layer (21231) is set to V1th, and the threshold voltage of the second selection layer (21232) is set to V2th, V1th and V2th satisfy the relationship: V1th<V2th, and the threshold voltage adjustment layer (21233) is suitable for adjusting the threshold voltage of the second selection layer (21232).

4. The storage unit according to claim 3, characterized in that V1th and V2th satisfy the relationship: 0.2V≤V1th≤1.0V, 0.6V≤V2th≤5V.

5. The storage unit according to claim 2, characterized in that: The thickness of the threshold voltage adjustment layer (21233) in the first direction is smaller than the thickness of the first selection layer (21231) in the first direction, and the thickness of the threshold voltage adjustment layer (21233) in the first direction is smaller than the thickness of the second selection layer (21232) in the first direction.

6. The storage unit according to claim 5, characterized in that The thickness of the threshold voltage adjustment layer (21233) in the first direction is set to D, and D satisfies the relationship: 0<D<10nm.

7. The storage unit according to claim 2, characterized in that The material of the threshold voltage adjustment layer (21233) includes at least one of silicon dioxide, titanium dioxide, tantalum pentoxide, tungsten trioxide, hafnium dioxide and zirconium dioxide.

8. The storage unit according to claim 2, characterized in that The first gating layer (21231) and / or the second gating layer (21232) includes at least one of a bidirectional threshold switch layer, a diode layer, and a converter layer of a metal-insulator-metal structure.

9. The storage unit according to claim 2, characterized in that: The switching layer material of the first gating layer (21231) and / or the second gating layer (21232) includes at least one of niobium oxide and vanadium oxide.

10. The storage unit according to claim 2, characterized in that The first gating layer (21231), and / or the second gating layer (21232), and / or the threshold voltage adjustment layer (21233) are made by at least one of chemical vapor deposition, physical vapor deposition and atomic layer deposition.

11. The storage unit according to any one of claims 1 to 10, characterized in that: The memory (211) includes at least one of a resistive memory, a phase change memory, a magnetic random access memory and a ferroelectric memory.

12. A method for operating a storage unit, applicable to the storage unit (21) according to any one of claims 1 to 11, characterized in that: The following steps are involved: Setting the voltage difference between the word line driving circuit (12) and the bit line driving circuit (11) respectively connected to the two ends of the storage unit (21) to be Vsel, and setting Vsel to satisfy the relationship: V1th≤Vsel, so as to control the gate (212) of the storage unit (21) to enter a first open state, and perform a read operation on the memory (211) of the storage unit (21); The threshold voltage of the first on state of the gate (212) is V1th.

13. The method for operating a storage unit according to claim 12, characterized in that: The gate (212) comprises at least a first gate layer (21231) and a second gate layer (21232), and the Vsel is set to satisfy the relationship: V1th≤Vsel<V2th, the first gate layer (21231) of the storage unit (21) is controlled to be turned on, and the second gate layer (21232) of the storage unit (21) is controlled to be turned off, and a read operation is performed on the memory (211) of the storage unit (21); The threshold voltage of the first selection layer (21231) of the storage unit (21) is V1th, and the threshold voltage of the second selection layer (21232) of the storage unit (21) is V2th.

14. A method for operating a storage unit, applicable to the storage unit (21) according to any one of claims 1 to 11, characterized in that: The following steps are involved: Setting the voltage difference between the word line driving circuit (12) and the bit line driving circuit (11) respectively connected to the two ends of the storage unit (21) to Vsel, and setting Vsel to satisfy the relationship: V2th≤Vsel, so as to control the gate (212) of the storage unit (21) to enter the second open state, and perform a write operation on the memory (211) of the storage unit (21); The threshold voltage of the second on state of the gate (212) is V2th.

15. The method for operating a storage unit according to claim 14, characterized in that: The gate (212) comprises at least a first gate layer (21231) and a second gate layer (21232), and the Vsel is set to satisfy the relationship: V1th≤Vsel and V2th≤Vsel, so as to control the first gate layer (21231) and the second gate layer (21232) of the storage unit (21) to be turned on, and perform a write operation on the memory (211) of the storage unit (21); The threshold voltage of the first selection layer (21231) of the storage unit (21) is V1th, the threshold voltage of the second selection layer (21232) of the storage unit (21) is V2th, and V1th<V2th.

16. The method for operating a storage unit according to claim 15, characterized in that: The step of performing a write operation on the memory (211) of the storage unit (21) further comprises: When a write 1 operation is performed on the memory (211), Vsel satisfies the relationship: Vsel=Vset, wherein the threshold voltage of the memory (211) for performing a write 1 operation is Vset; When a write-0 operation is performed on the memory (211), Vsel satisfies the relationship: Vsel=Vreset, wherein the threshold voltage for the memory (211) to perform a write-0 operation is Vreset.

17. A storage device, characterized in that: include: A front-end driving circuit (10), the front-end driving circuit (10) comprising a bit line driving circuit (11) and a word line driving circuit (12); A memory array (20), the memory array (20) comprising a plurality of memory cells (21) according to any one of claims 1 to 11, the first end of the memory (211) of the memory cell (21) being electrically connected to the word line drive circuit (12), the first end of the gate (212) of the memory cell (21) being electrically connected to the bit line drive circuit (11), and the second end of the gate (212) being suitable for being electrically connected to the second end of the memory (211).

18. A method for operating a storage device, applicable to the storage device (100) according to claim 17, characterized in that: The following steps are involved: The threshold voltage of the on state of the selector (212) of the storage unit (21) is V1th, the voltage difference between the word line driving circuit (12) and the bit line driving circuit (11) respectively connected to the two ends of the target storage unit (21) in the storage device (100) is set to Vsel, and the voltage difference between the word line driving circuit (12) and the bit line driving circuit (11) respectively connected to the two ends of the non-target storage unit (21) in the storage device (100) is set to Vunsel; Vsel is set to satisfy the relationship: V1th≤Vsel, the gate (212) of the target storage unit (21) is controlled to be turned on, and a read operation or a write operation is performed on the memory (211) of the target storage unit (21); Vunsel is set to satisfy the relationship: Vunsel<V1th, and the gate (212) of the non-target storage unit (21) is controlled to be closed.

19. The method for operating a storage device according to claim 18, characterized in that: The gate (212) comprises at least a first gate layer (21231) and a second gate layer (21232); Vsel is set to satisfy the relationship: V1th≤Vsel<V2th, the first gating layer (21231) of the target storage unit (21) is controlled to be turned on, the second gating layer (21232) of the target storage unit (21) is controlled to be turned off, and a read operation is performed on the memory (211) of the target storage unit (21); or Vsel is set to satisfy the relationship: V2th≤Vsel, the first gating layer (21231) and the second gating layer (21232) of the target storage unit (21) are controlled to be turned on, and a write operation is performed on the memory (211) of the target storage unit (21); Vunsel is set to satisfy the relationship: Vunsel<V1th, and the first gating layer (21231) and the second gating layer (21232) of the non-target storage unit (21) are controlled to be turned off; The threshold voltage of the first selection layer (21231) of the storage unit (21) is V1th, the threshold voltage of the second selection layer (21232) of the storage unit (21) is V2th, and V1th and V2th satisfy the relationship: V1th<V2th.

20. The method for operating a storage device according to claim 19, characterized in that: The step of performing a write operation on the memory (211) of the target storage unit (21) further comprises: When a write-1 operation is performed on the target memory cell (21), Vsel satisfies the relationship: Vsel=Vset, wherein the threshold voltage of the target memory cell (21) for performing a write-1 operation is Vset; When a write-0 operation is performed on the target memory cell (21), Vsel satisfies the relationship: Vsel=reset, wherein the threshold voltage for performing a write-0 operation on the target memory cell (21) is Vreset.

Images