Memory

Abstract

The invention relates to the technical field of semiconductors, in particular to a memory, which comprises a memory cell array comprising a first edge region, a connection region and a second edge region which are arranged along a first direction, and the connection region is located between the first edge region and the second edge region; the driving lines extend in the first direction, each driving line is coupled with a column of storage units arranged in the first direction and comprises a first end portion area, a middle area and a second end portion area, the first end portion area corresponds to the first edge area, the middle area corresponds to the connecting area, and the second end portion area corresponds to the second edge area. The second end part area corresponds to the second edge area; the control lines extend in the first direction and correspond to the driving lines, and the control lines are electrically connected with the middle areas of the corresponding driving lines and are electrically connected with at least one of the first end areas and the second end areas.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a memory. Background Art

[0002] The memory is used to store information in various electronic devices (such as computers, wireless communication devices, and cameras, etc.), and the information is stored by regulating the different states of the memory. With the rapid development of artificial intelligence technology, higher requirements are placed on the computing performance, reading performance, writing performance, reliability, and data retention capabilities of electronic devices.

[0003] As the feature size of memory cells approaches the lower limit, it becomes challenging and costly to further increase the feature size of memory cells in planar processes and manufacturing technologies. The 3D memory architecture can solve the density limitations in planar memory cells.

[0004] In order to selectively activate word lines (WL) and bit lines (BL), the memory includes a word line driver structure (WL Driver) and a bit line driver structure (BL Driver). The word line driver structure is coupled to the word line through a word line contact and is used to decode the word line address, so that the word line is activated when addressing a specific word line. The bit line driver structure is coupled to the bit line through a bit line contact and is used to decode the bit line address, so that the bit line is activated when addressing a specific bit line.

[0005] However, the voltage drop on the word line and bit line increases significantly as the line length (word line length or bit line length) between the contact and the target memory cell increases, and may cause insufficient current at the target memory cell, resulting in memory read and write errors. Summary of the invention

[0006] The main purpose of the present disclosure is to provide a memory, aiming to improve the driving capability of a driving structure in a memory cell to a driving line.

[0007] To achieve the above-mentioned purpose, the present disclosure proposes a memory, comprising: a memory cell array, comprising a first edge region, a connection region, and a second edge region arranged along a first direction, and the connection region is located between the first edge region and the second edge region; a plurality of drive lines extending along the first direction, each of the drive lines being coupled to a column of memory cells arranged along the first direction, and comprising a first end region, a middle region, and a second end region, the first end region corresponding to the first edge region, the middle region corresponding to the connection region, and the second end region corresponding to the second edge region; a plurality of control lines extending along the first direction and corresponding to the drive lines, the control lines being electrically connected to the middle region corresponding to the drive lines, and being electrically connected to at least one of the first end region and the second end region.

[0008] In some embodiments, the resistivity of the control line is less than the resistivity of the drive line.

[0009] In some embodiments, the driving line is made of tungsten, and the control line is made of copper.

[0010] In some embodiments, the memory further includes: a driving structure located in at least one of the connection area, the first edge area, or the second edge area, the driving structure being electrically connected to the control line.

[0011] In some embodiments, the driving structure is symmetrically arranged in the first edge area and the second edge area, one end of the control line is electrically connected to the first end area of ​​the corresponding driving line and the driving structure in the first edge area, the other end is electrically connected to the second end area of ​​the corresponding driving line and the driving structure in the second edge area, and the middle end is connected to the middle area of ​​the corresponding driving line.

[0012] In some embodiments, the driving structure is located in the connection area, and the control line includes a first sub-control line and a second sub-control line, one end of the first sub-control line and one end of the second sub-control line are respectively connected to the driving structure, the other end of the first sub-control line is connected to the first end area, and the other end of the second sub-control line is connected to the second end area.

[0013] In some embodiments, a distance from the first sub-control line to the driving line is the same as or different from a distance from the second sub-control line to the driving line.

[0014] In some embodiments, between the driving structure and the first end region or between the second end region, the first sub-control line of any control line is adjacent to the second sub-control line of an adjacent control line, or the first sub-control line of any control line is adjacent to the first sub-control line of an adjacent control line.

[0015] In some embodiments, the driving lines include word lines and / or bit lines.

[0016] In some embodiments, the memory cell array includes a multi-layer stacked memory cell array, and the connection area of ​​any layer of the memory cell array overlaps with the projection of the first edge area or the second edge area of ​​the memory cell array of an adjacent layer on the array plane of the memory cell array.

[0017] The technical solution disclosed in this disclosure has the following beneficial effects:

[0018] On the basis of the driving structure driving based on the driving line, a control line corresponding to the driving line is also set, and the driving structure indirectly drives the driving line through the control line. The control line and the driving line are connected through multiple contacts, which reduces the line length between the contacts on the word line and the bit line and the target storage unit; in addition, the resistance of the control line can be controlled by adjusting the resistivity and width of the control line to adjust the driving ability of the driving structure to the target storage unit, so as to avoid the limitation of the width of the word line and the bit line on the driving ability of the target storage unit.

[0019] In some embodiments, the resistance of the control line is reduced to reduce the resistance between the driving structure and the target memory cell on the driving line, thereby improving the driving capability of the driving structure and avoiding read and write errors of the memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0021] Figure 1 A schematic diagram of the structure of a single memory cell array in the word line direction provided by an embodiment of the present disclosure;

[0022] Figure 2 A schematic diagram of the structure of a single memory cell array in the bit line direction provided by an embodiment of the present disclosure;

[0023] Figure 3 A schematic diagram of a connection structure of a driving structure, a control line and a driving line provided in an embodiment of the present disclosure;

[0024] Figure 4 A schematic diagram of a connection structure of another driving structure, control lines and driving lines provided in an embodiment of the present disclosure;

[0025] Figure 5A schematic diagram of a connection structure of another driving structure, control lines and driving lines provided in an embodiment of the present disclosure;

[0026] Figure 6 A schematic diagram of the layout structure of a first sub-control line and a second sub-control line provided in an embodiment of the present disclosure;

[0027] Figure 7 A schematic diagram of another layout structure of a first sub-control line and a second sub-control line provided in an embodiment of the present disclosure;

[0028] Figure 8 A schematic diagram of a connection structure of a driving structure, control lines, and driving lines corresponding to a multi-layer memory cell array provided in an embodiment of the present disclosure.

[0029] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0030] As can be seen from the background technology, 3D memory architecture can solve the density limitation in planar memory cells. In 3D phase change memory (3D-PCM), the bit lines and word lines are formed by tungsten (W) with relatively high resistivity; however, due to the scattering of electrons at the surface and grain boundaries, the resistivity of tungsten increases rapidly as the critical dimension or critical dimension (CD) decreases.

[0031] In addition, in order to selectively activate word lines (WL) and bit lines (BL), the memory includes a word line driver structure (WL Driver) and a bit line driver structure (BL Driver). The word line driver structure is coupled to the word line through a word line contact and is used to decode the word line address, so that the word line is activated when addressing a specific word line. The bit line driver structure is coupled to the bit line through a bit line contact and is used to decode the bit line address, so that the bit line is activated when addressing a specific bit line.

[0032] The voltage drop on the word line and the bit line increases significantly as the line length (word line length or bit line length) between the contact and the target memory cell increases, and may cause insufficient current at the target memory cell, thereby causing read and write errors of the memory. In this case, the voltage drop problem caused by the line length can be avoided to a certain extent by compensating the voltage on the word line and the bit line, but it will cause the problem of excessive current at other memory cells along the word line or the bit line.

[0033] In summary, the reasons why the memory density of 3D phase change memory cannot be further improved include: (1) In order to reduce the resistance of word lines and bit lines, word lines and bit lines need to have a certain width, resulting in the inability to further compress the memory array area; (2) In order to ensure the driving capability of the driver structure (Driver), the length of word lines and bit lines needs to be shortened, which increases the number of driver structures in the memory and occupies part of the device area.

[0034] The present embodiment proposes a memory, comprising: a memory cell array, comprising a first edge region, a connection region, and a second edge region arranged along a first direction, and the connection region is located between the first edge region and the second edge region; a plurality of drive lines extending along the first direction, each of the drive lines being coupled to a column of memory cells arranged along the first direction, and comprising a first end region, a middle region, and a second end region, the first end region corresponding to the first edge region, the middle region corresponding to the connection region, and the second end region corresponding to the second edge region; a plurality of control lines extending along the first direction and corresponding to the drive lines, the control lines being electrically connected to the middle region corresponding to the drive lines, and being electrically connected to at least one of the first end region and the second end region.

[0035] The memory provided by the embodiment of the present disclosure is provided with control lines corresponding to the driving lines on the basis of the driving structure driving based on the driving lines. The driving structure drives the driving lines indirectly through the control lines. The control lines and the driving lines are connected through a plurality of contacts, thereby reducing the line length between the contacts on the word lines and the bit lines and the target memory cells. In addition, the resistance of the control lines can be controlled by controlling the resistivity and width of the control lines, so as to adjust the driving ability of the driving structure to the target memory cells and avoid the limitation of the width of the word lines and the bit lines on the driving ability of the target memory cells.

[0036] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0037] In addition, in the present invention, descriptions such as "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0038] For the memory provided in this embodiment, the driving line includes a word line WL and / or a bit line BL. If the driving line is only exemplified by the word line WL, the word line WL extends along the first direction, and the bit line BL extends along the second direction; if the driving line is only exemplified by the bit line BL, the bit line BL extends along the first direction, and the word line WL extends along the second direction; if the driving line includes both the word line WL and the bit line BL, the word line WL extends along the first direction, and the bit line BL extends along the second direction.

[0039] It should be noted that the memory provided in this embodiment can be implemented based on the driving lines being word lines WL, or based on the driving lines being bit lines BL, or a combination of the embodiments in which the driving lines are word lines WL and the embodiments in which the driving lines are bit lines BL.

[0040] It should also be noted that in order to illustrate the difference between the memory examples based on whether the driving line is a word line WL or a bit line BL, when the driving line is a word line WL, the control line is described based on the first control line; when the driving line is a bit line BL, the control line is described based on the second control line.

[0041] In some embodiments, the first direction and the second direction are perpendicular to each other.

[0042] Figure 1 A schematic diagram of the structure of a single memory cell array in the word line direction provided by this embodiment, Figure 2 A schematic diagram of the structure of a single memory cell array in the bit line direction provided by this embodiment.

[0043] In some embodiments, if the driving line is a word line WL, reference Figure 1The memory includes a memory cell array 100, including a first edge region 201, a connection region 200, and a second edge region 202 arranged along a first direction (X direction, in this case, the second direction is the Y direction), and the connection region 200 is located between the first edge region 201 and the second edge region 202. A plurality of word lines 210 extending along the first direction, the word lines 210 are coupled to a column of memory cells arranged along the first direction, and each word line 210 includes a first end region, a middle region, and a second end region, the first end region corresponds to the first edge region, the middle region corresponds to the connection region, and the second end region corresponds to the second edge region. A plurality of first control lines extending along the first direction and corresponding to the word lines 210, the first control lines are electrically connected to the middle region of the corresponding word lines 210, and are electrically connected to at least one of the first end region and the second end region.

[0044] In some embodiments, if the driving line is a bit line BL, reference Figure 2 The memory includes a memory cell array 100, including a first edge region 201, a connection region 200, and a second edge region 202 arranged along a first direction (Y direction, in this case, the second direction is the X direction), and the connection region 200 is located between the first edge region 201 and the second edge region 202. A plurality of bit lines 220 extending along the first direction, the bit lines 220 are coupled to a column of memory cells arranged along the first direction, and each bit line 220 includes a first end region, a middle region, and a second end region, the first end region corresponds to the first edge region, the middle region corresponds to the connection region, and the second end region corresponds to the second edge region. A plurality of second control lines extending along the first direction and corresponding to the bit lines 220, the second control lines are electrically connected to the middle region of the corresponding bit lines 220, and are electrically connected to at least one of the first end region and the second end region.

[0045] It should be noted that Figure 1 and Figure 2 The memory in the example is implemented based on the driving lines being word lines WL and bit lines BL at the same time, but in order to distinguish whether the driving lines are based on word lines WL or bit lines BL, the implementation methods of the driving lines based on word lines WL or bit lines BL are numbered separately in the accompanying drawings to illustrate the difference between the driving lines based on word lines WL or bit lines BL.

[0046] for Figure 1 and Figure 2 For example, the first edge region 201 and the second edge region 202 are used to increase the number of contacts of the driving line and the control line to reduce the line length between the contact on the driving line and the target storage unit.

[0047] In addition, compared to the driving structure driving directly through the driving line, the driving structure drives the driving line indirectly through the control line. The determining factor of the driving capability is changed from the driving line to the control line, so that the driving line does not need to consider the influence of resistance on the driving capability during the design process, and the size of the driving line can be further miniaturized.

[0048] In some embodiments, the resistivity of the control lines is less than the resistivity of the drive lines.

[0049] In one example, the control line can be set up using metals or alloys with low resistivity such as copper (Cu) and silver (Ag). By reducing the resistance of the control line, the resistance between the drive structure and the target storage unit on the drive line is reduced, and the driving ability of the drive structure is improved to avoid read and write errors of the memory.

[0050] Regarding the memory cell array 100 , the memory cell array 100 includes a plurality of memory cells arranged in an array, a plurality of memory cells arranged in a row are coupled to the same word line 210 , and a plurality of memory cells arranged in a column are coupled to the same bit line 220 .

[0051] In some embodiments, the memory cell array 100 may include a static random access memory cell array, a dynamic random access memory cell array, a ferroelectric random access memory cell array, or a phase change random access memory cell array.

[0052] The connection region 200 is used for connection between the driving structure 230, the control line and the driving line. The connection region 200 is arranged between the first edge region 201 and the second edge region 202 to reduce the maximum value of the line length from the contact to the target storage unit.

[0053] In some embodiments, the memory further includes a driving structure 230 , and the driving structure 230 is connected to at least one control line. Specifically, the driving structure 230 is connected to the control line through a conductive plug 240 , and the control line is connected to the driving line through the conductive plug 240 .

[0054] It should be noted that one driving structure 230 can drive one control line or multiple control lines, and the multiple control lines driven by the same driving structure 230 can be driving structures arranged in the same layer or driving structures arranged in different layers.

[0055] It should also be noted that the driving structure 230 includes a word line driver and a bit line driver. The word line driver is used to drive the word line WL, and the bit line driver is used to drive the bit line BL. The word line driver and the bit line driver can be set at the same layer or different layers; accordingly, the control lines corresponding to the word line driver and the bit line driver can also be set at the same layer or different layers.

[0056] The driving structure is located in at least one of the connection region 200 , the first edge region 201 or the second edge region 202 .

[0057] In some embodiments, if the driving structure is located in the connection region 200 , the control line is electrically connected to the first end region and the second end region of the corresponding driving line.

[0058] In an application example, there is a first distance between the connection area 200 and the first edge area 201, there is a second distance between the connection area 200 and the second edge area 202, and the difference between the first distance and the second distance is less than a first preset value; by limiting the distance difference between the connection area 200 and the first edge area 201 and the second edge area 202, the difference in driving capability of the driving structure 230 for the left storage unit and the right storage unit is reduced.

[0059] In an application example, the first distance and the second distance are equal; that is, the distances between the three contacts arranged on the connection area 200, the first edge area 201, and the second edge area 202 are equal to balance the driving ability of the driving structure 230 to the left storage unit and the right storage unit.

[0060] It should be noted that Figure 1 and Figure 2 The example describes the memory provided by this embodiment by taking a single memory cell array 100 as an example, which does not constitute a limitation on the number of memory cell arrays 100 in the memory. The number of memory cell arrays 100 in the memory can be any number.

[0061] In some embodiments, the first edge region 201 and the second edge region 202 are disposed at edge positions of the memory cell array 100 , and the first edge region 201 and the second edge region 202 are opposite side edges of the memory cell array 100 .

[0062] In some embodiments, the control lines and the driving lines are arranged in different layers to avoid the limitation of the control line routing on the size reduction.

[0063] In one example, the control line is located on the side of the drive line away from the memory cell. Figure 3 , Figure 3 The following is a schematic diagram of a connection structure of a driving structure, a control line, and a driving line provided in this embodiment. Specifically, Figure 3 Can be considered as Figure 1 The cross-sectional structure diagram at section AB can also be regarded as Figure 2 A schematic cross-sectional structure diagram on the CD section. The driving structure 301 is connected to the control line 302, and the control line 302 is connected to the driving line 304 through a conductive plug.

[0064] In some embodiments, the conductive plug 240 includes a first conductive plug 303 and a second conductive plug 313, wherein the first conductive plug 303 is used to electrically connect the control line 302 and the drive line 304 in the connection area 200, and the second conductive plug 313 is used to electrically connect the control line 302 and the drive line 304 in the edge area (the first edge area 201 and the second edge area 202).

[0065] exist Figure 3 In this example, each position of the control line 302 is at the same distance from the driving line 304 .

[0066] It should be noted that Figure 3 In the example, the control line 302 and the driving structure 301 are arranged in the same or adjacent semiconductor structure, so the control line 302 can be directly connected to the driving structure 301. In addition, the control line and the driving structure can also be arranged in the spacer semiconductor structure, in which case the control line is connected to the driving structure through a conductive plug.

[0067] In some embodiments, Figure 3 The memory shown includes a substrate, and a first metal layer, an insulating layer, and a second metal layer located on the substrate and arranged from near to far; wherein a driving structure 301 is arranged in the substrate, the first metal layer is used for wiring of a control line 302, the second metal layer is used for wiring of a driving line 304, the insulating layer is used for insulation between the first metal layer and the second metal layer, a via is arranged in the insulating layer, and a conductive material is filled in the via to form a conductive plug (a first conductive plug 303 and a second conductive plug 313) to electrically connect the control line 302 and the driving line 304.

[0068] refer to Figure 4 , Figure 4 This is another schematic diagram of the connection structure of the driving structure, control line and driving line provided in this embodiment. Specifically, Figure 4 Can be considered as Figure 1 The cross-sectional structure diagram on the AB section can also be regarded as Figure 2 Schematic diagram of the cross-sectional structure on the CD section. In some embodiments, the control line is located on the side of the driving line away from the storage unit, and each control line includes a first sub-control line 401 and a second sub-control line 402, one end of the first sub-control line 401 and one end of the second sub-control line 402 are respectively connected to the driving structure 301, the other end of the first sub-control line 401 is connected to the first end area, and the other end of the second sub-control line 402 is connected to the second end area.

[0069] In some embodiments, the distance from the first sub-control line 401 to the driving line 304 is the same as or different from the distance from the second sub-control line 402 to the driving line 304 .

[0070] For example, in Figure 4In the example, the distance from the first sub-control line 401 to the driving line 304 is different from the distance from the second sub-control line 402 to the driving line 304. Specifically, the distance from the first sub-control line 401 to the driving line 304 is less than the distance from the second sub-control line 402 to the driving line 304. In other examples, the distance from the first sub-control line 401 to the driving line 304 is the same as the distance from the second sub-control line 402 to the driving line 304, which can be referred to Figure 3 Example.

[0071] In some embodiments, the distances from the first sub-control line 401 to the second sub-control line 402 to the driving line are different. Figure 4 and Figure 6 , Figure 6 A schematic diagram of the layout structure of a first sub-control line and a second sub-control line provided in this embodiment, Figure 6 For the corresponding Figure 1 A schematic diagram of the layout structure of a control line of the driving structure 230 is shown. Between the driving structure 230 and the first end area or between the driving structure 230 and the second end area, the first sub-control line 401 of any control line is adjacent to the adjacent first sub-control line 401. In some embodiments, between the driving structure 230 and the first end area or between the driving structure 230 and the second end area, the second sub-control line 402 of any control line is adjacent to the adjacent second sub-control line 402. In short, the control lines on the same side of the driving structure 230 are of the same type, and the control lines on the same side of the driving structure 230 are of the same type, that is, the heights of the control lines on the same side of the driving structure 230 are the same. By adjusting the heights of the control lines on the same side, the driving capability difference on both sides of the driving structure 230 can be fine-tuned.

[0072] In some embodiments, the driving structure is symmetrically arranged in the first edge area and the second edge area, one end of the control line is electrically connected to the first end area of ​​the corresponding driving line and the driving structure in the first edge area, the other end is electrically connected to the second end area of ​​the corresponding driving line and the driving structure in the second edge area, and the middle end is connected to the middle area of ​​the corresponding driving line.

[0073] refer to Figure 5 , Figure 5 A schematic diagram of another driving structure, control line, and driving line connection structure provided in this embodiment. The driving structure 301 is disposed in the first edge region and the second edge region, and the driving structure is connected to the control line 302 in the first edge region and the second edge region. In the first edge region and the second edge region, the control line 302 is connected to the driving line 304 through the second conductive plug 313; in the connection region 200, the middle end of the control line 302 is connected to the middle region of the driving line 304 through the first conductive plug 303.

[0074] In some other embodiments, the distances from the first sub-control line 401 to the second sub-control line 402 to the driving line are different. Figure 4 and Figure 7 , Figure 7 A schematic diagram of the layout structure of the second first sub-control line and the second sub-control line provided in this embodiment, Figure 6 For the corresponding Figure 1 Another schematic diagram of the layout structure of the control lines of the driving structure 230 is shown, where the first sub-control line 401 of any control line is adjacent to the adjacent second sub-control line 402 between the driving structure 230 and the first end region or between the driving structure 230 and the second end region. In short, the first sub-control lines 401 and the second sub-control lines 402 on the same side or different sides of the only driving structure 230 are alternately arranged, and the first sub-control lines 401 and the second sub-control lines 402 at different heights are alternately arranged to increase the spacing between adjacent control lines and avoid electrical signal crosstalk between adjacent control lines.

[0075] In some embodiments, the lengths of the first sub-control line 401 and the second sub-control line 402 are different. That is, the lengths of the control lines on the same side of the driving structure 230 are different, and by adjusting the lengths of the control lines on the same side, the driving capability difference between the two sides of the driving structure 230 is fine-tuned. In other embodiments, the lengths of the first sub-control line 401 and the second sub-control line 402 are the same.

[0076] In some embodiments, the widths of the first sub-control line 401 and the second sub-control line 402 are different. That is, the widths of the control lines on the same side of the driving structure 230 are different, and by adjusting the widths of the control lines on the same side, the driving capability difference between the two sides of the driving structure 230 is fine-tuned. In other embodiments, the widths of the first sub-control line 401 and the second sub-control line 402 are the same.

[0077] In some embodiments, the materials of the first sub-control line 401 and the second sub-control line 402 are different. That is, the materials of the control lines on the same side of the driving structure 230 are different, and by adjusting the materials of the control lines on the same side, the driving capability difference between the two sides of the driving structure 230 is fine-tuned. In other embodiments, the materials of the first sub-control line 401 and the second sub-control line 402 are the same.

[0078] It should be noted that whether the specific length, width and material of the first sub-control line 401 and the second sub-control line 402 are the same does not constitute a limitation of this embodiment. Those skilled in the art can set the specific length, width and material of the first sub-control line 401 and the second sub-control line 402 based on the position of the connection area to balance the driving capability from the connection area to the first edge area and the driving capability from the connection area to the second edge area.

[0079] In some embodiments, the memory cell array comprises a multi-layer stacked memory cell array, and the connection region of any layer of the memory cell array overlaps with the projection of the first edge region or the second edge region of the adjacent layer of the memory cell array on the array plane of the memory cell array.

[0080] In one example, it is assumed that the memory cell array is multi-layered, and each layer of the memory cell array includes a plurality of Figure 1 and Figure 2 In the memory cell array shown, at this time, in the stacking direction of the memory cell array, the connection area of ​​the second memory cell array corresponds to the edge area (first edge area or second edge area) of the first memory cell array, and the edge area (first edge area or second edge area) of the second memory cell array corresponds to the connection area of ​​the first memory cell array; the connection area of ​​the third memory cell array corresponds to the edge area (first edge area or second edge area) of the second memory cell array, and the edge area (first edge area or second edge area) of the third memory cell array corresponds to the connection area of ​​the second memory cell array; that is, the connection area of ​​any memory cell array overlaps with the projection of the first edge area or the second edge area of ​​the adjacent memory cell array on the array plane of the memory cell array. By alternately arranging the memory cell arrays, the gaps between the memory cell arrays are utilized to complete the wiring of the driving structure, thereby further reducing the size of the memory.

[0081] For a two-layer memory cell array, refer to Figure 8 , Figure 8 A schematic diagram of a connection structure of a driving structure, control lines, and driving lines corresponding to a multi-layer memory cell array provided in this embodiment, wherein the memory includes a first-layer memory cell array 501 and a second-layer memory cell array 502, wherein the second-layer memory cell array 502 is located on the first-layer memory cell array 501; in the stacking direction of the memory cell arrays, a connection area 520 of the second-layer memory cell array 502 corresponds to an edge area (the first edge area 511 or the second edge area 512) of the first-layer memory cell array 501, and an edge area (the first edge area 521 or the second edge area 522) of the second-layer memory cell array 502 corresponds to a connection area 510 of the first-layer memory cell array 501.

[0082] The first layer of storage cell array 501 is driven based on the first driving structure 602, and the second layer of storage cell array 502 is driven based on the second driving structure 601. Since the two layers of storage cell arrays are stacked, the driving lines corresponding to the storage cell arrays are located at different heights. As shown in the figure, the first layer of storage cell array 501 corresponds to the first driving line 530, and the second layer of storage cell array 502 corresponds to the second driving line 540. The second driving line 540 is located above the first driving line 530. Based on the foregoing, the connection areas of different storage cells are alternately arranged, that is, the first driving structure 602 and the second driving structure 601 are alternately arranged, wherein the driving connection corresponding to the first driving structure 602 or the second driving structure 601 can refer to Figure 3 and Figure 4 Specifically, the control line 302 is illustrated based on black lines, the first conductive plug 303 is illustrated based on blue lines, and the second conductive plug 313 is illustrated based on red lines; wherein the drive connections corresponding to the first drive structure 602 or the second drive structure 601 are staggered and superimposed to form Figure 8 This example is not described in detail in this embodiment.

[0083] It should be noted that the memory cell array provided in this embodiment may include a static random access memory cell array, a dynamic random access memory cell array, a ferroelectric random access memory cell array or a phase change random access memory cell array.

[0084] Based on the foregoing, it can be known that, on the basis of the driving structure driving based on the driving line, a control line corresponding to the driving line is also set, and the driving structure indirectly drives the driving line through the control line. The control line and the driving line are connected through multiple contacts, which reduces the line length between the contacts on the word line and the bit line and the target storage unit; in addition, the resistance of the control line can be controlled by adjusting the resistivity and width of the control line to adjust the driving ability of the driving structure to the target storage unit, so as to avoid the limitation of the width of the word line and the bit line on the driving ability of the target storage unit.

[0085] It should be noted that, in the absence of conflict, the features disclosed in the memory provided in the above embodiments can be randomly combined to obtain a new memory embodiment.

[0086] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the detailed description of other embodiments above, and will not be repeated here.

[0087] The basic concepts have been described above. Obviously, for those skilled in the art, the above detailed disclosure is only for example and does not constitute a limitation of the present disclosure. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements and corrections to the present disclosure. Such modifications, improvements and corrections are suggested in the present disclosure, so such modifications, improvements and corrections still belong to the spirit and scope of the exemplary embodiments of the present disclosure.

[0088] The above is a detailed introduction to a memory provided by an embodiment of the present disclosure. Specific examples are used herein to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method of the present disclosure and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present disclosure, there will be changes in the specific implementation methods and application scopes. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

Claims

1. A memory, characterized in that: include: A memory cell array, comprising a first edge region, a connection region and a second edge region arranged along a first direction, wherein the connection region is located between the first edge region and the second edge region; A plurality of driving lines extending along the first direction, each of the driving lines being coupled to a column of memory cells arranged along the first direction and comprising a first end region, a middle region, and a second end region, the first end region corresponding to the first edge region, the middle region corresponding to the connection region, and the second end region corresponding to the second edge region; A plurality of control lines extending along the first direction and corresponding to the driving lines, wherein the control lines are electrically connected to a middle region corresponding to the driving lines and to at least one of the first end region and the second end region.

2. The memory according to claim 1, wherein: The resistivity of the control line is smaller than the resistivity of the driving line.

3. The memory according to claim 2, wherein: The driving line is made of tungsten, and the control line is made of copper.

4. The memory according to claim 1, wherein: Also includes: A driving structure is located in at least one of the connection area, the first edge area, or the second edge area, and the driving structure is electrically connected to the control line.

5. The memory according to claim 4, wherein: The driving structure is symmetrically arranged in the first edge area and the second edge area, one end of the control line is electrically connected to the first end area of ​​the corresponding driving line and the driving structure in the first edge area, the other end is electrically connected to the second end area of ​​the corresponding driving line and the driving structure in the second edge area, and the middle end is connected to the middle area of ​​the corresponding driving line.

6. The memory according to claim 4, wherein: The driving structure is located in the connection area, and the control line includes a first sub-control line and a second sub-control line, one end of the first sub-control line and one end of the second sub-control line are respectively connected to the driving structure, the other end of the first sub-control line is connected to the first end area, and the other end of the second sub-control line is connected to the second end area.

7. The memory according to claim 6, wherein: The distance from the first sub-control line to the driving line is the same as or different from the distance from the second sub-control line to the driving line.

8. The memory according to claim 7, wherein: Between the driving structure and the first end region or between the second end region, the first sub-control line of any control line is adjacent to the second sub-control line of an adjacent control line, or the first sub-control line of any control line is adjacent to the first sub-control line of an adjacent control line.

9. The memory according to claim 1, wherein: The driving lines include word lines and / or bit lines.

10. The memory according to any one of claims 1 to 9, characterized in that: The memory cell array comprises a multi-layer stacked memory cell array, wherein the connection region of any layer of the memory cell array overlaps with the projection of the first edge region or the second edge region of the memory cell array of an adjacent layer on the array plane of the memory cell array.

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