Eye pattern scanning method and device, control unit and system on chip

Abstract

The invention provides an eye pattern scanning method, which comprises the following steps in a data reading direction: after memory training is completed and an operating system service starts to run, a CU (Control Unit) dynamically adjusts a physical layer interface delay value through an MC (Management Controller) under the same physical layer interface reference voltage, carries out a pressure test, and obtains an interval range of physical layer interface delay of which an ECC (Error Correction Code) result is passing; the CU dynamically adjusts the value of the reference voltage of the physical layer interface through the MC under the same physical layer interface time delay, carries out a pressure test, and obtains the interval range of the reference voltage of the physical layer interface of which the ECC result is passing; and the CU generates a current eye pattern scanning result according to the interval range of the physical layer interface delay and the interval range of the physical layer interface reference voltage. According to the method, the real-time eye diagram result which truly reflects the system running state can be obtained under the condition that the operation system business is not interrupted, so that whether the memory under the current business is reliable or not can be determined according to the real-time eye diagram result, and normal operation of the system business is ensured.

Description

Technical Field

[0001] The present invention relates to the field of memory testing technology, and in particular to an eye diagram scanning method, device, control unit and system on chip. Background Art

[0002] With the development of storage technology, the memory rate of DDR (double data rate SDRAM) has also been greatly improved, which has introduced many challenges in signal integrity. The most direct challenge is signal quality issues such as crosstalk, jitter, and inter-symbol interference. At present, the rapid generation and analysis of digital eye diagrams of transmission signals is an important means to debug high-speed DDR signals and solve signal quality problems.

[0003] The digital eye diagram focuses on the tolerance of the MC (Memory Controller) to data signal sampling deviation during signal transmission. It is used to evaluate the reliability of motherboard memory operation. Since it does not require the help of an oscilloscope, it plays an important role in actual DDR debugging.

[0004] At present, the eye diagram scanning method is mainly based on the DDR Training (memory training) process in the system startup phase. The so-called memory training is to ensure that the DDR bus signal can meet the specified timing requirements at both the receiving end and the transmitting end, and to ensure that there is enough margin on the left and right sides of the sampling points of DQ and CA (command / address signal).

[0005] However, this eye diagram scanning method is different from the actual situation in the system, resulting in the eye diagram results not being able to truly reflect the system operation status. Taking the DQ signal reference voltage Vref as an example, the eye height in the system startup phase is larger than the eye height in the stress test phase, that is, after the system runs the business, the DQ eye diagram will shrink due to factors such as voltage fluctuations and business operations. If the degree of this eye diagram shrinkage cannot be well evaluated, and the eye diagram scanning results obtained after memory training are still used, it will result in normal eye diagram data in the system startup phase, but after the system runs the business, it will crash due to data errors. Summary of the invention

[0006] The eye diagram scanning method, device, control unit and system on chip provided by the present invention can obtain real-time eye diagram results that truly reflect the operating status of the system without interrupting the operating system business, so as to confirm whether the memory is reliable under the current business based on the real-time eye diagram results, thereby ensuring the normal operation of the system business.

[0007] In a first aspect, the present invention provides an eye diagram scanning method, in a data reading direction, the method comprising:

[0008] After completing the memory training and starting to run the operating system business, the control unit dynamically adjusts the value of the physical layer interface delay through the memory controller under the same physical layer interface reference voltage, performs a stress test, and obtains the interval range of the physical layer interface delay for which the ECC result passes;

[0009] The control unit dynamically adjusts the value of the physical layer interface reference voltage through the memory controller under the same physical layer interface delay, performs a stress test, and obtains an interval range of the physical layer interface reference voltage for which the ECC result passes;

[0010] The control unit generates a current eye diagram scanning result according to the interval range of the physical layer interface delay and the interval range of the physical layer interface reference voltage.

[0011] Optionally, the control unit dynamically adjusts the value of the physical layer interface delay through the memory controller under the same physical layer interface reference voltage to perform a stress test, and the range of the physical layer interface delay for which the ECC result is passed includes:

[0012] S1, the control unit starts scanning the physical layer interface delay parameters and configures the initial value of the physical layer interface delay scan;

[0013] S2, the control unit triggers the memory controller to dynamically adjust the value of the physical layer interface delay, the memory controller stops responding to the memory read and write requests, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface delay; after the physical layer interface dynamically adjusts the value of the physical layer interface delay, the memory controller resumes responding to the memory read and write requests;

[0014] S3. The control unit reads the ECC data of the memory channel of the memory controller. If the ECC count is equal to 0, the physical layer interface delay is reduced by 1 / added by 1, and the process returns to step S2 to continue scanning the boundary. If the ECC count is greater than 0, the scanning is stopped when the boundary is scanned. The current physical layer interface delay, i.e., the ECC result, is the minimum / maximum value of the range of the passed physical layer interface delay.

[0015] Optionally, the control unit dynamically adjusts the value of the physical layer interface reference voltage through the memory controller under the same physical layer interface delay to perform a stress test, and the range of the physical layer interface reference voltage for which the ECC result is passed includes:

[0016] T1, the control unit starts scanning the physical layer interface reference voltage parameters and configures the scanning initial value of the physical layer interface reference voltage;

[0017] T2, the control unit triggers the memory controller to dynamically adjust the value of the physical layer interface reference voltage, the memory controller stops responding to memory read and write requests, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface reference voltage; after the physical layer interface dynamically adjusts the value of the physical layer interface reference voltage, the memory controller resumes responding to memory read and write requests;

[0018] T3. The control unit reads the ECC data of the memory channel of the memory controller. If the ECC count is equal to 0, the physical layer interface reference voltage is reduced by 1 / added by 1, and the process returns to step T2 to continue scanning the boundary. If the ECC count is greater than 0, the scanning stops when the boundary is reached. The current physical layer interface reference voltage, i.e., the ECC result, is the minimum / maximum value of the range of the passed physical layer interface reference voltage.

[0019] In a second aspect, the present invention provides an eye diagram scanning method, in a data writing direction, the method comprising:

[0020] After completing the memory training and starting to run the operating system business, the control unit dynamically adjusts the value of the physical layer interface delay through the memory controller under the same memory reference voltage, performs a stress test, and obtains the interval range of the physical layer interface delay for which the CRC result passes;

[0021] The control unit dynamically adjusts the value of the memory reference voltage on the physical layer interface and the memory through the memory controller under the same physical layer interface delay, performs a stress test, and obtains the interval range of the memory reference voltage for which the CRC result passes;

[0022] The control unit generates a current eye diagram scanning result according to the interval range of the physical layer interface delay and the interval range of the memory reference voltage.

[0023] Optionally, the control unit dynamically adjusts the value of the physical layer interface delay through the memory controller under the same memory reference voltage to perform a stress test, and the interval range of the physical layer interface delay for which the CRC result is passed includes:

[0024] M1. The control unit starts scanning the physical layer interface delay parameters and configures the initial value of the physical layer interface delay scan;

[0025] M2. The control unit triggers the memory controller to dynamically adjust the value of the physical layer interface delay, the memory controller stops responding to the memory read and write requests, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface delay; after the physical layer interface dynamically adjusts the value of the physical layer interface delay, the memory controller resumes responding to the memory read and write requests;

[0026] M3. The control unit reads the CRC data of the memory channel of the memory controller. If the CRC count is equal to 0, the physical layer interface delay is reduced by 1 / added by 1, and the process returns to step M2 to continue scanning the boundary. If the CRC count is greater than 0, the scanning is stopped when the boundary is scanned. The current physical layer interface delay, i.e., the CRC result, is the minimum / maximum value of the range of the passed physical layer interface delay.

[0027] Optionally, the control unit dynamically adjusts the value of the memory reference voltage on the physical layer interface and the memory through the memory controller under the same physical layer interface delay to perform a stress test, and the interval range of the memory reference voltage for which the CRC result is passed includes:

[0028] N1. The control unit starts scanning the memory reference voltage parameters and configures the initial value of the memory reference voltage scan;

[0029] N2. The control unit triggers the memory controller to dynamically adjust the value of the memory reference voltage on the physical layer interface and the memory, the memory controller stops responding to the memory read and write requests, and sends an instruction to the physical layer interface and the memory to dynamically adjust the value of the memory reference voltage; after the physical layer interface and the memory dynamically adjust the value of the memory reference voltage, the memory controller resumes responding to the memory read and write requests;

[0030] N3. The control unit reads the CRC data of the memory channel of the memory controller. If the CRC count is equal to 0, the memory reference voltage is reduced by 1 / added by 1, and the process returns to step N2 to continue scanning the boundary. If the CRC count is greater than 0, the scanning is stopped when the boundary is reached. The current memory reference voltage, i.e., the CRC result, is the minimum value / maximum value of the passed memory reference voltage interval.

[0031] In a third aspect, the present invention provides an eye diagram scanning device, in a data reading direction, the device comprises:

[0032] The first test unit is used to dynamically adjust the value of the physical layer interface delay through the memory controller under the same physical layer interface reference voltage after completing the memory training and starting to run the operating system business, perform a stress test, and obtain the interval range of the physical layer interface delay for which the ECC result is passed;

[0033] The second test unit is used to dynamically adjust the value of the physical layer interface reference voltage through the memory controller under the same physical layer interface delay, perform stress testing, and obtain the interval range of the physical layer interface reference voltage for which the ECC result is passed;

[0034] The first generating unit is used to generate a current eye diagram scanning result according to the interval range of the physical layer interface delay and the interval range of the physical layer interface reference voltage.

[0035] Optionally, the first testing unit includes:

[0036] The first configuration module is used to start scanning of physical layer interface delay parameters and configure the scanning initial value of the physical layer interface delay;

[0037] The first trigger module is used to trigger the memory controller to dynamically adjust the value of the physical layer interface delay, so that the memory controller stops responding to the memory read and write request, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface delay; after the physical layer interface dynamically adjusts the value of the physical layer interface delay, the memory controller resumes responding to the memory read and write request;

[0038] The first test module is used to read the ECC data of the memory channel of the memory controller. If the ECC count is equal to 0, the physical layer interface delay is reduced by 1 / added by 1, and the first trigger module performs the above operation and continues to scan the boundary; if the ECC count is greater than 0, the scanning is stopped when the boundary is scanned, and the current physical layer interface delay, that is, the ECC result, is the minimum value / maximum value of the interval range of the passed physical layer interface delay.

[0039] Optionally, the second testing unit includes:

[0040] The second configuration module is used to start scanning of the reference voltage parameters of the physical layer interface and configure the scanning initial value of the reference voltage of the physical layer interface;

[0041] A second trigger module is used to trigger the memory controller to dynamically adjust the value of the physical layer interface reference voltage, so that the memory controller stops responding to memory read and write requests, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface reference voltage; after the physical layer interface dynamically adjusts the value of the physical layer interface reference voltage, the memory controller resumes responding to the memory read and write requests;

[0042] The second test module is used to read the ECC data of the memory channel of the memory controller. If the ECC count is equal to 0, the physical layer interface reference voltage is reduced by 1 / added by 1, and the second trigger module performs the above operation and continues to scan the boundary; if the ECC count is greater than 0, the scanning is stopped when the boundary is scanned, and the current physical layer interface reference voltage, that is, the ECC result, is the minimum value / maximum value of the interval range of the passed physical layer interface reference voltage.

[0043] In a fourth aspect, the present invention provides an eye diagram scanning device, in a data writing direction, the device comprising:

[0044] The third test unit is used for, after completing the memory training and starting to run the operating system service, the control unit dynamically adjusts the value of the physical layer interface delay through the memory controller under the same memory reference voltage, performs a stress test, and obtains the interval range of the physical layer interface delay for which the CRC result passes;

[0045] A fourth test unit is used to dynamically adjust the value of the memory reference voltage on the physical layer interface and the memory through the memory controller under the same physical layer interface delay, perform a stress test, and obtain an interval range of the memory reference voltage for which the CRC result passes;

[0046] The second generating unit is used to generate the current eye diagram scanning result according to the interval range of the physical layer interface delay and the interval range of the memory reference voltage.

[0047] Optionally, the third test unit includes:

[0048] The third configuration module is used to start scanning of physical layer interface delay parameters and configure the scanning initial value of the physical layer interface delay;

[0049] A third trigger module is used to trigger the memory controller to dynamically adjust the value of the physical layer interface delay, so that the memory controller stops responding to the memory read and write request, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface delay; after the physical layer interface dynamically adjusts the value of the physical layer interface delay, the memory controller resumes responding to the memory read and write request;

[0050] The third test module is used to read the CRC data of the memory channel of the memory controller. If the CRC count is equal to 0, the physical layer interface delay is reduced by 1 / added by 1, and the third trigger module performs the above operation and continues to scan the boundary; if the CRC count is greater than 0, the scanning is stopped when the boundary is scanned, and the current physical layer interface delay, that is, the CRC result, is the minimum value / maximum value of the passed physical layer interface delay interval range.

[0051] Optionally, the fourth test unit includes:

[0052] A fourth configuration module, used to start a memory reference voltage parameter scan and configure an initial value of the memory reference voltage scan;

[0053] A fourth trigger module is used to trigger the memory controller to dynamically adjust the value of the memory reference voltage on the physical layer interface and the memory, so that the memory controller stops responding to the memory read and write request, and sends an instruction to the physical layer interface and the memory to dynamically adjust the value of the memory reference voltage; after the physical layer interface and the memory dynamically adjust the value of the memory reference voltage, the memory controller resumes responding to the memory read and write request;

[0054] The fourth test module is used to read the CRC data of the memory channel of the memory controller. If the CRC count is equal to 0, the memory reference voltage is reduced by 1 / added by 1, and the fourth trigger module performs the above operation and continues to scan the boundary; if the CRC count is greater than 0, the scanning is stopped when the boundary is scanned, and the current memory reference voltage, that is, the CRC result, is the minimum value / maximum value of the interval range of the passed memory reference voltage.

[0055] In a fifth aspect, the present invention provides a control unit, which includes the eye pattern scanning device as described above.

[0056] In a sixth aspect, the present invention provides a system on chip, comprising the control unit as described above, a memory controller connected to the control unit, and a physical layer interface of the memory controller.

[0057] In a seventh aspect, the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and when the computer instructions are executed by a processor, the eye diagram scanning method as described above is implemented.

[0058] The eye diagram scanning method, device, control unit and system on chip provided by the embodiments of the present invention can dynamically adjust the physical layer interface delay and the value of the physical layer interface reference voltage in the data read direction through the memory controller without interrupting the operating system service, and obtain the ECC result as the interval range of the physical layer interface reference voltage and the physical layer interface delay that pass, and dynamically adjust the physical layer interface delay and the value of the memory reference voltage in the data write direction through the memory controller, and obtain the CRC result as the interval range of the memory reference voltage and the physical layer interface delay that pass, thereby obtaining a real-time eye diagram result that truly reflects the system operation status, so as to confirm whether the memory is reliable under the current service according to the real-time eye diagram result, thereby ensuring the normal operation of the system service. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 A sampling diagram of PHY DQ Delay and PHY DQ Vref provided in an embodiment of the present invention;

[0060] Figure 2 A schematic diagram of generating a digital eye diagram provided by an embodiment of the present invention;

[0061] Figure 3 A schematic diagram of the hardware framework of a system on a chip provided by an embodiment of the present invention;

[0062] Figure 4 A flowchart of an eye pattern scanning method according to an embodiment of the present invention;

[0063] Figure 5 A flow chart of an eye pattern scanning method according to another embodiment of the present invention;

[0064] Figure 6 A flowchart of an eye diagram scanning method according to another embodiment of the present invention;

[0065] Figure 7 A schematic diagram of scanning of PHY DQ Delay provided by an embodiment of the present invention;

[0066] Figure 8 A schematic diagram of scanning of PHY DQ Vref provided by an embodiment of the present invention;

[0067] Fig. 9 A flowchart of an eye diagram scanning method according to another embodiment of the present invention;

[0068] Fig.10 It is a structural schematic diagram of an eye pattern scanning device according to an embodiment of the present invention;

[0069] Fig.11 It is a schematic structural diagram of an eye pattern scanning device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0070] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] First, the professional terms involved in the embodiments of the present invention are explained.

[0072] DDR: The full name is DDR SDRAM, which stands for Double Data Rate SDRAM.

[0073] SDRAM: Synchronous Dynamic Random Access Memory.

[0074] The DQ signal (Data Signal) is used to transmit data in DDR memory. In DDR technology, the DQ signal can be sampled on both the rising and falling edges of the clock. This feature is called Dual Edge Transmission.

[0075] The working principle of DQ signal is based on dual edge clocking. In SDR (Single Data Rate) technology, data is only transmitted on the rising or falling edge of the clock, while in DDR (Double Data Rate) technology, data can be transmitted on both the rising and falling edges of the clock, thus achieving a higher data transmission rate.

[0076] In order to accurately receive data, DQS (Data Strobe Signal) is introduced. The DQS signal is used as a synchronous timing reference signal to accurately distinguish the transmission cycle of DQ data in each clock cycle. In a read operation, DQS is generated by the memory chip and sent to the controller; in a write operation, DQS is generated by the controller and sent to the memory chip. DQS is aligned with the data edge during a read operation and with the data center during a write operation.

[0077] The digital eye diagram focuses on the tolerance of the MC to the sampling deviation of the data signal during the signal transmission process. Take the data when DQS (Data Strobe Signal) samples DQ (data bus) as an example. Figure 1 The left side of the diagram is a schematic diagram of the deviation between DQS and DQ. It can be seen that the margin is the largest only when the rising edge of DQS is in the middle of DQ. Therefore, in practice, the width of the left and right margins, i.e., DQ Margin, can be scanned by moving the position of the signal. Figure 1 The right side of is a schematic diagram of reference voltage margin deviation. In DDR design of digital circuits, the identification of 0 and 1 is determined by the reference voltage value Vref. If the voltage when DQS samples DQ is greater than Vref, the DQ value is determined to be 1; if the voltage when DQS samples DQ is less than Vref, the DQ value is determined to be 0. Therefore, in practice, the width of the upper and lower margins of the signal, namely VrefMargin, can be scanned by moving the value of Vref.

[0078] It can be seen that each reference voltage value Vref can correspond to a set of left and right margin widths of DQ. Collecting them and plotting them on the coordinate axis will form the following: Figure 2 The digital eye diagram shown in Figure 1. Each horizontal dotted line indicates the width and starting position of the DQ sampling margin under a characteristic decision voltage Vref. Figure 2 As shown, the width of Vref is the eye height of the digital eye diagram, and the DQ signal margin width is the eye width of the digital eye diagram.

[0079] In practical applications, the digital eye diagram is used to evaluate the reliability of the motherboard memory operation. Since it does not use an oscilloscope, it plays an important role in actual DDR debugging. The purpose of the entire DDR debugging is to increase the area of ​​the black box in the figure to ensure the stability of the signal quality.

[0080] like Figure 3 As shown, the hardware architecture based on the eye diagram scanning method provided in the embodiment of the present invention includes a system on chip and DDR (the DIMM shown in the figure is the smallest unit of DDR - memory stick), and the system on chip includes a CU (Control Unit), MC and DDR PHY, wherein,

[0081] CU is the main service object of MC and DDR PHY. All system services run on CU, and the eye diagram dynamic scanning program also runs on CU.

[0082] MC is used to initiate access to memory. One of its important designs is to support dynamic scanning of SI (Signal Integrity) parameters. When the dynamic scanning function is triggered, the memory traffic can be stopped and PHY can be notified to update the PHY SI parameters and DRAM SI parameters.

[0083] DDR PHY is the physical layer interface of the memory controller. It controls the DDR bus during the memory training phase and hands over the control to the MC after the training. DDR needs to be able to dynamically update the SI parameters of PHY.

[0084] DFI (DDR PHY Interface) bus is the communication interface between MC and DDR PHY. MC mainly sends memory read and write commands through DFI bus. At the same time, it can control PHY through DFI signal to complete some management control processes, such as Ctrl Update in DFI standard protocol.

[0085] The DDR bus includes the CA bus (DDR instruction address) and the DQ bus (DDR PHY data bus). The CA bus is responsible for sending commands, and the DQ bus is responsible for sending and receiving data. Memory training mainly refers to the adjustment of the sampling center point of the CA bus and the DQ bus, so as to ensure that the receiving end has the maximum signal reception sampling redundancy.

[0086] In the embodiment of the present invention, the eye diagram scanning method is described from the data reading (Rx) direction and the data writing (Tx) direction respectively.

[0087] The embodiment of the present invention provides an eye diagram scanning method, in the data reading direction, such as Figure 4 As shown, the method includes:

[0088] S11. After completing memory training and starting to run operating system services, the CU dynamically adjusts the value of the physical layer interface delay (PHY DQ Delay) through the MC under the same physical layer interface reference voltage (PHY DQ Vref), performs a stress test, and obtains the range of the physical layer interface delay for which the ECC (Error Checking and Correcting) result passes.

[0089] S12. CU dynamically adjusts the value of the physical layer interface reference voltage through MC under the same physical layer interface delay, performs stress testing, and obtains the interval range of the physical layer interface reference voltage for which the ECC result passes.

[0090] S13. The CU generates a current eye diagram scanning result according to the interval range of the physical layer interface delay and the interval range of the physical layer interface reference voltage.

[0091] The eye diagram scanning method provided by the embodiment of the present invention can dynamically adjust the physical layer interface delay and the value of the physical layer interface reference voltage in the data reading direction through MC without interrupting the operating system business, and obtain the ECC result as the interval range of the passed physical layer interface reference voltage and the physical layer interface delay, and then obtain the real-time eye diagram result that truly reflects the system operation status, so as to confirm whether the memory is reliable under the current business according to the real-time eye diagram result, thereby ensuring the normal operation of the system business.

[0092] The embodiment of the present invention provides an eye diagram scanning method, in the data writing direction, such as Figure 5 As shown, the method includes:

[0093] S21. After completing the memory training and starting to run the operating system business, the CU dynamically adjusts the value of the physical layer interface delay through the MC under the same memory reference voltage (DRAM Vref), performs a stress test, and obtains the CRC (Cyclic Redundancy Check) result as the range of the passed physical layer interface delay.

[0094] S22, CU dynamically adjusts the value of the memory reference voltage on the physical layer interface and the memory through MC under the same physical layer interface delay, performs a stress test, and obtains a range of the memory reference voltage for which the CRC result passes.

[0095] S23. The CU generates a current eye diagram scanning result according to the interval range of the physical layer interface delay and the interval range of the memory reference voltage.

[0096] The eye diagram scanning method provided by the embodiment of the present invention can dynamically adjust the physical layer interface delay and the memory reference voltage value in the data write direction through MC without interrupting the operating system business, and obtain the CRC result as the interval range of the passed memory reference voltage and physical layer interface delay, and then obtain the real-time eye diagram result that truly reflects the system operation status, so as to confirm whether the memory is reliable under the current business according to the real-time eye diagram result, thereby ensuring the normal operation of the system business.

[0097] The eye pattern scanning method of the present invention is described in detail below in conjunction with specific embodiments.

[0098] In this embodiment, only one DQ is used as an example to describe the eye diagram scanning process. In actual eye diagram scanning, the number of DQs of the channel (memory channel) is used as a cycle to complete the eye diagram scanning of the entire system. Furthermore, by using the method provided in this embodiment, the eye diagram scanning of various modes such as motherboard level -> MC > SubChannel -> DQ can be realized by increasing the granularity of the scan.

[0099] First, the eye diagram scanning method in the Rx direction is described, such as Figure 6 As shown, the process in the black box is the hardware behavior, which is implemented by the hardware of the SOC. The core process in the Rx direction is to respond in time when the SI parameters are dynamically updated through the MC and to inform the PHY through the DFI that there is no memory data access at present, and the PHY SI parameters can be updated normally.

[0100] In actual hardware design, in order to avoid system abnormalities when PHY switches SI parameters, the dynamic update of MC's SI parameters generally stops memory access and notifies PHY to update SI parameters.

[0101] In this embodiment, the SI parameters in the Rx direction include PHY DQ Delay and PHY DQ Vref.

[0102] like Figure 6 As shown, in the data reading direction, the eye diagram scanning method provided by the embodiment of the present invention includes the following steps:

[0103] S301. After memory training, the CU enters the operating system normally and starts running normal business programs.

[0104] S302: MC enables the ECC check function normally and clears all ECC error counts.

[0105] S303, the CU starts to obtain the SI parameters of DQ and saves them. Assume that the scanning range of DQ Delay is 0-255 and the initial value is 0x80.

[0106] S304, the CU-side program starts SI parameter scanning, configures DQ Delay to the scanning initial value 0x80, and scans the left boundary.

[0107] S305. The CU-side program triggers the SI dynamic parameter refresh function of the MC.

[0108] S306 , MC starts refreshing SI dynamic parameters, stops memory channel access requests, and notifies PHY to update SI parameters.

[0109] S307 , the PHY receives the dynamic parameter update request from the MC and updates the DQ Delay register of the PHY.

[0110] S308 , PHY notifies MC that the DQ Delay register update is complete and the test can start.

[0111] S309, MC resumes channel memory data access and waits for stress test results. Generally, the stress test waiting time is configured to be 2s.

[0112] S310, CU reads the ECC data of the MC memory channel. If the ECC count is 0, it means that the DQ Delay is within the normal margin range. Set DQ Delay=DQ Delay-1, and return to step S305 to continue scanning the boundary.

[0113] S311, CU reads the ECC data of the MC memory channel. If the ECC count is > 0, it means that the DQ Delay will cause abnormal DQ data reception. The scanning stops when the boundary is reached, and the left boundary scanning ends.

[0114] S312, the CU-side program starts SI parameter scanning, configures DQ Delay to the scanning initial value 0x80, and starts scanning the right boundary.

[0115] S313. The CU-side program triggers the dynamic update function of the SI parameters of the MC.

[0116] S314, MC starts to update SI dynamic parameters, stops memory channel access requests, and notifies PHY to update SI parameters.

[0117] S315 . The PHY receives the SI parameter update request from the MC and updates the DQ Delay register of the PHY.

[0118] S316. PHY notifies MC that the DQ Delay register update is complete and the test can start.

[0119] S317, MC restores channel memory data access and waits for the stress test result. Generally, the stress test waiting time is configured to 2s.

[0120] S318, CU reads the ECC data of the MC memory channel. If the ECC count is 0, it means that the DQ Delay is within the normal margin range. Configure DQ Delay=DQ Delay+1, return to step S313, and continue scanning the boundary.

[0121] S319, CU reads the ECC data of the MC memory channel. If the ECC count is > 0, it means that the DQ Delay will cause abnormal DQ data reception. The scanning stops when the boundary is reached, and the right boundary scanning ends.

[0122] S320: CU restores the Delay of DQ to the original value in the system.

[0123] S321. CU clears the ECC count.

[0124] S322: The CU generates a DQ scan test result, that is, an ECC result is a passed DQ Delay interval range.

[0125] The above process is that the CU adjusts the PHY DQ Delay value through MC under the same DQ Vref, performs stress testing, and obtains the DQ Delay range for which the ECC result passes. Figure 7 As shown in the figure, the scanning process is actually to find the left and right boundaries of the correct sampling data on the DQS rising edge, that is, to find the interval range of DQ Delay where the ECC result is PASS.

[0126] Replace DQ Delay in the above process with DQ Vref and execute the same process. You can adjust the PHY DQ Vref value through MC under the same DQDelay, perform stress testing, and obtain the DQ Vref range for which the ECC result passes. Figure 8 As shown, the scanning process is actually to find the upper and lower boundaries of the correct sampling data on the DQS rising edge, that is, to find the interval range of DQ Vref where the ECC result is PASS.

[0127] like Figure 2 As shown in the figure, according to the scanning results of the two sets of parameters DQ Delay and DQ Vref, the eye diagram can be drawn to achieve signal quality evaluation. The vertical axis is Vref, and the horizontal axis is the left and right delay widths scanned by DQ under each Vref.

[0128] The eye diagram scanning method in the Tx direction is described below. In this embodiment, only one DQ is used as an example to describe the eye diagram scanning process. In actual eye diagram scanning, the number of DQs of the channel (memory channel) is used as a cycle to complete the eye diagram scanning of the entire system.

[0129] like Fig. 9 As shown, the process in the black box is the hardware behavior, which is implemented by the hardware of the SOC. The core process in the Tx direction is to switch the SI dynamic parameters through the MC. The MC must modify the SI parameters of the DRAM particles without process access, otherwise it will cause abnormal access to the DRAM particles.

[0130] Compared with the Rx direction, the Tx direction increases the interaction with the DRAM particles. The dynamic switching support of the MC's SI parameters ensures that the DRAM's TxVref can be safely modified without affecting the system's services. The WRCRC function supported by both the MC and the DRAM particles is used to implement the SI parameter scanning boundary judgment.

[0131] In this embodiment, the SI parameters in the Tx direction include PHY DQ Delay and Vref of the DRAM particle, that is, MR10 described in DRAM SPEC, wherein the Vref of the particle needs the MC to send a DRAM command to be correctly configured.

[0132] The scanning process of the PHY DQ Delay parameter in the Tx direction is similar to the scanning process of the PHY DQ Delay parameter in the Rx direction, except that the scanning boundary is determined by judging the count value of the ECC in the Rx direction, and is modified to determine the scanning boundary by judging the count value of the WRCRC, which will not be repeated here. By using this process, the interval range of the DQDelay in which the WRCRC result in the Tx direction passes can be obtained.

[0133] The scanning process of the DRAM Vref parameter in the Tx direction is introduced below.

[0134] like Fig. 9 As shown, in the Tx direction, the eye diagram scanning method provided by the embodiment of the present invention includes the following steps:

[0135] S401. After memory training, the CU enters the operating system normally and starts running normal business programs.

[0136] S402: MC enables the ECC check function normally and clears all ECC error counts.

[0137] S403, the CU starts to obtain the SI parameter MR10 (VrefDQ) of the DRAM particle DQ and records the initial value, which is assumed to be 0x40.

[0138] S404, the CU-side program starts SI parameter scanning, configures DRAM VrefDQ to the scan initial value 0x40, and scans the left boundary.

[0139] S405. The CU-side program triggers the MC to start the Tx SI parameter dynamic refresh function.

[0140] S406 , the MC starts to update the SI dynamic parameters, stops the memory channel access request, and notifies the PHY to update the SI parameters.

[0141] S407 . The MC sends a command to the DRAM to update the value of DRAM Vref.

[0142] S408 . The PHY receives the dynamic parameter update request from the MC and updates MR10 of the DRAM particle, namely, TxVref.

[0143] S409: DRAM updates the value of DRAM Vref.

[0144] S410. PHY notifies MC that the DRAM MR10 register update is complete and testing can begin.

[0145] S411, MC resumes channel memory data access and waits for stress test results. Generally, the stress test waiting time is configured to be 2s.

[0146] S412, CU reads the CRC error data (MR50) of the particle where the DQ of the MC memory channel is located. If there is a WRCRC count = 0, it means that the VrefDQ is within the normal margin range, and VrefDQ is configured to be VrefDQ = VrefDQ-1, and returns to step S405 to continue scanning the boundary.

[0147] S413, CU reads the CRC error data (MR50) of the particle where the MC memory channel DQ is located. If there is a CRC count = 1, it means that the VrefDQ will cause abnormal DQ data reception. The scanning stops when the boundary is reached, and the left boundary scanning ends.

[0148] S414, MC clears WRCRC error.

[0149] S415, the CU starts to obtain the SI parameter MR10 (VrefDQ) of DQ and records the initial value, which is assumed to be 0x40.

[0150] S416, the CU-side program starts SI parameter scanning, configures DRAM particle VrefDQ to the scanning initial value 0x40, and starts scanning the right boundary.

[0151] S417: The CU-side program triggers the MC to start the Tx SI parameter dynamic update function.

[0152] S418. MC starts to dynamically update Tx SI parameters, stops memory channel access requests, and notifies PHY to update SI parameters.

[0153] S419. PHY receives the SI parameter update request from MC and updates MR10 of the DRAM particle, namely TxVref.

[0154] S420. The MC sends a command to the DRAM to update the value of DRAM Vref.

[0155] S421. PHY notifies MC that the DRAM MR10 register update is complete and testing can begin.

[0156] S422. DRAM updates the value of DRAM Vref.

[0157] S423, MC restores channel memory data access and waits for the stress test result. Generally, the stress test waiting time is configured to be 2s.

[0158] S424, CU reads the CRC error data (MR50) of the particle where the DQ of the MC memory channel is located. If there is a WRCRC count = 0, it means that the D is within the normal margin range, configure VrefDQ = VrefDQ+1, return to step S417, and continue scanning the boundary.

[0159] S425, CU reads the CRC error data (MR50) of the particle where the MC memory channel DQ is located. If there is a CRC count = 1, it means that the VrefDQ will cause abnormal DQ data reception. The scanning stops when the boundary is reached, and the right boundary scan ends.

[0160] S426. CU restores the DRAM TxVref value and writes it into MR10.

[0161] S427: The CU-side program triggers the MC to start the Tx SI parameter dynamic refresh function.

[0162] S428. MC starts to restore SI parameters, stops memory channel access requests, and notifies PHY to restore SI parameters.

[0163] S429. MC sends an instruction to DRAM to restore the value of DRAM Vref.

[0164] S430 , PHY receives the SI parameter recovery request from MC and recovers MR10 of DRAM particle, namely TxVref.

[0165] S431. DRAM restores the value of DRAM Vref.

[0166] S432, PHY notifies MC that the DRAM MR10 register update is complete.

[0167] S433, MC restores channel memory data access.

[0168] S434, CU clears the DRAM WRCRC count and writes into MR50.

[0169] S435. The CU generates a DQ scan test result, that is, the ECC result is a passed DRAM Vref interval range.

[0170] Refer to Figure 2 As shown in the schematic diagram of eye diagram generation, DQ Vref is replaced with DRAM Vref. According to the interval range of DQ Delay that passes the WRCRC result and the interval range of DRAM Vref that passes the WRCRC result, the eye diagram can be drawn, thereby realizing signal quality evaluation.

[0171] The embodiment of the present invention also provides an eye diagram scanning device, in the data reading direction, such as Fig.10 As shown, the device comprises:

[0172] The first test unit 11 is used to dynamically adjust the value of the physical layer interface delay through the memory controller under the same physical layer interface reference voltage after completing the memory training and starting to run the operating system service, perform a stress test, and obtain the interval range of the physical layer interface delay for which the ECC result is passed;

[0173] The second test unit 12 is used to dynamically adjust the value of the physical layer interface reference voltage through the memory controller under the same physical layer interface delay, perform stress testing, and obtain the interval range of the physical layer interface reference voltage for which the ECC result is passed;

[0174] The first generating unit 13 is used to generate a current eye diagram scanning result according to the interval range of the physical layer interface delay and the interval range of the physical layer interface reference voltage.

[0175] The eye diagram scanning device provided by the embodiment of the present invention can dynamically adjust the physical layer interface delay and the value of the physical layer interface reference voltage in the data reading direction through MC without interrupting the operating system business, and obtain the ECC result as the interval range of the passed physical layer interface reference voltage and the physical layer interface delay, and then obtain the real-time eye diagram result that truly reflects the system operation status, so as to confirm whether the memory is reliable under the current business according to the real-time eye diagram result, thereby ensuring the normal operation of the system business.

[0176] Optionally, the first testing unit 11 includes:

[0177] The first configuration module is used to start scanning of physical layer interface delay parameters and configure the scanning initial value of the physical layer interface delay;

[0178] The first trigger module is used to trigger the memory controller to dynamically adjust the value of the physical layer interface delay, so that the memory controller stops responding to the memory read and write request, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface delay; after the physical layer interface dynamically adjusts the value of the physical layer interface delay, the memory controller resumes responding to the memory read and write request;

[0179] The first test module is used to read the ECC data of the memory channel of the memory controller. If the ECC count is equal to 0, the physical layer interface delay is reduced by 1 / added by 1, and the first trigger module performs the above operation and continues to scan the boundary; if the ECC count is greater than 0, the scanning is stopped when the boundary is scanned, and the current physical layer interface delay, that is, the ECC result, is the minimum value / maximum value of the interval range of the passed physical layer interface delay.

[0180] Optionally, the second testing unit 12 includes:

[0181] The second configuration module is used to start scanning of the reference voltage parameters of the physical layer interface and configure the scanning initial value of the reference voltage of the physical layer interface;

[0182] A second trigger module is used to trigger the memory controller to dynamically adjust the value of the physical layer interface reference voltage, so that the memory controller stops responding to memory read and write requests, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface reference voltage; after the physical layer interface dynamically adjusts the value of the physical layer interface reference voltage, the memory controller resumes responding to the memory read and write requests;

[0183] The second test module is used to read the ECC data of the memory channel of the memory controller. If the ECC count is equal to 0, the physical layer interface reference voltage is reduced by 1 / added by 1, and the second trigger module performs the above operation and continues to scan the boundary; if the ECC count is greater than 0, the scanning is stopped when the boundary is scanned, and the current physical layer interface reference voltage, that is, the ECC result, is the minimum value / maximum value of the interval range of the passed physical layer interface reference voltage.

[0184] The device of this embodiment can be used to execute the technical solution of the method embodiment of the above data reading direction. Its implementation principle and technical effect are similar and will not be repeated here.

[0185] The embodiment of the present invention also provides another eye diagram scanning device, in the data writing direction, such as Fig.11 As shown, the device comprises:

[0186] The third test unit 21 is used for, after completing the memory training and starting to run the operating system service, the control unit dynamically adjusts the value of the physical layer interface delay through the memory controller under the same memory reference voltage, performs a stress test, and obtains the interval range of the physical layer interface delay for which the CRC result passes;

[0187] The fourth test unit 22 is used to dynamically adjust the value of the memory reference voltage on the physical layer interface and the memory through the memory controller under the same physical layer interface delay, perform a stress test, and obtain an interval range of the memory reference voltage for which the CRC result passes;

[0188] The second generating unit 23 is used to generate the current eye diagram scanning result according to the interval range of the physical layer interface delay and the interval range of the memory reference voltage.

[0189] The eye diagram scanning device provided by the embodiment of the present invention can dynamically adjust the physical layer interface delay and the memory reference voltage value in the data write direction through the memory controller without interrupting the operating system business, and obtain the CRC result as the interval range of the passed memory reference voltage and the physical layer interface delay, and then obtain the real-time eye diagram result that truly reflects the system operation status, so as to confirm whether the memory is reliable under the current business according to the real-time eye diagram result, thereby ensuring the normal operation of the system business.

[0190] Optionally, the third testing unit 21 includes:

[0191] The third configuration module is used to start scanning of physical layer interface delay parameters and configure the scanning initial value of the physical layer interface delay;

[0192] A third trigger module is used to trigger the memory controller to dynamically adjust the value of the physical layer interface delay, so that the memory controller stops responding to the memory read and write request, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface delay; after the physical layer interface dynamically adjusts the value of the physical layer interface delay, the memory controller resumes responding to the memory read and write request;

[0193] The third test module is used to read the CRC data of the memory channel of the memory controller. If the CRC count is equal to 0, the physical layer interface delay is reduced by 1 / added by 1, and the third trigger module performs the above operation and continues to scan the boundary; if the CRC count is greater than 0, the scanning is stopped when the boundary is scanned, and the current physical layer interface delay, that is, the CRC result, is the minimum value / maximum value of the passed physical layer interface delay interval range.

[0194] Optionally, the fourth testing unit 22 includes:

[0195] A fourth configuration module, used to start a memory reference voltage parameter scan and configure an initial value of the memory reference voltage scan;

[0196] A fourth trigger module is used to trigger the memory controller to dynamically adjust the value of the memory reference voltage on the physical layer interface and the memory, so that the memory controller stops responding to the memory read and write request, and sends an instruction to the physical layer interface and the memory to dynamically adjust the value of the memory reference voltage; after the physical layer interface and the memory dynamically adjust the value of the memory reference voltage, the memory controller resumes responding to the memory read and write request;

[0197] The fourth test module is used to read the CRC data of the memory channel of the memory controller. If the CRC count is equal to 0, the memory reference voltage is reduced by 1 / added by 1, and the fourth trigger module performs the above operation and continues to scan the boundary; if the CRC count is greater than 0, the scanning is stopped when the boundary is scanned, and the current memory reference voltage, that is, the CRC result, is the minimum value / maximum value of the interval range of the passed memory reference voltage.

[0198] The device of this embodiment can be used to execute the technical solution of the method embodiment of the above data writing direction. Its implementation principle and technical effect are similar and will not be repeated here.

[0199] An embodiment of the present invention further provides a control unit, which includes the eye pattern scanning device described in the above embodiment.

[0200] An embodiment of the present invention further provides a system on chip, which includes the control unit described in the above embodiment, a memory controller connected to the control unit, and a DDR PHY interface of the memory controller.

[0201] An embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, and when the computer instructions are executed by a processor, the eye diagram scanning method described in the above embodiment is implemented.

[0202] Those skilled in the art can understand that all or part of the processes in the above method embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes in the above method embodiments. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0203] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. An eye diagram scanning method, characterized in that: In the data reading direction, the method includes: After completing the memory training and starting to run the operating system business, the control unit dynamically adjusts the value of the physical layer interface delay through the memory controller under the same physical layer interface reference voltage, performs a stress test, and obtains the range of the physical layer interface delay for which the error check and correction ECC result passes; The control unit dynamically adjusts the value of the physical layer interface reference voltage through the memory controller under the same physical layer interface delay, performs a stress test, and obtains an interval range of the physical layer interface reference voltage for which the ECC result passes; The control unit generates a current eye diagram scanning result according to the interval range of the physical layer interface delay and the interval range of the physical layer interface reference voltage.

2. The method according to claim 1, characterized in that The control unit dynamically adjusts the value of the physical layer interface delay through the memory controller under the same physical layer interface reference voltage to perform a stress test, and the range of the physical layer interface delay for which the ECC result is passed includes: S1, the control unit starts scanning the physical layer interface delay parameters and configures the initial value of the physical layer interface delay scan; S2, the control unit triggers the memory controller to dynamically adjust the value of the physical layer interface delay, the memory controller stops responding to the memory read and write requests, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface delay; after the physical layer interface dynamically adjusts the value of the physical layer interface delay, the memory controller resumes responding to the memory read and write requests; S3. The control unit reads the ECC data of the memory channel of the memory controller. If the ECC count is equal to 0, the physical layer interface delay is reduced by 1 / added by 1, and the process returns to step S2 to continue scanning the boundary. If the ECC count is greater than 0, the scanning is stopped when the boundary is scanned. The current physical layer interface delay, i.e., the ECC result, is the minimum / maximum value of the range of the passed physical layer interface delay.

3. The method according to claim 1, characterized in that The control unit dynamically adjusts the value of the physical layer interface reference voltage through the memory controller under the same physical layer interface delay to perform a stress test, and the range of the physical layer interface reference voltage for which the ECC result is passed includes: T1, the control unit starts scanning the physical layer interface reference voltage parameters and configures the scanning initial value of the physical layer interface reference voltage; T2, the control unit triggers the memory controller to dynamically adjust the value of the physical layer interface reference voltage, the memory controller stops responding to memory read and write requests, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface reference voltage; after the physical layer interface dynamically adjusts the value of the physical layer interface reference voltage, the memory controller resumes responding to memory read and write requests; T3. The control unit reads the ECC data of the memory channel of the memory controller. If the ECC count is equal to 0, the physical layer interface reference voltage is reduced by 1 / added by 1, and the process returns to step T2 to continue scanning the boundary. If the ECC count is greater than 0, the scanning stops when the boundary is reached. The current physical layer interface reference voltage, i.e., the ECC result, is the minimum / maximum value of the range of the passed physical layer interface reference voltage.

4. An eye diagram scanning method, characterized in that: In the data writing direction, the method comprises: After completing the memory training and starting to run the operating system service, the control unit dynamically adjusts the value of the physical layer interface delay through the memory controller under the same memory reference voltage, performs a stress test, and obtains the interval range of the physical layer interface delay for which the cyclic redundancy check CRC result passes; The control unit dynamically adjusts the value of the memory reference voltage on the physical layer interface and the memory through the memory controller under the same physical layer interface delay, performs a stress test, and obtains the interval range of the memory reference voltage for which the CRC result passes; The control unit generates a current eye diagram scanning result according to the interval range of the physical layer interface delay and the interval range of the memory reference voltage.

5. The method according to claim 4, characterized in that The control unit dynamically adjusts the value of the physical layer interface delay through the memory controller under the same memory reference voltage to perform a stress test, and the interval range of the physical layer interface delay for which the CRC result is passed includes: M1. The control unit starts scanning the physical layer interface delay parameters and configures the initial value of the physical layer interface delay scan; M2. The control unit triggers the memory controller to dynamically adjust the value of the physical layer interface delay, the memory controller stops responding to the memory read and write requests, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface delay; after the physical layer interface dynamically adjusts the value of the physical layer interface delay, the memory controller resumes responding to the memory read and write requests; M3. The control unit reads the CRC data of the memory channel of the memory controller. If the CRC count is equal to 0, the physical layer interface delay is reduced by 1 / added by 1, and the process returns to step M2 to continue scanning the boundary. If the CRC count is greater than 0, the scanning is stopped when the boundary is scanned. The current physical layer interface delay, i.e., the CRC result, is the minimum / maximum value of the range of the passed physical layer interface delay.

6. The method according to claim 4, characterized in that The control unit dynamically adjusts the value of the memory reference voltage on the physical layer interface and the memory through the memory controller under the same physical layer interface delay, performs a stress test, and obtains a memory reference voltage interval range with a CRC result of passing, including: N1. The control unit starts scanning the memory reference voltage parameters and configures the initial value of the memory reference voltage scan; N2. The control unit triggers the memory controller to dynamically adjust the value of the memory reference voltage on the physical layer interface and the memory, the memory controller stops responding to the memory read and write requests, and sends an instruction to the physical layer interface and the memory to dynamically adjust the value of the memory reference voltage; after the physical layer interface and the memory dynamically adjust the value of the memory reference voltage, the memory controller resumes responding to the memory read and write requests; N3. The control unit reads the CRC data of the memory channel of the memory controller. If the CRC count is equal to 0, the memory reference voltage is reduced by 1 / added by 1, and the process returns to step N2 to continue scanning the boundary. If the CRC count is greater than 0, the scanning is stopped when the boundary is reached. The current memory reference voltage, i.e., the CRC result, is the minimum value / maximum value of the passed memory reference voltage interval.

7. An eye pattern scanning device, characterized in that: In the data reading direction, the device comprises: The first test unit is used to dynamically adjust the value of the physical layer interface delay through the memory controller under the same physical layer interface reference voltage after completing the memory training and starting to run the operating system business, perform a stress test, and obtain the interval range of the physical layer interface delay for which the ECC result is passed; The second test unit is used to dynamically adjust the value of the physical layer interface reference voltage through the memory controller under the same physical layer interface delay, perform stress testing, and obtain the interval range of the physical layer interface reference voltage for which the ECC result is passed; The first generating unit is used to generate a current eye diagram scanning result according to the interval range of the physical layer interface delay and the interval range of the physical layer interface reference voltage.

8. The device according to claim 7, characterized in that The first testing unit comprises: The first configuration module is used to start scanning of physical layer interface delay parameters and configure the scanning initial value of the physical layer interface delay; The first trigger module is used to trigger the memory controller to dynamically adjust the value of the physical layer interface delay, so that the memory controller stops responding to the memory read and write request, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface delay; after the physical layer interface dynamically adjusts the value of the physical layer interface delay, the memory controller resumes responding to the memory read and write request; The first test module is used to read the ECC data of the memory channel of the memory controller. If the ECC count is equal to 0, the physical layer interface delay is reduced by 1 / added by 1, and the first trigger module performs the above operation and continues to scan the boundary; if the ECC count is greater than 0, the scanning is stopped when the boundary is scanned, and the current physical layer interface delay, that is, the ECC result, is the minimum value / maximum value of the interval range of the passed physical layer interface delay.

9. The device according to claim 7, characterized in that The second test unit comprises: The second configuration module is used to start scanning of the reference voltage parameters of the physical layer interface and configure the scanning initial value of the reference voltage of the physical layer interface; A second trigger module is used to trigger the memory controller to dynamically adjust the value of the physical layer interface reference voltage, so that the memory controller stops responding to memory read and write requests, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface reference voltage; after the physical layer interface dynamically adjusts the value of the physical layer interface reference voltage, the memory controller resumes responding to the memory read and write requests; The second test module is used to read the ECC data of the memory channel of the memory controller. If the ECC count is equal to 0, the physical layer interface reference voltage is reduced by 1 / added by 1, and the second trigger module performs the above operation and continues to scan the boundary; if the ECC count is greater than 0, the scanning is stopped when the boundary is scanned, and the current physical layer interface reference voltage, that is, the ECC result, is the minimum value / maximum value of the interval range of the passed physical layer interface reference voltage.

10. An eye pattern scanning device, characterized in that: In the data writing direction, the device comprises: The third test unit is used for, after completing the memory training and starting to run the operating system service, the control unit dynamically adjusts the value of the physical layer interface delay through the memory controller under the same memory reference voltage, performs a stress test, and obtains the interval range of the physical layer interface delay for which the CRC result passes; A fourth test unit is used to dynamically adjust the value of the memory reference voltage on the physical layer interface and the memory through the memory controller under the same physical layer interface delay, perform a stress test, and obtain an interval range of the memory reference voltage for which the CRC result passes; The second generating unit is used to generate the current eye diagram scanning result according to the interval range of the physical layer interface delay and the interval range of the memory reference voltage.

11. The device according to claim 10, characterized in that The third test unit comprises: The third configuration module is used to start scanning of physical layer interface delay parameters and configure the scanning initial value of the physical layer interface delay; A third trigger module is used to trigger the memory controller to dynamically adjust the value of the physical layer interface delay, so that the memory controller stops responding to the memory read and write request, and notifies the physical layer interface to dynamically adjust the value of the physical layer interface delay; after the physical layer interface dynamically adjusts the value of the physical layer interface delay, the memory controller resumes responding to the memory read and write request; The third test module is used to read the CRC data of the memory channel of the memory controller. If the CRC count is equal to 0, the physical layer interface delay is reduced by 1 / added by 1, and the third trigger module performs the above operation and continues to scan the boundary; if the CRC count is greater than 0, the scanning is stopped when the boundary is scanned, and the current physical layer interface delay, that is, the CRC result, is the minimum value / maximum value of the passed physical layer interface delay interval range.

12. The device according to claim 10, characterized in that The fourth test unit comprises: A fourth configuration module, used to start a memory reference voltage parameter scan and configure an initial value of the memory reference voltage scan; A fourth trigger module is used to trigger the memory controller to dynamically adjust the value of the memory reference voltage on the physical layer interface and the memory, so that the memory controller stops responding to the memory read and write request, and sends an instruction to the physical layer interface and the memory to dynamically adjust the value of the memory reference voltage; after the physical layer interface and the memory dynamically adjust the value of the memory reference voltage, the memory controller resumes responding to the memory read and write request; The fourth test module is used to read the CRC data of the memory channel of the memory controller. If the CRC count is equal to 0, the memory reference voltage is reduced by 1 / added by 1, and the fourth trigger module performs the above operation and continues to scan the boundary; if the CRC count is greater than 0, the scanning is stopped when the boundary is scanned, and the current memory reference voltage, that is, the CRC result, is the minimum value / maximum value of the interval range of the passed memory reference voltage.

13. A control unit, characterized in that: The control unit comprises a device as claimed in any one of claims 7-12.

14. A system on chip, characterized in that: The system on chip comprises the control unit as claimed in claim 13, a memory controller connected to the control unit, and a physical layer interface of the memory controller.

15. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and when the computer instructions are executed by a processor, the method according to any one of claims 1 to 6 is implemented.

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