Method for testing multi-core synchronization performance of chip of flash memory controller

Abstract

A method for testing multi-core synchronization performance of a flash memory controller chip relates to the technical field of flash memories, and adopts a mode that a plurality of test cores send commands to a flash memory controller drive core (rear end core) according to a certain synchronization mechanism to replace a mode that a single test core sends commands, so that the pressure density of test excitation can be improved; errors caused by insufficient computing power of the processor in the test process of performance indexes such as 4K random reading are reduced, and when test program firmware runs on a plurality of processor cores, the problem of insufficient pressure of a single core can be relieved.

Description

Technical Field

[0001] The present invention relates to the field of flash memory technology, and in particular to a method for testing the multi-core synchronization performance of a flash memory controller chip. Background Art

[0002] Flash controller chip refers to the main control chip of solid-state storage (SSD) and other devices that rely on flash memory particles as storage media. It usually includes a flash read and write channel driver that interacts with flash memory particles and a physical layer interface for the transmission of commands and data. Multiple embedded processor cores serve as the operating platform for firmware. In addition, there are SRAM / DRAM memory controllers and other hardware acceleration module peripherals. The performance test of the flash controller chip is mainly to check whether the read and write rate of the flash controller chip to the flash memory particles meets the design indicators. It needs to generate or transmit test stimuli (flash read and write command sequences) by the firmware running in the processor. In some test cases, the density and pressure of the stimuli are relatively large (a large number of commands are sent in a short period of time, such as 4K read scenarios), which requires high processor computing power. Summary of the invention

[0003] In order to overcome the deficiencies of the above technologies, the present invention provides a flash memory controller chip multi-core synchronization performance testing method that can alleviate the problem of insufficient pressure on a single core when a test program firmware runs on multiple processor cores.

[0004] The technical solution adopted by the present invention to overcome the technical problems is: A method for testing multi-core synchronization performance of a flash memory controller chip, comprising: S1. Multi-core flash memory controller SoC chip The processor core is used as the back-end core to run the flash controller driver, and the other cores of the multi-core flash controller SoC chip are The processor cores are used as test cores to run the flash memory performance test program. is the number of processor cores of the multi-core flash controller SoC chip; S2. The flash memory control chip is powered on, and one of the test cores is used as the main test core. The main test core initializes the multi-core synchronization test information, and the other test cores are in a waiting state. The multi-core synchronization test information is a set of sequentially arranged global structures. Each test core corresponds to a global structure. The content of the global structure includes the synchronization test start flag of the current test core, the timestamp of the synchronization test start, the synchronization test end flag, the timestamp of the synchronization test end, the test command type, and the data volume; S3. After the test core and the backend core are started and ready, the host computer transmits a test command to the multi-core flash controller SoC chip; S4. After the multi-core flash memory controller SoC chip receives the test command sent by the host computer, the main test core forwards the test command to each test core designated to participate in the multi-core synchronous test; S5. After receiving the test command, the test core generates a flash memory read and write test command sequence; S6. After the flash read and write test command sequence is prepared, each test core polls the synchronization test start flag of the corresponding global structure to detect whether the synchronization test start flag of other test cores is set; S7. When the synchronous test start flags of all test cores are set, all test cores are resumed from the waiting state. If the waiting time of the test core during polling detection exceeds the preset timeout threshold and the synchronous test start flags of all test cores are not set, each test core ends the waiting state; S8. Each test core independently sends a flash memory read and write command to the corresponding backend core.

[0005] Furthermore, the flash memory performance test program in step S1 is a firmware running on the flash memory controller SoC chip for testing the performance of the flash memory controller hardware and its driver.

[0006] Furthermore, in step S1, the flash memory performance test program receives test instructions and parameter texts in the form of character strings through the serial port, and parses the test instructions and parameter texts into test stimuli for the flash memory driver, wherein the test stimuli are read, write or erase commands.

[0007] Furthermore, in step S1, each backend core is independent of each other, each test core corresponds to a backend core, and the test core generates a test stimulus for the flash controller channel controlled by the corresponding backend core, and sends the generated test stimulus to the corresponding backend core for execution through the inter-core message pipeline.

[0008] Furthermore, in step S2, the method for the main test core to initialize the multi-core synchronous test information is: S2-1. Define a memory space accessible to all test cores within the addressable range of the multi-core flash controller SoC chip; S2-2. Establish multi-core synchronization test information.

[0009] Furthermore, each test core starts to run independently after detecting that the content of the multi-core synchronous test information is valid. Each structure in the multi-core synchronous test information is maintained by the corresponding test core, and all test cores can query and read the data in the structure.

[0010] Furthermore, in step S3, the host computer transmits a test command in the form of a string to the multi-core flash controller SoC chip through the serial port. The test command includes the flash physical address, read and write data memory address, data volume, synchronization bit mask, and output core number.

[0011] Furthermore, in step S4, the main test core uses a text parsing program to forward the test command to each test core designated to participate in the multi-core synchronization test according to the synchronization bit mask in the test command.

[0012] Furthermore, in step S7, after all test cores resume operation from the waiting state, the timestamp of the start of the synchronization test, the test command type, and the data volume are recorded and stored in the global structure corresponding to each test core.

[0013] Furthermore, in step S7, after each test core ends the waiting state, the multi-core synchronization test information is reset, and a timeout exception is output and output to the serial port in the form of a log.

[0014] The beneficial effects of the present invention are as follows: the flash controller multi-core synchronization performance test method does not rely on the operating system and hardware mutex mechanisms, has strong versatility and is easy to deploy and implement on different platforms, and can be applied to most flash controller SoC chips with multi-processor cores to overcome the problem of insufficient test pressure caused by software computing power when a single processor is used as a test core. Moreover, it has relatively little additional overhead on storage resources. The basic space occupied by each test core attribute structure in the multi-core synchronization test information is only tens of bytes, and it has certain scalability. In addition to basic attributes such as command type and total amount of test data, other information can be added and expanded. In addition, the test method receives and parses the test command control parameters from the host computer in the form of text characters through a serial port or other debugging interface. The interactive method is simple and convenient, and does not require the participation of complex front-end communication protocols and flash conversion layer algorithms. It can eliminate the interference of other external factors on the performance results, and more directly and accurately reflect the read and write performance level of the flash memory particles and their controllers. DETAILED DESCRIPTION

[0015] The present invention is further described below.

[0016] A method for testing multi-core synchronization performance of a flash memory controller chip, comprising: S1. Place the multi-core flash controller SoC chip (system on chip) The processor core is used as the back-end core to run the flash controller driver, and the other cores of the multi-core flash controller SoC chip are The processor cores are used as test cores to run the flash memory performance test program. The number of processor cores of the multi-core flash controller SoC chip. Large-capacity flash controller SoC chips usually have multiple processor cores, and each processor core executes its own business logic code to increase the parallelism of the flash controller system. (For example, 8 processor cores, 4 of which are back-end business cores, responsible for interacting with the flash drive module and Nand storage particles; the other 4 are front-end and algorithm business cores, responsible for receiving read and write IO commands from the host computer and mapping the logical address of the read and write data block to the physical address of the flash particle).

[0017] S2. The flash memory control chip is powered on, and one of the test cores is used as the main test core. The main test core initializes the multi-core synchronization test information, and the other test cores are in a waiting state. The multi-core synchronization test information is a set of sequentially arranged global structures. Each test core corresponds to a global structure. The content of the global structure includes the synchronization test start flag of the current test core, the timestamp of the synchronization test start, the synchronization test end flag, the timestamp of the synchronization test end, the test command type, and the data volume.

[0018] S3. After the test core and the backend core are started and ready, the host computer transmits a test command to the multi-core flash memory controller SoC chip.

[0019] S4. After the multi-core flash memory controller SoC chip receives the test command sent by the host computer, the main test core forwards the test command to each test core designated to participate in the multi-core synchronous test.

[0020] S5. After receiving the test command, the test core generates a flash memory read and write test command sequence.

[0021] S6. After the flash memory read and write test command sequence is prepared, each test core polls the synchronous test start flag of its corresponding global structure to detect whether the synchronous test start flag of other test cores is set.

[0022] S7. When the synchronous test start flags of all test cores are set, all test cores are resumed from the waiting state. If the waiting time of the test core during polling detection exceeds the preset timeout threshold and the synchronous test start flags of all test cores are not set, each test core ends the waiting state.

[0023] S8. Each test core independently sends a flash memory read and write command to the corresponding backend core.

[0024] When a test core completes the task of sending all its own command sequences, it will set its own synchronization test end flag and record the timestamp of the core's end test time. Then the test core will enter the waiting state and poll to detect whether the synchronization test end flags of other test cores are set. After the synchronization test end flags of all participating test cores are set, each test core will resume operation from the blocked waiting state. The test core corresponding to the output core number parameter will retrieve the data volume, start and end time and other information of each test core in the multi-core synchronization test information, calculate the total amount of flash read and write command data generated by each test core, use the timestamp of the latest ended test core to calculate the duration of the synchronization test process and then calculate the read and write rate of the multi-core concurrent test, and then output the performance data in the form of logs through the serial port or other debugging interface. After the multi-core synchronization test process is completed, each test core will reset the corresponding structure content in the multi-core synchronization test information for the next test.

[0025] In one embodiment of the present invention, the flash memory performance test program in step S1 is a firmware running on a flash memory controller SoC chip for testing the performance of the flash memory controller hardware and its driver.

[0026] In one embodiment of the present invention, in step S1, the flash memory performance test program receives the test instruction and parameter text in the form of a string through the serial port, and parses the test instruction and parameter text into a test stimulus for the flash memory driver, wherein the test stimulus is a read, write or erase command, thereby replacing the complex firmware running on the front end and the algorithm business core to achieve the purpose of fast and direct testing of the flash memory read and write performance.

[0027] In one embodiment of the present invention, the backend cores in step S1 are independent of each other, each test core corresponds to a backend core, the test core generates a test stimulus for the flash controller channel controlled by the corresponding backend core, and sends the generated test stimulus to the corresponding backend core for execution through the inter-core message pipeline.

[0028] In one embodiment of the present invention, in step S2, the method for the main test core to initialize the multi-core synchronization test information is: S2-1. Define a memory space accessible to all test cores within the addressable range of the multi-core flash controller SoC chip.

[0029] S2-2. Establish multi-core synchronization test information.

[0030] In one embodiment of the present invention, each test core starts to run independently after detecting that the content of the multi-core synchronous test information is valid. Each structure in the multi-core synchronous test information is maintained by the corresponding test core, and all test cores can query and read the data in the structure.

[0031] In one embodiment of the present invention, in step S3, the host computer transmits a test command in the form of a string to the multi-core flash memory controller SoC chip through a serial port, and the test command includes a flash memory physical address, a read / write data memory address, a data amount, a synchronization bit mask, and an output core number. The synchronization bit mask specifies which test cores participate in the synchronization test in the form of a binary bitmap (for example, if there are 4 test cores from 0 to 3, 0111 means that cores 0, 1, and 2 execute the performance test program synchronously, and core 3 does not participate).

[0032] In one embodiment of the present invention, in step S4, the main test core uses a text parsing program to forward the test command to each test core designated to participate in the multi-core synchronization test according to the synchronization bit mask in the test command.

[0033] In one embodiment of the present invention, in step S7, after all test cores resume operation from the waiting state, the timestamp of the start of the synchronization test, the test command type, and the data volume are recorded and stored in the global structure corresponding to each test core.

[0034] In one embodiment of the present invention, in step S7, after each test core ends the waiting state, the multi-core synchronization test information is reset, and a timeout exception is output and output to the serial port in the form of a log.

[0035] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A flash memory controller chip multi-core synchronization performance test method, characterized in that: include: S1. Multi-core flash memory controller SoC chip The processor core is used as the back-end core to run the flash controller driver, and the other cores of the multi-core flash controller SoC chip are The processor cores are used as test cores to run the flash memory performance test program. is the number of processor cores of the multi-core flash controller SoC chip; S2. The flash memory control chip is powered on, and one of the test cores is used as the main test core. The main test core initializes the multi-core synchronization test information, and the other test cores are in a waiting state. The multi-core synchronization test information is a set of sequentially arranged global structures. Each test core corresponds to a global structure. The content of the global structure includes the synchronization test start flag of the current test core, the timestamp of the synchronization test start, the synchronization test end flag, the timestamp of the synchronization test end, the test command type, and the data volume; S3. After the test core and the backend core are started and ready, the host computer transmits a test command to the multi-core flash controller SoC chip; S4. After the multi-core flash memory controller SoC chip receives the test command sent by the host computer, the main test core forwards the test command to each test core designated to participate in the multi-core synchronous test; S5. After receiving the test command, the test core generates a flash memory read and write test command sequence; S6. After the flash read and write test command sequence is prepared, each test core polls the synchronization test start flag of the corresponding global structure to detect whether the synchronization test start flag of other test cores is set; S7. When the synchronous test start flags of all test cores are set, all test cores are resumed from the waiting state. If the waiting time of the test core during polling detection exceeds the preset timeout threshold and the synchronous test start flags of all test cores are not set, each test core ends the waiting state; S8. Each test core independently sends a flash memory read and write command to the corresponding backend core.

2. The flash memory controller chip multi-core synchronization performance testing method according to claim 1, characterized in that: The flash memory performance test program in step S1 is a firmware running on the flash memory controller SoC chip and used to test the performance of the flash memory controller hardware and its driver.

3. The flash memory controller chip multi-core synchronization performance testing method according to claim 1, characterized in that: In step S1, the flash memory performance test program receives test instructions and parameter texts in the form of character strings through a serial port, and parses the test instructions and parameter texts into test stimuli for the flash memory driver, wherein the test stimuli are read, write or erase commands.

4. The flash memory controller chip multi-core synchronization performance testing method according to claim 1, characterized in that: In step S1, each backend core is independent of each other, and each test core corresponds to a backend core. The test core generates a test stimulus for the flash controller channel controlled by the corresponding backend core, and sends the generated test stimulus to the corresponding backend core for execution through the inter-core message pipeline.

5. The flash memory controller chip multi-core synchronization performance testing method according to claim 1, characterized in that: In step S2, the method for the main test core to initialize the multi-core synchronous test information is: S2-1. Define a memory space accessible to all test cores within the addressable range of the multi-core flash controller SoC chip; S2-2. Establish multi-core synchronization test information.

6. The flash memory controller chip multi-core synchronization performance testing method according to claim 5, characterized in that: Each test core starts to run independently after detecting that the content of the multi-core synchronization test information is valid. Each structure in the multi-core synchronization test information is maintained by the corresponding test core, and all test cores can query and read the data in the structure.

7. The flash memory controller chip multi-core synchronization performance testing method according to claim 1, characterized in that: In step S3, the host computer transmits a test command in the form of a string to the multi-core flash memory controller SoC chip through the serial port. The test command includes the flash memory physical address, read and write data memory address, data volume, synchronization bit mask, and output core number.

8. The flash memory controller chip multi-core synchronization performance testing method according to claim 7, characterized in that: In step S4, the main test core uses a text parsing program to forward the test command to each test core designated to participate in the multi-core synchronization test according to the synchronization bit mask in the test command.

9. The flash memory controller chip multi-core synchronization performance testing method according to claim 7, characterized in that: In step S7, after all test cores resume operation from the waiting state, the timestamp of the start of the synchronization test, the test command type, and the data volume are recorded and stored in the global structure corresponding to each test core.

10. The flash memory controller chip multi-core synchronization performance testing method according to claim 7, characterized in that: In step S7, after each test core ends the waiting state, the multi-core synchronization test information is reset, and a timeout exception is output and output to the serial port in the form of a log.

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