Capacitor and preparation method thereof, circuit board assembly and preparation method thereof, and electronic equipment

Abstract

The embodiment of the invention provides a capacitor and a preparation method thereof, a circuit board assembly and a preparation method thereof, and electronic equipment, relates to the technical field of electronics, and is used for reducing the influence of capacitor vibration on a circuit board. The capacitor comprises a capacitor body and a first electrode; two opposite ends of the capacitor body are respectively provided with a first electrode; the capacitor body comprises a plurality of dielectric layers and a plurality of second electrodes; the multiple dielectric layers are stacked; any surface of the capacitor body can be provided with a mark pattern. Therefore, when the capacitor is bonded with the circuit board, the second electrode can be ensured to be perpendicular to the circuit board by identifying the mark pattern, so that the howling problem is reduced or eliminated.

Description

Technical Field

[0001] The present application relates to the field of electronic technology, and in particular to a capacitor and a preparation method thereof, a circuit board assembly and a preparation method thereof, and an electronic device. Background Art

[0002] Multi-layer ceramic capacitors (MLCC) are one of the main passive chip components in electronic devices due to their high reliability, high precision, high frequency, low power consumption, large capacity, miniaturization and low cost.

[0003] Mainstream MLCCs include stacked dielectric layers and electrodes arranged between adjacent dielectric layers. The dielectric layers are mainly made of ferroelectric materials. During use, due to the strong electrostrictive properties of ferroelectric materials, after an AC voltage is applied to the MLCC, the dielectric layer will expand and contract in the stacking direction, causing the MLCC to vibrate. The vibration of the MLCC will cause the circuit board carrying the MLCC to resonate, causing the circuit board to vibrate, bend, break leads, disconnect couplings, and other problems, thereby affecting the performance of the entire device. Summary of the invention

[0004] Embodiments of the present application provide a capacitor and a manufacturing method thereof, a circuit board assembly and a manufacturing method thereof, and an electronic device, which are used to reduce the influence of capacitor vibration on the circuit board.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions:

[0006] In a first aspect of an embodiment of the present application, a capacitor is provided, and the capacitor may be, for example, a chip-type multilayer ceramic capacitor. A capacitor body and a first electrode; the first electrodes are respectively arranged at opposite ends of the capacitor body; the capacitor body includes multiple dielectric layers and multiple second electrodes; the multiple dielectric layers are stacked; the second electrode is arranged between two adjacent dielectric layers, the two adjacent layers of second electrodes are staggered, and the two adjacent layers of second electrodes are coupled to the first electrodes at different ends; wherein the capacitor body includes a marking surface, and the marking surface is provided with a marking pattern. .

[0007] The capacitor provided in the embodiment of the present application has a marking pattern on the marking surface of the capacitor body. When the capacitor is bonded to the circuit board, the capacitor can be placed in the expected position by identifying the marking pattern so that the plane where the second electrode is located intersects with the circuit board (for example, vertically). In this way, even when an electric field is applied to the first electrode, the dielectric layer expands in a direction perpendicular to the second electrode to generate a first stress, and shrinks in a direction parallel to the second electrode to generate a second stress. The combined force of the first stress and the second stress is the stress on the circuit board. However, the direction of the first stress (large stress) changes from being perpendicular to the circuit board to being parallel to the circuit board, and the angle between the final synthesized stress and the circuit board is an acute angle, so the lever arm will be reduced. Therefore, although the capacitor still vibrates during operation. However, when the stress remains unchanged, the lever arm is reduced, and the torque (torque equals force * lever arm) can be reduced, thereby reducing the impact of capacitor vibration on the circuit board to improve problems such as howling.

[0008] In a possible implementation, the capacitor body includes a first surface and a second surface that are arranged opposite to each other, the plane where the first surface is located intersects with the plane where the second electrode is located; a first distance from the second electrode to the first surface is not equal to a second distance from the second electrode to the second surface. The first distance may be greater than the second distance, or the first distance may be less than the second distance.

[0009] By designing the second electrode to be non-centered, when the capacitor is bonded to the circuit board, the surface of the capacitor with a large margin faces the circuit board, which can increase the transmission distance of the stress generated by the vibration of the capacitor to the circuit board. In the process of stress transmission to the circuit board, the dielectric layer can consume the stress to reduce the magnitude of the stress transmitted to the circuit board. Moreover, the capacitor provided in the embodiment of the present application increases the distance from the capacitor to the circuit board through its own dielectric layer. On the one hand, the thickness of the dielectric layer hardly decreases with the vibration of the capacitor, so the possibility of the howling gradually worsening with the increase of the applicable time is relatively small, and the improvement effect on the howling problem can be guaranteed. On the other hand, there is no need to set other structures externally, which can simplify the structure of the circuit board assembly and improve the bonding reliability of the capacitor and the circuit board.

[0010] In a possible implementation, the first surface or the second surface is a marking surface. The marking surface is selected as the surface intersecting with the second electrode, so that the large distance surface and the small distance surface can be distinguished to ensure that when the capacitor is bonded to the circuit board, the large distance surface is arranged toward the circuit board.

[0011] In a possible implementation, the plane where the marking surface is located intersects with the plane where the first surface is located; the marking pattern is used to indicate the first surface or the second surface. In this way, when the capacitor is bonded to the circuit board, the first surface or the second surface can be determined by the marking pattern, thereby ensuring that the second electrode is perpendicular to the circuit board to reduce or eliminate the howling problem.

[0012] In a possible implementation, the difference between the first distance and the second distance is 20um-150um. Since the stress loss on the capacitor is increased by increasing the second distance in the embodiment of the present application, the size of the second distance can be less than 150um, which is conducive to reducing the thickness from the first surface of the capacitor to the circuit board and meeting the demand for thinness.

[0013] In a possible implementation, the first electrode includes a first conductive layer and a second conductive layer; the first conductive layer is arranged close to the capacitor body relative to the second conductive layer, and the toughness of the first conductive layer is greater than the toughness of the second conductive layer. By arranging the first conductive layer with greater toughness in the first electrode, when the dielectric layer applies a second stress in a direction parallel to the second electrode to the circuit board, the second stress can be buffered and borne by the first conductive layer first, and when the second stress exceeds the deformation limit of the first conductive layer, the remaining stress will be transmitted to the circuit board, which can reduce the stress transmitted to the circuit board by the inverse piezoelectric effect of the capacitor, and the howling problem can be improved after the stress on the circuit board is reduced.

[0014] In a possible implementation, the material of the first conductive layer includes silver, which is a conductive layer material with mature technology.

[0015] In a possible implementation, the material of the marking pattern is a dielectric material. In this way, after the capacitor is applied to an electronic device, the marking pattern can be prevented from generating parasitic capacitance or conducting electricity.

[0016] In a possible implementation, the first electrode includes a side surface, the plane where the side surface is located intersects with the capacitor body, and the shape of the side surface is a positive direction. The capacitor in the embodiment of the present application can be applicable to a capacitor with a square side surface.

[0017] A second aspect of an embodiment of the present application provides a circuit board assembly, comprising: a circuit board and a capacitor, wherein the capacitor is arranged on the circuit board, and a plane where a second electrode of the capacitor is located intersects with the circuit board; the capacitor comprises any capacitor of the first aspect.

[0018] The circuit board assembly provided in the second aspect of the embodiment of the present application includes the capacitor of the first aspect, and its beneficial effects are the same as those of the capacitor, which will not be repeated here.

[0019] In a possible implementation, the surface of the first surface and the second surface of the capacitor that is far from the second electrode is arranged toward the circuit board. The surface of the capacitor with a large margin faces the circuit board, which can increase the transmission distance of the stress generated by the vibration of the capacitor to the circuit board. In the process of stress transmission to the circuit board, the dielectric layer can lose the stress to reduce the magnitude of the stress transmitted to the circuit board.

[0020] According to a third aspect of an embodiment of the present application, an electronic device is provided, comprising: a housing and a circuit board assembly, wherein the circuit board assembly is disposed in the housing; the circuit board assembly comprises the circuit board assembly of the second aspect.

[0021] According to a fourth aspect of an embodiment of the present application, an electronic device is provided, comprising: a housing and a capacitor, wherein the capacitor is disposed in the housing; the capacitor comprises the capacitor of any one of the first aspects.

[0022] In a fifth aspect of the embodiments of the present application, a method for preparing a capacitor includes: forming a capacitor body stack, the capacitor body stack includes a plurality of dielectric films with a second electrode formed on the surface; cutting the capacitor body stack to form a plurality of capacitor bodies; forming a marking pattern on the marking surface of the capacitor body, the plane where the marking surface is located intersects with the plane where the end surface of the capacitor body to be covered with the first electrode is located; forming a first electrode at both ends of the capacitor body to form a capacitor. The beneficial effects of the capacitor preparation method provided in the embodiments of the present application are the same as the beneficial effects of the capacitor, and will not be repeated here.

[0023] In a possible implementation, forming a capacitor body stack includes: forming a dielectric film; printing a second electrode on the surface of the dielectric film; the distances from the second electrode to two opposite edges of the dielectric film are not equal, and both edges intersect with the plane where the end surface is located. In this way, the capacitor body finally formed includes a first surface and / or a second surface arranged oppositely, the first surface intersects with the second electrode; the first distance from the second electrode to the first surface is not equal to the second distance from the second electrode to the second surface.

[0024] In a possible implementation, the plane where the marking surface is located intersects with the plane where the second electrode is located. In other words, the first surface or the second surface of the capacitor body is the marking surface.

[0025] In a possible implementation, the plane where the marking surface is located is parallel to the plane where the second electrode is located; and the marking pattern is used to indicate the surfaces where the two edges are located. That is, the marking surface of the capacitor body is not the first surface or the second surface.

[0026] In a possible implementation, the preparation method further includes: identifying the marking pattern, positioning the capacitor according to a preset rule, and taping the capacitor.

[0027] In a possible implementation, forming a marking pattern on the marking surface of the capacitor body includes: using a coding process or a laser engraving process to form the marking pattern on the marking surface.

[0028] In a sixth aspect of the embodiments of the present application, a method for preparing a circuit board assembly is provided, comprising: obtaining a capacitor according to any one of the first aspects; identifying a marking pattern of the capacitor, and bonding the capacitor to a circuit board in a preset position to form a circuit board assembly; wherein the plane where the second electrode of the capacitor is located intersects with the circuit board. The beneficial effects of the method for preparing a circuit board assembly provided in the embodiments of the present application are the same as those of the capacitor, and will not be repeated here.

[0029] In a possible implementation manner, the preset position is that, of the first surface and the second surface of the capacitor, the surface far from the second electrode is placed toward the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1A An architecture diagram of an electronic device provided in an embodiment of the present application;

[0031] Figure 1B An architecture diagram of a radio frequency front-end module provided in an embodiment of the present application;

[0032] Figure 2A A partial cross-sectional view of a capacitor provided in an embodiment of the present application;

[0033] Figure 2B for Figure 2A A1-A2 sectional view;

[0034] Figure 2C A schematic diagram of the force of a circuit board assembly consisting of a capacitor and a circuit board is shown in an embodiment of the present application;

[0035] Figure 2D is a schematic diagram of the structure of the second electrode and the circuit board in the capacitor;

[0036] Figure 2E It is the equivalent force diagram of the circuit board;

[0037] Figure 3 A schematic diagram of the structure of a circuit board assembly consisting of a capacitor and a circuit board illustrated in an embodiment of the present application;

[0038] Figure 4 A schematic diagram of the structure of a circuit board assembly consisting of a capacitor and a circuit board illustrated in an embodiment of the present application;

[0039] Figure 5 A schematic diagram of the structure of a circuit board assembly consisting of a capacitor and a circuit board illustrated in an embodiment of the present application;

[0040] Fig. 6A and Figure 6B A schematic diagram of the structure of a capacitor provided in an embodiment of the present application;

[0041] Figure 6C A schematic diagram of the force of a circuit board assembly consisting of a capacitor and a circuit board provided in an embodiment of the present application;

[0042] Fig.6D A schematic diagram of equivalent force of a circuit board provided in an embodiment of the present application;

[0043] Fig. 7A A method provided in the embodiment of the present application Fig. 6A A cross-sectional view along the B1-B2 direction;

[0044] Figure 7B A method provided in the embodiment of the present application Fig. 6A A cross-sectional view along the B1-B2 direction;

[0045] Figure 8 A method provided in the embodiment of the present application Fig. 6A A cross-sectional view along the C1-C2 direction;

[0046] Fig. 9 A schematic diagram of a preparation process of a capacitor provided in an embodiment of the present application;

[0047] Fig.10 A schematic diagram of the structure of a circuit board assembly provided in an embodiment of the present application;

[0048] Fig.11 A schematic structural diagram of a second electrode and a circuit board in a capacitor provided in an embodiment of the present application. DETAILED DESCRIPTION

[0049] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0050] In the following, the terms "second", "first", etc. are used only for convenience of description and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "second", "first", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0051] In addition, in the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the schematic placement of the components in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0052] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. In addition, the term "coupled" can be a direct electrical connection or an indirect electrical connection through an intermediate medium. The term "contact" can be a direct contact or an indirect contact through an intermediate medium.

[0053] In the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that there may be three relationships. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B may be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0054] An electronic device is provided in an embodiment of the present application. The electronic device is, for example, a consumer electronic product with a camera or display function, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. Among them, consumer electronic products are such as mobile phones, tablet computers (pad), laptop computers, e-readers, personal computers (PC), personal digital assistants (PDA), desktop displays, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronic products are such as smart door locks, televisions, remote controls, refrigerators, rechargeable small household appliances (e.g., soybean milk machines, sweeping robots), etc. Vehicle-mounted electronic products are such as vehicle-mounted navigation systems, vehicle-mounted high-density digital video discs (DVD), etc. Financial terminal products are such as automated teller machines (ATMs), self-service terminals, etc. Communication electronic products are such as communication equipment such as servers, non-volatile memories, radars, base stations, etc. The embodiments of the present application do not impose any special restrictions on the specific form of the above-mentioned electronic device.

[0055] Figure 1A An architectural diagram of an electronic device provided in an embodiment of the present application.

[0056] Taking the electronic device provided in the embodiment of the present application as a mobile phone as an example, for example, Figure 1AAs shown, the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 129, a universal serial bus (USB) interface 130, a charging management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, a camera 190 and a display screen 191, etc.

[0057] It is to be understood that the structures illustrated in the embodiments of the present application do not constitute a specific limitation on the electronic device 100. In other embodiments of the present application, the electronic device 100 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0058] In some embodiments, the electronic device 100 also includes a circuit board. Electronic components such as the processor 110, internal memory 129, unit management module 141, microphone 170C, etc. in the electronic device 100 can be arranged on the circuit board. The circuit board is used to carry the above-mentioned electronic components and complete signal interaction with the above-mentioned electronic components.

[0059] In some embodiments, the electronic device 100 also includes a capacitor, which is mounted on a circuit board. For example, the capacitor can be fixed to the circuit board by welding. The capacitor is electrically connected to the circuit board to meet the functions of tuning, bypassing, coupling or filtering in the circuit. Of course, the capacitor can be integrated into other electronic devices arranged on the circuit board, and the capacitor can also be independently arranged on the circuit board. With the continuous improvement of product functional characteristics, the electronic device 100 has an increasing demand for the amount and capacity of capacitors. Multi-layer ceramic capacitors (MLCC) are widely used in electronic devices 100 because of their high reliability, high precision, high frequency, low power consumption, large capacity, miniaturization and low cost.

[0060] Below, several application scenarios of capacitors are explained by way of example.

[0061] Figure 1B An architecture diagram of a radio frequency front-end module provided in an embodiment of the present application.

[0062] In some application scenarios, the capacitor 10 can be used as Figure 1BThe filter matching capacitor of the RF power supply in the RF front-end module in the 4G / 5G scenario shown. The capacitance of the capacitor 10 can be, for example, 1uF, and the size of the capacitor 10 can be, for example, British "0201". The RF front-end module illustrated in the embodiment of the present application can be applied to the mobile communication module 150 of the above-mentioned electronic device 100, for example.

[0063] The RF front-end module may include a transmitting channel and a receiving channel, wherein the transmitting channel includes a power amplifier (PA) and a transmitting channel filter, wherein the RF output of the PA is coupled to the input of the transmitting channel filter. The receiving channel includes a low noise amplifier (LNA) and a receiving channel filter, wherein the output of the receiving channel filter is coupled to the RF input of the LNA.

[0064] The duplexer is responsible for duplex switching of the frequency division duplex system and filtering of RF signals in the receiving channel / transmitting channel, and the RF switch is responsible for switching between the receiving channel and the transmitting channel.

[0065] The baseband signal is transmitted to the transmission channel through the transceiver. The transmission channel amplifies the received RF signal and outputs it to the antenna, which transmits it through the antenna. The PA is responsible for amplifying the RF signal of the transmission channel, and the transmission channel filter is responsible for filtering the RF signal of the transmission channel.

[0066] In the transmission phase, the PA needs to work and needs to be powered by an RF power supply to ensure the transmission power. In the reception phase or during the communication subframe gap, the PA does not need to work, so the RF power supply can be turned off to save power. Since the RF power supply is frequently turned on and off, the periodic large voltage difference will cause the external capacitor 10 to produce an inverse piezoelectric effect, thereby generating vibration and causing "plate vibration".

[0067] In other application scenarios, the capacitor 10 can be used as an external filter matching capacitor for battery power supply and main power supply in 2G scenarios. The capacitance of the capacitor 10 can be, for example, 4.7uF or 10uF, and the size of the capacitor 10 can be, for example, the British "0402". Or the capacitance of the capacitor 10 can be, for example, 22uF, and the size of the capacitor 10 can be, for example, the British "0603". Battery power supply and main power supply can be applied to the power management module 141 of the above-mentioned electronic device 100, for example.

[0068] The time division multiple access (TDMA) of the global system for mobile communications (GSM) has a time slot of 577uS, and each frame has 8 time slots. The length of each frame is 577us×8=4.616ms, that is, the frequency is 216.6HZ. Due to the working principle of the GSM standard, the PA will have a burst of large current demand (about 1.5A-2A) every time it transmits. The power circuit of the electronic device will transmit this noise to the entire circuit board, resulting in a voltage drop on the battery power supply and the main power supply, and all the filter matching capacitors externally mounted on the power supply will produce "board vibration".

[0069] In some other application scenarios, the capacitor 10 can be used as a filter capacitor for the rectified voltage (Vrect) in wireless charging. The capacitance of the capacitor 10 can be, for example, 10uF, and the size of the capacitor 10 can be, for example, British "0603". The rectified voltage can be applied to the charging management module 140 of the electronic device 100.

[0070] During wireless charging, the voltage received by the electronic device is the power voltage of electromagnetic induction superimposed on the voltage obtained (polling) by the wireless charging communication protocol. After full-bridge rectification, the power voltage is rectified into DC, but the voltage polled by the wireless charging communication protocol is not rectified, resulting in "board vibration".

[0071] The capacitor 10 provided in the embodiment of the present application can be applied to a variety of scenarios. Since the dielectric layer 111 of the capacitor 10 provided in the embodiment of the present application is perpendicular to the circuit board 20 in the electronic device 100, the vibration direction of the capacitor 10 is also perpendicular to the circuit board 20. Therefore, the resonance of the circuit board 20 is small, which can effectively suppress the whistling problem caused by the vibration of the capacitor 10, and can effectively improve the performance of the electronic device 100.

[0072] Figure 2A A partial cross-sectional view of a capacitor provided in an embodiment of the present application, Figure 2B for Figure 2A A1-A2 cross-sectional view, Figure 2C This is a schematic diagram of the structure of a circuit board assembly consisting of a capacitor and a circuit board according to an embodiment of the present application. Figure 2D is a schematic diagram of the structure of the second electrode and the circuit board in the capacitor, Figure 2E This is a schematic diagram of the equivalent force on the circuit board.

[0073] Regarding the structure of the capacitor, in some embodiments, such as Figure 2A and Figure 2B As shown, the capacitor 10 includes a capacitor body 11 and a first electrode (or terminal electrode) 12. The capacitor body 11 includes multiple dielectric layers 111 and multiple second electrodes 112, which are alternately arranged along the second direction Y.

[0074] Typically, when preparing the second electrode 112, due to reliability requirements, a gap is left between the second electrode 112 and the surface of the capacitor 10. Taking into account the capacity, preparation process, miniaturization and other requirements of the capacitor 10, the second electrode 112 is usually designed to be centered, so that the first distance L1 and the second distance L2 between the two sides of the second electrode 112 and the surface of the capacitor 10 are set to be equal or approximately equal.

[0075] like Figure 2C As shown, the surface of the circuit board 20 used to support the capacitor 10 is parallel to the plane formed by the first direction X and the third direction Z. The capacitor 10 is arranged on the surface of the circuit board 20. Since the arrangement direction of the second electrode 112 inside the capacitor 10 cannot be determined after the capacitor 10 is sealed to form the first electrode 12, this results in that after the capacitor 10 is coupled to the circuit board 20, the arrangement direction (second direction Y) of the multi-layer dielectric layer 111 and the multi-layer second electrode 112 in the capacitor 10 is perpendicular to the circuit board 20. In this case, Figure 2D As shown, the stacking direction of the second electrode 112 in the capacitor 10 is parallel to the circuit board 20 .

[0076] The dielectric layer 111 of the high-capacity MLCC is mainly made of ferroelectric materials of Class II porcelain. During use, due to the inverse piezoelectric effect of the dielectric layer 111, when an AC voltage is applied to the first electrode 12, the dielectric layer 111 will expand and contract in the second direction Y perpendicular to the second electrode 112. The dielectric material usually has a Poisson's ratio (lateral deformation coefficient) less than 1, causing the dielectric layer 111 to expand and contract in the first direction X parallel to the second electrode 112.

[0077] The capacitor 10 is soldered on the circuit board 20. Figure 2C Taking the stress applied by the first electrode 12 on the left side of the middle diagram to the circuit board 20 as an example, when the dielectric layer 111 expands and contracts in a direction perpendicular to the second electrode 112, as shown in FIG. Figure 2E As shown in FIG. 1 , the circuit board 20 is subjected to a first stress F1 in the vertical direction. When the dielectric layer 111 expands and contracts in a direction parallel to the second electrode 112, as shown in FIG. Figure 2E As shown, the circuit board 20 is also subjected to a second stress F2 in the horizontal direction. The stress F on the circuit board 20 is the resultant force of the first stress F1 and the second stress F2. Limited by the angle of the stress F, the force arm L of the stress on the circuit board 20 is as follows: Figure 2EAs shown. When the stress F is fixed, the larger the arm L is, the larger the torque is, and the larger the deformation of the capacitor 10 is. The deformation of the capacitor 10 will pull the circuit board 20, thereby causing the circuit board 20 to generate surface vibration, which is commonly referred to as "board vibration" in the art. If the frequency of the vibration is within the range of 20Hz-20KHz that can be heard by the human ear, a harsh whistling sound will be heard. When the electronic device 100 is close to the human ear, the whistling noise generated affects the user's perception.

[0078] Figure 3 A schematic diagram of the structure of a circuit board assembly consisting of a capacitor and a circuit board according to an embodiment of the present application.

[0079] In order to improve the howling problem, in some embodiments, such as Figure 3 As shown, the capacitor 10 includes a plurality of second electrodes 112 , the second electrodes 112 close to the circuit board 20 are arranged sparsely, and the second electrodes 112 far from the circuit board 20 are arranged densely.

[0080] In this way, the number of dielectric layers 111 near the circuit board 20 is reduced, which can reduce the stress transmitted to the circuit board 20 by the inverse piezoelectric effect of the capacitor. After the stress on the circuit board 20 is reduced, its deformation is not enough to drive the circuit board 20 to vibrate, thereby reducing the problem of capacitor howling.

[0081] However, after the second electrode 112 sparse area is set inside the capacitor 10, the capacity of the capacitor 10 will be reduced based on the same device thickness. In order to ensure the capacity of the capacitor 10, the thickness of the capacitor 10 needs to be increased, resulting in a large thickness of the capacitor 10, which does not meet the requirements of miniaturization and thinness of the device.

[0082] Figure 4 A schematic diagram of the structure of a circuit board assembly consisting of a capacitor and a circuit board according to an embodiment of the present application.

[0083] In other embodiments, Figure 4 As shown, a substrate is added between the capacitor 10 and the circuit board 20. The position where the substrate contacts the first electrode 12 is wrapped with a conductive layer, and the conductive layer is respectively coupled to the capacitor 10 and the circuit board 20. The material of the substrate is elastic material, and the thickness of the substrate is greater than 150um.

[0084] By selecting an elastic substrate, the force applied by the capacitor 10 to the circuit board 20 can be absorbed by the substrate, and only the force exceeding the deformation limit of the substrate is transmitted to the circuit board 20. The stress transmitted to the circuit board 20 by the inverse piezoelectric effect of the capacitor can be reduced. After the stress on the circuit board 20 is reduced, the deformation amount of the circuit board 20 is not enough to drive the circuit board 20 to vibrate, thereby reducing the problem of capacitor howling.

[0085] However, in order to significantly improve the capacitor howling problem and avoid substrate breakage, the thickness of the substrate needs to be relatively large, generally more than 150um. This results in the sum of the thickness of the capacitor 10 and the substrate being relatively large after the substrate is added, which does not meet the requirements of miniaturization and thinness of the device. Moreover, as the number of uses increases, the elastic force of the substrate will age, the howling will gradually worsen, and the improvement effect cannot be guaranteed. Furthermore, the capacitor 10 and the circuit board 20 are bonded through a conductive layer. Compared with the direct bonding of the capacitor 10 and the circuit board 20, the bonding interface increases. During the vibration process of the capacitor 10 and the circuit board 20, the bonding reliability of the capacitor 10 and the circuit board 20 cannot be guaranteed.

[0086] Figure 5 A schematic diagram of the structure of a circuit board assembly consisting of a capacitor and a circuit board according to an embodiment of the present application.

[0087] In some other embodiments, Figure 5 As shown, an elastic metal frame is added at the first electrode 12 of the capacitor 10 , and the elastic metal frame is coupled to the first electrode 12 and the circuit board 20 respectively.

[0088] By adding an elastic metal frame, the force applied by the capacitor 10 to the circuit board 20 can be absorbed by the elastic metal frame, and only the force exceeding the deformation limit of the elastic metal frame will be transmitted to the circuit board 20. The stress transmitted to the circuit board 20 by the inverse piezoelectric effect of the capacitor can be reduced. After the stress on the circuit board 20 is reduced, the deformation amount of the circuit board 20 is not enough to drive the circuit board 20 to vibrate, thereby reducing the problem of capacitor howling.

[0089] However, in order to significantly improve the capacitor howling problem, the height of the elastic metal frame needs to be relatively large, generally more than 150um. This results in that after the elastic metal frame is added, the sum of the thickness of the capacitor 10 and the elastic metal frame is relatively large, which does not meet the needs of miniaturization and thinness of the device. Moreover, as the number of uses increases, the elastic force of the elastic metal frame will age, the howling will gradually worsen, and the improvement effect cannot be guaranteed. Furthermore, the capacitor 10 and the circuit board 20 are bonded through the elastic metal frame. Compared with the direct bonding of the capacitor 10 and the circuit board 20, the bonding interface increases. During the vibration process of the capacitor 10 and the circuit board 20, the bonding reliability of the capacitor 10 and the circuit board 20 cannot be guaranteed.

[0090] Fig. 6A and Figure 6B A schematic diagram of the structure of a capacitor provided in an embodiment of the present application.

[0091] The present application embodiment provides a capacitor 10, and the capacitor 10 is, for example, an MLCC. Fig. 6AAs shown, the capacitor 10 includes a capacitor body 11 and a first electrode 12 (or called an end electrode, an external electrode). Along a first direction X, the first electrodes 12 are respectively disposed at two opposite ends of the capacitor body 11.

[0092] The first electrodes 12 are respectively provided at the opposite ends of the capacitor body 11. When the capacitor 10 is coupled to the circuit board 20, the capacitor 10 is coupled to the circuit board 20 through the first electrodes 12 to complete signal interaction. Then, the first electrode 12 can be used as a lead-out terminal of the capacitor body 11, so as to facilitate the electrical connection of the capacitor body 11 with an external circuit.

[0093] The capacitor body 11 includes a marking surface w, on which a marking pattern 13 is disposed. The first electrode 12 exposes the marking pattern 13 , and the marking pattern 13 is used to identify the arrangement direction of the second electrode 112 .

[0094] like Figure 6C As shown, the capacitor body 11 includes a plurality of dielectric layers 111 and a plurality of second electrodes 112. The dielectric layers 111 and the second electrodes 112 extend in a plane surrounded by the third direction Z and the first direction X, and the plurality of dielectric layers 111 are stacked along the second direction Y, and the second electrodes 112 are arranged between two adjacent dielectric layers 111. For example, along the second direction Y, the dielectric layers 111 and the second electrodes 112 are alternately arranged. That is, a second electrode 112 is arranged between any two dielectric layers 111. Or, for example, along the second direction Y, the second electrode 112 is arranged between some of the dielectric layers 111, and the second electrode 112 is not arranged between some of the dielectric layers 111. The embodiment of the present application is not limited to this, as long as the dielectric layers 111 are respectively arranged on both sides of any second electrode 112.

[0095] like Figure 6C As shown, two adjacent layers of second electrodes 112 are staggered and arranged, and two adjacent layers of second electrodes 112 are coupled to the first electrodes 12 at different ends.

[0096] The staggered arrangement of two adjacent layers of second electrodes 112 in the capacitor body 11 can also be understood as the projections of the two adjacent layers of second electrodes 112 on the dielectric layer 111 overlap but do not overlap (overlap). Alternatively, it can be understood as the two adjacent layers of second electrodes 112 are staggered in a relative and separated manner along the second direction Y. The first direction X, the second direction Y, and the third direction Z intersect each other.

[0097] On this basis, two adjacent layers of second electrodes 112 are coupled to the first electrodes 12 located on different sides. For example, along the first direction X, two first electrodes 12 are arranged on the opposite first side (e.g., the left side) and second side (e.g., the right side) of the multi-layer second electrodes 112, the second electrodes 112 of the odd-numbered layers are coupled to the first electrodes 12 on the first side, and the second electrodes 112 of the even-numbered layers are coupled to the first electrodes 12 on the second side.

[0098] In some embodiments, the spacing between the two first electrodes 12 is greater than the dimension of the second electrode 112 along the first direction X. Then, the second electrode 112 coupled to the first electrode 12 on the first side has a gap with the first electrode 12 on the second side. Similarly, the second electrode 112 coupled to the first electrode 12 on the second side has a gap with the first electrode 12 on the first side.

[0099] It should be understood that the embodiment of the present application does not limit the shape of the second electrode 112. The second electrode 112 can be Figure 6C The sheet-shaped electrode shown in the figure may also be an electrode of any other shape, which is only a schematic diagram. For example, the shape of the second electrode 112 is selected from at least one of a rectangle, a trapezoid, a triangle, a rhombus or a circle. The embodiment of the present application does not limit the number of layers of the second electrode 112. Figure 6C A total of four layers of second electrodes 112 are shown in FIG. However, any number of second electrodes 112 may be used in the capacitor 10 to obtain the capacitance required by the application.

[0100] In the present application embodiment, Fig. 6A As shown, the marking surface w of the capacitor body 11 may be a surface intersecting (eg, perpendicular to) the second electrode 112. Then, when the capacitor 10 is bonded to the circuit board 20, the marking surface w is placed parallel to the circuit board 20. Figure 6B As shown, the marking surface w of the capacitor body 11 may also be a surface parallel to the second electrode 112. Then, when the capacitor 10 is bonded to the circuit board 20, the marking surface w is placed perpendicular to the circuit board 20.

[0101] The embodiment of the present application does not limit the shape of the marking pattern 13. The marking pattern 13 can be a pattern of any texture. The figure is only a schematic diagram and does not impose any limitation.

[0102] In some embodiments, the material of the marking pattern 13 is a dielectric material. In this way, after the capacitor 10 is applied to an electronic device, the marking pattern 13 can be prevented from generating parasitic capacitance or conducting electricity.

[0103] In the embodiment of the present application, the dielectric layer 111 may be formed of a specific type of material having a specific dielectric constant to determine the electrical characteristics of the capacitor 10. For example, in some embodiments, the dielectric layer 111 may be formed of a material having a relatively high dielectric constant (K).

[0104] In some embodiments, the material of dielectric layer 111 may include ceramic. The ceramic may be provided in various forms, for example, as a pre-fired wafer or as a co-fired dielectric material within the device itself.

[0105] For example, the material of the dielectric layer 111 may include a ferroelectric material (perovskite) using a type II ceramic. For example, the material of the dielectric layer 111 may include barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lead lanthanum zirconate titanate), sodium bismuth titanate, strontium titanate, etc.

[0106] In some other embodiments, the material of the dielectric layer 111 may include oxide.

[0107] For example, the material of the dielectric layer 111 may include zinc, zirconium, niobium, magnesium, tantalum, titanium, cobalt, strontium, neodymium, samarium, silicon, etc., or a mixture thereof.

[0108] In yet other embodiments, the material of the dielectric layer 111 may include a combination of titanate and oxide.

[0109] For example, the material of the dielectric layer 111 may include a combination of barium titanate and oxide.

[0110] In the embodiment of the present application, the first electrode 12 and the second electrode 112 can be formed of any conductive metal known in the art to conduct current.

[0111] In some embodiments, the materials of the first electrode 12 and the second electrode 112 may include precious metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, aluminum, zinc, etc.), alloys (e.g., titanium / tungsten alloy, chromium / nickel alloy, copper alloy), etc., and various combinations thereof.

[0112] The first electrode 12 is coupled to the second electrode 112, for example, the first electrode 12 may wrap the entire end of the capacitor body 11 where the second electrode 112 is exposed. In this way, the connection strength between the first electrode 12 and the capacitor body 11 can be improved, while ensuring reliable electrical connection between the first electrode 12 and each second electrode 112 exposed from the end of the capacitor body 11.

[0113] In some embodiments, Fig. 6A As shown, the first electrode 12 includes a side surface c, which intersects (eg, is perpendicular to) the first direction X, and is in the shape of a square, a rectangle, etc. The embodiment of the present application does not limit the shape of the end surface of the first electrode 12, which may be any shape.

[0114] The capacitor 10 provided in the embodiment of the present application has a marking pattern 13 on the marking surface w of the capacitor body 11. The arrangement direction of the second electrode 112 can be known through the marking pattern 13. Then, when the capacitor 10 is bonded to the circuit board 20, the capacitor 10 can be placed in the expected position by identifying the marking pattern 13, ensuring that after the capacitor 10 is bonded to the circuit board 20, the plane where the second electrode 112 is located intersects with the circuit board 20 (for example, perpendicular). In this way, Figure 6C As shown, even when an electric field is applied to the first electrode 12, the dielectric layer 111 expands in a direction perpendicular to the second electrode 112 to generate a first stress F1, and shrinks in a direction parallel to the second electrode 112 to generate a second stress F2. However, the equivalent force diagram of the circuit board 20 is as shown in FIG. Fig.6D As shown, Figure 6C Taking the stress applied by the first electrode 12 at the front end to the circuit board 20 as an example, the circuit board 20 will be subjected to the second stress F2 in the vertical direction and the first stress F1 in the horizontal direction. The direction of the first stress F1 is parallel to the circuit board 20, and the direction of the second stress F2 intersects with the circuit board 20. The first stress F1 is greater than the second stress F2, and the angle between the synthesized stress F and the circuit board 20 is an acute angle, so the lever arm L will decrease. Therefore, although the capacitor 10 will still vibrate during operation. However, when the stress F remains unchanged, the lever arm L is reduced, which can reduce the torque (torque equals force * lever arm L), thereby reducing the impact of the vibration of the capacitor 10 on the circuit board 20 to improve the problem of howling. For example, a certain model of capacitor 10 is selected and the capacitor 10 is bonded to the circuit board 20. If the second electrode 112 is parallel to the circuit board 20, the amplitude of the circuit board 20 can reach about 5060pm. But if the second electrode 112 is perpendicular to the circuit board 20, the amplitude of the circuit board 20 can be reduced by about 210pm. When the capacitor 10 is applied to a radio frequency circuit, the second electrode 112 is parallel to the circuit board 20, and the howling sound can reach about 36.13 dBA. However, if the second electrode 112 is perpendicular to the circuit board 20, the howling sound can be reduced to about 29.61 dBA.

[0115] Typically, when preparing the second electrode 112 , a gap is left between the second electrode 112 and the surface of the capacitor 10 due to reliability requirements.

[0116] Fig. 7A and Figure 7B A method provided in the embodiment of the present application Fig. 6A Cross-sectional view along B1-B2 direction.

[0117] In some embodiments, Fig. 7AAs shown, the capacitor body 11 includes a first surface a and a second surface b that are arranged opposite to each other, and the plane where the first surface a is located and the plane where the second surface b is located both intersect with the second electrode 112. The second distance L2 from the second electrode 112 to the second surface b of the capacitor body 11 is equal to the first distance L1 from the second electrode 112 to the first surface a of the capacitor body 11.

[0118] Taking into account the capacity of the capacitor 10 and the manufacturing process requirements, the second electrode 112 is designed to be centered, which is beneficial to the miniaturization of the capacitor 10 .

[0119] In other embodiments, Figure 7B As shown, the capacitor body 11 includes a first surface a and a second surface b that are arranged opposite to each other, and the plane where the first surface a is located and the plane where the second surface b is located both intersect with the second electrode 112. A first distance L1 from the second electrode 112 to the first surface a of the capacitor body 11 is not equal to a second distance L2 from the second electrode 112 to the second surface b of the capacitor body 11.

[0120] For example, the first distance L1 may be greater than the second distance L2, or the first distance L1 may be smaller than the second distance L2, as long as the first distance L1 and the second distance L2 are not equal. Figure 7B In the figure, the first distance L1 is smaller than the second distance L2.

[0121] Taking the example that the first distance L1 is smaller than the second distance L2 , for example, the first surface a is the marking surface w. When the capacitor 10 is bonded to the circuit board 20 , the first surface a provided with the marking pattern 13 is disposed away from the circuit board 20 .

[0122] Or, for example, the second surface b is a marking surface, and when the capacitor 10 is bonded to the circuit board 20 , the second surface b provided with the marking pattern 13 is disposed toward the circuit board 20 .

[0123] Or, for example, Figure 6B As shown, the plane where the marking surface w is located is intersecting and parallel to the plane where the first surface a is located; at this time, the marking surface w cannot identify the first surface a and the second surface b, but the marking pattern 13 is used to indicate the first surface a and the second surface b. Then, the first surface a and the second surface b can be identified through the marking pattern 13. For example Figure 6BThe apex of the triangle in the figure faces the first surface a, and the base of the triangle faces the second surface b. When the capacitor 10 is bonded to the circuit board 20, the first surface a is set away from the circuit board 20, and the second surface b is set toward the circuit board 20. Alternatively, for example, the marking pattern 13 is an arrow, the direction pointed by the arrow (or facing away from) is the first surface a, and the direction facing away from (or pointing to) the arrow is the second surface b. Alternatively, for example, the side close to (or away from) the marking pattern 13 is the first surface a, and the side away from (or close to) the marking pattern 13 is the second surface b.

[0124] No matter on which surface the marking pattern 13 is set and in what shape the marking pattern 13 is set, it is sufficient to ensure that after the capacitor 10 is bonded to the circuit board 20, the surface of the first surface a and the second surface b that is far from the second electrode 112 is set toward the circuit board 20, and the surface of the first surface a and the second surface b that is close to the second electrode 112 is set away from the circuit board 20.

[0125] This is equivalent to designing the second electrode 112 to be non-centered. When forming the second electrode 112, the margin of the second electrode 112 is left with a larger distance on one side and a smaller distance on the other side. When the capacitor 10 is bonded to the circuit board 20, the surface of the capacitor 10 with a larger margin faces the circuit board 20 to increase the distance between the capacitor 10 and the circuit board 20.

[0126] By designing the second electrode 112 to be non-centered, when the capacitor 10 is bonded to the circuit board 20, the surface of the capacitor 10 with a large margin faces the circuit board 20, which can increase the transmission distance of the stress F generated by the vibration of the capacitor 10 to the circuit board 20. In the process of stress transmission to the circuit board 20, the dielectric layer 111 can lose stress to reduce the magnitude of the stress transmitted to the circuit board 20. Moreover, the capacitor 10 provided in the embodiment of the present application increases the distance from the capacitor 10 to the circuit board 20 through its own dielectric layer 111. On the one hand, the thickness of the dielectric layer 111 hardly decreases with the vibration of the capacitor 10, so the possibility of the howling gradually worsening with the increase in the applicable time is relatively small, and the improvement effect on the howling problem can be guaranteed. On the other hand, there is no need to set up other external structures, which can simplify the structure of the circuit board 20 assembly and improve the bonding reliability of the capacitor 10 and the circuit board 20.

[0127] In some embodiments, the difference between the second distance L2 and the first distance L1 is 20um-150um. For example, the difference between the second distance L2 and the first distance L1 is 30um, 40um, 50um, 60um, 70um, 80um, 90um, 100um, 110um, 120um, 130um, 140um.

[0128] Since the loss of stress F generated on the capacitor 10 is increased by increasing the second distance L2 in the embodiment of the present application, the size of the second distance L2 can be less than 150um, which is beneficial to reducing the thickness from the first surface a of the capacitor 10 to the circuit board 20 and meeting the demand for lightness and thinness.

[0129] Figure 8 A method provided in the embodiment of the present application Fig. 6A Cross-sectional view along C1-C2 direction.

[0130] In some embodiments, Figure 8 As shown, the first electrode 12 includes a first conductive layer 121 and a second conductive layer 122 . The first conductive layer 121 is arranged close to the capacitor body 11 relative to the second conductive layer 122 . The toughness of the first conductive layer 121 is greater than that of the second conductive layer 122 .

[0131] For example, the material of the first conductive layer 121 includes silver, and the material of the second conductive layer 122 includes tin.

[0132] Of course, other conductive layers may be provided between the first conductive layer 121 and the capacitor body 11, between the first conductive layer 121 and the second conductive layer 122, between the second conductive layer 122 and the third conductive layer 123, and on the side of the third conductive layer 123 away from the second conductive layer 122. The added conductive layer may be a soft conductive layer or a hard conductive layer, which is not limited in the embodiments of the present application.

[0133] like Figure 8 As shown, the first electrode 12 further includes a third conductive layer 123 and a fourth conductive layer 124 . The third conductive layer 123 is disposed on a side of the second conductive layer 122 away from the first conductive layer 121 , and the fourth conductive layer 124 is disposed on a side of the first conductive layer 121 away from the second conductive layer 122 .

[0134] For example, the material of the fourth conductive layer 124 includes a material with good conductivity such as copper or silver, and the fourth conductive layer 124 is electrically connected to the second electrode 112 to facilitate the input of an external power source. The material of the first conductive layer 121 includes a soft material such as silver, which acts as a stress buffer. The material of the second conductive layer 122 includes nickel, which acts as a heat barrier. The material of the third conductive layer 123 includes tin, which provides solderability.

[0135] By providing a first conductive layer 121 with greater toughness in the first electrode 12, when the dielectric layer 111 applies a second stress F2 to the circuit board 20 in a direction parallel to the second electrode 112, the second stress F2 can be first buffered and borne by the first conductive layer 121. When the second stress F2 exceeds the deformation limit of the first conductive layer 121, the remaining stress will be transmitted to the circuit board 20, which can reduce the stress transmitted to the circuit board 20 by the inverse piezoelectric effect of the capacitor. After the stress on the circuit board 20 is reduced, the howling problem can be improved.

[0136] Fig. 9 A schematic diagram of the preparation process of a capacitor provided in an embodiment of the present application.

[0137] The present application also provides a method for preparing the capacitor 10. Fig. 9 As shown, including:

[0138] S1. Ingredients.

[0139] Ceramic powder, adhesive, solvent and additives are ball-milled or sand-milled in a certain proportion for a certain period of time to form a uniform and stable ceramic slurry.

[0140] S2: Casting.

[0141] The ceramic slurry is passed through the pouring port of the casting machine and coated on the winding silicone film (such as polyethylene terephthalate (PET) film) to form a uniform ceramic slurry film layer. It then passes through the hot air zone (to volatilize most of the solvent in the slurry) and is heated and dried to obtain a dielectric film (ceramic diaphragm) with a certain thickness and density and uniformity.

[0142] S3: Printing.

[0143] According to the process requirements, the second electrode 112 slurry is printed onto the dielectric film through a screen printing plate, and a clear and complete dielectric film is obtained after drying. When executing step S3, the second electrode 112 can be set in the center, or the second electrode 112 can be set not in the center. That is, the distances from the second electrode 112 to the two opposite edges of the dielectric film are not equal, and the two edges intersect with the plane where the end face of the first electrode 12 to be covered is located, and are the edges on the side where the surface intersecting with the end face is located, rather than the edges on the side where the end face is located.

[0144] S4: Lamination.

[0145] The dielectric films printed with the second electrode 112 are stacked one by one according to the designed offset requirements, and upper and lower protective layer films are made to form a capacitor body stack (Bar), which includes multiple layers of dielectric films with the second electrode 112 formed on the surface. The capacitor body stack can be formed through steps S1-S4.

[0146] S5: Lamination.

[0147] The capacitor body is stacked in a laminating bag, vacuum-encapsulated, and pressurized by a hydrostatic pressure method with uniform temperature, so that the layers in the capacitor body stack are more tightly and tightly bonded, thereby improving the density of the porcelain body after sintering.

[0148] S6: Cutting.

[0149] According to the design requirements of the product, a thin blade is used to cut the capacitor body stack horizontally and vertically according to the designed size to make it into a completely separated independent chip (capacitor green body). After cutting the capacitor body stack, a plurality of capacitor green bodies are formed, each of which includes a stacked dielectric layer 111 and a second electrode 112 located on the surface of the dielectric layer 111.

[0150] S7. Debonding.

[0151] The capacitor embryo is placed on a firing plate and baked at a high temperature according to a certain temperature curve (the highest temperature is generally around 400°C) to remove organic substances such as adhesives in the capacitor body 11, so as to avoid rapid volatilization of organic substances during firing, causing product stratification and cracking, to ensure that a good capacitor embryo with a desired shape is fired, and to eliminate the reducing effect of the adhesive during firing.

[0152] S8: Sintering.

[0153] The debinding capacitor embryo is subjected to high temperature treatment in an atmosphere furnace. Generally, the sintering temperature is between 1140°C and 1340°C. This can make the debinding capacitor embryo become a ceramic body with a complete second electrode 112, good density, qualified size, high mechanical strength and excellent electrical properties.

[0154] S9: Chamfer.

[0155] Chamfering is also called grinding. The capacitor green embryo that has been sintered into porcelain has sharp edges and corners, which is not conducive to the connection with the first electrode 12, so it needs to be ground and chamfered. The chamfering process is to put the capacitor green embryo, water and grinding medium in a chamfering tank, and move it by ball milling, planetary milling, etc. to remove the burrs on the surface of the capacitor green embryo, so that the surface of the capacitor green embryo is smooth, and at the same time, it is ensured that the two ends of the capacitor green embryo fully expose the second electrode 112 in the direction parallel to the length of the second electrode 112, so as to process the capacitor body 11. A plurality of capacitor bodies 11 can be formed through steps S5-S9.

[0156] S10: Marking pattern.

[0157] A marking pattern 13 is formed on the marking surface w of the capacitor body 11, the plane where the marking surface w is located intersects with the plane where the end surface of the first electrode 12 to be covered of the capacitor body 11 is located, and the marking surface w does not expose the second electrode 112. After step S9 is completed, the second electrode 112 in the capacitor body 11 will be exposed, and the surface exposing the second electrode 112 is not used as the marking surface w, so the marking surface w of the capacitor body 11 is the surface that wraps the second electrode 112, and the plane where the end surface w is located can be parallel to or intersecting with the plane where the second electrode 112 is located.

[0158] For example, the marking surface w is identified by the visual detection technology of an image sensor (charge-coupled device, CCD), and a marking pattern 13 is formed on the marking surface w of the capacitor body 11 by using a coding process or a laser engraving process.

[0159] If the second electrode 112 is not centered, the marking surface w is fixed to a surface where the plane thereof intersects with the plane where the second electrode 112 is located, and the marking surface w may be the first surface a or the second surface b. Alternatively, the marking surface w is fixed to a surface parallel to the second electrode 112, and the marking pattern 13 is designed to indicate the first surface a and the second surface b.

[0160] S11: Capping (or termination).

[0161] Along a direction parallel to the length of the second electrode 112, the first electrode slurry is coated on the two ends of the exposed second electrode 112 of the capacitor body 11 through a sealing machine, or the two ends of the exposed second electrode 112 of the capacitor body 11 are dipped into the first electrode slurry respectively, or the first electrode slurry is sputtered onto the two ends of the exposed second electrode 112 of the capacitor body 11 by a sputtering process to form the first electrode 12.

[0162] S12: Burning end.

[0163] The capped product is sintered at low temperature to fully burn the organic binder in the first electrode slurry, melt the glass and infiltrate the copper powder, so that the second electrode 112 is connected to the first electrode 12, and the first electrode 12 and the dielectric layer 111 in the capacitor body 11 have a certain bonding strength.

[0164] S13: Electroplating.

[0165] The end treatment of the product after the burn-in end is essentially an electroplating process. Depending on the structure of the first electrode 12, the electroplating process includes different processes. For example, the first electrode 12 also includes a silver layer, a nickel layer and a tin layer. Then, the electroplating process includes using the burn-in end electrode of the capacitor as a cathode in an electrolyte solution containing silver ions, and plating a layer of silver on the burn-in end electrode through a certain low-voltage direct current. Then a layer of nickel is plated on the silver layer, and then a layer of tin is plated on the nickel layer, thereby processing the first electrode 12. Through steps S11-S13, the first electrode 12 can be formed at both ends of the capacitor body 11 to form a capacitor 10.

[0166] S14: Testing.

[0167] Test whether the electrical performance parameters of the capacitor 10 meet the requirements, including capacity, loss, insulation, withstand voltage, etc., and eliminate defective products.

[0168] S15: Appearance inspection.

[0169] The appearance of the capacitor 10 is inspected, and products with poor appearance are rejected.

[0170] S16: Taping packaging.

[0171] Identify the marking pattern 13, position the capacitor 10 according to a preset rule, for example, position it in a fixed position with the marking pattern 13 facing upward or downward, weave it into a carrier tape according to the size and quantity requirements, and roll it into a plastic reel according to a fixed quantity and put it into an outer package.

[0172] The method for preparing a capacitor provided in the embodiment of the present application can add or delete steps based on the above steps, or change the order of the steps. The embodiment of the present application is only an illustration and is not limited in any way.

[0173] If there is no marking pattern 13, the orientation of the second electrode 112 in the capacitor 10 after taping is not fixed. After the capacitor 10 is bonded to the circuit board 20, the second electrodes 112 of some capacitors 10 may be parallel to the circuit board 20, and the probability of capacitor howling after AC current passes through during operation is relatively high. However, in the embodiment of the present application, the marking pattern 13 is used for marking and identification, so that the orientation of the second electrode 112 in the capacitor 10 after taping is fixed. After the capacitor 10 is bonded to the circuit board 20, the plane where the second electrode 112 of the capacitor 10 is located intersects with the circuit board 20 to reduce or eliminate the howling.

[0174] The present application also provides a circuit board assembly, such as Fig.10 As shown, it includes a circuit board 20 and any one of the above-mentioned capacitors 10 , and the plane where the second electrode 112 of the capacitor 10 is located intersects with the circuit board 20 .

[0175] In some embodiments, the dielectric layer 111 and the second electrode 112 are perpendicular to the circuit board 20 .

[0176] In the embodiment of the present application, "vertical" means that the angle between the dielectric layer 111 and the circuit board 20 is within a preset range. For example, the preset range is [75°, 110°]. For example, the angle between the dielectric layer 111 and the circuit board 20 is 80°, 85°, 86°, 87°, 88°, 89°, 90°, 91°, 92°, 93°, 94°, 95°, 96°, 97°, 100° or 105°.

[0177] In some embodiments, the plane where the marking surface w of the capacitor 10 provided with the marking pattern 13 is located intersects with the plane where the second electrode 112 is located. Then the marking surface w is the first surface a or the second surface b of the capacitor 10. Of the first surface a and the second surface b of the capacitor 10, the surface far from the second electrode 112 is arranged toward the circuit board 20, and the marking surface w can be arranged toward the circuit board 20 or away from the circuit board 20.

[0178] The present application also provides a method for preparing a circuit board assembly, including:

[0179] S10, obtaining any one of the above capacitors 10.

[0180] S20, identifying the marking pattern 13 of the capacitor 10, and bonding the capacitor 13 to the circuit board 20 according to a preset position to form a circuit board assembly. Fig.11 As shown, the plane where the second electrode 112 in the capacitor is located intersects with the circuit board 20 .

[0181] For example, if it is known that the marking surface w provided with the marking pattern 13 is parallel to the second electrode 112 , the preset position is to place the marking surface w perpendicular to the circuit board 20 .

[0182] If it is known that the plane where the marking surface w with the marking pattern 13 is located intersects with the plane where the second electrode 112 is located, the preset position is to place the marking surface w parallel to the circuit board 20 , and the marking surface w can face the circuit board 20 or away from the circuit board 20 .

[0183] In some embodiments, if the plane where the marking surface w of the capacitor 10 is located intersects with the plane where the second electrode 112 is located, and the distances from the second electrode 112 to the relative first surface a and second surface b are not equal, the preset position is that the surface of the first surface a and the second surface b of the capacitor 10, which is far from the second electrode 112, is placed toward the circuit board 20 to increase the distance from the second electrode 112 to the circuit board 20.

[0184] The electronic device provided in the embodiment of the present application includes any of the above-mentioned capacitors 10 and a shell. The capacitor 10 can be arranged in the shell after forming a circuit board assembly with the circuit board 20. The capacitor 10 can also be arranged in the shell in other ways, which is not limited in the embodiment of the present application.

[0185] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A capacitor, characterized in that: include: A capacitor body and a first electrode; the first electrodes are respectively disposed at two opposite ends of the capacitor body; The capacitor body includes multiple dielectric layers and multiple second electrodes; The plurality of dielectric layers are stacked; the second electrode is arranged between two adjacent dielectric layers, the second electrodes of two adjacent layers are staggered, and the second electrodes of two adjacent layers are coupled to the first electrodes at different ends; Wherein, the capacitor body comprises a marking surface, and the marking surface is provided with a marking pattern.

2. The capacitor according to claim 1, characterized in that The capacitor body includes a first surface and a second surface arranged opposite to each other, the plane where the first surface is located intersects with the plane where the second electrode is located; a first distance from the second electrode to the first surface is not equal to a second distance from the second electrode to the second surface.

3. The capacitor according to claim 2, characterized in that The first surface or the second surface is the marking surface.

4. The capacitor according to claim 2, characterized in that The plane where the marking surface is located intersects with the plane where the first surface is located, and the marking pattern is used to indicate the first surface or the second surface.

5. The capacitor according to any one of claims 2 to 4, characterized in that: The difference between the first distance and the second distance is in the range of 20um-150um.

6. The capacitor according to any one of claims 1 to 5, characterized in that: The first electrode includes a first conductive layer and a second conductive layer; the first conductive layer is arranged close to the capacitor body relative to the second conductive layer, and the toughness of the first conductive layer is greater than the toughness of the second conductive layer.

7. The capacitor according to claim 6, characterized in that The material of the first conductive layer includes silver.

8. The capacitor according to any one of claims 1 to 7, characterized in that: The material of the marking pattern is a dielectric material.

9. The capacitor according to any one of claims 1 to 8, characterized in that: The first electrode includes a side surface, a plane where the side surface is located intersects with the capacitor body, and a shape of the side surface is a positive direction.

10. A circuit board assembly, characterized in that: include: A circuit board and a capacitor, wherein the capacitor is arranged on the circuit board, and a plane where a second electrode of the capacitor is located intersects with the circuit board; The capacitor comprises the capacitor according to any one of claims 1 to 9.

11. The circuit board assembly according to claim 10, characterized in that: Of the first surface and the second surface of the capacitor, the surface far from the second electrode is arranged toward the circuit board.

12. An electronic device, characterized in that: include: A housing and a circuit board assembly, wherein the circuit board assembly is arranged in the housing; the circuit board assembly comprises the circuit board assembly according to claim 10 or 11; or, A shell and a capacitor, wherein the capacitor is arranged in the shell; the capacitor comprises the capacitor according to any one of claims 1-9.

13. A method for preparing a capacitor, characterized in that: include: Forming a capacitor body stack, wherein the capacitor body stack includes a plurality of dielectric films with a second electrode formed on the surface; Cutting the capacitor body stack to form a plurality of capacitor bodies; A marking pattern is formed on the marking surface of the capacitor body; the plane where the marking surface is located intersects with the plane where the end surface of the capacitor body to be covered with the first electrode is located; First electrodes are formed at two ends of the capacitor body to form a capacitor.

14. The preparation method according to claim 13, characterized in that: A capacitor body stack is formed, including: forming a dielectric film; A second electrode is printed on the surface of the dielectric film; the distances between the second electrode and two opposite edges of the dielectric film are unequal, and the two edges intersect with the plane where the end face is located.

15. The preparation method according to claim 13 or 14, characterized in that: The plane where the marking surface is located intersects with the plane where the second electrode is located.

16. The preparation method according to claim 13 or 14, characterized in that: The plane where the marking surface is located is parallel to the plane where the second electrode is located; and the marking pattern is used to indicate the surfaces where the two edges are located respectively.

17. The preparation method according to any one of claims 13 to 16, characterized in that: The preparation method further includes: identifying the marking pattern, positioning the capacitor according to a preset rule, and taping the capacitor.

18. A method for preparing a circuit board assembly, characterized in that: include: Obtain the capacitor according to any one of claims 1 to 9; The marking pattern of the capacitor is identified, and the capacitor is bonded to the circuit board in a preset position to form the circuit board assembly; wherein the plane where the second electrode of the capacitor is located intersects with the circuit board.

19. The preparation method according to claim 18, characterized in that: The preset position is that, of the first surface and the second surface of the capacitor, the surface far from the second electrode is placed toward the circuit board.

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