Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure. The method includes the following steps: obtaining a device design pattern of a wafer, where the device design pattern includes a pattern of a gate structure; dividing the pattern of the gate structure into a first type of pattern and a second type of pattern according to the pattern length of the gate structure, where the length of the second type of pattern is greater than that of the first type of pattern; disposing a support pattern in a blank area of the wafer, where the support pattern is adjacent to the pattern of the gate structure or adjacent to another support pattern, and the area of the support pattern adjacent to the first type of pattern is greater than the area of the support pattern adjacent to the second type of pattern; and processing the wafer according to the device design pattern and the support pattern to form a gate structure and a support structure. The present invention provides a manufacturing method of a semiconductor structure and a semiconductor structure, which can improve the manufacturing yield of the gate structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly relates to a manufacturing method of a semiconductor structure and a semiconductor structure. Background Art

[0002] In the step of forming a metal dummy gate, a chemical mechanical polishing (CMP) method is used to planarize an interlayer dielectric layer. However, chemical mechanical polishing can only roughly balance the surface height of the polished layer, and the resulting dummy gate has poor height uniformity. Therefore, after removing the dummy gate, there is a large difference in gate height in different regions, resulting in failed electrical measurements and low product manufacturing yield. Summary of the Invention

[0003] The purpose of the present invention is to provide a manufacturing method of a semiconductor structure and a semiconductor structure, which can improve the manufacturing yield of a gate structure.

[0004] To solve the above technical problems, the present invention is realized through the following technical solutions:

[0005] The present invention provides a manufacturing method of a semiconductor structure, including the following steps:

[0006] Obtain a device design pattern of a wafer, where the device design pattern includes a pattern of a gate structure;

[0007] According to the graphic length of the gate structure pattern, divide the gate structure pattern into a first type of pattern and a second type of pattern, where the length of the second type of pattern is greater than that of the first type of pattern;

[0008] Set support patterns in the blank area of the wafer, where the support patterns are adjacent to the gate structure pattern or adjacent to another support pattern, and the area of the support pattern adjacent to the first type of pattern is greater than the area of the support pattern adjacent to the second type of pattern; and

[0009] Process the wafer according to the device design pattern and the support patterns to form the gate structure and the support structure.

[0010] In an embodiment of the present invention, the step of setting the support patterns includes: obtaining the blank area of the wafer, dividing the blank area into a first blank area, a second blank area, and a third blank area, where the first blank area surrounds the first type of pattern, the third blank area surrounds the second type of pattern, and the area other than the first blank area and the third blank area in the blank area is the second blank area.

[0011] In an embodiment of the present invention, the step of setting the support pattern further includes: setting a first support pattern, a second support pattern, and a third support pattern, wherein the area of the first support pattern is larger than the area of the second support pattern, and the area of the second support pattern is larger than the area of the third support pattern.

[0012] In an embodiment of the present invention, the step of setting the support pattern further includes: arranging a plurality of the first support patterns in the first blank area, arranging a plurality of the second support patterns in the second blank area, arranging a plurality of the third support patterns in the third blank area, and obtaining a device manufacturing pattern of the wafer.

[0013] In an embodiment of the present invention, the area of the first support pattern is greater than 0.04 μm 2 and less than or equal to 1 μm 2 , the area of the second support pattern is greater than or equal to 0.01 μm 2 and less than or equal to 0.04 μm 2 , the area of the third support pattern is less than or equal to 1225 nm 2 .

[0014] In an embodiment of the present invention, in the step of arranging the first support pattern, the second support pattern, and the third support pattern, obtain the density range requirement of the blank area, and arrange the first support pattern, the second support pattern, and the third support pattern according to the density range requirement.

[0015] In an embodiment of the present invention, the manufacturing method of the semiconductor structure includes: setting a pattern length threshold, the pattern length of the first type of pattern is less than or equal to the pattern length threshold, and the pattern length of the second type of pattern is greater than the pattern length threshold, wherein the pattern length threshold is 100 nm.

[0016] In an embodiment of the present invention, the step of processing the wafer includes:

[0017] Forming a gate oxide layer on the wafer;

[0018] Forming a polysilicon layer on the gate oxide layer;

[0019] According to the device design pattern and the support pattern, patterning the gate oxide layer and the polysilicon layer to form a pseudo-gate structure and a first support structure;

[0020] Forming an interlayer dielectric layer on the pseudo-gate structure, on the first support structure, and on the wafer;

[0021] Planarize the interlayer dielectric layer so that the surfaces of the interlayer dielectric layer, the first support structure, and the dummy gate structure are flush;

[0022] Remove the polysilicon layer in the first support structure and the polysilicon layer of the dummy gate structure to form a deposition trench; and

[0023] Fill the deposition trench to form a gate structure and a second support structure.

[0024] The present invention provides a semiconductor structure. Based on the manufacturing method of a semiconductor structure as described above, the semiconductor structure includes:

[0025] A wafer, the wafer including a blank area and a device area;

[0026] A gate structure disposed in the device area, the pattern of the gate structure including a first type of pattern and a second type of pattern, wherein the length of the second type of pattern is greater than that of the first type of pattern; and

[0027] A support structure disposed in the blank area, the support structure being adjacent to the gate structure or adjacent to another support structure, wherein the graphic area of the support structure adjacent to the first type of pattern is greater than the graphic area of the support structure adjacent to the second type of pattern.

[0028] In an embodiment of the present invention, the support structure is divided into a first support structure, a second support structure, and a third support structure, wherein the first support structure is adjacent to the gate structure of the first type of pattern, the third support structure is adjacent to the gate structure of the second type of pattern, the second support structure is located between the first support structure and the third support structure, wherein the area of the second support structure is greater than the area of the third support structure, and the area of the second support structure is less than the area of the first support structure.

[0029] As described above, the present invention provides a manufacturing method and a semiconductor structure of a semiconductor structure. The unexpected technical effect of the present invention is that it can improve the manufacturing yield of the gate structure, form a gate structure with a flush surface and consistent height on the same wafer, improve the layer uniformity of each device and chip on the wafer, improve the consistency between devices on the wafer, which can not only improve the manufacturing yield of the device, but also be beneficial to improving the accuracy of wafer testing.

[0030] Of course, it is not necessary for any product implementing the present invention to achieve all the above advantages simultaneously. Description of the Drawings

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0032] Figure 1 FIG. 4 is a schematic diagram of device distribution on a wafer in an embodiment of the present invention.

[0033] Figure 2 FIG. 4 is a flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the present invention.

[0034] Figure 3 FIG. 1 is a schematic diagram showing the relationship between the gate structure length and the oxide layer thickness in an embodiment of the present invention.

[0035] Figure 4 FIG. 1 is a flow chart of step S30 in an embodiment of the present invention.

[0036] Figure 5 FIG. 4 is a schematic diagram of the distribution of blank areas in an embodiment of the present invention.

[0037] Figure 6 Schematic diagram of the distribution of support patterns in one embodiment of the present invention.

[0038] Figure 7 It is a schematic diagram of the structure of forming a gate oxide layer and a polysilicon layer in one embodiment of the present invention.

[0039] Figure 8 Schematic diagram of the structure of a dummy gate structure and a first supporting structure corresponding to a first type of graphic in an embodiment of the present invention.

[0040] Figure 9 Schematic diagram of the structure of the dummy gate structure and the first supporting structure corresponding to the second type of graphics in one embodiment of the present invention.

[0041] Figure 10 FIG. 4 is a schematic diagram of the structure of a planarized interlayer dielectric layer in one embodiment of the present invention.

[0042] Figure 11 FIG. 4 is a schematic diagram of the structure of a planarized interlayer dielectric layer in one embodiment of the present invention.

[0043] Figure 12 FIG. 4 is a schematic diagram of a structure for forming a deposition groove in one embodiment of the present invention.

[0044] Figure 13 FIG. 4 is a schematic diagram of a structure for forming a deposition groove in one embodiment of the present invention.

[0045] In the figure: 100, wafer; 101, chip particles; 102, cutting roads; 103, blank areas; 104, semiconductor devices; 1041, substrate; 1042, gate oxide layer; 1043, polysilicon layer; 105, pseudo gate structure; AA, first type of graphics; BB, second type of graphics; 200, first supporting graphics; 300, second supporting graphics; 400, third supporting graphics. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] The design of integrated circuits is very complex. A chip can easily use millions to billions of logic gates (gate count), and the electrical parameters of each logic gate and other devices must meet the standards at the same time, otherwise the chip may not function properly. A wafer usually has tens to tens of thousands of chips, so it is very important to maintain the uniformity of the process. During the process, the monitoring of the key electrical and physical properties of the wafer requires not only that the entire wafer meet the standards, but also that each wafer produced meet this standard. Therefore, process control monitoring (PCM) must be introduced to improve quality monitoring.

[0048] See also Figure 1 As shown, the present invention provides a method for manufacturing a semiconductor structure, first obtaining a wafer 100 and a device design pattern of the wafer 100. The wafer 100 is used to carry and form a plurality of chip particles 101. The chip particles 101 include a plurality of semiconductor devices 104, and the semiconductor devices 104 are electrically connected through at least one layer of metal wiring and a plurality of contact plugs. The device design pattern is a design pattern of the semiconductor device 104. In this embodiment, the semiconductor device 104 includes at least a gate structure. The gate structure is, for example, a metal gate with a high dielectric constant. The semiconductor device 104 may also include a drain region and a source region, as well as a plurality of doped regions for realizing specific circuit functions. The present invention does not limit this. In this embodiment, the device design pattern includes a pattern of a gate structure, and patterns of other functional areas of the semiconductor device 104. The present invention does not limit patterns of other functional areas of the semiconductor device 104.

[0049] See also Figure 1As shown, in one embodiment of the present invention, the semiconductor device 104 can be a field effect transistor (Field Effect Transistor, FET), a metal-oxide semiconductor field effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET), a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS), an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), a fast recovery diode (Fast Recovery Diode, FRD), a high-speed and high-efficiency rectifier diode (High Efficiency Diode, HED), a constant voltage diode, a high-frequency diode, a light-emitting diode (Light-Emitting Diode, LED), a gate light-closed thyristor (GTO), a light-triggered thyristor (Light Triggered Thyristor, LTT), a thyristor (Thyristor), a charge coupled device (Charge Coupled Device, CCD image sensor), a digital signal processor (Digital Signal processor, DSP), a photo relay (Photo Relay) or a microprocessor (Micro One or more of the semiconductor devices 104 such as processor.

[0050] See also Figure 1 and Figure 2 As shown, the method for manufacturing a semiconductor structure provided by the present invention includes steps S10 to S40.

[0051] Step S10 , obtaining a device design pattern of the wafer 100 , wherein the device design pattern includes a pattern of a gate structure.

[0052] Step S20 , dividing the patterns of the gate structure into first-type patterns AA and second-type patterns BB according to the pattern lengths of the gate structure, wherein the lengths of the second-type patterns BB are greater than the lengths of the first-type patterns AA.

[0053] Step S30, setting a support pattern in the blank area 103 of the wafer 100, wherein the support pattern is adjacent to the pattern of the gate structure or adjacent to another support pattern, and the area of ​​the support pattern adjacent to the first type of pattern AA is larger than the area of ​​the support pattern adjacent to the second type of pattern BB.

[0054] Step S40: processing the wafer 100 according to the device design pattern and the support pattern to form a gate structure and a support structure.

[0055] See also Figures 1 to 3 As shown, in one embodiment of the present invention, in step S10, the device design graphics of the wafer 100 are obtained from the computer, and the graphics of the gate structure are selected from the device design graphics of the wafer 100. In this embodiment, the gate structure graphics can be obtained by filtering the graphic names. In step S20, the graphic length of the gate structure is obtained. In this embodiment, a graphic length threshold is set, and the gate structure is divided into a first type of graphics AA and a second type of graphics BB according to the graphic length threshold. The graphic length of the first type of graphics AA is less than or equal to the graphic length threshold, and the graphic length of the second type of graphics BB is greater than the graphic length threshold. The graphic length threshold is 100nm. Figure 3 The relationship between the gate length and the thickness of the hard mask layer HM and the oxide layer OX is shown. Figure 3 The horizontal axis represents the gate length, and the vertical axis represents the layer thickness of the hard mask layer and the oxide layer. When the gate length is greater than 100 nm, the thickness of the hard mask layer HM and the oxide layer OX does not change much, so the pattern length threshold is set to, for example, 100 nm to distinguish the two gate structures.

[0056] See also Figure 1 , Figure 2 and Figure 4 As shown, in one embodiment of the present invention, the area on the wafer 100 is divided into a device area and a blank area 103. The device area is the area occupied by the device design pattern. The area other than the device area is the blank area 103. In this embodiment, step S30 includes steps S31 to S33.

[0057] Step S31 , obtaining the blank area 103 of the wafer 100 , dividing the blank area 103 into a first blank area 103 , a second blank area 103 and a third blank area 103 , wherein the first blank area 103 surrounds the first type of graphics AA, and the third blank area 103 surrounds the second type of graphics BB.

[0058] Step S32 , setting a first supporting pattern 200 , a second supporting pattern 300 and a third supporting pattern 400 , wherein the area of ​​the first supporting pattern 200 is larger than that of the second supporting pattern 300 , and the area of ​​the second supporting pattern 300 is larger than that of the third supporting pattern 400 .

[0059] Step S33, arranging multiple first support patterns 200 in the first blank area 103, arranging multiple second support patterns 300 in the second blank area 103, arranging multiple third support patterns 400 in the third blank area 103, and obtaining the device manufacturing pattern of the wafer 100.

[0060] See also Figure 1 and Figure 2 , Figure 4 and Figure 5 As shown, in one embodiment of the present invention, a test key is provided in the cutting path 102. The blank area 103 on the wafer 100 may be a blank area 103 in a single chip, or may be a blank area 103 on the wafer 100 outside the chip, such as an area in the cutting path 102 excluding the test key, such as an area excluding the chip and the cutting path 102. In step S30, a support pattern is planned in the blank area 103. In step S31, the area surrounding the first type of pattern AA is marked as the first blank area 103, and the area surrounding the second type of pattern BB is marked as the third blank area 103. The area in the blank area 103 except the first blank area 103 and the second blank area 103 is marked as the second blank area 103. Among them, the second blank area 103 is located between the first blank area 103 and the third blank area 103. The present invention does not limit the area of ​​the first blank area 103 and the third blank area 103. The length and width of the blank area 103 are greater than the maximum length of the supporting pattern to ensure that the blank area 103 can accommodate at least one row of supporting patterns. In this embodiment, the first blank area 103 and the third blank area 103 can be in the shape of a Chinese character "回". The Chinese character "回" can be expressed as a square outer frame and a square inner frame, wherein the center of the square outer frame and the center of the positive direction inner frame are consistent. The Chinese character "回" can also be expressed as a rectangular outer frame and a rectangular inner frame, wherein the center of the rectangular outer frame and the center of the rectangular inner frame are consistent. Figure 5 As shown, the present invention does not limit the shape of the second blank area 103 .

[0061] See also Figure 1 and Figure 2 , Figures 4 to 6As shown, in one embodiment of the present invention, in step S32, a first support pattern 200, a second support pattern 300 and a third support pattern 400 are set. The first support pattern 200 is set in the first blank area 103, the second support pattern 300 is set in the second blank area 103, and the third support pattern 400 is set in the third blank area 103. In this embodiment, the area of ​​the first support pattern 200 is greater than the area of ​​the second support pattern 300, and the area of ​​the second support pattern 300 is greater than the area of ​​the third support pattern 400. In this embodiment, the area of ​​the first support pattern 200 is greater than 0.04μm² and less than or equal to 1μm², the area of ​​the second support pattern 300 is greater than or equal to 0.01μm² and less than or equal to 0.04μm², and the area of ​​the third support pattern 400 is less than or equal to 1225nm 2 .

[0062] See also Figure 1 and Figure 2 , Figures 4 to 6 As shown, in one embodiment of the present invention, in step S33, in the step of arranging the first support pattern 200, the second support pattern 300 and the third support pattern 400, the density range requirement of the blank area 103 is obtained, and the first support pattern 200, the second support pattern 300 and the third support pattern 400 are arranged according to the density range requirement and the critical size requirement. In this embodiment, the first support pattern 200, the second support pattern 300 and the third support pattern 400 can be randomly arranged by the system. After the arrangement is completed, check whether the arranged pattern meets the density range requirement and the critical size requirement. The density range requirement is reflected in the number of patterns per unit area, for example, the number of patterns per unit area is required to be 3-5. The present invention does not limit the threshold value of the density range. The critical size requirement is reflected in the minimum spacing between the patterns, for example, the spacing between the patterns is required to be greater than 12nm. The present invention does not limit the value of the critical size. In this embodiment, in a single blank area 103, the spacing between multiple support patterns can be equal or unequal. The spacing between the support patterns between different blank areas 103 may be equal or unequal. In this embodiment, multiple rows and columns of support patterns may be arranged in a single blank area 103, or a single row and column of patterns may be arranged. In this embodiment, when arranging the support patterns, when the remaining blank area 103 is not enough to place a support pattern, the arrangement is stopped. The device manufacturing pattern is obtained by combining the support pattern and the pattern of the gate structure.

[0063] See also Figure 1 and Figure 2 , Figure 7As shown, in one embodiment of the present invention, in step S40, the wafer 100 is processed according to the device manufacturing pattern. The steps of processing the wafer 100 are as follows. The wafer 100 includes a substrate 1041, a gate oxide layer 1042 is formed on the wafer 100, and a polysilicon layer 1043 is formed on the gate oxide layer 1042. The substrate 1041 is, for example, a silicon substrate for forming a semiconductor structure. The substrate 1041 may include a substrate and a silicon layer disposed above the substrate, and the substrate may be, for example, silicon (Si), silicon carbide (SiC), sapphire (Al 2 O 3 ), gallium arsenide (GaAs), lithium aluminate (LiAlO 2 ) and other semiconductor substrate materials, a silicon layer is formed on the substrate. In this embodiment, silicon dioxide is deposited on the substrate 1041 by chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD) to form a gate oxide layer 1042. Then, polysilicon is deposited on the gate oxide layer 1042 by chemical vapor deposition plasma enhanced chemical vapor deposition to form a polysilicon layer 1043. The thickness of the polysilicon layer 1043 and the gate oxide layer 1042 is set according to the design requirements of the semiconductor device 104, and the present invention does not limit it.

[0064] See also Figure 1 and Figure 2 , Figures 7 to 9 As shown, in one embodiment of the present invention, the gate oxide layer 1042 and the polysilicon layer 1043 are patterned according to the device design pattern and the support pattern to form a pseudo gate structure 105 and a first support structure. Then, an interlayer dielectric layer is formed on the pseudo gate structure 105, on the first support structure and on the wafer 100. In the step of patterning the gate oxide layer 1042 and the polysilicon layer 1043, a photoresist layer is first formed on the polysilicon layer 1043, and then the photoresist layer is patterned by exposure etching. Then, using the photoresist layer as a mask, the polysilicon layer 1043 and the gate oxide layer 1042 are etched to form a pseudo gate structure 105 at a position corresponding to the gate structure pattern, and a support structure at a position corresponding to the support pattern. As shown Figure 8 As shown, Figure 8 The pattern of the dummy gate structure 105 shown is a first type pattern AA, and adjacent to the dummy gate structure 105 of the first type pattern AA is a first support structure of the first support pattern 200. Figure 9 As shown, Figure 9The figure of the pseudo gate structure 105 shown is a second type figure BB, and adjacent to the pseudo gate structure 105 of the second type figure BB is a third support structure of the first support figure 200. After the pseudo gate structure 105 is formed, before the interlayer dielectric layer, a sidewall structure can be formed on the side of the pseudo gate structure 105 by a sidewall formation process, wherein the sidewall structure may include at least one silicon nitride layer and may also include a silicon oxide layer. The silicon nitride layer may cover the top of the polysilicon layer 1043. In this embodiment, silicon oxide is deposited on the substrate 1041, on the first support structure, on the pseudo gate structure 105, and on the sidewall structure by chemical vapor deposition plasma enhanced chemical vapor deposition and the like, thereby forming an interlayer dielectric layer. It should be noted that the sidewall structure can be simultaneously formed on the side of the first support structure.

[0065] See also Figure 1 and Figure 2 , Figures 9 to 11 As shown, in one embodiment of the present invention, the interlayer dielectric layer is then planarized to make the surface of the interlayer dielectric layer, the surface of the first support structure and the surface of the dummy gate structure 105 flush. In this embodiment, in the step of planarizing the interlayer dielectric layer, the top surface of the dummy gate structure 105 can be used as a stop layer to process the interlayer dielectric layer by chemical mechanical polishing (CMP). The top surface of the dummy gate structure 105 can be the surface of the polysilicon layer 1043, or can be the silicon oxide layer or silicon nitride layer when forming the sidewall structure.

[0066] See also Figure 1 and Figure 2 , Figures 11 to 13 As shown, in one embodiment of the present invention, the polysilicon layer 1043 in the first support structure and the polysilicon layer 1043 of the pseudo gate structure 105 are removed to form a deposition groove. The length of the deposition groove is equal to the length of the corresponding support pattern or gate pattern. Then, the deposition groove is filled with a metal material, a gate structure is formed at the position of the original pseudo gate structure 105, and a second support structure is formed at the position of the original first support structure. After polishing and etching are completed, the surface of the interlayer dielectric layer in each area is flush and flush with the surface of the sidewall structure. Then, after the gate structure and the second support structure are formed, a level with a flush surface can still be obtained with good support, thereby forming a semiconductor device 104 with uniform properties.

[0067] The present invention provides a method for manufacturing a semiconductor structure and a semiconductor structure, the method comprising the following steps: obtaining a device design pattern of a wafer, wherein the device design pattern includes a pattern of a gate structure; dividing the pattern of the gate structure into a first type of pattern and a second type of pattern according to the length of the pattern of the gate structure, wherein the length of the second type of pattern is greater than the first type of pattern; setting a support pattern in a blank area of ​​the wafer, wherein the support pattern and the pattern of the gate structure are adjacent or adjacent to another support pattern, and the area of ​​the support pattern adjacent to the first type of pattern is greater than the area of ​​the support pattern adjacent to the second type of pattern; and processing the wafer according to the device design pattern and the support pattern to form a gate structure and a support structure. The unexpected technical effect of the present invention is that it can improve the manufacturing yield of the gate structure, and form a gate structure with a flush surface and high consistency on the same wafer, improve the level uniformity of each device and chip on the wafer, and improve the consistency between devices on the wafer, which can not only improve the manufacturing yield of the device, but also help to improve the accuracy of wafer testing.

[0068] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: Acquire a device design pattern of a wafer, wherein the device design pattern includes a pattern of a gate structure; According to the length of the pattern of the gate structure, the pattern of the gate structure is divided into a first type of pattern and a second type of pattern, wherein the length of the second type of pattern is greater than the length of the first type of pattern; A support pattern is arranged in a blank area of ​​the wafer, wherein the support pattern is adjacent to the pattern of the gate structure or adjacent to another support pattern, and the area of ​​the support pattern adjacent to the first type of pattern is larger than the area of ​​the support pattern adjacent to the second type of pattern, wherein the step of arranging the support pattern comprises: Acquire a blank area of ​​the wafer, and divide the blank area into a first blank area, a second blank area, and a third blank area, wherein the first blank area surrounds the first type of graphics, the third blank area surrounds the second type of graphics, and the area in the blank area other than the first blank area and the third blank area is the second blank area; providing a first supporting pattern, a second supporting pattern and a third supporting pattern, wherein the area of ​​the first supporting pattern is larger than the area of ​​the second supporting pattern, and the area of ​​the second supporting pattern is larger than the area of ​​the third supporting pattern; and Arrange a plurality of the first support patterns in the first blank area, arrange a plurality of the second support patterns in the second blank area, arrange a plurality of the third support patterns in the third blank area, and obtain a device manufacturing pattern of the wafer; The wafer is processed according to the device design pattern and the support pattern to form the gate structure and the support structure.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The area of ​​the first supporting pattern is greater than 0.04 μm 2 And less than or equal to 1μm 2 The area of ​​the second supporting pattern is greater than or equal to 0.01 μm 2 And less than or equal to 0.04μm 2 The area of ​​the third supporting pattern is less than or equal to 1225nm 2 .

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: In the step of arranging the first supporting pattern, the second supporting pattern and the third supporting pattern, a density range requirement of the blank area is obtained, and the first supporting pattern, the second supporting pattern and the third supporting pattern are arranged according to the density range requirement.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The manufacturing method of the semiconductor structure includes: setting a graphic length threshold, the graphic length of the first type of graphics is less than or equal to the graphic length threshold, and the graphic length of the second type of graphics is greater than the graphic length threshold, wherein the graphic length threshold is 100nm.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The steps of processing the wafer include: forming a gate oxide layer on the wafer; forming a polysilicon layer on the gate oxide layer; According to the device design pattern and the support pattern, patterning the gate oxide layer and the polysilicon layer to form a dummy gate structure and a first support structure; forming an interlayer dielectric layer on the dummy gate structure, the first supporting structure and the wafer; Planarizing the interlayer dielectric layer to make the surface of the interlayer dielectric layer, the surface of the first supporting structure and the surface of the dummy gate structure flush; removing the polysilicon layer in the first supporting structure and the polysilicon layer of the dummy gate structure to form a deposition trench; and The deposition trench is filled to form a gate structure and a second supporting structure.

6. A semiconductor structure, based on the method for manufacturing a semiconductor structure according to claim 1, characterized in that: The semiconductor structure comprises: A wafer, wherein the wafer comprises a blank area and a device area; A gate structure is disposed in the device region, wherein the pattern of the gate structure includes a first type of pattern and a second type of pattern, wherein the length of the second type of pattern is greater than the length of the first type of pattern; and A support structure is arranged in the blank area, and the support structure is adjacent to the gate structure or adjacent to another support structure, wherein the graphic area of ​​the support structure adjacent to the first type of graphics is larger than the graphic area of ​​the support structure adjacent to the second type of graphics.

7. A semiconductor structure according to claim 6, characterized in that: The support structure is divided into a first support structure, a second support structure and a third support structure, wherein the first support structure is adjacent to the gate structure of the first type of graphics, the third support structure is adjacent to the gate structure of the second type of graphics, and the second support structure is located between the first support structure and the third support structure, wherein an area of ​​the second support structure is larger than an area of ​​the third support structure, and an area of ​​the second support structure is smaller than an area of ​​the first support structure.

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