IC assembly with self-aligned structure with zero misalignment

Abstract

The subject matter of the invention is an IC assembly with a self-aligned structure with zero misalignment. A surface of an integrated circuit (IC) die structure or a main structure to which the IC die structure is to be bonded includes a biphilic surface for droplet formation and droplet-based fine alignment of the IC die structure with the substrate. The hydrophobic region can be self-aligned with the hydrophilic region of the hydrophilic and hydrophobic surface by forming a metallization feature in the hydrophilic region while forming a precursor metallization feature in the hydrophobic region. The metallization feature within the hydrophobic region may then be at least partially removed as a sacrificial to promote formation of the hydrophobic surface. Metallization features within the hydrophilic region may be retained and ultimately bonded to complementary features of another IC die structure or substrate structure.

Description

Background Art

[0001] Integrated circuit (IC) dies can be assembled using solder attach techniques, where solder features contact to bond the die to a host structure. However, solder assembly techniques are difficult to scale down to less than solder joint feature pitches within tens of microns (eg, 10-25 μm).

[0002] The IC die can alternatively be assembled using a hybrid bonding technique, in which the metal joints of the IC die are directly interdiffused with the corresponding metal joints of the main structure. When a bond is also formed between the dielectric materials adjacent to the metal joints, such a bond is called "hybrid". During the hybrid bonding process, components (e.g., dies) with corresponding joints are brought together to butt against each other. At room temperature, the dielectric materials are sufficiently adhered to establish an initial bond (e.g., due to van der Waals forces). Thermal annealing can then fuse the complementary metal joints and also increase the strength of the dielectric material bonding interface. Hybrid bonding technology can be well expanded at bonding feature spacings below 1 μm. However, such nano-pitch assembly techniques rely on fine alignment of the IC die to the nanoscale (e.g., <500nm) of the main structure, and achieving such fine alignment may be time-consuming and / or expensive.

[0003] Therefore, techniques and architectures for hybrid bonding at the nanoscale in large-scale manufacturing would be commercially advantageous. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] In the accompanying drawings, the material described herein is illustrated by way of example and not by way of limitation. For simplicity and clarity of illustration, the elements shown in the accompanying drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements. In addition, where deemed appropriate, reference numerals have been repeated among the accompanying drawings to indicate corresponding or similar elements. In the accompanying drawings:

[0005] Figure 1 is a flow chart illustrating a method for self-alignment assisted assembly (SA3) of an integrated circuit (IC) die structure according to some embodiments;

[0006] Figure 2A is a cross-sectional view of a trench patterning of a master structure according to some embodiments;

[0007] Figure 2B According to some embodiments Figure 2A A plan view of the main structure shown in;

[0008] Figure 3A is a cross-sectional view of a metal joint feature and an adjacent metal alignment feature of a primary structure according to some embodiments;

[0009] Figure 3BAccording to some embodiments Figure 3A A plan view of the main structure shown in;

[0010] Figure 4A is a cross-sectional view of a selective recess of a metal alignment feature of a master structure according to some embodiments;

[0011] Figure 4B According to some embodiments Figure 4A A plan view of the main structure shown in;

[0012] Figure 5A is a cross-sectional view of a hydrophobic feature on a primary structure according to some embodiments;

[0013] Figure 5B According to some embodiments Figure 5A A plan view of the main structure shown in;

[0014] Fig. 6A is a cross-sectional view of a wafer or panel including a plurality of main structures, each main structure including a hydrophilic and hydrophobic surface structure, according to some embodiments;

[0015] Figure 6B According to some embodiments Fig. 6A A plan view of a wafer or panel as shown in FIG.

[0016] Fig. 7A is a cross-sectional view of an IC die structure roughly aligned and placed on a droplet confined to a bonding area according to some embodiments;

[0017] Figure 7B is the alignment and placement according to some embodiments Fig. 7A A plan view of the IC die structure;

[0018] Fig. 8A is a cross-sectional view of a composite structure including an IC die structure hybrid bonded to a bonding region of a hydrophilic-hydrophobic structure according to some embodiments;

[0019] Figure 8B According to some embodiments Fig. 8A A plan view of the composite structure shown in ;

[0020] Fig. 9A is a cross-sectional view of a composite structure including an IC die structure and a dielectric material therebetween according to some embodiments;

[0021] Fig. 9B According to some embodiments Fig. 8A A plan view of the composite structure shown in;

[0022] Fig.10is a cross-sectional view of a system including a heat sink and a main assembly assembled with a hybrid bonded composite structure further including an IC die structure according to some embodiments;

[0023] Fig.11A is a cross-sectional view of a trench patterning of a master structure according to some alternative embodiments;

[0024] Fig. 11B According to some embodiments Fig.11A A plan view of the main structure shown in;

[0025] Fig. 12A is a cross-sectional view of a selective recess of a metal alignment feature in a primary structure according to some alternative embodiments;

[0026] Fig. 12B According to some alternative embodiments Fig. 12A A plan view of the main structure shown in;

[0027] Fig.13A is a cross-sectional view of a hydrophobic feature formed on a primary structure according to some alternative embodiments;

[0028] Fig. 13B According to some embodiments Fig.13A A plan view of the main structure shown in;

[0029] Fig.14 illustrates a mobile computing platform and a data server machine using a multi-chip package according to some embodiments; and

[0030] Fig.15 is a functional block diagram of an electronic computing device according to some embodiments. DETAILED DESCRIPTION

[0031] Embodiments are described with reference to the accompanying drawings. Although specific configurations and arrangements are described and discussed in detail, this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements are possible without departing from the spirit and scope of the description. It will be clear to those skilled in the relevant art that the techniques and / or arrangements described herein may be used in a variety of systems and applications in addition to those described in detail herein.

[0032] Reference is made in the following detailed description to the accompanying drawings, which form a part of the detailed description and illustrate exemplary embodiments. In addition, structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It is noted that directions and directional references such as up, down, top, bottom, etc. may be used only to facilitate the description of features in the accompanying drawings. Therefore, the following detailed description is not to be taken in a limiting sense, and the scope of the claimed subject matter is limited only by the appended claims and their equivalents.

[0033] In the following description, a lot of details are set forth. However, it will be clear to those skilled in the art that embodiments can be implemented without these specific details. In some instances, known methods and devices are shown in block diagram form rather than in detail to avoid blurring the embodiments. Throughout the specification, reference to "an embodiment" or "an embodiment" or "some embodiments" means that the specific features, structures, functions or characteristics described in conjunction with the embodiments are included in at least one embodiment. Therefore, the appearance of the phrase "in one embodiment" or "in one embodiment" or "some embodiments" in various places throughout this specification does not necessarily refer to the same embodiment. In addition, in one or more embodiments, specific features, structures, functions or characteristics can be combined in any suitable manner. For example, the first embodiment can be combined with the second embodiment anywhere where the specific features, structures, functions or characteristics associated with the two embodiments are not mutually exclusive.

[0034] As used in the description and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0035] The terms "coupled" and "connected" and their derivatives may be used herein to describe functional or structural relationships between components. These terms are not intended to be synonymous with each other. On the contrary, in a particular embodiment, "connected" may be used to indicate that two or more elements are in direct physical, optical or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect (with other intervening elements) physical or electrical contact with each other, and / or that two or more elements cooperate or interact with each other (e.g., as in a causal relationship).

[0036] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials where such physical relationship is noteworthy. For example, in the context of materials, a material or layer above or below another material or layer may be in direct contact, or may have one or more intervening materials or layers. Additionally, a material between two materials or layers may be in direct contact with both materials / layers, or may have one or more intervening materials / layers. Conversely, a first material or layer "above" a second material or layer is in direct contact with the second material / layer. In the context of component assembly, a similar distinction is to be made.

[0037] As used throughout this description and in the claims, a list of items connected by the term "at least one of" or "one or more of" may mean any combination of the listed terms. For example, the phrase "at least one of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0038] Unless otherwise indicated in the specific context of use, the term "predominantly" means more than 50%, or more than half. For example, a composition that is predominantly the first component means that more than half of the composition is the first component (e.g., >50at.%). The term "predominantly" means the majority or largest portion. For example, a composition that is predominantly the first component means that the composition has more of the first component than any other component. A composition that is predominantly the first and second components means that the composition has more of the first and second components than any other component. The term "substantially" means that only accidental variations exist. For example, a composition that is substantially the first component means that the composition may further include <1% of any other component. A composition that is substantially the first and second components means that the composition may further include <1% of any component that replaces the first or second component.

[0039] As previously described, hybrid bonding techniques provide advantages in assembling IC die structures to other IC die structures or some other main structure (such as a package substrate structure, an interposer structure, etc.). According to the embodiments described herein, the IC die structure may include any monolithic integrated circuit device that provides electrical, computing, memory, or similar functionality. The IC die structure itself may include more than one monolithic integrated circuit device. For example, the IC die structure may include two vertically stacked IC dies or two coplanar IC dies. The IC dies within the IC die structure may be directly bonded to each other or coupled by interconnect features. For example, the IC die structure according to the embodiments herein may be referred to as a "chiplet", "chiplet die", "dice", "tile", or "chip". Although the terms chiplet and IC die or chip may be used interchangeably, a full-function ASIC is generally considered to be an IC die or chip, while a chiplet or tile will have more limited functionality, such as supplementing one or more other IC chiplets to be part of the same multi-chiplet device. The chiplets or tiles may be, for example, wireless radio circuits, microprocessor cores, electronic memory circuits, floating point gate arrays (FPGAs), power management and / or power supply circuits, or include MEMS devices.

[0040] In the context of directly bonding IC die structures, self-aligned assisted assembly (SA3) can promote greater die-to-wafer hybrid bonding (D2W HB) yields by reducing the fine alignment burden. In some exemplary SA3 processes, the bonding area is incorporated into a "biphilic" or "heterogeneous" surface structure on the IC die structure or the main structure (or both the IC die structure and the main structure). As used herein, a biphilic / heterogeneous surface has a high wettability contrast between different regions thereof. As further described herein, the high wettability contrast can be achieved by physical patterning (e.g., creating grooves around the bonding area to confine liquid via a centripetal effect), chemical patterning (e.g., depositing a hydrophobic coating around the bonding area to reduce surface energy), or a combination of the two (e.g., creating grooves with hydrophobic coating sidewalls around the bonding area).

[0041] Within the hydrophilic and hydrophobic surface structure, one area has high wettability relative to another area with low wettability. This wettability contrast can improve the control of droplet diffusion so that the droplet can be confined to the junction of the IC die structure or the main structure (or both the IC die structure and the main structure). When the droplet evaporates, the surface tension of the droplet is used to passively finely align the IC die structure, so that the bonding area remains in contact and is ready for hybrid bonding. At room temperature, the surface attraction between the dielectric area on the IC die structure and the main structure may be sufficient to temporarily fix the two. A hybrid bond can then be formed by the application of pressure and / or elevated temperature to form and / or strengthen the bond between metal features (e.g., copper pads) dispersed in the surrounding dielectric material. Once bonded, the metal features form composite metal features that electrically interconnect the IC die structure and the main structure. However, in some embodiments, the bond may be only dielectric-dielectric or only metal-metal (e.g., for thermal applications or some RF applications).

[0042] With SA3, a bonder can pick and place an IC die structure on a host structure relying only on rough alignment (e.g., about 25-50 μm), enabling rapid assembly. When a droplet is confined to the bonding area between the IC die structure and the host structure, capillary forces and liquid surface tension induce alignment with high positional accuracy (e.g., <200 nm) due to hydrophilic or transitional structures on the mating surfaces of the IC die structure and / or the host structure. Therefore, such hydrophilic, heterogeneous, or transitional structures may be more specifically referred to as "self-aligned features" or "SA3 features."

[0043] As further described below, in order to enable excellent alignment performance during the hybrid bonding of the IC die structure to the main structure, the IC die structure and / or the main structure include a hydrophobic area that is self-aligned with the hydrophilic area. Utilize self-alignment, the error associated with the lateral or rotational offset between the hydrophobic and hydrophilic areas of the hydrophobic SA3 surface can be significantly reduced, with a misalignment that is substantially zero. As further described below, by forming a precursor metallization feature at the place where the hydrophobic area will eventually be located, the hydrophobic area can be self-aligned with the hydrophilic area. Such a precursor metallization feature can be formed simultaneously with the formation of the metallization feature in the hydrophilic area. Then, before or during the further processing responsible for forming the hydrophobic surface, these precursor metallization features can be at least partially removed. The precursor metallization feature can thus locate the hydrophobic surface feature without suffering from misalignment with the hydrophilic area. The metallization feature in the hydrophilic area can be protected during the further processing of the precursor metallization feature, and finally bonded to the complementary features of another IC die structure, package substrate structure or other main structures.

[0044] Figure 11 is a flow chart illustrating a self-alignment assisted assembly method 101 for an integrated circuit (IC) die structure according to some first embodiments. According to method 101, the IC die structure is assembled to a main structure by implementing one or more SA3 techniques. Prior to assembly, the IC die structure and / or the main structure are processed to form SA3 alignment features that self-align with metallization features to be joined during assembly. Method 101 can be implemented, for example, to form one or more of the composite assemblies described elsewhere herein. Method 101 is illustrated as including several discrete frames to ensure clarity of description. However, in practice, the number of frames and / or the order of such frames may be modified without departing from the principles illustrated by method 101.

[0045] Method 101 begins with input 110, where a host structure is received. The host structure can be part of any wafer, panel, strip, etc. suitable for forming joint features to be directly bonded or otherwise interconnected with one or more IC die structures. The joint features are formed in a bonding area of ​​the host structure. The bonding area is integrated into one or more hydrophilic and hydrophobic surfaces suitable for SA3 assembly.

[0046] In some embodiments, the primary structure received at input 110 is a base (package) substrate structure, and an IC die structure to be assembled with the substrate structure is received at input 115. In other embodiments, the primary structure received at input 110 is an IC die structure, and another IC die structure to be assembled with the primary IC die structure is received at input 115.

[0047] Method 101 continues at frame 112, where a joint feature is formed on the main structure. At frame 112, adjacent to the joint feature, an alignment feature precursor is also formed. In an exemplary embodiment, the alignment feature precursor is formed simultaneously with the joint feature. Therefore, the alignment feature precursor can be formed by a process substantially the same as the process used to manufacture the joint feature. Advantageously, the same photolithographic patterning process is implemented to simultaneously pattern both the joint feature and the alignment feature precursor to ensure that there is no misalignment between them. Since it is formed simultaneously, the alignment feature precursor can have a composition substantially the same as the joint feature. In some exemplary embodiments in which the joint feature includes metallization, the alignment feature precursor includes substantially the same metallization.

[0048] In some embodiments, block 112 includes a damascene metallization process suitable for use at a back-end metallization level of an IC die structure or a metallization level of a package substrate structure. The metallization process may, for example, include forming a trench in a dielectric material, filling the trench with metallization, and planarizing the metallization to expose the dielectric material around the metallization trench. For such embodiments, trenches corresponding to both the joint features and the alignment feature precursors may be defined with a single patterning process.

[0049] Figure 2A is a cross-sectional view of a trench patterning of a main structure 200 according to some embodiments. Figure 2B is a plan view of a main structure 200 according to some further embodiments. Figure 2A The cross section A-A' shown in Figure 2B The center is marked by a dot-dash line A-A'.

[0050] The main structure 200 includes one or more mask materials 214 on one or more substrate materials 201. The mask material 214 is patterned to have openings, and within these openings, trenches 228 and 229 are etched to a depth D1 in the substrate material 201. Figure 2B , the grooves 228 are arranged on the inner region of the main structure 200, while the grooves 229 are in the outer or peripheral region of the main structure 200. In the example shown, the grooves 229 are continuous around the perimeter of the grooves 228. However, alternative embodiments may include multiple grooves 229 that are laterally adjacent to one or more of the grooves 228.

[0051] The substrate material 201 may vary depending on the implementation. In some embodiments where the main structure 200 is a package substrate structure or a package interposer structure, the substrate material 201 may include one or more structural material layers, such as semiconductor materials (single crystals), sapphire or glass. The substrate material 201 may include any material found in an integrated circuit wafer, such as semiconductor materials (e.g., silicon, germanium, GaN, GaAs, InP, InGaAS, etc.), interconnect layers on the die (e.g., copper, aluminum, tantalum, other metals), and dielectrics on the die (e.g., silicon dioxide, carbon-doped silicon dioxide, silicon nitride, silicon carbide, etc.). For glass embodiments, the structural material may be predominantly silica (e.g., silicon and oxygen), and may further include one or more elements, such as hydrogen, carbon and / or metals, such as, but not limited to, copper, silver, gold, aluminum, beryllium, magnesium, calcium, strontium, barium or radium. Additional dopants (e.g., boron, phosphorus) may also be present in the structural material (e.g., borosilicate glass, etc.).

[0052] The substrate material 201 may also include one or more layers of metallization features 202. The metallization features 202 may be embedded, for example, in a dielectric material. For example, the dielectric material may have been built onto one or more sides of a structural material layer. The structural material layer may be retained or eventually discarded so that the substrate material 201 may include only the dielectric material and the embedded wiring metallization features 202.

[0053] The dielectric material can be an organic dielectric such as an epoxy resin, a phenolic glass, or a resin film such as the GX series films available from Ajinomoto Fine-Techno Co., Inc. (ABF). The organic dielectric material can include an epoxy resin (e.g., an acrylate ester of a phenolic novolac such as epoxy phenol novolac (EPN, phenol novolac epoxy resin) or epoxy cresol novolac (ECN, o-cresol novolac epoxy resin)). In other examples, the encapsulating dielectric material includes an aliphatic epoxy resin, which can be monofunctional (e.g., dodecanol glycidyl ether), difunctional (butylene glycol diglycidyl ether), or have a higher functionality (e.g., trimethylolpropane triglycidyl ether).

[0054] The main structure 200 may also include an inorganic dielectric material (e.g., including at least 20 atomic % of one or more of silicon, oxygen, or nitrogen). In some embodiments, the inorganic dielectric material is primarily silicon and oxygen (e.g., SiO2), primarily silicon and nitrogen (e.g., Si3N2), or primarily silicon, oxygen, and nitrogen (e.g., Si x O y N x ), any of which may further include one or more dopants, such as carbon. Inorganic dielectric materials are different from organic dielectrics (e.g., epoxy resins and phenolic glass), which have much higher carbon content and a higher percentage of carbon-hydrogen bonds. In some exemplary embodiments, trenches 228 and 229 are fabricated into the inorganic dielectric material.

[0055] The substrate material 201 may also include one or more IC die structures (not depicted). In some embodiments where the main structure 200 is a package substrate or interposer, the IC die structure is embedded within a dielectric material. In other embodiments, the main structure 200 is an IC die structure. Such an IC die structure may be a fully functional ASIC, or may be a chiplet or tile of more limited functionality to complement one or more other IC die structures to be part of the same multi-chip device. For embodiments where the main structure 200 is an IC die structure, the substrate material 201 may include any of those typical materials of a monolithically manufactured IC die, such as, but not limited to, device material layers and / or silicon (e.g., single crystal) layers, and inorganic dielectric materials (e.g., including at least 20 atomic % of one or more of silicon, oxygen, or nitrogen).

[0056] Any suitable metallization may be formed within trenches 228 and 229. In some embodiments, a barrier material such as, but not limited to, Ti, TiN, Ta, or TaN may be deposited as a liner within trenches 228 and 229. In some further embodiments, a fill metal is deposited over the barrier material. An exemplary fill metal predominantly comprises Cu, but may alternatively predominantly comprise another metal, such as W or Ru. Figure 3A 2 is a cross-sectional view after metallization is formed in trenches 228 and 229. According to some exemplary embodiments, joint feature 230 and adjacent alignment feature precursor 231 are metallized. Because trenches 228, 229 are etched to the same depth D1, the bottom surface of joint feature 230 is substantially coplanar with the bottom surface of alignment feature precursor 231. Figure 3B As further shown in the plan view of FIG. 2 , all features in the joint feature 230 are substantially surrounded by one continuous alignment feature precursor 231. As a result of the simultaneous trench patterning, the alignment feature precursor 231 has no misalignment with the joint feature 230.

[0057] Back to Figure 1, method 101 continues at box 114, where the alignment feature precursors are further processed to convert them into alignment features suitable for self-alignment assisted assembly. This additional processing can be selective to the alignment feature precursors (e.g., performed while the junction features are masked). In some embodiments, at least a portion of the alignment feature precursors is removed and / or recessed, for example to restore a portion of the topography associated with the previous groove patterning. The alignment feature precursors are advantageously recessed relative to the junction features. Depending on the material or chemical composition of the alignment feature precursors (one or more), one or more etching processes can be used at box 114. As described above, high wettability contrast can be achieved by physical patterning (e.g., creating grooves around the junction area to confine the liquid via an oblique effect). Therefore, restoring at least a portion of the grooves at box 114 can be an aspect of manufacturing SA3 alignment features from a precursor that does not have misalignment with the junction features.

[0058] The topographical features generated at block 114 can advantageously increase the wettability contrast relative to the bonding region. Such topographical features (e.g., grooves) can change the effective contact angle of the droplet to greater than 90° and thereby alter the surface energy characteristics of the droplet. In some further embodiments, block 114 results in the topographical features having a significantly higher average surface roughness than in the bonding region. Thus, block 114 can include any surface texturing technique, such as laser surface roughening.

[0059] exist Figure 4A and Figure 4B In the example further shown in , although one or more mask materials 214 are in the joint area 203 to protect the joint feature 230, the metallization is substantially removed from the alignment feature precursor to form an alignment feature including a groove 229. In some embodiments where the metallization includes both a barrier material and a fill metal, at least the fill metal is substantially removed in the peripheral area 205. Any etching process suitable for a particular fill metal can be used to recess and / or remove the fill metal. In some examples where the fill metal is predominantly Cu, the main structure 200 can be exposed to a wet chemical etchant capable of dissolving Cu (or its oxide). Dry etching (e.g., atomic layer etching) and / or other plasma-based processes can also be used in combination with wet chemical etching, or as an alternative to wet chemical etching. For example, after etching the fill metal, the barrier material (e.g., Ta) can be removed with a plasma etching process. Other barrier material compositions (such as those comprising Ti) can be removed with a wet chemical process or a dry etching process. With at least the fill metal being substantially removed, the groove 229 approaches the depth D1 again. Thus, the bottom surface of the groove 229 can be substantially coplanar with the joint feature 230, such as Figure 4A Indicated by the dotted line.

[0060] The surface of the groove 229 can advantageously have a rougher surface roughness than the surface roughness of the adjacent joining area. For example, the joint feature 230, as protected by the mask material 214, can have a lower surface roughness (e.g., an average roughness of <15 nm for metallization and an average roughness of <1 nm for dielectrics), while the groove 229 has a higher surface roughness (e.g., an average roughness of >50 nm). In some embodiments, the average surface roughness of the bottom of the groove 229 is at least twice the average surface roughness of the surface of the joint feature 230, and can be five times, ten times, or twenty times the average surface roughness of the joint feature 230. As used herein, the average roughness (or centerline average) is as described in ASME B46.1. The average roughness is the arithmetic mean of the absolute values ​​of the profile height deviations from the center line recorded for the evaluation length. The average roughness can be measured, for example, with a profilometer or atomic force microscope (AFM) that includes a stylus that moves back and forth on the surface. For a surface having a longitudinal length in a first dimension (e.g., with a length greater than 100 nm), the average roughness can be measured. Figure 4B For groove 229 having a first dimension and a second dimension (e.g., coinciding with the y-axis in the longitudinal direction), the average roughness can be measured over a distance of approximately 60%-70% of the longitudinal length while remaining near a centerline of the lateral width of the groove 229, which is in a dimension substantially orthogonal to the first dimension (e.g., coinciding with the x-axis).

[0061] It is worth noting that some misalignment of the mask material 214 relative to the land features 230 and the trenches 229 can be expected, for example Figure 4A , Figure 4B However, because the etching process selectively recesses and / or removes metallization to the exposed substrate material 201 (eg, inorganic dielectric material), the position of the trench 229 is independent of such mask misalignment and thus remains perfectly aligned with the joint feature 230 .

[0062] Back to Figure 1 The method 101 continues at block 116 where the hydrophobicity of the alignment feature is enhanced. The hydrophobicity enhancement may include at least forming a hydrophobic material in a region peripheral to the bonding region.

[0063] Figure 5A and Figure 5BA cross-sectional view and a plan view of a hydrophobic feature 204 formed in a peripheral region 205 according to some embodiments are shown. The hydrophobic feature 204 ensures that the main structure 200 has a hydrophilic or transitional structure, wherein there is sufficient wettability contrast between the bonding area including the junction feature 230 (e.g., a bonding area with high wettability where a droplet is to be formed) and the adjacent peripheral region 205 (e.g., a peripheral region with low wettability where the droplet will be confined). The liquid used for self-alignment assisted assembly can vary (polar or non-polar, etc.). However, in the exemplary SA3 embodiment using water, the bonding area with high wettability is hydrophilic (i.e., causing the water droplet to have a contact angle of less than 90°). Therefore, when the liquid minimizes its surface energy, the water droplet will tend to spread over the bonding area. The peripheral region 205 with low wettability is hydrophobic (i.e., causing the water droplet to have a large contact angle greater than 90°). Therefore, the water droplets on the bonding area will tend to minimize contact with the peripheral region 205.

[0064] The coplanarity between the joint feature 230 and the SA3 alignment feature within the peripheral region 205 indicates that the alignment feature has been derived from an alignment feature precursor that was patterned simultaneously with the joint feature 230. For embodiments where some portion of the metallization remains within the trench 229, both the coplanarity shown and the presence of residual metallization (e.g., barrier material) indicate that the alignment feature has been derived from an alignment feature precursor that was patterned simultaneously with the joint feature 230. Figure 5A In the exemplary embodiment shown, because the hydrophobic feature 204 is formed within the trench 229, the bottom surfaces of the feature 204 and the junction feature 230 are coplanar along the xy plane P1. For embodiments where residual metallization (e.g., barrier material) remains in the trench 229, the hydrophobic feature 204 will be above and in direct contact with the residual metallization.

[0065] Feature 204 can include any chemical coating or film material and / or topographic structure, which enhances the hydrophobic boundary adjacent to one or more edges of the bonding area 203. In some embodiments, feature 204 includes a self-assembled monolayer (SAM) material, such as alkyl or fluoroalkyl silane (e.g., ODS, FDTS), thiol (e.g., hexadecanethiol), phosphonic acid (e.g., octadecyl or perfluorooctanephosphonic acid), or alkanoic acid (e.g., heptadecanoic acid). Other SAM embodiments can include disulfides, amines, azoles, amides, imides, pyridine derivatives, cyanoacrylate derivatives or other parts including sulfur atoms or nitrogen atoms. SAM reactions usually form monolayer molecules aligned to each other in a uniform manner. Such molecules can be introduced in the gas phase and "self-assembled" by forming highly selective bonds at the surface and making themselves face perpendicular to the surface. However, non-SAM-based materials or films are also possible. In some embodiments, feature 204 is or includes a polymer film, such as siloxane (e.g., PDMS and its derivatives, HMDSO), silazane (HMDS), polyolefin (e.g., PP) or fluorinated polymer (e.g., PTFE, PFPE, PFDA, C4F8 plasma polymerized film, etc.). In some advantageous embodiments, feature 204 has the following chemical composition: having at least ten atomic percent (at.%) carbon or at least 10 at.% fluorine.

[0066] After forming the hydrophobic feature(s) 204, the main structure 200 retains a plurality of joint features 230, each of which is to be joined to a corresponding IC die structure. Figure 5A In the example shown in FIG. 2 , feature 204 is in direct contact with the sidewalls of trench 229 (or in direct contact with the barrier material lining trench 229). However, feature 204 may be on any other surface of trench 229. Figure 5B As shown in , feature 204 substantially surrounds the base or table of substrate material 201 including junction feature 230. Feature 204 can be adjacent to multiple non-parallel edges of the junction area and / or formed on the sidewalls of the junction area according to any (one or more) suitable techniques. A conformal hydrophobic material layer can be formed on the exposed surface of the junction area, for example, using a spin coating or conformal vapor deposition process. The conformal hydrophobic material layer can then be patterned using an anisotropic "spacer" etch.

[0067] The main structure 200 may be part of a wafer or panel further comprising many such main structures. Fig. 6A6 is a cross-sectional view of an exemplary wafer (or panel) 600 including a plurality of aggregated primary structures 200A, 200B, 200C. In the example shown, each primary structure 200A-200C includes a plurality of bonding regions 203A and 203B on a first side (e.g., top side) of one or more substrate materials 201. In some exemplary embodiments, each of the bonding regions 203A and 203B is substantially as described above for the bonding region 203. Figure 6B A plan view of a portion of wafer (or panel) 600 is further shown. Four bonding areas 203A, 203B, 203C, and 203D are within separate quadrants of main structure 200A. Each of the bonding areas is surrounded by a hydrophobic feature 204, which is within a trench (e.g., substantially as described above). In an exemplary embodiment, one IC die is to be assembled on each of bonding areas 203A-203D. However, in other embodiments, as few as one IC die may be assembled on each of main structures 200A-200C.

[0068] Back to Figure 1 , method 101 continues at block 120 where droplets are formed on each of the bonded regions of the master structure. Any suitable technique for liquids, such as vapor condensation or direct liquid dispensing (i.e., printing), may be implemented at block 120 as the embodiments are not limited in this regard. In some exemplary embodiments, water droplets are dispensed at block 120. However, depending on the nature of the wettability contrast of the master structure, a selected polar (e.g., alcohol) or non-polar (e.g., solvent) liquid may be dispensed at block 120.

[0069] At input 115, a die structure is received. In addition to or as an alternative to the droplets formed on the bonding area at block 120, droplets may be formed on the IC die structure. Method 101 then continues to block 130, where the IC die structure received at input 115 is placed over the bonding area of ​​the main structure prepared at block 120. The die structure received at input 115 may include a single IC die, or may include any number of IC dies assembled (e.g., hybrid bonded) into a coplanar or 3D IC die structure. The IC die structure may, but need not, further include an organic dielectric material and / or a metallization layer built on the surface of the IC die using a suitable semi-additive process (SAP).

[0070] Fig. 7A2 is a cross-sectional view of an IC die structure 701 undergoing an initial rough alignment 250 with a land feature 230. As a result of such alignment, the IC die structure 701 is placed on a droplet 705, which is confined to the land area by the adjacent hydrophobic region. For example, the rough alignment 250 may be performed with a pick-and-place device. For example, such a device may have a positional accuracy that may be capable of within 25-50 μm in each of the x- and y-dimensions. Figure 7B is a plan view of a rough alignment 250 and placement of an IC die structure 701 according to some embodiments. Figure 7B Some alignment errors shown in 704 are to be corrected by a droplet (e.g., water droplet) 705 during a passive fine alignment phase (e.g., via capillary forces, etc.) until the droplet evaporates. In an exemplary embodiment, the fine alignment is advantageously within 200 nm in each of the x-dimension and the orthogonal y-dimension.

[0071] In by Fig. 7A and Figure 7B In the illustrated exemplary embodiment, the IC die structures 701 each include an IC die substrate material 717, a device layer 710 in contact with the IC die substrate material 717, and an IC die metallization layer 715 on the device layer 710. The IC die structure may include a through substrate via (TSV) 735 extending from the device layer 710 into the IC die substrate material 717. Although the chemical composition of the IC die substrate material 717 may vary with implementation, in an exemplary embodiment, the IC die substrate material 717 is a silicon (e.g., single crystal) layer. The IC die substrate material 717 may also be an alternative composition, such as, but not limited to, germanium (Ge), silicon germanium alloy (SiGe), gallium arsenide alloy (GaAs), indium phosphide alloy (InP), gallium nitride alloy (GaN), silicon carbide alloy (SiC), etc. The device layer 710 includes active devices (not depicted). In some embodiments, the active devices within the device layer 710 are field effect transistors (FETs). The FET can be of any structure (e.g., planar, non-planar, single-gate, multi-gate, stacked nanosheets, etc.), and can have a characteristic spacing of, for example, 10-30 nm. In addition, or alternatively, the device layer 710 can include active devices other than FETs. For example, the device layer 710 can include electronic memory structures, spin valves, etc.

[0072] The IC die structure 701 includes an IC die metallization level 715 on the front side of the device layer 710. In an exemplary embodiment, the metallization level 715 includes die metallization features embedded in a dielectric material 718. Although the IC die metallization features can have any (one or more) compositions that are sufficiently conductive, in an exemplary embodiment, the IC die metallization features are predominantly Cu. In other examples, the metallization features are predominantly other than Cu, such as, but not limited to, predominantly Ru, or predominantly W.

[0073] In some advantageous embodiments, IC die structure 701 includes hydrophilic and hydrophobic surface structures corresponding to complementary surfaces on main structure 200A. For IC die structure 701, bonding region 703 includes bonding point features 730 in the uppermost metallization level in metallization levels 715. Bonding point features 730 can have any spacing comparable to bonding point features 230. In some exemplary embodiments, individual bonding point features 730 correspond to individual bonding point features 230 and have feature spacings, for example, in the range of 100 nm to 10 μm. Bonding point features 730 can have any suitable composition and can have substantially the same composition (e.g., the same metallization) as bonding point features 230. Bonding point features 730 are embedded in dielectric material 718, which can have any composition, for example, of the inorganic composition described above for the main structure.

[0074] At the periphery of the bonding area 703, the IC die structure 701 may further include topographic alignment features, such as substantially as described above for the main structure 200 (and thus the main structure 200A). As shown, the IC die structure 701 may have one or more grooves at the periphery of the bonding area 703, the one or more grooves having a depth substantially equal to the thickness of the bonding point feature 730. The IC die structure 701 further includes one or more hydrophobic features 704 adjacent to the bonding area 703. The feature 704 may have any of the properties or characteristics discussed elsewhere herein for the feature 204. For example, the bottom surface of the feature 704 may be substantially coplanar with the bonding point feature 730 along the plane P2. In some embodiments, the bonding point feature 730 and the peripheral hydrophobic feature 704 are manufactured according to any of the techniques discussed above for the corresponding area of ​​the main structure 200. For example, the SA3 feature on the IC die structure 701 may be substantially self-aligned with the bonding point feature 730, as described above for the main structure 200. Thus, the hydrophilic and hydrophobic surfaces of main structure 200A and IC die structure 701 may be substantially the same (as shown). Alternatively, the hydrophilic and hydrophobic surfaces of main structure 200A and IC die structure 701 may differ in composition and / or structure.

[0075] like Figure 7B As further shown in dashed lines, one or more hydrophobic features 704 substantially surround the perimeter of the joining region 703. Feature 704 can be a single continuous material and / or structure having a hydrophobic surface. Alternatively, feature 704 can include multiple discontinuous segments of hydrophobic material that delineate the perimeter around two or more edges of the joining region 703. Although Fig. 7A and Figure 7B An example is shown where two IC die structures 701 are placed adjacent to each other on one host structure 200A, but one or more IC die structures may be placed on a particular host structure.

[0076] Back to Figure 1 , method 101 continues at block 140, where the droplet between the IC die structure and the host structure is evaporated so that the IC die structure joint point is in direct contact with the host joint point. The IC die structure can then be bonded to the host structure according to any (one or more) suitable bonding techniques, such as a hybrid bonding technique. Fig. 8A An exemplary hybrid bonded composite structure 800 is shown, wherein the IC die structure 701 is now in contact with the main structure 200A along a bonding interface 850, which is represented by a thick dashed line. As shown, the joint features 230 in one bonding area are in direct contact with at least a portion of the corresponding ones of the joint features 730 in the complementary bonding area. The dielectric material of the main structure 200A is also in direct contact with the dielectric material of the IC die structure 701. The magnitude of the lateral offset between the joint features 230 and 730 along the bonding interface 850 indicates the fine alignment tolerances associated with the assembly process and helps to distinguish the bonding interface 850.

[0077] Individual ones of the hydrophobic features 204 are similarly co-located with corresponding ones of the features 704 on the IC die structure 701. The hydrophobic features 204 may also be in direct contact with the hydrophobic features 704 along the bonding interface 850, although they may not diffuse or fuse with each other to form a unified composite structure, even after the thermal and / or compression bonding process. Since the IC die structure 701 is bonded along the substantially planar bonding interface 850, the IC die backsides may not be coplanar if there are differences between the die structure thicknesses.

[0078] Back to Figure 1, method 101 ends at output 180, where any process can be implemented to complete the package. For example, the filling material can be deposited on the bonded IC die structure, and on the portion of the main structure that is not blocked by the IC die structure. The filling material is advantageously a dielectric material (e.g., an inorganic dielectric material or an organic dielectric material), such as any of those previously described. In an exemplary embodiment, the filling material is deposited to a thickness at least equal to the thickness of the IC die structure. The filling material can be deposited by any known technique suitable for the selected material composition and thickness. In some embodiments, the dielectric filling material can be applied with a spin coating or spray coating process and then cured. In other embodiments, the dielectric filling material can be deposited with a chemical vapor deposition (CVD) process. In still other embodiments, the dielectric filling material can be deposited with a molding process. Depending on the deposition process, the dielectric filling material can be flat along the length that spans the IC die structure and extends beyond the edge of the IC die structure, or it is not flat. The filling material can be flattened, for example, with a chemical mechanical flattening (CMP) system or any other suitable grinder and / or polisher.

[0079] exist Fig. 9A and 9B , the composite structure 900 further includes a dielectric material 905 above the IC die structure 701. The dielectric material 905 also substantially backfills the gap between adjacent edge sidewalls of the IC die structure 701. In some embodiments, the dielectric material 905 is any one or more of the inorganic dielectric compositions previously described. In some other embodiments, the dielectric material 905 is any one or more of the organic dielectric compositions previously described. As shown, the dielectric material 905 is substantially planarized across the IC die structure 701. Such planarization may be attributable to the dielectric deposition process and / or post-deposition polishing or CMP process.

[0080] Fig.10 1 is a cross-sectional view of a system 1000 including a heat sink 1004 and a primary assembly 1011 assembled with a hybrid bonded composite structure 900, the hybrid bonded composite structure 900 further including an IC die structure and a primary structure. For example, according to one or more embodiments described herein, at least one of the IC die and the primary structure has an SA3 feature that has been self-aligned with a bond point feature. The system 1000 may include any number of composite structures 900 mounted to the primary assembly 1011 by way of interconnects 1009, which are optionally embedded in an underfill material 1012. For example, the primary assembly 1011 may be a cored or coreless package substrate, an interposer, or a board (such as a motherboard).

[0081] The system 1000 further includes a power source 1056 coupled to one or more of the main component 1011 (i.e., a board, package substrate, or interposer), the composite structure 900, and / or other components of the system 1000. The power source 1056 may include a battery, a voltage converter, a power circuit, etc. The system 1000 further includes a thermal interface material (TIM) 1001 on the composite structure 900. The TIM 1001 may include any suitable thermal interface material. The system 1000 further includes an integrated heat sink (IHS) and / or cover 1002 in contact with the TIM 1001 and extending above the composite structure 900. The system 1000 further includes another TIM 1003 in contact with the top surface of the IHS 1002. The TIM 1003 may include any suitable thermal interface material and may or may not have the same composition as the TIM 1001. The system 1000 includes a heat sink 1004 (e.g., an exemplary heat sink device or thermal solution) in contact with the TIM 1003. System 1000 may further be integrated into a computer, such as, for example, a mobile device or a server.

[0082] Figure 2A-Figure 10 Exemplary embodiments are shown in which a self-aligned SA3 alignment feature has a topographic depth substantially equal to the thickness of an adjacent joint feature, for example because the SA3 alignment feature is defined simultaneously with the joint feature. However, where multiple levels of overlapping metallization features are recessed and / or removed, topographic alignment features that are deeper than the joint feature are also possible. Where each metallization level is associated with a certain metallization feature thickness, the trench generated by removing substantially all of the metallization features in each metallization feature can have a depth substantially equal to the number of metallization levels removed multiplied by their respective thicknesses. With increased SA3 alignment feature sidewall depth, such embodiments can also adjust the alignment feature sidewall profile by controlling the overlap between metallization features at different metallization levels.

[0083] Figures 11A-13B Exemplary embodiments are shown in which a self-aligned SA3 alignment feature has a topography depth substantially equal to the thickness of an adjacent joint feature plus the thickness of one or more metallization levels beneath the joint feature.

[0084] Fig.11A 1 is a cross-sectional view showing the patterning of trenches 228 and 229 for the top metallization level of the main structure 1101. The trench patterning is to form a joint feature in the bonding area 203 and also to form an alignment feature precursor in the peripheral area 205. This patterning can be performed in the method 101 ( Figure 1), for example, as substantially described elsewhere herein. The main structure 1101 includes stacked metallization features 202 spanning multiple metallization levels, upper metallization levels of the multiple metallization levels being exposed by trenches 229. One or more of the stacked metallization features 202 may be alignment feature precursors. Fig.11A As shown in , at least the uppermost one of the stacked metallization features 202 substantially surrounds the perimeter of the bonding area 203 .

[0085] Fig. 12A The main structure 1101 is further shown after the groove is metallized to form the joint feature 230, for example, substantially as described elsewhere herein. As further shown, while the joint feature 230 is protected by one or more mask materials 214, the metallization within the groove in the peripheral region 205 is substantially removed. In this example, the process implemented to remove the metallization not only removes the metallization coplanar with the joint feature 230, but also removes two levels of the stacked metallization feature 202. Therefore, the groove 229 is not only restored, but also becomes deeper by the additional thickness of the stacked metallization feature 202 to reach a depth D2. Notably, the top portion of the groove 229 remains self-aligned with the joint feature 230, and the additional depth of the groove 229 can enhance the wettability contrast between the joint area 203 and the peripheral area 205.

[0086] The portion of the groove 229 corresponding to the stacked metallization feature 202 may not be self-aligned with the joint feature 230. The overlap between the stacked metallization features 202 can be used to control the sidewall profile 1205 of the groove 229. Such sidewall profile control can be used to further enhance the wettability contrast between the joint area 203 and the peripheral area 205. In the example shown, the sidewall profile 1205 is stepped because the metallization features 202 are offset in the lateral direction in the first direction (e.g., along the x-axis). In other embodiments, the stacked metallization features 202 can be offset in an alternative manner, for example, to generate a concave sidewall profile that undercuts a portion of the joint area 203.

[0087] like Fig. 12B As further shown in FIG. 1 , the groove 229 having the sidewall profile 1205 surrounds the bonding region 203. Therefore, both stacked metallization features 202 are sacrificial as alignment feature precursors. For example, in method 101 ( Figure 1 ), at block 116 of the process, the alignment feature(s) fabricated by recessing metallization from the alignment feature(s) precursors may be enhanced with further processing. Fig.13A and Fig. 13BAn exemplary embodiment is shown in which the hydrophobic features 204 are formed within the peripheral region 205. Structural aspects of the hydrophobic features 204 can be adjusted by controlling the sidewall profile 1205.

[0088] Both the sidewall profile 1205 and the depth D2 indicate a self-aligned process for fabricating the SA3 alignment feature. Fig.13A , the depth D2 is approximately equal to the sum of the thickness of the joint feature 230 and the corresponding thickness of an integer number of metallization levels. Thus, the bottom surface of the alignment feature is substantially coplanar (along plane P2) with the bottom surface of the metallization feature 1330 associated with the lower metallization level. In addition, the discrete offsets in the sidewall profile 1205 corresponding to the thickness of the metallization level indicate that the alignment feature is derived from a precursor feature that is at least partially self-aligned with the joint feature.

[0089] Fig.14 An exemplary computer platform 1405 is shown including a composite structure including a bonded IC die having a hydrophilic and hydrophobic surface structure proximate a hybrid bonding interface, the hybrid bonding interface indicating a drop-based fine alignment technique. For example, platform 1405 can be a mobile computing platform and / or a data server machine. The server machine can be any commercial server, for example, including any number of high-performance computing platforms placed in a rack and networked together for electronic data processing. Platform 1405 can be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, etc. Platform 1405 can include a chip-level or package-level integrated system 1410 and a battery 1415. In some examples, the disclosed system can be implemented using a decomposed subsystem 1460.

[0090] Subsystem 1460 may include memory circuits and / or processor circuits 1450 (e.g., RAM, microprocessors, multi-core microprocessors, graphics processors, etc.), power management integrated circuits (PMICs) 1430, and radio frequency integrated circuits (RFICs) 1425 (e.g., including broadband RF transmitters and / or receivers (TX / RX)). As shown, one or more IC dies, such as memory circuits and / or processor circuits 1450, may be co-packaged and / or co-assembled within a composite structure that includes an IC die having a hydrophilic-hydrophobic structure proximate a hybrid bonding interface, such as described herein.

[0091] In some embodiments, RFIC 1425 includes a digital baseband and an analog front-end module, which further includes a power amplifier on the transmit path and a low noise amplifier on the receive path. Functionally, PMIC 1430 can perform battery power regulation, DC to DC conversion, etc., and thus has an input coupled to battery 1415 and an output that provides current supply to other functional modules. Fig.14 As further shown in the figure, in an exemplary embodiment, RFIC 1425 has an output coupled to an antenna (not shown) to implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G and above. Memory circuits and / or processor circuits 1450 can provide memory functions, high-level control, data processing, etc. for subsystem 1460.

[0092] Fig.15 1 is a block diagram of a cryogenically cooled computing device 1500 according to some embodiments. For example, one or more components of the computing device 1500 may include any of the devices or structures discussed elsewhere herein. Fig.15 1500, but any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some of the components included in computing device 1500 may be attached to one or more printed circuit boards (e.g., a motherboard). In some embodiments, various of these components may be fabricated on a single system-on-chip (SoC) die, or implemented with separate multiple chiplets or tiles packaged together. Additionally, in various embodiments, computing device 1500 may not include Fig.15 1500, but computing device 1500 may include interface circuitry for coupling to one or more of the components shown in . For example, computing device 1500 may not include display device 1503, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 1503 may be coupled.

[0093] Computing device 1500 may include processing device 1501 (e.g., one or more processing devices). As used herein, the term processing device or processor indicates a device that processes electronic data from registers and / or memory to convert the electronic data into other electronic data that can be stored in registers and / or memory. Processing device 1501 may include memory 1521, communication device 1522, refrigeration / active cooling device 1523, battery / power regulation device 1524, logic 1525, interconnect 1526, thermal regulation device 1527, and hardware security device 1528.

[0094] Processing device 1501 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device.

[0095] The processing device 1501 may include a memory 1502, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or a hard drive. In some embodiments, the processing device 1501 shares a package with the memory 1502. This memory may be used as a cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0096] The computing device 1500 may include a thermal conditioning / cooling device 1523. The thermal conditioning / cooling device 1523 may maintain the processing device 1501 (and / or other components of the computing device 1500) at a predetermined low temperature during operation. This predetermined low temperature may be any temperature discussed elsewhere herein.

[0097] In some embodiments, computing device 1500 may include a communication chip 1507 (e.g., one or more communication chips). For example, communication chip 1507 may be configured to manage wireless communications for transmitting data to and from computing device 1500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., which may communicate data using modulated electromagnetic radiation through a non-solid medium.

[0098] The communication chip 1507 can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE802.16-2005 amendment), Long Term Evolution (LTE) project and any amendments, updates and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are generally referred to as WiMAX networks, which is an acronym for Worldwide Interoperability for Microwave Access, which is a certification mark for products that have passed the IEEE802.16 standard conformance and interoperability testing. The communication chip 1507 can operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA) or LTE network. The communication chip 1507 may operate in accordance with Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1507 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and its derivative protocols, as well as any other wireless protocols designated as 3G, 4G, 5G and above. In other embodiments, the communication chip 1507 may operate in accordance with other wireless protocols. The computing device 1500 may include an antenna 1513 to facilitate wireless communications and / or receive other wireless communications (such as AM or FM radio transmissions).

[0099] In some embodiments, the communication chip 1507 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1507 can include multiple communication chips. For example, the first communication chip 1507 can be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, while the second communication chip 1507 can be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication chip 1507 can be dedicated to wireless communications, while the second communication chip 1507 can be dedicated to wired communications.

[0100] Computing device 1500 may include battery / power circuit 1508. Battery / power circuit 1508 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of computing device 1500 to an energy source separate from computing device 1500 (e.g., AC line power).

[0101] Computing device 1500 may include display device 1503 (or corresponding interface circuitry, as discussed above). Display device 1503 may include any visual indicator such as, for example, a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.

[0102] Computing device 1500 may include audio output device 1504 (or corresponding interface circuitry, as discussed above). Audio output device 1504 may include any device that generates an audible indicator, such as, for example, a speaker, headphones, or earbuds.

[0103] Computing device 1500 may include audio input device 1510 (or corresponding interface circuitry, as discussed above). Audio input device 1510 may include any device that generates a signal representative of sound, such as a microphone, a microphone array, or a digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0104] Computing device 1500 may include a global positioning system (GPS) device 1509 (or corresponding interface circuitry, as discussed above). As is known in the art, GPS device 1509 may communicate with a satellite-based system and may receive the location of computing device 1500.

[0105] Computing device 1500 may include another output device 1505 (or corresponding interface circuitry, as discussed above). Examples include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0106] The computing device 1500 may include another input device 1511 (or corresponding interface circuitry, as discussed above). Examples may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0107] Computing device 1500 may include security interface device 1512. Security interface device 1512 may include any device that provides security measures for computing device 1500, such as intrusion detection, biometric authentication, security encoding or decoding, management access lists, malware detection, or spyware detection.

[0108] Computing device 1500 or a subset of its components may have any suitable form factor, such as a handheld or mobile computing device (e.g., a cellular telephone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.

[0109] Although certain features set forth herein have been described with reference to various implementations, this description is not intended to be interpreted in a limiting sense. Therefore, it is clear to those skilled in the art that various modifications and other implementations of the implementations described herein are considered to be within the spirit and scope of the present disclosure.

[0110] In a first example, a device includes a main structure, the main structure including a plurality of metallization levels, an uppermost metallization level of the metallization levels including one or more first metal features of a first thickness within a first region of the main structure, the main structure further including an inorganic dielectric material. The first region is adjacent to a second region of the main structure, the second region including a recess having a depth substantially equal to a cumulative thickness of one or more of the metallization levels of the metallization levels. The device includes an integrated circuit (IC) die structure coupled to the main structure. The IC die structure has a third region and an adjacent fourth region, the third region including one or more second metal features of an inorganic dielectric material and a second thickness. The second metal feature is in direct contact with at least a portion of a corresponding first metal feature of the first metal feature.

[0111] In a second example, for any of the first examples, the depth of the groove is substantially equal to the first thickness.

[0112] In a third example, for any one of the first to second examples, the groove has a greater average surface roughness than the first region, or wherein the second region includes an organic material in contact with a sidewall of the groove.

[0113] In a fourth example, for any of the third examples, the organic material has a composition of at least ten atomic percent carbon or at least ten atomic percent fluorine, and the organic material at least partially fills the first groove and the second groove.

[0114] In a fifth example, for any one of the first to fourth examples, the first metal feature includes a fill metal and a barrier material between the fill metal and the inorganic dielectric material. The second region includes the barrier material lining the groove, but the fill metal is substantially absent from the groove.

[0115] In a sixth example, the plurality of metallization levels includes a second metallization level located below the first metallization level, the second metallization level having a third thickness. The depth of the groove is substantially equal to a sum of the first thickness and the third thickness.

[0116] In a seventh example, for any of the sixth examples, a first sidewall portion of the groove spanning the first thickness is laterally offset from a second sidewall portion of the groove spanning the third thickness.

[0117] In an eighth example, for any one of the first to seventh examples, the fourth region includes a second groove of a second depth, the second depth being substantially equal to the second thickness.

[0118] In a ninth example, for any one of the first to eighth examples, the second region is adjacent to two non-parallel edges of the first region.

[0119] In a tenth example, for any of the ninth examples, the second region substantially surrounds a perimeter of the first region.

[0120] In an eleventh example, a device includes a main structure, the main structure including one or more first metal features of a first thickness within a first region of the main structure, the main structure further including an inorganic dielectric material. The first region is adjacent to a second region of the main structure. The device includes an integrated circuit (IC) die structure coupled to the main structure. The IC die structure has a third region and an adjacent fourth region, the third region including an inorganic dielectric material and one or more second metal features of a second thickness. The second metal feature is in direct contact with at least a portion of a corresponding first metal feature in the first metal feature along a plane of a bonding interface. The second region includes a first groove having a depth substantially equal to the first thickness. The fourth region includes a second groove having a depth substantially equal to the second thickness.

[0121] In a twelfth example, for any of the eleventh examples, the first recess includes a groove substantially surrounding a perimeter of the first region, and wherein the second recess includes a groove substantially surrounding a perimeter of the fourth region.

[0122] In a thirteenth example, for any one of the twelfth examples, the first groove has an average surface roughness greater than that of the first region, or wherein the second region includes an organic material in contact with the sidewall of the first groove, and wherein the second groove has an average surface roughness greater than that of the third region, or wherein the fourth region includes an organic material in contact with the sidewall of the second groove.

[0123] In a fourteenth example, for any of the thirteenth examples, the organic material has a composition of at least ten atomic percent carbon or at least ten atomic percent fluorine, and the organic material at least partially fills the first groove and the second groove.

[0124] In a fifteenth example, for any one of the eleventh to fourteenth examples, the first metal feature and the second metal feature include a filler metal and a barrier material between the filler metal and the inorganic dielectric material. The barrier material lines the first groove and the second groove, but the filler metal is substantially absent in the first groove and the second groove.

[0125] In a sixteenth example, a method includes receiving a first of an integrated circuit (IC) die structure or a package substrate structure, the first of the integrated circuit (IC) die structure or the package substrate structure including a first region having a first metallization feature within a first trench in an inorganic dielectric material, and a second region having one or more second metallization features within a second trench in the inorganic dielectric material. The method includes removing at least a portion of the second metallization feature from the second trench. The method includes aligning the first of the integrated circuit (IC) die structure or the package substrate structure with a second of the integrated circuit (IC) die structure or the package substrate structure based on a wettability comparison between the first region and the second region. The method includes bonding the first of the IC die structure or the package substrate structure with the second of the IC die structure or the package substrate structure, wherein the bonding includes contacting the first metallization feature with a corresponding metallization feature.

[0126] In a seventeenth example, for any one of the sixteenth examples, the method includes forming the first trench and the one or more second trenches within the inorganic dielectric material, depositing metallization into both the first trench and the second trench, and forming the first metallization feature and the second metallization feature by planarizing the metallization until the inorganic material is exposed.

[0127] In an eighteenth example, for any of the seventeenth examples, removing at least a portion of the second metallization feature from the second trench includes wet chemical etching of the metallization.

[0128] In a nineteenth example, for any one of the seventeenth to eighteenth examples, depositing the metallization includes forming a barrier layer in the first trench and the second trench, and plating copper on the barrier layer. Removing at least a portion of the second metallization feature includes removing substantially all of the copper from the second trench.

[0129] In a twentieth example, for any one of the sixteenth to nineteenth examples, the method includes forming a hydrophobic material in contact with at least a sidewall of the second trench after removing at least a portion of the second metallization feature.

[0130] It will be appreciated that the principles of the present disclosure are not limited to the embodiments described herein, but may instead be implemented with modification and alteration without departing from the scope of the appended claims. The above-described embodiments may include employing only a subset of such features, employing a different order of such features, employing a different combination of such features, and / or employing additional features in addition to those features explicitly listed. Accordingly, the scope of the embodiments should be determined by reference to the appended claims and the full scope of equivalents to which such claims are entitled.

Claims

1. A device comprising: a main structure comprising a plurality of metallization levels, an uppermost one of the metallization levels comprising one or more first metal features of a first thickness within a first region of the main structure, the main structure further comprising an inorganic dielectric material, wherein the first region is adjacent to a second region of the main structure, the second region comprising a recess having a depth substantially equal to a cumulative thickness of one or more of the metallization levels; as well as An integrated circuit (IC) die structure coupled to the main structure, wherein the IC die structure has a third region and an adjacent fourth region, the third region comprising one or more second metal features of an inorganic dielectric material and a second thickness, and wherein the second metal features are in direct contact with at least a portion of corresponding first metal features of the first metal features.

2. The device according to claim 1, wherein: The depth of the groove is substantially equal to the first thickness.

3. The device according to any one of claims 1 to 2, wherein: The groove has a greater average surface roughness than the first region, or wherein the second region includes an organic material in contact with a sidewall of the groove.

4. The device as claimed in claim 3, wherein: The organic material has a composition of at least ten atomic percent carbon or at least ten atomic percent fluorine, and the organic material at least partially fills the groove.

5. The device according to any one of claims 1 to 2, wherein: The first metal feature includes a fill metal and a barrier material between the fill metal and the inorganic dielectric material; as well as The second region includes the barrier material lining the recess, but the filler metal is substantially absent from the recess.

6. The device according to any one of claims 1 to 2, wherein: The plurality of metallization levels include a second metallization level below the uppermost metallization level, the second metallization level having a third thickness; and The depth of the groove is substantially equal to the sum of the first thickness and the third thickness.

7. The device according to claim 6, wherein: A first sidewall portion of the groove spanning the first thickness is laterally offset from a second sidewall portion of the groove spanning the third thickness.

8. The device according to any one of claims 1 to 2, wherein: The fourth region includes a second groove having a second depth, the second depth being substantially equal to the second thickness.

9. The device according to any one of claims 1 to 2, wherein: The second region is adjacent to two non-parallel edges of the first region.

10. The device of claim 9, wherein: The second region substantially surrounds a perimeter of the first region.

11. The device according to any one of claims 1 to 2, wherein: The second metal feature is in direct contact with at least a portion of a corresponding one of the first metal features along a plane of the bonding interface.

12. The device of claim 11, wherein: The groove is a first groove including a groove substantially surrounding a perimeter of the first region, and a second groove including a groove substantially surrounding a perimeter of the fourth region.

13. The device of claim 12, wherein: The first groove has a larger average surface roughness than the first region, or the second region includes an organic material in contact with a sidewall of the first groove, and the second groove has a larger average surface roughness than the third region, or the fourth region includes an organic material in contact with a sidewall of the second groove.

14. The device of claim 13, wherein: The organic material has a composition of at least ten atomic percent carbon or at least ten atomic percent fluorine, and the organic material at least partially fills the first groove and the second groove.

15. The apparatus of claim 12, wherein: The first metal feature and the second metal feature include a fill metal and a barrier material between the fill metal and the inorganic dielectric material; as well as The barrier material lines the first groove and the second groove, but the filler metal is substantially absent from the first groove and the second groove.

16. A method comprising: receiving a first of an integrated circuit (IC) die structure or a package substrate structure, the first of the integrated circuit (IC) die structure or the package substrate structure comprising: a first region having a first metallization feature within a first trench in an inorganic dielectric material, and a second region having one or more second metallization features within a second trench in the inorganic dielectric material; removing at least a portion of the second metallization feature from the second trench; aligning the first of the integrated circuit (IC) die structures or the package substrate structures with a second of the integrated circuit (IC) die structures or the package substrate structures based on a wettability comparison between the first region and the second region; and The first of the IC die structure or the package substrate structure is bonded to a second of the IC die structure or the package substrate structure, wherein the bonding includes contacting the first metallization feature with a corresponding metallization feature.

17. The method of claim 16, further comprising: forming the first trench and the one or more second trenches in the inorganic dielectric material; depositing metallization into both the first trench and the second trench; as well as The first and second metallization features are formed by planarizing the metallization until the inorganic material is exposed.

18. The method of claim 17, wherein: Removing at least a portion of the second metallization feature from the second trench includes wet chemical etching of the metallization.

19. The method of claim 17, wherein: Depositing the metallization includes forming a barrier layer in the first trench and the second trench and plating copper on the barrier layer, and wherein removing at least a portion of the second metallization feature includes removing substantially all of the copper from the second trench.

20. The method of claim 16, further comprising forming a hydrophobic material in contact with at least a sidewall of the second trench after removing at least a portion of the second metallization feature.

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