Wafer scribing method and wafer structure

Abstract

The invention discloses a scribing method of a wafer and a wafer structure. The scribing method comprises the following steps: forming a groove in a scribing groove area; forming a filling layer in the groove; wherein the material hardness of the filling layer is smaller than a hardness threshold value, and the material hardness of the wafer is the hardness threshold value. According to the wafer scribing method and the wafer structure, the groove is formed in the scribing groove area in advance and filled with the low-hardness material, on one hand, the thickness of the high-hardness material during cutting in the scribing process is reduced, and on the other hand, the groove can serve as a position limiting groove of a blade during cutting.

Description

Technical Field

[0001] The present invention relates to the technical field of wafer dicing, and in particular to a wafer dicing method and a wafer structure. Background Art

[0002] Wafer cutting, as a key post-process in the semiconductor chip manufacturing process, is mainly used to divide the whole wafer with completed pattern production into individual chips (Die) according to the chip size. At present, the diamond saw blade cutting method has become one of the more common wafer cutting methods due to its high cutting efficiency and good cutting quality; and the laser cutting process has also become one of the more common wafer cutting methods due to its high cutting rate.

[0003] However, for wafer materials with higher hardness, such as silicon carbide (SiC), the SiC wafer produced is a third-generation semiconductor material with a hardness second only to diamond. Traditional diamond blade cutting technology has many problems when cutting, including slow cutting speed, low efficiency, repeated processing at the same position, the blade is easy to bounce off, resulting in inaccurate cutting position, and severe blade wear. If the laser cutting process is used, the laser beam requires high energy. If the cutting time is too long, it is easy to cause the device near the wafer dicing area to have problems such as reduced yield due to high temperature. Summary of the invention

[0004] In view of the above problems, the purpose of the present invention is to provide a wafer slicing method and wafer structure. By forming a groove in the slicing groove area in advance and filling it with a low hardness material, on the one hand, the thickness of the high hardness material during cutting during the slicing process is reduced, thereby reducing the difficulty of cutting. On the other hand, the groove can also serve as a position limiting groove for the blade during cutting.

[0005] According to one aspect of the present invention, a wafer slicing method is provided, wherein the wafer includes a plurality of chip areas, and adjacent chip areas are divided by slicing groove areas. The slicing method comprises: forming grooves in the slicing groove areas; forming a filling layer in the grooves; wherein the material hardness of the filling layer is less than a hardness threshold, and the hardness threshold is the material hardness of the wafer.

[0006] Optionally, a lateral dimension of the groove is smaller than or equal to a lateral dimension of the scribe line region.

[0007] Optionally, the step of forming a groove in the scribe line area includes: forming a mask layer on the first surface of the wafer, the mask layer exposing at least a portion of the first surface of the scribe line area; and etching the scribe line area through the mask layer to form the groove.

[0008] Optionally, the step of forming a filling layer in the groove includes: removing the mask layer, and filling the groove with a material of low hardness, wherein the material of low hardness refers to a material having a hardness less than a hardness threshold.

[0009] Optionally, before the step of forming a groove in the scribe line area, the step further includes: forming a semiconductor device in the chip area of ​​the wafer.

[0010] Optionally, the step of forming a groove in the scribe line area includes: forming a doped region in the wafer; forming a mask layer on the first surface of the wafer, the mask layer exposing the first surface of the scribe line area of ​​the wafer and a portion of the first surface of the chip area; etching in the scribe line area to form a groove, and etching in the chip area to form a groove via the mask layer.

[0011] Optionally, the step of forming a filling layer in the groove includes: depositing a dielectric layer and a polysilicon layer in the groove and the trench, the dielectric layer separating the polysilicon layer and the wafer; removing the dielectric layer and the polysilicon layer on the first surface of the wafer, the filling layer includes the dielectric layer and the polysilicon layer in the groove, and the hardness of the dielectric layer and the polysilicon layer is less than a hardness threshold.

[0012] Optionally, after the step of forming a filling layer in the groove, the method further includes: forming a semiconductor device in the chip region of the wafer.

[0013] Optionally, after the step of forming a filling layer in the groove, the method further includes: dividing the wafer along the scribe line region to obtain a plurality of independent chips.

[0014] According to another aspect of the present invention, a wafer structure is provided, wherein the wafer includes a plurality of chip areas, and adjacent chip areas are separated by scribe line areas; wherein the scribe line areas have grooves, and the grooves include a filling layer, and the material hardness of the filling layer is less than a hardness threshold, and the hardness threshold is the material hardness of the wafer.

[0015] Optionally, the material of the filling layer includes at least one of silicon oxide, silicon nitride, polysilicon, borophosphosilicate glass, borosilicate glass, tetraethyl orthosilicate, and non-doped silicate glass materials.

[0016] Optionally, a lateral dimension of the filling layer is smaller than or equal to a lateral dimension of the scribe line region.

[0017] Optionally, the wafer region includes a trench-type semiconductor device, and a longitudinal height of the filling layer is less than or equal to a longitudinal height of a trench in the trench-type semiconductor device.

[0018] The wafer slicing method and wafer structure provided by the present invention form grooves in the slicing groove area in advance and fill them with low hardness materials. When the wafer is slicing after the device structure is completed, the low hardness materials are easier to cut and the cutting thickness of the high hardness materials is reduced, which can increase the cutting speed and improve the efficiency of the slicing process.

[0019] The wafer dicing method and wafer structure provided by the present invention enable the blade to complete cutting quickly due to the low hardness material when cutting with a blade, and can reduce the cutting thickness of the blade for high hardness materials, thereby reducing the wear of the blade; in addition, the low hardness material filled in the groove enables the blade to complete partial cutting quickly during cutting and thus form a position limiting groove, thereby reducing the movement problem of the blade during the cutting process and improving the cutting accuracy.

[0020] Furthermore, the wafer dicing method and wafer structure provided by the present invention form grooves in the dicing groove area in advance and fill them with low-hardness material. The filled low-hardness material can also play a bonding and / or supporting role in the subsequent device formation process in the wafer, thereby avoiding problems such as wafer breakage in the grooves at the cutting front. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0022] Figure 1 and Figure 2 A top view and a cross-sectional view of a wafer structure according to an embodiment of the present invention are shown;

[0023] Figure 3 A flow chart of a wafer dicing method according to a first embodiment of the present invention is shown;

[0024] Figures 4a to 4c Shows cross-sectional views of various stages of a wafer dicing method according to a first embodiment of the present invention;

[0025] Figure 5 A flow chart of a wafer dicing method according to a second embodiment of the present invention is shown;

[0026] Figures 6a to 6d 1 and 2 show cross-sectional views of various stages of a wafer dicing method according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0027] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0028] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0029] When integrated circuits are produced, repetitive patterns are usually formed on a wafer for mass production. In this way, tens to hundreds of thousands of chips can be produced on a wafer at a time. Each chip is independently packaged to form a chip to achieve a specific function. In order to achieve independent chip packaging, the wafer needs to be well cut. Generally, a certain distance is designed between multiple chips on the wafer. This distance is called the scribe groove area. When dicing, the tool cuts the wafer from the middle of the scribe groove area to separate multiple chips.

[0030] The present application discloses a wafer structure for dicing, which can improve the wafer dicing rate.

[0031] Figure 1 and Figure 2 A top view and a cross-sectional view of a wafer structure according to an embodiment of the present application are shown.

[0032] refer to Figure 1 and Figure 2 , on the wafer 100, including a scribe line area 120 and a chip area 110, adjacent chip areas 110 are separated by the scribe line area 120. Each chip area 110 is used to form a chip, each chip has at least one semiconductor device formed therein, and the semiconductor device includes a planar semiconductor device and a trench semiconductor device, and no semiconductor structure is formed in the wafer 100 below the scribe line area 120.

[0033] The middle part of the scribe line area 120 also includes a groove etching area 121. The groove etching area 121 is used to partially etch the scribe line area 120 of the wafer 100 to form a groove, and fill the groove after etching with a low hardness material to form a filling layer 130, so that the vertical structure of the wafer 100 in the scribe line area 120 is as follows: Figure 2 As shown, therefore, the groove etching area 121 corresponds to the area where the filling layer 130 is subsequently formed. The filling layer 130 can be composed of a single layer of material or a stacked structure composed of multiple layers of material.

[0034] refer to Figure 2 In the lateral direction, the lateral dimension of the filling layer 130 is less than or equal to the lateral dimension of the scribe line region 120. In some embodiments, if the semiconductor device is a trench-type semiconductor device, in the longitudinal direction, the longitudinal height of the filling layer 130 is less than or equal to the longitudinal height of the trench in the trench-type semiconductor device in the wafer region 110.

[0035] Therefore, in the process of cutting the scribe line area 120 to separate the multiple chip areas 110, due to the presence of the filling layer 130, the part of the material of the high-hardness wafer 100 that is cut is reduced, and the hardness of the filling layer 130 is less than the hardness of the wafer material, thereby reducing the cutting difficulty and improving the cutting efficiency.

[0036] Figure 3 A flow chart of a wafer dicing method according to a first embodiment of the present invention is shown; Figures 4a to 4c 1 and 2 show cross-sectional views of various stages of a wafer dicing method according to a first embodiment of the present invention.

[0037] Step S201: forming a semiconductor device in a chip region of a wafer.

[0038] In this step, a plurality of semiconductor devices are formed in the wafer region 210 of the wafer 200 near the first surface through etching processes, deposition processes, ion implantation processes, etc., and adjacent wafer regions 210 are divided by scribe line regions 220, such as Figure 4a shown.

[0039] The semiconductor device formed in the wafer region 210 includes, for example, at least one of an active device and a passive device. In some embodiments, a transistor is formed in the wafer region 210, and the transistor includes a body region, a source region, a contact region, a gate structure, a conductive structure, and the like.

[0040] Step S202: forming a mask layer on the first surface of the wafer, and forming a groove in the scribe line area of ​​the wafer through the mask layer.

[0041] In this step, a photoresist layer is first formed on the first surface of the wafer 200, and then exposed and developed to form a patterned mask layer 241, the mask layer 241 exposes a portion of the first surface of the wafer scribe line region 220, such as Figure 4a shown.

[0042] Further, an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or vapor etching, is used to etch the wafer through the mask layer 241 to form a groove 242 in the scribe line area 220 of the wafer 200, and the mask layer 241 is removed. Figure 4b shown.

[0043] In this embodiment, the lateral width H1 of the groove 242 is less than or equal to the lateral width H2 of the scribe line region 220. Preferably, the lateral width H1 of the groove 242 is less than the lateral width H2 of the scribe line region 220, so that the semiconductor devices in the wafer region 210 will not be affected after the wafer is separated along the scribe line region 220 in the subsequent steps.

[0044] Step S203: forming a filling layer in the groove.

[0045] In this step, a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., is used to deposit a low hardness material in the groove 242 to form a filling layer 230, such as polysilicon (Si), silicon nitride (Si3N4), silicon oxide (SiO2), borophosphosilicate glass (BPSG), borosilicate glass (BSG), tetraethyl orthosilicate (TEOS), undoped silicate glass (USG) and the like. Figure 4c shown.

[0046] In addition, the low hardness material and high hardness material in this application are relative to the set hardness threshold. Specifically, the hardness threshold in this application is the hardness of the wafer material. Different wafer materials have different hardness thresholds. As shown in Table 1 below, the hardness of several common wafer materials and filling layer materials is shown. In addition to the materials shown in the table, the method of this application can also be used for wafer dicing of other materials.

[0047] Table 1: Hardness of wafer materials and filler materials Material Mohs hardness Knoop hardness Polysilicon (Si) 6.5 <![CDATA[1000-1400 Kg / mm 2 ]]> <![CDATA[Silicon nitride (Si3N4)]]> 8.9 <![CDATA[2000-2500Kg / mm 2 ]]> <![CDATA[Silicon dioxide (SiO2)]]> 7 <![CDATA[1200-1700Kg / mm 2 ]]> Silicon Carbide (SiC) 9 <![CDATA[2400-3000(2800 Kg / mm 2 : 4H-SiC)]]> <![CDATA[Boron carbide (B4C)]]> 9.35 <![CDATA[2,900-3,580 Kg / mm 2 ]]> Boron Nitride (BN) 9.9 <![CDATA[4,500-5,000 Kg / mm 2 ]]>

[0048] In this embodiment, for example, when the wafer material is 4H-SiC, the hardness threshold is 9 when measured by Mohs hardness, so that materials with a Mohs hardness of 9 or more are high-hardness materials, and materials with a Mohs hardness of less than 9 are low-hardness materials; when measured by Knoop hardness, the hardness threshold is 2800Kg / mm 2 , so the Knoop hardness is 2800Kg / mm 2 The above materials are high hardness materials, with Knoop hardness less than 2800Kg / mm 2 The material is a low hardness material.

[0049] In this embodiment, the material hardness can be measured by other hardnesses in addition to the Mohs hardness and Knoop hardness shown in Table 1. The Mohs hardness and Knoop hardness shown in Table 1 are just some examples used to illustrate the implementation process of this application.

[0050] Step S204: dividing the wafer along the scribe line region to obtain a plurality of independent chips.

[0051] In this step, a dicing process is used to separate the wafer along the scribe line region 220 , thereby obtaining a plurality of independent chips.

[0052] The cutting process includes a mechanical cutting process and a laser cutting process, etc. In this embodiment, for example, a mechanical cutting process is adopted.

[0053] In this step, a diamond blade is used in the mechanical cutting process. When the blade splits the wafer along the scribe groove area, the blade first splits the filling layer 230 in the groove 242. Due to the hardness difference, the blade can quickly complete the splitting of the filling layer 230, so that the blade is in the limiting groove formed by cutting the filling layer 230, which can reduce the probability of the blade bouncing when it subsequently splits the high hardness material of the wafer 200, and can cut at the correct position, reducing the number of repeated processing.

[0054] In addition, for wafer 200, since the filling layer 230 is etched and formed in advance, the thickness of the high-hardness material cut by the blade during the dicing process can be reduced, which not only increases the cutting rate but also reduces the wear of the blade and increases the life of the blade, thereby reducing costs by reducing the number of times the blade is polished or replaced.

[0055] The wafer dicing method provided in this embodiment can be applied to wafers made of any high-hardness material and will not affect the chips that have already been formed in the wafer.

[0056] Figure 5 A flow chart of a wafer dicing method according to a second embodiment of the present invention is shown; Figures 6a to 6d The sectional views of various stages of the wafer dicing method according to the second embodiment of the present invention are shown. Compared with the first embodiment, the dicing method of the second embodiment is applicable to a wafer in which the semiconductor device in the wafer includes a trench gate structure or an isolation structure, so that the groove and the filling layer located in the dicing groove area in the second embodiment are formed during the formation process of the semiconductor device in the wafer without the need for additional steps.

[0057] The following will refer to Figure 5 , Figures 6a to 6d The dicing method of the second embodiment of the present application is described in detail.

[0058] Step S301: forming a mask layer on a first surface of a wafer, and forming a groove in a scribe line region of the wafer and a trench in a chip region through the mask layer.

[0059] In this step, a photoresist layer is first formed on the first surface of the wafer 300, and then exposed and developed to form a patterned mask layer 341, the mask layer 341 exposes the first surface of the scribe line area 320 in the wafer 300 and the first surface of the trench etching area 346 of the wafer area 310, as shown in FIG. Figure 6a shown.

[0060] Further, an etching process, such as dry etching, including ion milling etching, plasma etching, reactive ion etching, laser ablation, or wet etching or vapor etching, is used to etch the scribe line area 320 and the groove etching area 346 through the mask layer 341 to form a groove 342 in the scribe line area 320 of the wafer 300, and a groove 343 is formed in the groove etching area 346 in the wafer area 310, and then the mask layer 341 is removed, as shown in FIG. Figure 6b shown.

[0061] In this embodiment, the lateral width H1 of the groove 342 is less than or equal to the lateral width H2 of the scribe line region 320, and the depth of the groove 343 in the wafer region 310 is greater than or equal to the depth of the groove 342 in the scribe line region. For example, in some embodiments, the depth of the groove 343 is equal to the depth of the groove 342 in the scribe line region.

[0062] The trench 343 is used to form a trench gate structure or an isolation structure in a semiconductor device. In the present application, the trench 343 is used to form a trench gate structure, for example.

[0063] In addition, before forming the mask layer 341 , regions such as a body region, a source region, and a contact region may be formed in the chip region 310 of the wafer 300 .

[0064] Step S302: forming a filling layer in the recesses and trenches.

[0065] In this step, a deposition process, such as physical vapor deposition, chemical vapor deposition, etc., is used to sequentially deposit materials on the first surface of the wafer 300 to form a dielectric layer 344 and a polysilicon layer 345. Figure 6c shown.

[0066] The dielectric layer 344 and the polysilicon layer 345 fill the trench 343 and the recess 342, so that the dielectric layer 344 and the polysilicon layer 345 serve as filling layers for the recess 342, and the dielectric layer 344 isolates the polysilicon layer 345 from the wafer 300. At the same time, since the etching and filling of the recess 342 and the trench 343 can be formed simultaneously, no additional steps are required.

[0067] The material of the dielectric layer 344 may be silicon oxide (SiO2), polysilicon (Si), silicon nitride (Si3N4), borophosphosilicate glass (BPSG), borosilicate glass (BSG), tetraethyl orthosilicate (TEOS), undoped silicate glass (USG) and the like.

[0068] Furthermore, the dielectric layer 344 and the polysilicon layer 345 on the first surface of the wafer 300 are removed by chemical mechanical polishing. Figure 6d shown.

[0069] In other embodiments, if the groove 343 is used to form other structures, other materials may be selected to fill the groove. The filling layer can also play a bonding and / or supporting role in the subsequent formation of semiconductor devices in the wafer, thereby preventing the wafer from breaking along the groove 342 during the formation of the semiconductor device, which may affect the yield of the device.

[0070] Step S303: forming a semiconductor device in the chip region of the wafer.

[0071] In this step, a semiconductor device is completed in the chip region 310 of the wafer 300 near the first surface through an etching process, a deposition process, an ion implantation process, etc., and adjacent chip regions 310 are divided by a scribe line region 320, such as Figure 6d shown.

[0072] The semiconductor devices formed in the wafer region 310 include, for example, at least one of an active device and a passive device, and include at least one active device.

[0073] Step S304: dividing the wafer along the scribe line region to obtain a plurality of independent chips.

[0074] In this step, a dicing process is used to separate the wafer along the scribe line area to obtain multiple independent chips.

[0075] The cutting process includes a mechanical cutting process and a laser cutting process, etc. In this embodiment, for example, a mechanical cutting process is adopted.

[0076] In this step, a diamond blade is used in the mechanical cutting process. When the blade splits the wafer along the scribe groove area, the blade first splits the polysilicon layer 345 and the dielectric layer 344 in the groove 342. Due to the hardness difference, the blade can quickly complete the splitting of the filling layer in the groove 342, so that the blade is in the limiting groove formed by cutting the filling layer, which can reduce the probability of the blade bouncing when it subsequently splits the high hardness material of the wafer 300, and can cut at the correct position, reducing the number of repeated processing.

[0077] In addition, for wafer 300, since the filling layer is etched in advance and formed, the thickness of the high-hardness material cut by the blade during the dicing process can be reduced, which not only increases the cutting rate but also reduces the wear of the blade and increases the life of the blade, thereby reducing costs by reducing the number of times the blade is polished or replaced.

[0078] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A wafer dicing method, wherein the wafer comprises a plurality of wafer regions, and adjacent wafer regions are divided by dicing groove regions, the dicing method comprising: forming a groove in the scribe line region; forming a filling layer in the groove; The material hardness of the filling layer is less than a hardness threshold, and the hardness threshold is the material hardness of the wafer.

2. The dicing method according to claim 1, wherein: The lateral dimension of the groove is smaller than or equal to the lateral dimension of the scribe line region.

3. The dicing method according to claim 1 or 2, wherein: The step of forming a groove in the scribe line region comprises: forming a mask layer on the first surface of the wafer, wherein the mask layer exposes at least a portion of the first surface of the scribe line region; The mask layer is used for etching in the scribe line region to form a groove.

4. The dicing method according to claim 3, wherein: The step of forming a filling layer in the groove comprises: removing the mask layer, and filling the groove with a material having a low hardness, The low hardness material refers to a material whose hardness is less than the hardness threshold.

5. The dicing method according to claim 4, wherein: Before the step of forming a groove in the scribe line region, the method further includes: Semiconductor devices are formed in the die region of the wafer.

6. The dicing method according to claim 1 or 2, wherein: The step of forming a groove in the scribe line region comprises: forming a doped region in the wafer; Forming a mask layer on the first surface of the wafer, the mask layer exposing the first surface of the scribe line region of the wafer and a portion of the first surface of the chip region; Through the mask layer, etching is performed in the scribe line region to form a recess, and etching is performed in the wafer region to form a trench.

7. The dicing method according to claim 6, wherein: The step of forming a filling layer in the groove comprises: Depositing a dielectric layer and a polysilicon layer in the groove and the trench, wherein the dielectric layer separates the polysilicon layer and the wafer; removing the dielectric layer and the polysilicon layer on the first surface of the wafer, The filling layer includes the dielectric layer and the polysilicon layer in the groove, The hardness of the dielectric layer and the polysilicon layer is less than the hardness threshold.

8. The dicing method according to claim 7, wherein: After the step of forming a filling layer in the groove, the method further comprises: Semiconductor devices are formed in the die region of the wafer.

9. The dicing method according to claim 1, wherein: After the step of forming a filling layer in the groove, the method further comprises: The wafer is divided along the scribe line region to obtain a plurality of independent chips.

10. A wafer structure, wherein the wafer comprises a plurality of wafer regions, and adjacent wafer regions are separated by scribe line regions; in, The scribe line region has a groove, the groove includes a filling layer, the material hardness of the filling layer is less than a hardness threshold, and the hardness threshold is the material hardness of the wafer.

11. The wafer structure according to claim 10, wherein: The material of the filling layer includes at least one of silicon oxide, silicon nitride, polysilicon, borophosphosilicate glass, borosilicate glass, tetraethyl orthosilicate, and non-doped silicate glass materials.

12. The wafer structure according to claim 10, wherein: The lateral dimension of the filling layer is smaller than or equal to the lateral dimension of the scribe line region.

13. The wafer structure according to claim 10, wherein: The wafer region includes a trench-type semiconductor device, and the vertical height of the filling layer is less than or equal to the vertical height of the trench in the trench-type semiconductor device.

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