Narrow-pitch copper bump interconnection structure based on nano twin silver and preparation method of narrow-pitch copper bump interconnection structure

Abstract

The invention provides a narrow-pitch copper bump interconnection structure based on nano twin silver and a preparation method thereof, and the preparation method comprises the following steps: coating the upper surface of a chip or wafer with copper bumps with photoresist, then carrying out exposure, stripping the photoresist on the surfaces of the copper bumps, and exposing the upper surfaces of the copper bumps; performing chemical mechanical polishing treatment on the upper surfaces of the copper bumps; depositing a nano-twin silver layer on the upper surface of the copper bump by adopting a magnetron sputtering process, and then removing the rest of photoresist and the redundant silver layer by using a stripping solution to obtain a copper bump structure with nano-twin silver on the upper surface; and aligning the two copper bump structure chips or wafers with the nano-twin silver on the upper surfaces, heating to 200-250 DEG C, and performing hot-pressing interconnection to obtain the narrow-pitch copper bump interconnection structure based on the nano-twin silver. By the adoption of the technical scheme, low-temperature interconnection between the narrow-pitch copper bumps on the upper chip and the lower chip is achieved, and the obtained interconnection structure has excellent service reliability.

Description

Technical Field

[0001] The invention relates to the technical field of microelectronic packaging, and in particular to a nano-twin silver-based narrow-pitch copper bump interconnection structure and a preparation method thereof. Background Art

[0002] The demand for high integration, multifunctionality and miniaturization of electronic devices has promoted the rapid development of high-density chip packaging. The chip packaging density continues to increase, and the size and pitch of solder joints on the chip have dropped sharply. When the solder joint pitch is reduced to below 10-20μm, the traditional Sn-based solder interconnection process will have the problem of solder overflow causing solder joint bridging. This traditional process can no longer meet the narrow pitch interconnection requirements of copper bumps on the chip. On the other hand, the copper-tin solder joints in the Sn-based solder interconnection process have problems such as intermetallic compound (IMC) brittle cracking and void initiation, poor mechanical reliability, and easy electromigration failure under thermal-electric effects, which seriously affect the service reliability of the chip in harsh environments.

[0003] The solid-state interconnection process does not involve the melting and solidification process of traditional solder, and the interconnection solder joints have excellent electrical, thermal and mechanical properties after being formed. It is considered to be a key technology for achieving high-density interconnection between three-dimensional integrated chips. However, due to the easy oxidation of the copper surface and the low self-diffusion coefficient of copper, the interconnection temperature of the Cu-Cu direct bonding technology currently proposed for copper bump interconnection between chips is relatively high (usually 250-300°C) and requires a long insulation time. High interconnection temperature often introduces problems such as wafer warping and thermal stress, making it difficult to achieve alignment between solder joints, limiting the application of Cu-Cu bonding technology in high-density chip interconnection. In addition, the process flow of the Cu / SiO2 hybrid bonding technology that can currently achieve narrow pitch interconnection is very complicated, requiring processes such as surface activation, SiO2 pre-bonding, and Cu annealing bonding, and requires a high vacuum environment, which has extremely high requirements for equipment and processes and is costly.

[0004] The solid-state interconnection process can achieve narrow pitch interconnection of chips, but the high interconnection temperature and complex interconnection process limit its application in the field of high-density interconnection of chips. Currently, it is of great significance for high-density packaging of chips to find a copper bump interconnection structure that can achieve narrow pitch, high performance and high reliability interconnection under interconnection temperature and low process requirements. Summary of the invention

[0005] In view of the above technical problems, the present invention discloses a narrow pitch copper bump interconnect structure based on nano-twinned silver and a preparation method thereof, which is used for high-density interconnection between narrow pitch copper bumps on a chip, and the interconnect bumps have excellent service reliability. Wherein, the narrow pitch refers to a solder joint pitch of less than 20 μm.

[0006] To this end, the technical solution adopted by the present invention is:

[0007] A nano-twinned silver-based narrow pitch copper bump interconnect structure and a preparation method thereof, comprising the following steps:

[0008] Step S1, coating a photoresist on the upper surface of a chip or wafer with copper bumps, then exposing the photoresist to peel off the surface of the copper bumps to expose the upper surface of the copper bumps;

[0009] Step S2, performing chemical mechanical polishing on the upper surface of the copper bump;

[0010] Step S3, depositing a nano-twinned silver layer on the upper surface of the copper bump by a magnetron sputtering process, and then removing the remaining photoresist and the excess silver layer by a stripping solution (referring to the silver layer on the photoresist outside the copper bump after magnetron sputtering, the photoresist below is stripped by a stripping solution, and the silver layer will automatically fall off), to obtain a copper bump structure with nano-twinned silver on the upper surface;

[0011] Step S4, aligning two copper bump structure chips or wafers with nano-twin silver on their upper surfaces, heating them to 200-250° C., and performing hot pressing interconnection to obtain a narrow pitch copper bump interconnection structure based on nano-twin silver.

[0012] With this technical solution, a nano-twin silver layer is deposited on the copper bumps of the chip obtained by roughening treatment by magnetron sputtering. The nano-twin silver structure on the surface of the copper bump has both high conductivity and mechanical properties, and also has excellent high-temperature structural stability and anti-electromigration performance. The low-temperature interconnection characteristics of the nano-twin silver are further utilized to achieve low-temperature interconnection between the copper bumps on the upper and lower chips, and the resulting narrow-pitch copper pillar interconnection bumps have excellent service reliability.

[0013] As a further improvement of the present invention, in step S1, the copper bump is polycrystalline copper, and the grains are randomly oriented.

[0014] As a further improvement of the present invention, in step S2, the surface roughness Ra after the chemical mechanical polishing treatment is 10-100 nm.

[0015] As a further improvement of the present invention, in step S3, the nano-twin silver is a full nano-twin structure, the interior of the nano-twin silver is composed of columnar crystals with a width of 100 to 1500 nm, and the surface has a {111} wire texture; the nano-twin layer perpendicular to the deposition direction is located inside the columnar crystal, and the thickness of the nano-twin layer is 8 to 50 nm. With this technical solution, due to the high self-diffusion coefficient of silver, the {111} wire texture on the silver surface can promote interface diffusion, and high-quality interconnection can be formed between the nano-twin silver at low temperature.

[0016] As a further improvement of the present invention, in step S3, the conditions of the magnetron sputtering process are: sputtering power 100-300 W, argon gas flow rate 40-60 sscm, and chamber vacuum degree less than 5×10 -3 mbar, substrate bias voltage is -50~-150V, and target material is 99.999% silver target.

[0017] As a further improvement of the present invention, in step S3, before magnetron sputtering, the surface of the copper bump is cleaned and dried, and then placed in a magnetron sputtering chamber for surface bombardment with argon ions to remove surface oxides and contaminants and improve the bonding strength of the nano-twin silver layer. Further, the surface of the copper bump is cleaned with a 5wt.% citric acid aqueous solution.

[0018] As a further improvement of the present invention, in step S4, hot pressing interconnection is adopted, the atmosphere is air condition, the pressure is 5-20 MPa, and the insulation time is 5-20 min.

[0019] The invention also discloses a nano-twin silver-based narrow pitch copper bump interconnection structure, which is prepared by the above-mentioned method for preparing the nano-twin silver-based narrow pitch copper bump interconnection structure.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] First, by adopting the technical solution of the present invention, the interconnection between the narrow pitch copper bumps of the chip can be realized at a relatively low temperature (as low as 200°C), with low heat input, avoiding the problems of wafer warping and rotation deviation caused by high temperature; at the same time, the nano-twin silver interconnection can be completed under air conditions, without the need for surface activation and high vacuum conditions, and has low requirements for bonding equipment.

[0022] Second, compared with existing nano-interconnection materials, the technical solution of the present invention deposits all-nano twinned structure silver on the surface of copper bumps by magnetron sputtering, which has excellent thermal storage, anti-electromigration reliability and high-temperature structural stability. In addition, the introduction of twin boundaries also improves the anti-electromigration life of nano-twinned silver under high current density. Therefore, compared with the traditional Sn-based solder interconnection structure, the interconnection structure of the technical solution of the present invention has excellent service reliability and can adapt to the narrow pitch interconnection requirements, providing a solution for the narrow pitch copper bump interconnection of chip-to-chip (C2C), chip-to-wafer (C2W), and wafer-to-wafer (W2W) packaging.

[0023] Third, the technical solution of the present invention has strong process compatibility. It does not require epitaxial growth on nanotwinned copper, and does not require a Cu substrate with a characteristic microstructure to prepare a nanotwinned Ag structure. In addition, the nanotwinned silver layer has a high density of nanotwins and a {111} surface texture, with 111 grains accounting for more than 90%. This {111} texture can promote interface diffusion during bonding and improve the shear strength of the interconnection structure. At the same time, the high-density nanotwins can improve the reliability of the interconnection structure, such as organizational stability and anti-electromigration performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 The schematic diagram of the interconnection structure of the nano-twinned silver-based narrow-pitch copper bump of the present invention.

[0025] Figure 2 This is a cross-sectional focused ion (FIB) imaging picture of a nanotwin silver layer deposited on a copper bump with a diameter of 25 μm by magnetron sputtering in Example 1 of the present invention, wherein (a) is a cross-sectional focused ion (FIB) imaging picture, and (b) is a partial enlarged picture of the box in (a).

[0026] Figure 3 This is a cross-sectional SEM image of the copper bump flip-chip structure based on {111} preferentially oriented all-nano twinned silver in Example 1 of the present invention.

[0027] Figure 4 This is a cross-sectional SEM image of the copper bump flip-chip structure based on {111} preferentially oriented all-nano twinned silver in Example 2 of the present invention.

[0028] Figure 5 This is a cross-sectional focused ion (FIB) imaging picture of the nanotwin silver layer deposited on a copper bump with a diameter of 25 μm by magnetron sputtering in Comparative Example 1 of the present invention, wherein (a) is a cross-sectional focused ion (FIB) imaging picture, and (b) is a partial enlarged picture of the box in (a).

[0029] Reference numerals include:

[0030] 1- chip or wafer, 2- copper bumps, 3- nanotwinned silver layer. DETAILED DESCRIPTION

[0031] The preferred embodiments of the present invention are described in further detail below.

[0032] A method for preparing a narrow pitch copper bump interconnect structure based on nano-twinned silver comprises the following steps:

[0033] Step S1, coating the upper surface of the chip or wafer with copper bumps with photoresist, then exposing and partially peeling off to expose the upper surface of the copper bumps. The copper bumps may be polycrystalline copper with randomly oriented grains, and the copper bumps are not required to have a {111} preferred orientation.

[0034] Step S2, performing chemical mechanical polishing (CMP) on the copper bumps on the chip or wafer; after the chemical mechanical polishing, the surface roughness Ra of the copper bumps is 10-100 nm.

[0035] Step S3, depositing a nano-twin silver layer on the polished copper bump by a magnetron sputtering process, removing the remaining photoresist and the excess silver layer by a stripping solution after deposition, and obtaining a copper bump structure with nano-twin silver on the upper surface; the sputtering power of the nano-twin silver layer prepared by magnetron sputtering is 100-300W, the argon gas flow rate is 40-60sscm, and the chamber vacuum degree during deposition should be less than 5×10 -3 mbar, the substrate bias voltage is -50 to -150 V, the target material is a 99.999% silver target. The surface of the nano twinned silver has a {111} filament texture, the width of the columnar crystal is 100 to 1500 nm, the nano twinned lamellae are located inside the columnar crystals and the twinned lamellae are perpendicular to the deposition direction, and the thickness of the nano twinned lamellae is 8 to 50 nm.

[0036] Step S4, aligning the copper bumps 2 of the upper and lower chips or wafers 1 having the composite copper bump structure obtained above, such as Figure 1 As shown, the nano twin silver layers 3 of the two correspond to each other, and the nano twin silver layers 3 on the upper and lower copper bumps 2 are used for interconnection to obtain a chip interconnection structure. The conditions for the hot pressing bonding are: the temperature is not higher than 250°C, preferably 200-250°C, the atmosphere is air condition, the pressure is 5-20MPa, and the holding time is 5-20min.

[0037] The following is a detailed description with reference to embodiments.

[0038] Example 1

[0039] A method for preparing a narrow pitch copper bump interconnect structure based on nano-twin silver, using bias DC magnetron sputtering technology to deposit {111} preferentially oriented all-nano twin silver on a chip copper bump (diameter 25 μm), and using hot pressing bonding to achieve a chip narrow pitch copper bump flip-chip interconnect based on nano-twin silver. Specifically comprising the following steps:

[0040] Step S1, coating the upper surface of the chip or wafer with copper bumps with photoresist, then exposing and partially peeling off to expose the upper surface of the copper bumps.

[0041] Step S2: using a polishing liquid to perform chemical mechanical polishing (CMP) on the copper bumps of the chip and the surface of the copper substrate to ensure that the surface roughness Ra is less than 100 nm.

[0042] Step S3, using 5 wt. % citric acid aqueous solution to clean the copper bumps of the chip and the surface of the copper substrate, and then using deionized water to clean and dry.

[0043] Step S4: Place the cleaned chip and copper substrate into the chamber of the magnetron sputtering equipment, set the voltage, and introduce argon gas to bombard the copper surface with ions to remove surface pollutants and oxides; then, after vacuuming, set the process parameters of sputtering deposition as follows: deposition power 250 W, argon gas flow rate 50 sccm, sputtering chamber vacuum degree 5×10 -3 mbar, substrate bias -150V, sputtering time 30min, then deposited on the copper bumps all nano twinned silver with a thickness of about 3μm, the proportion of {111} preferentially oriented grains in the nano twinned silver is about 90%, and there is no transition layer at the bottom of the silver layer.

[0044] After deposition, a stripping solution is used to remove the remaining photoresist and the excess silver layer to obtain a copper bump structure with nano-twin silver on the upper surface.

[0045] Step S5, the copper bumps of the chip or wafer with the composite copper bump structure obtained above and the copper substrate on which nano-twin silver is deposited are arranged opposite to each other, that is, the nano-twin silver layers on the bumps of the two are in contact, and placed in a wafer bonding device, and hot pressing bonding is performed after assembly. The hot pressing bonding process conditions are: bonding temperature 200°C, atmosphere is air condition, pressure is 10MPa, and insulation time is 20min.

[0046] Figure 2 This is a cross-sectional focused ion (FIB) imaging picture of the nanotwin silver layer deposited on a copper bump with a diameter of 25 μm by magnetron sputtering in Example 1. It can be seen from the figure that by controlling the magnetron sputtering process parameters, there is no transition layer at the bottom of the silver layer deposited on the copper bump, and all columnar crystals have a high-density nanotwin layer parallel to the surface, and the proportion of {111} preferentially oriented grains is about 90%.

[0047] Figure 3 This is a cross-sectional SEM image of the copper bump flip-chip structure based on {111} preferred orientation all-nano twinned silver in Example 1. It can be seen from the figure that under the air condition of 200℃-10MPa and 20min of heat preservation, there are no obvious holes and unbonded defects on the bonding interface between the nano twinned silver. The interconnection of nano twinned silver realizes the low-temperature and high-quality interconnection of narrow pitch copper bumps on the chip.

[0048] Example 2

[0049] Nano-twinned silver was deposited on the chip copper bumps (diameter 25 μm) using bias DC magnetron sputtering technology, and hot compression bonding was used to achieve chip narrow pitch copper bump flip-chip interconnection based on nano-twinned silver.

[0050] The nano-twinned silver-based narrow pitch copper bump interconnect structure and implementation method described in this embodiment include the following steps:

[0051] Step S1, coating a photoresist on the upper surface of a chip or wafer with copper bumps, then exposing and partially peeling off to expose the upper surface of the copper bumps;

[0052] Step S2, using a polishing liquid to perform chemical mechanical polishing (CMP) on the copper bumps of the chip and the surface of the copper substrate to ensure that the surface roughness Ra is less than 100 nm;

[0053] Step S3, using 5wt.% citric acid aqueous solution to clean the copper bumps of the chip and the surface of the copper substrate, and then using deionized water to clean and dry;

[0054] Step S4: Place the cleaned chip and copper substrate into the chamber of the magnetron sputtering equipment, set the voltage, and introduce argon gas to bombard the copper surface with ions to remove surface pollutants and oxides; then, after vacuuming, set the process parameters of sputtering deposition as follows: deposition power 250 W, argon gas flow rate 50 sccm, sputtering chamber vacuum degree 5×10 -3 mbar, substrate bias voltage -150V, sputtering time 30min, a nano twinned silver layer with a thickness of about 3μm can be deposited on the copper bump; after deposition, a stripping liquid is used to remove the remaining photoresist and the excess silver layer to obtain a copper bump structure with nano twinned silver on the upper surface;

[0055] Step S5, placing the chip with the composite copper bump structure obtained above and the copper substrate deposited with nano-twin silver into a wafer bonding device, and performing hot pressing bonding after assembly. The hot pressing bonding process conditions are: bonding temperature 250°C, atmosphere is air condition, pressure is 20MPa, and insulation time is 5min.

[0056] Figure 4 This is a cross-sectional SEM image of the copper bump flip-chip structure based on nanotwin silver in Example 2. It can be seen from the figure that under the conditions of 250°C, 20MPa, and 5 minutes of heat preservation in air, there are no obvious holes and unbonded defects on the bonding interface between the nanotwin silver. By increasing the bonding temperature, high-quality interconnection of narrow-pitch copper bumps on the chip can be achieved through the interconnection of nanotwin silver in a shorter time.

[0057] Comparative Example 1

[0058] Nanotwinned silver with a low (111) oriented grain ratio was deposited on the chip copper bumps (25 μm in diameter) using unbiased DC magnetron sputtering technology, and hot compression bonding was used to achieve chip narrow pitch copper bump flip-chip interconnection based on nanotwinned silver.

[0059] The nano-twinned silver-based narrow pitch copper bump interconnect structure and implementation method described in this comparative example include the following steps:

[0060] Step S1, coating the upper surface of the chip or wafer with copper bumps with photoresist, then exposing and partially peeling off to expose the upper surface of the copper bumps.

[0061] Step S2: using a polishing liquid to perform chemical mechanical polishing (CMP) on the copper bumps of the chip and the surface of the copper substrate to ensure that the surface roughness Ra is less than 100 nm.

[0062] Step S3, using 5 wt. % citric acid aqueous solution to clean the copper bumps of the chip and the surface of the copper substrate, and then using deionized water to clean and dry.

[0063] Step S4: Place the cleaned chip and copper substrate into the chamber of the magnetron sputtering equipment, set the voltage, and introduce argon gas to bombard the copper surface with ions to remove surface pollutants and oxides; then, after vacuuming, set the process parameters of sputtering deposition as follows: deposition power 250 W, argon gas flow rate 30 sccm, sputtering chamber vacuum degree 5×10 -3 mbar, no substrate bias voltage was applied, and the sputtering time was 30 min, after which nano-twinned silver with a thickness of about 3 μm was deposited on the copper bump. The proportion of {111} preferred orientation grains in the nano-twinned silver obtained under this condition was about 55%.

[0064] After deposition, a stripping solution is used to remove the remaining photoresist and the excess silver layer to obtain a copper bump structure with nano-twin silver on the upper surface.

[0065] Step S5, the copper bumps of the chip or wafer with the composite copper bump structure obtained above and the copper substrate on which nano-twin silver is deposited are arranged opposite to each other, that is, the nano-twin silver layers on the bumps of the two are in contact, and placed in a wafer bonding device, and hot pressing bonding is performed after assembly, and the hot pressing bonding process conditions are the same as those in Example 1.

[0066] Figure 5 This is a cross-sectional focused ion (FIB) imaging image of a nanotwinned silver layer deposited on a copper bump with a diameter of 25 μm by magnetron sputtering in Comparative Example 1. After EBSD analysis of the surface of the silver layer under this condition, the results show that the proportion of (111) preferentially oriented grains in the silver layer deposited on the copper bump with this process parameter is about 55%.

[0067] The shear strength of the interconnection structure obtained in the embodiment and the comparative example was tested, and the test results are shown in Table 1 below. The shear strength of the interconnection structure using nano-twin silver with a high (111) oriented grain ratio (90%) is 65.2 MPa, which is 1.51 times that of the nano-twin silver interconnection structure with a low (111) oriented grain ratio (55%). It can be seen that the surface of the nano-twin silver layer obtained under the high substrate bias voltage proposed by the present invention has a high (111) grain orientation ratio (90%), which can improve the shear strength of the interconnection structure.

[0068] Table 1. Shear strength test results of interconnect structures obtained in Examples and Comparative Examples

[0069] Object Example 1 Example 2 Comparative Example 1 Shear strength / MPa 65.2±3.8 60.4±4.2 43.1±5.1

[0070] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A method for preparing a narrow pitch copper bump interconnect structure based on nano-twinned silver, characterized in that: The steps include: Step S1, coating a photoresist on the upper surface of a chip or wafer with copper bumps, then exposing the photoresist to peel off the surface of the copper bumps to expose the upper surface of the copper bumps; Step S2, performing chemical mechanical polishing on the upper surface of the copper bump; Step S3, depositing a nano-twinned silver layer on the upper surface of the copper bump by a magnetron sputtering process, and then removing the remaining photoresist and the excess silver layer by a stripping solution to obtain a copper bump structure with nano-twinned silver on the upper surface; Step S4, aligning two copper bump structure chips or wafers with nano-twin silver on their upper surfaces, heating them to 200-250° C., and performing hot pressing interconnection to obtain a narrow pitch copper bump interconnection structure based on nano-twin silver.

2. The method for preparing a narrow pitch copper bump interconnect structure based on nano-twinned silver according to claim 1, characterized in that: In step S1, the copper bump is polycrystalline copper, and the grains are randomly oriented.

3. The method for preparing a narrow pitch copper bump interconnect structure based on nano-twinned silver according to claim 1, characterized in that: In step S2, the surface roughness Ra after chemical mechanical polishing is 10-100 nm.

4. The method for preparing a narrow pitch copper bump interconnect structure based on nano-twinned silver according to claim 1, characterized in that: In step S3, the nano-twinned silver is a full nano-twinned structure, the interior of the nano-twinned silver is composed of columnar crystals with a width of 100 to 1500 nm, and the surface has a {111} wire texture; The nano-twin lamellae perpendicular to the deposition direction are located inside the columnar crystals, and the thickness of the nano-twin lamellae is 8 to 50 nm.

5. The method for preparing a narrow pitch copper bump interconnect structure based on nano-twinned silver according to claim 4, characterized in that: In step S3, the conditions of the magnetron sputtering process are: sputtering power 100-300 W, argon gas flow rate 40-60 sscm, and chamber vacuum degree less than 5×10 -3 mbar, substrate bias voltage is -50~-150V, and target material is 99.999% silver target.

6. The method for preparing a nano-twinned silver-based narrow pitch copper bump interconnect structure according to claim 4, characterized in that: In step S3, before magnetron sputtering, the surface of the copper bump is cleaned and dried, and then placed in a magnetron sputtering chamber for surface bombardment with argon ions.

7. The method for preparing a narrow pitch copper bump interconnect structure based on nano-twinned silver according to claim 1, characterized in that: In step S4, hot pressing interconnection is adopted, the atmosphere is air condition, the pressure is 5-20 MPa, and the insulation time is 5-20 min.

8. A narrow pitch copper bump interconnect structure based on nano-twinned silver, characterized in that: The nano-twinned silver-based narrow pitch copper bump interconnect structure is prepared by the preparation method according to any one of claims 1 to 7.

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