Interconnect structure, method of manufacturing the same, and electronic device including the same

Abstract

The invention relates to an interconnection structure, a method of manufacturing the same, and an electronic device including the same. Disclosed is an interconnect structure including a substrate, a conductive layer on the substrate, and a passivation layer in contact with the conductive layer, in which the passivation layer includes a first layer including boron nitride (h-BN) having a hexagonal crystal structure and a second layer including amorphous boron nitride (a-BN), and the first layer is in contact with the conductive layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0131069, filed on September 27, 2023, and all rights arising therefrom, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to an interconnect structure, a method for manufacturing the same, and an electronic device (apparatus) including the same. Background Art

[0004] In order to provide high-density, high-performance semiconductor devices, efforts are being made to reduce the line width or thickness of metal wiring. By reducing the line width or thinning the thickness of metal wiring, the number of semiconductor chips integrated per wafer can be increased. In addition, when the thickness of metal wiring is thinned, the capacitance of the line can be reduced, and therefore, the speed at which signals pass through the wiring can be increased.

[0005] However, as the line width or thickness of metal wiring decreases, the resistance increases rapidly, and thus reducing the resistance of metal wiring becomes more important than anything else. The problem with current wiring technology is that as the line width decreases significantly, the resistivity increases significantly due to grain boundary scattering (scattering) and / or surface roughness scattering.

[0006] In addition, since degradation may occur due to oxidation occurring at a metal / oxide interface or an exposed metal surface, a technique for reducing the resistance of a wiring structure while preventing metal oxidation is desirable. Summary of the invention

[0007] Embodiments provide an interconnect structure that can prevent oxidation of metal wirings while reducing an increase in resistance due to a reduction in line width of the metal wirings.

[0008] Embodiments provide methods of manufacturing the interconnect structure.

[0009] An embodiment provides an electronic device including the interconnect structure.

[0010] According to one embodiment, an interconnect structure includes: a substrate; a conductive layer on the substrate; and a passivation layer in contact with the conductive layer, wherein the passivation layer includes: a first layer including boron nitride (h-BN) having a hexagonal crystal structure and a second layer including amorphous boron nitride (a-BN), and the first layer is in contact with the conductive layer.

[0011] The passivation layer may be disposed on at least one of an upper surface or a lower surface of the conductive layer.

[0012] The conductive layer may include a metal, a metal alloy, a conductive compound, or a combination thereof.

[0013] The metal may include a transition metal, a Group 2A metal, a Group 3A (Group 13) metal, or a combination thereof.

[0014] The conductive layer may include copper (Cu), ruthenium (Ru), aluminum (Al), cobalt (Co), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), osmium (Os), gold (Au), niobium (Nb), vanadium (V), scandium (Sc), erbium (Er), lanthanum (La), or a combination thereof.

[0015] The metal alloy may include NiCo, NiAl, CoMo, RuMo, NbV, TaNb, V 3 Cr、V 3 Mo, Er 2 Ni 7 、FeCo 3 , LaCu 13 , FeNi, FeRu, BeCo, TaV, CrNi, TiV, ZrNb, MoRu, MoRu 3 、Mo 3 Ru, or a combination thereof.

[0016] The conductive compound may include a metal nitride, a metal phosphide, a metal arsenide, or a combination thereof.

[0017] The conductive layer may have a thickness of less than or equal to about 10 nanometers (nm), and the passivation layer may have a thickness of less than or equal to about 30 nm.

[0018] A thickness ratio of the conductive layer to the passivation layer may be in a range of about 1:0.01 to about 1:3.

[0019] The passivation layer may further include a third layer including a dielectric on a surface of the second layer not in contact with the first layer.

[0020] Hexagonal boron nitride (h-BN) included in the first layer may be obtained (derived from) amorphous boron nitride (a-BN) included in the second layer.

[0021] Hexagonal boron nitride (h-BN) included in the first layer may form a van der Waals bond with a material constituting the conductive layer.

[0022] The first layer may have a thickness of less than or equal to about 3 nm, and the second layer may have a thickness of less than or equal to about 25 nm.

[0023] A thickness ratio of the first layer and the second layer may be in a range of about 1:1.5 to about 1:8.

[0024] The first layer may be formed as a continuous layer on a surface in contact with the conductive layer.

[0025] A barrier layer may be further included between the substrate and the conductive layer or between the substrate and the passivation layer.

[0026] The interconnect structure may include: a substrate including a dielectric layer (dielectric layer) defining a trench structure therein; a conductive layer filling an interior of the trench structure; and a passivation layer disposed on an upper surface of the conductive layer.

[0027] The interconnect structure may include: a substrate including a dielectric layer defining a trench structure therein; a conductive layer filling an interior of the trench structure; and a passivation layer disposed on a lower surface and a side surface of the conductive layer.

[0028] The interconnect structure may include: a substrate including a dielectric layer defining a trench structure therein; a conductive layer filling an interior of the trench structure; and a passivation layer surrounding the entire conductive layer.

[0029] At least one surface inside the trench structure may further include a barrier layer.

[0030] The barrier layer may include a metal, an alloy of a metal, a metal oxide, a metal nitride, or a combination thereof.

[0031] According to another embodiment, a method for manufacturing an interconnect structure includes: forming a conductive layer on a substrate; forming a dielectric layer including amorphous boron nitride (a-BN) on the conductive layer; and converting the amorphous boron nitride (a-BN) present at an interface between the dielectric layer and the conductive layer into hexagonal boron nitride (h-BN) to form a passivation layer, the passivation layer including: a first layer including hexagonal boron nitride (h-BN) and a second layer including amorphous boron nitride (a-BN).

[0032] According to another embodiment, a method for manufacturing an interconnect structure includes: forming a dielectric layer including amorphous boron nitride (a-BN) on a substrate; forming a conductive layer on the dielectric layer; and converting amorphous boron nitride (a-BN) present at an interface between the dielectric layer and the conductive layer into hexagonal boron nitride (h-BN) to form a passivation layer, the passivation layer including: a first layer including hexagonal boron nitride (h-BN) and a second layer including amorphous boron nitride (a-BN).

[0033] The passivation layer may be formed by a process of locally applying energy to amorphous boron nitride (a-BN) included in the dielectric layer to convert it into hexagonal boron nitride (h-BN) included in the first layer.

[0034] The energy application process may include annealing, laser irradiation, or a combination thereof.

[0035] Another embodiment provides an electronic device including the interconnect structure.

[0036] The electronic device may be a transistor, a capacitor, a diode, or a resistor.

[0037] The interconnect structure can effectively reduce an increase in resistance due to grain boundary scattering and / or surface roughness scattering caused by a decrease in line width of a metal wiring (eg, a conductive layer). BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figures 1 to 3 is a cross-sectional view of an interconnect structure according to some example embodiments.

[0039] Figures 4 to 9 is a cross-sectional view of an interconnect structure according to some example embodiments.

[0040] Fig.10 is a cross-sectional view of an interconnect structure according to an embodiment.

[0041] Fig.11 and 12 is a cross-sectional view of an electronic device according to some example embodiments.

[0042] Fig.13 : is a graph showing the results of Raman spectroscopy evaluation to confirm the formation of hexagonal boron nitride in the structures according to Examples 1 to 3 and Comparative Example 1. DETAILED DESCRIPTION

[0043] Hereinafter, example embodiments of the present disclosure will be described in detail so that those skilled in the art will understand it. However, the present disclosure may be embodied in many different forms and is not to be construed as limited to the example embodiments set forth herein.

[0044] The terms used herein are only used to describe the embodiments and are not intended to limit the present disclosure. Unless the context clearly dictates otherwise, a singular expression includes a plural expression.

[0045] It will be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components (components), regions, layers, and / or parts, these elements, components (components), regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component (component), region, layer, or part from another element, component (component), region, layer, or part. Therefore, without departing from the teachings herein, the "first element", "component (component)", "region", "layer", or "part" discussed below may be referred to as the second element, component (component), region, layer, or part. The terms used herein are only used to describe the purpose of a specific embodiment and are not intended to be restrictive. As used herein, the singular forms "one (kind) (indefinite article) (a, an)" and "said (the)" are intended to include plural forms, including "at least one (kind)", unless the content clearly indicates otherwise. Therefore, after mentioning the element in the claim, "said" element is mentioned, including a kind of element and multiple elements. "At least one (kind)" will not be interpreted as limiting "one (kind)". “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0046] As used herein, terms such as "comprising", "including" or "having" are intended to specify the presence of implemented features, quantities, steps, components (components), or a combination thereof, but should not be understood as excluding the possibility of the presence or addition of one or more additional features, quantities, steps, components (components), or a combination thereof.

[0047] In the accompanying drawings, the thickness of layers, films, panels, regions, etc., is exaggerated for clarity. Throughout the specification, the same reference numerals designate the same elements. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0048] As used herein, "about" includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±10%, ±5%, ±3%, or ±1% relative to the stated value.

[0049] Relative terms, such as "downward," "lower," or "bottom," and "upward," "upper," or "top," may be used herein to describe the relationship of one element to another element as shown in the figures. It will be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in one of the figures is turned over, an element described as being on the "lower" side of the other element would be oriented on the "upper" side of the other element. Thus, the exemplary term "lower" may encompass both "lower" and "upper" orientations, depending on the specific orientation of the figure.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless clearly so defined herein.

[0051] Example embodiments are described herein with reference to cross-sectional views of schematic diagrams as idealized embodiments. Thus, deviations from the shapes of the figures as a result of, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions as shown herein, but rather include deviations in shape caused by, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features. In addition, the illustrated sharp corners may be rounded. Therefore, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions and are not intended to limit the scope of the claims.

[0052] In addition, herein, the "layer" includes not only a shape formed on the entire surface when viewed from a plan view but also a shape formed on a part of the surface.

[0053] The use of the term "said" and similar referential terms may refer to both the singular and the plural. Unless the order of steps constituting a method is explicitly stated or stated to the contrary, the steps may be performed in any suitable order and are not necessarily limited to the order described.

[0054] In addition, terms such as “unit” and “module” used in the specification refer to a unit that processes at least one function or operation, which can be implemented as hardware or software, or as a combination of hardware and software.

[0055] The line connections or connecting means between components shown in the drawings illustrate functional connections and / or physical or circuit connections, and in actual devices, multiple functional connections, physical connections, or circuit connections may be represented.

[0056] As used herein, "at least one of A, B, or C," "one of A, B, C, or a combination thereof," and "one of A, B, C, and a combination thereof" refer to each component and to any combination (e.g., A; B; C; A and B; A and C; B and C; or A, B and C).

[0057] As used herein, "a combination thereof" means a mixture, a stack, a composite, an alloy, a blend, etc. of the components (components).

[0058] In this document, "metal" is interpreted as a concept including metals and metalloids (semi-metals).

[0059] Hereinafter, an interconnection structure according to an embodiment will be described with reference to the accompanying drawings.

[0060] Figures 1 to 3 is a cross-sectional view of an interconnect structure according to some embodiments.

[0061] refer to Figure 1 and 2 The interconnect structures 100a and 100b include a substrate 101, a conductive layer 103 on the substrate 101, and a passivation layer 105 in contact with the conductive layer 103, and refer to Figure 3 The interconnect structure 100 c includes a substrate 101 , a conductive layer 103 on the substrate 101 , and passivation layers 105 - 1 and 105 - 2 contacting the conductive layer 103 .

[0062] The passivation layer 105 includes a first layer 105a including hexagonal boron nitride (h-BN) and a second layer 105b including amorphous boron nitride (a-BN). The first layer 105a may not include amorphous boron nitride (a-BN).

[0063] The passivation layer 105 may be disposed on the upper surface, the lower surface, or both of the conductive layer 103 .

[0064] Figure 1 shows a structure in which a passivation layer 105 is located on the upper surface of a conductive layer 103, Figure 2 shows a structure in which a passivation layer 105 is formed on the lower surface of the conductive layer 103 (ie, between the substrate 101 and the conductive layer 103), and Figure 3 A structure is shown in which passivation layers 105 - 1 and 105 - 2 are formed on both the upper and lower surfaces of the conductive layer 103 .

[0065] The substrate 101 may include at least one of a group IV semiconductor material, a semiconductor compound (e.g., a group III-V compound semiconductor, or a group II-VI compound semiconductor), an insulator, or a metal. For example, the substrate 101 may include a group IV semiconductor material such as Si, Ge, or Sn. For another example, the substrate 101 may include at least one of Si, Ge, C, Zn, Cd, Al, Ga, In, B, N, P, S, Se, As, Sb, Te, Ta, Ru, Rh, Ir, Co, Ti, W, Pt, Au, Ni, or Fe. For another example, the substrate 101 may include Si, Ge, SiC, SiGe, SiGeC, Ge alloy, GaAs, InAs, InP, etc. The substrate may include a plurality of layers or a single layer stacked with different materials.

[0066] For example, the substrate 101 may include a silicon on insulator ("SOI") substrate or a silicon germanium on insulator ("SGOI") substrate. For example, the substrate may further include N or F in a SiCOH-based composition and may further include pores to reduce a dielectric constant. Meanwhile, the substrate 101 may further include a dopant.

[0067] The conductive layer 103 may include a metal, a metal alloy, a conductive compound, or a combination thereof.

[0068] The metal may include a transition metal, a Group 2A metal, a Group 3A (Group 13) metal, or a combination thereof.

[0069] The metal may include copper (Cu), ruthenium (Ru), aluminum (Al), cobalt (Co), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), osmium (Os), gold (Au), niobium (Nb), vanadium (V), scandium (Sc), erbium (Er), lanthanum (La), or a combination thereof.

[0070] The metal alloy may include NiCo, NiAl, CoMo, RuMo, NbV, TaNb, V 3 Cr、V 3 Mo, Er 2 Ni 7 、FeCo 3 , LaCu 13 , FeNi, FeRu, BeCo, TaV, CrNi, TiV, ZrNb, MoRu, MoRu 3 、Mo 3 Ru, or a combination thereof.

[0071] The conductive compound may include a metal nitride, a metal phosphide, a metal arsenide, or a combination thereof. For example, the conductive compound may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium nitride (RuN), tungsten nitride (WN), aluminum nitride (AlN), iridium tantalum nitride (IrTaN), titanium silicon nitride (TiSiN), niobium nitride (NbN), molybdenum nitride (MoN), molybdenum phosphide (MoP), niobium arsenide (NbAs), etc.

[0072] The conductive layer 103 may have a single crystal structure.

[0073] Conductive layer 103 may have a thickness of less than or equal to about 10 nm, such as less than or equal to about 9 nm, less than or equal to about 8 nm, less than or equal to about 7 nm, less than or equal to about 6 nm, and greater than or equal to about 0.1 nm. Within the above range, a nanoscale wiring structure can be provided.

[0074] The passivation layer 105, 105-1, or 105-2 may have a thickness of less than or equal to about 30 nm, for example, less than or equal to about 25 nm, less than or equal to about 20 nm, less than or equal to about 15 nm, less than or equal to about 10 nm, less than or equal to about 9 nm, less than or equal to about 8 nm, less than or equal to about 7 nm, or less than or equal to about 6 nm, and may have a thickness of greater than or equal to about 0.1 nm. Within the above range, oxidation of the conductive layer 103 may be prevented while suppressing grain boundary scattering and / or surface roughness scattering effects, thereby preventing a rapid increase in resistance.

[0075] The thickness ratio of the conductive layer 103 and the passivation layer 105, 105-1, or 105-2 may be in the range of about 1:0.01 to about 1:3. For example, the thickness ratio of the passivation layer 105, 105-1, or 105-2 to the conductive layer 103 may be greater than or equal to about 0.01, greater than or equal to about 0.02, greater than or equal to about 0.03, greater than or equal to about 0.04, greater than or equal to about 0.05, greater than or equal to about 0.06, greater than or equal to about 0.07, greater than or equal to about 0.08, greater than or equal to about 0.09, greater than or equal to about 0.1, greater than or equal to about 0.2, greater than or equal to about 0.3, greater than or equal to about 0.4, or greater than or equal to about 0.5. The thickness of the passivation layer 105, 105-1, or 105-2 to the conductive layer 103 may be less than or equal to about 0.5, and may be less than or equal to about 2.9, less than or equal to about 2.7, less than or equal to about 2.6, less than or equal to about 2.5, less than or equal to about 2.4, less than or equal to about 2.2, less than or equal to about 2.0, less than or equal to about 1.9, less than or equal to about 1.7, less than or equal to about 1.6, less than or equal to about 1.5, less than or equal to about 1.4, less than or equal to about 1.3, less than or equal to about 1.2, less than or equal to about 1.1, less than about 1, or less than or equal to about 1. In addition, the thickness ratio of the passivation layer 105, 105-1, or 105-2 to the conductive layer 103 may be within a range combining the above numerical ranges (e.g., about 0.01 to about 1.9).

[0076] The conductive wiring configured as a heterogeneous structure having the conductive layer 103 and the passivation layers 105, 105-1, and 105-2 can prevent an increase in resistance due to a reduction in the wiring line width and reduce or prevent defects in the wiring due to electromigration. The passivation layers 105, 105-1, and 105-2 can be used as a barrier layer to prevent the material of the conductive layer 103 from diffusing.

[0077] refer to Figure 1 and 2 , the passivation layer 105 includes: a first layer 105a including hexagonal boron nitride (h-BN) and a second layer 105b including amorphous boron nitride (a-BN), and the first layer 105a is arranged to contact the conductive layer 103. The first layer 105a may not include amorphous boron nitride (a-BN). Figure 3 , a first passivation layer 105-1 is formed on the lower surface of the conductive layer 103, and a second passivation layer 105-2 is formed on the upper surface of the conductive layer 103, and these first and second passivation layers 105-1 and 105-2 include: a first layer 105-1a and 105-2a including hexagonal boron nitride (h-BN) and a second layer 105-1b and 105-2b including amorphous boron nitride (a-BN), and the first layers 105-1a and 105-2a are in contact with the conductive layer 103.

[0078] Hexagonal boron nitride (h-BN) included in the first layer 105a may be obtained from amorphous boron nitride (a-BN) included in the second layer 105b.

[0079] Conventionally, hexagonal boron nitride (h-BN) is formed by depositing a precursor material (e.g., borazine) at a high temperature, but the high temperature deposition process may have a negative effect on the material constituting the device, which reduces the efficiency of the device. Therefore, in an embodiment, instead of using a high temperature deposition process, amorphous boron nitride (a-BN) is used as a precursor, and the metal included in the conductive layer 103 is used as a catalyst to convert the amorphous boron nitride (a-BN) into hexagonal boron nitride (h-BN) at a relatively low temperature to form the passivation layer 105. That is, the passivation layer 105 capable of preventing grain boundary scattering and / or surface roughness scattering effects can be formed by a low temperature process, thereby suppressing or reducing the scattering effect that causes signal transmission delay by a simple process without affecting the performance of the device. The process for converting amorphous boron nitride (a-BN) into hexagonal boron nitride (h-BN) is described below.

[0080] Hexagonal boron nitride (h-BN) included in the first layer 105a has a hexagonal crystal structure and can form a van der Waals bond with the wiring material constituting the conductive layer 103, thereby reducing the overlapping electron density at the interface with the conductive layer 103, and can serve as an interface control material that suppresses or reduces the grain boundary scattering and / or surface roughness scattering effect of the wiring material of the conductive layer 103 at the interface with the conductive layer 103. This can effectively improve the signal transmission delay problem in the wiring structure.

[0081] The first layer 105a, 105-1a, and 105-2a may have a thickness of less than or equal to about 3 nm, for example, less than or equal to about 2.9 nm, less than or equal to about 2.8 nm, less than or equal to about 2.7 nm, less than or equal to about 2.6 nm, less than or equal to about 2.5 nm, less than or equal to about 2.4 nm, less than or equal to about 2.3 nm, less than or equal to about 2.2 nm, less than or equal to about 2.1 nm, or less than or equal to about 2.0 nm, and may have a thickness greater than or equal to about 0.1 nm, for example, greater than or equal to about 0.2 nm, greater than or equal to about 0.3 nm, greater than or equal to about 0.4 nm, greater than or equal to about 0.5 nm, greater than or equal to about 0.6 nm, greater than or equal to about 0.7 nm, greater than or equal to about 0.8 nm, greater than or equal to about 0.9 nm, or greater than or equal to about 1.0 nm. In addition, the thickness of the first layers 105a, 105-1a, and 105-2a may be within a range combining the above numerical ranges (eg, about 0.1 nm to about 3 nm).

[0082] The second layers 105b, 105-1b, and 105-2b may have a thickness less than or equal to about 25 nm, for example, less than or equal to about 20 nm, less than or equal to about 18 nm, less than or equal to about 16 nm, less than or equal to about 15 nm, less than or equal to about 12 nm, less than or equal to about 10 nm, less than or equal to about 8 nm, less than or equal to about 7 nm, less than or equal to about 6 nm, less than or equal to about 5 nm, less than or equal to about 4.9 nm, less than or equal to about 4.8 nm, less than or equal to about 4.7 nm, less than or equal to about 4.6 nm, less than or equal to about 4.5 nm, less than or equal to about 4.4 nm, less than or equal to about 4.3 nm, less than or equal to about 4.2 nm, less than or equal to about 4.1 nm, or less than or equal to about 4.0 nm and greater than or equal to about 0.5 nm, for example, greater than or equal to about 0.6 nm, greater than or equal to about 0.7 nm, greater than or equal to about 0.8 nm, greater than or equal to about 0.9 In some embodiments, the thickness of the second layer 105b, 105-1b, and 105-2b may be within a range combining the above numerical ranges (e.g., about 0.5 nm to about 9 nm).

[0083] A thickness ratio of the first layers 105a, 105-1a, and 105-2a to the second layers 105b, 105-1b, and 105-2b may be in the range of about 1:1.5 to about 1:8. For example, the thickness ratio of the second layer 105b, 105-1b, and 105-2b to the first layer 105a, 105-1a, and 105-2a may be greater than or equal to about 1.5, greater than or equal to about 1.6, greater than or equal to about 1.7, greater than or equal to about 1.8, greater than or equal to about 1.9, or greater than or equal to about 2.0, and may be less than or equal to about 8.0, less than or equal to about 7.0, less than or equal to about 6.0, less than or equal to about 5.0, less than or equal to about 4.0, less than or equal to about 3.5, less than or equal to about 3.0, less than or equal to about 2.9, less than or equal to about 2.8, less than or equal to about 2.7, less than or equal to about 2.6, or less than or equal to about 2.5. In addition, a thickness ratio of the second layer 105b, 105-1b, and 105-2b to the first layer 105a, 105-1a, and 105-2a may be within a range combining the above numerical ranges (eg, about 1.5 to about 8).

[0084] exist Figures 1 to 3, the passivation layers 105, 105-1, and 105-2 are described as having a two-layer structure in which first layers 105a, 105-1a, and 105-2a are stacked with second layers 105b, 105-1b, and 105-2b, but a multilayer structure of three or more layers may also be possible.

[0085] In an implementation, the passivation layers 105 , 105 - 1 , and 105 - 2 may further include a third layer (not shown) including a dielectric on a surface of the second layer 105 b not in contact with the first layer 105 a .

[0086] The third layer may include an inorganic oxide, and specifically may include Al 2 O 3 、AlN、ZrO 2 , HfO x (0 <x≤2)、SiO 2 , SiCO, SiCN, SiON, SiCOH, AlSiO, or a combination thereof.

[0087] The third layer may have a thickness of less than or equal to about 20 nm, less than or equal to about 18 nm, less than or equal to about 16 nm, less than or equal to about 15 nm, less than or equal to about 12 nm, less than or equal to about 10 nm, less than or equal to about 8 nm, less than or equal to about 7 nm, less than or equal to about 6 nm, less than or equal to about 5 nm, less than or equal to about 4.9 nm, less than or equal to about 4.8 nm, less than or equal to about 4.7 nm, less than or equal to about 4.6 nm, less than or equal to about 4.5 nm, less than or equal to about 4.4 nm, less than or equal to about 4.3 nm, less than or equal to about 4.2 nm, less than or equal to about 4.1 nm, or less than or equal to about 4.0 nm, and may have a thickness of greater than or equal to about 0.5 nm, for example, greater than or equal to about 0.6 nm, greater than or equal to about 0.7 nm, greater than or equal to about 0.8 nm, greater than or equal to about 0.9 nm, greater than or equal to about 1.0 nm, greater than or equal to about 1.1 nm, or greater than or equal to about 1.2 nm. nm, greater than or equal to about 1.2 nm, greater than or equal to about 1.3 nm, greater than or equal to about 1.4 nm, or greater than or equal to about 1.5 nm.

[0088] Since the above-mentioned hexagonal boron nitride (h-BN) is formed by conversion of amorphous boron nitride (a-BN) as a dielectric material, the passivation layer 105 can be formed without reducing the area of ​​the conductive layer 103 .

[0089] In an interconnect structure according to an embodiment, since the passivation layer 105 is formed in contact with the conductive layer 103, a separate barrier layer for preventing the diffusion of the material of the conductive layer 103 or an underlayer for improving the adhesion strength of the conductive layer 103 is not required.

[0090] However, in another embodiment, a barrier layer may be further included between the substrate 101 and the conductive layer 103 or between the substrate 101 and the passivation layer 105. As described above, since the passivation layer 105 can act as a barrier layer, the barrier layer may not be included.

[0091] The barrier layer may include a metal, an alloy of a metal, a metal oxide, a metal nitride, or a combination thereof.

[0092] The barrier layer may prevent or reduce the diffusion of the materials of the conductive layer 103 and the passivation layer 105 into the substrate 101. The barrier layer may have a multi-layer structure in which a plurality of layers including different materials are stacked. For example, the barrier layer may include a first barrier layer in contact with the conductive layer 103 or the passivation layer 105 and a second barrier layer in contact with the substrate 101. The first barrier layer may include a metal or an alloy of a metal, and the second barrier layer may include a metal nitride or a metal oxide.

[0093] The metal that can be used for the barrier layer may be one of the following: magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), lead (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), bismuth (Bi), cobalt (Co), ruthenium (Ru), and combinations thereof. The metal alloy of the barrier layer may include RuTa, IrTa, etc.

[0094] The metal oxide of the barrier layer may be a compound represented by Chemical Formula 1.

[0095] [Chemical Formula 1]

[0096] M x O y

[0097] In Chemical Formula 1,

[0098] M may be at least one of Mn, Al, Ti, Zr, Hf, Mg, Si, Ge, Y, Lu, La, Ta, or Sr, 0 < x ≤ 2, and 0 < y ≤ 3.

[0099] Examples of the metal oxide may include MnO, AlO z(0 <z≤3 / 2)、TaO z (0 <z≤5 / 2)、TiO 2 、ZrO 2 , HfO 2 、MgO、SiO 2 ,GeO 2 , Y 2 O 3 、Lu 2 O 3 ,La 2 O 3 , SrO, etc.

[0100] The metal nitride of the barrier layer may include tantalum nitride (TaN), titanium nitride (TiN), ruthenium nitride (RuN), tungsten nitride (WN), aluminum nitride (AlN), IrTaN, TiSiN, or the like.

[0101] The multilayer metal wiring structure including the above-described conductive layer 103 and passivation layer 105 may be placed in the groove of the substrate 101 .

[0102] Reference Figures 4 to 8 The structure is described. Figures 4 to 8 is a cross-sectional view of an interconnect structure according to some example embodiments.

[0103] refer to Figure 4 , the interconnect structure 200a includes a conductive layer 103 filled inside the groove 101a of the substrate 101 and a passivation layer 1051 disposed on the upper surface of the conductive layer 103. The passivation layer 1051 includes: a first layer 1051a including hexagonal boron nitride (h-BN) and a second layer 1051b including amorphous boron nitride (a-BN), and the first layer 1051a is arranged to contact the conductive layer 103. The first layer 1051a may not include amorphous boron nitride (a-BN).

[0104] refer to Figure 5 , the interconnect structure 200b has a conductive layer 103 inside the groove 101a of the substrate 101 and a passivation layer 1052 on the upper surface of the conductive layer 103 and inside the groove 101a of the substrate 101. The passivation layer 1052 includes: a first layer 1052a including hexagonal boron nitride (h-BN) and a second layer 1052b including amorphous boron nitride (a-BN), and the first layer 1052a is arranged to contact the conductive layer 103. The first layer 1052a may not include amorphous boron nitride (a-BN).

[0105] refer to Figure 6, the interconnect structure 200c includes a passivation layer 1053 present along the groove 101a of the substrate 101 and a conductive layer 103 located in the groove 101a. The passivation layer 1053 includes: a first layer 1053a including hexagonal boron nitride (h-BN) and a second layer 1053b including amorphous boron nitride (a-BN), and the first layer 1053a is arranged to contact the conductive layer 103. The first layer 1053a may not include amorphous boron nitride (a-BN).

[0106] refer to Figure 7 The interconnect structure 200d has a first passivation layer 1053 located along the groove 101a of the substrate 101, a conductive layer 103 located in the groove, and a second passivation layer 1051 disposed on the upper surface of the conductive layer 103. The first passivation layer 1053 includes: a first layer 1053a including hexagonal boron nitride (h-BN) and a second layer 1053b including amorphous boron nitride (a-BN), and the first layer 1053a is arranged to contact the conductive layer 103. The second passivation layer 1051 includes: a first layer 1051a including hexagonal boron nitride (h-BN) and a second layer 1051b including amorphous boron nitride (a-BN), and the first layer 1051a is arranged to contact the conductive layer 103. The first layers 1053a, 1051a may not include amorphous boron nitride (a-BN). The first passivation layer 1053 and the second passivation layer 1051 together may surround the entirety (entirety) of the conductive layer 103 .

[0107] refer to Figure 8 , the interconnect structure 200e includes a first passivation layer 1053 existing along the groove 101a of the substrate 101, the conductive layer 103 buried in the groove, and a second passivation layer 1052 disposed on the upper surface of the conductive layer 103 and the first passivation layer 1053 and buried in the groove. The first passivation layer 1053 includes: a first layer 1053a including hexagonal boron nitride (h-BN) and a second layer 1053b including amorphous boron nitride (a-BN), and the first layer 1053a is arranged to contact the conductive layer 103. The second passivation layer 1052 includes: a first layer 1052a including hexagonal boron nitride (h-BN) and a second layer 1052b including amorphous boron nitride (a-BN), and the first layer 1052a is arranged to contact the conductive layer 103. The first layers 1053a and 1052a may not include amorphous boron nitride (a-BN). The first passivation layer 1053 and the second passivation layer 1052 together may surround the entirety of the conductive layer 103 .

[0108] As a method for forming the trench in the substrate 101 , a photolithography process and an etching process such as reactive ion etching (“RIE”) may be used.

[0109] Figures 5 to 8The substrate 101, the conductive layer 103, and the passivation layers 1051, 1052, and 1053 are Figures 1 to 3 The substrate 101, the conductive layer 103, and the passivation layers 105, 105-1, and 105-2 described in the drawings are the same as those described in the drawings, and thus their detailed descriptions are omitted.

[0110] exist Figures 5 to 8 In the interconnect structure shown in FIG. 1 , the barrier layer may be located on the inner surface of the trench 101 a . Fig. 9 It is shown in Figure 4 The interconnect structure further includes a barrier layer. Fig. 9 is a cross-sectional view of an interconnect structure according to an embodiment.

[0111] refer to Fig. 9 , the interconnect structure 200f includes a barrier layer 107 on opposite side surfaces and a lower surface of a trench 101a of a substrate 101, wherein the barrier layer 107 surrounds the conductive layer 103 inside the trench 101a, and a passivation layer 1051 is located on an upper surface of the conductive layer 103. The passivation layer 1051 includes: a first layer 1051a including hexagonal boron nitride (h-BN) and a second layer 1051b including amorphous boron nitride (a-BN), and the first layer 1051a is arranged to contact the conductive layer 103. The first layer 1051a may not include amorphous boron nitride (a-BN).

[0112] The barrier layer 107 may prevent or reduce the diffusion of materials of the conductive layer 103 and the passivation layer 1051 into the substrate 101. The barrier layer 107 may have a multilayer structure in which a plurality of layers including different materials are stacked. For example, the barrier layer 107 may include a first barrier layer in contact with the conductive layer 103 or the passivation layer 1051 and a second barrier layer in contact with the substrate 101. The first barrier layer may include a metal or an alloy of a metal, and the second barrier layer may include a metal nitride or a metal oxide. Specific examples of the metal, metal alloy, metal oxide, and metal nitride that can be used in the barrier layer are as described above.

[0113] The above description is Figure 4 An example of a barrier layer formed in a structure of Figures 5 to 8 The interconnect structure shown in FIG. 1 may also have a barrier layer formed along the trench 101 a of the substrate 101 .

[0114] As mentioned above, in Figures 6 to 8 In the interconnect structure shown in FIG. 1 , the passivation layer may serve as a barrier layer, and thus the barrier layer may be omitted.

[0115] If the upper surface of the substrate is flat, the multilayer wiring structure of the conductive layer and the passivation layer may have empty spaces on opposite sides. Fig.10 middle. Fig.10 is a cross-sectional view of an interconnect structure according to an embodiment.

[0116] refer to Fig.10 , the interconnect structure 300 has a multilayer structure of a conductive layer 103 on a substrate 101 and a passivation layer 105 surrounding the conductive layer 103, and empty spaces 110a and 110b are formed on opposite sides of the multilayer structure. The passivation layer 105 includes: a first layer 105a including hexagonal boron nitride (h-BN) and a second layer 105b including amorphous boron nitride (a-BN), and the first layer 105a is arranged to contact the conductive layer 103. The first layer 105a may not include amorphous boron nitride (a-BN).

[0117] exist Fig.10 In the embodiment, the empty spaces 110a and 110b may be filled with air or the like, and if the empty spaces 110a and 110b are air gaps filled with air, the air gaps themselves may function as a dielectric. Fig.10 A structure in which the upper surface and the side surface of the conductive layer 103 are surrounded by the passivation layer 105 is shown, but in another embodiment, the passivation layer may also exist on the lower surface of the conductive layer 103. In addition, the passivation layer may also be provided on any one of the upper surface, the side surface, and the lower surface of the conductive layer 103.

[0118] The interconnect structure can mitigate an increase in resistance due to a reduction in line width of wiring (eg, conductive layer 103) caused by high integration of semiconductor devices, and can reduce or prevent defects caused by electromigration due to an increase in resistance within the interconnect structure.

[0119] Hereinafter, a method for manufacturing the above-mentioned interconnection structure is described.

[0120] For manufacturing Figure 1 The method of interconnect structure 100a shown in includes: forming a conductive layer 103 on a substrate; forming a dielectric layer including amorphous boron nitride (a-BN) on the conductive layer 103; and converting amorphous boron nitride (a-BN) present at an interface between the dielectric layer and the conductive layer 103 into hexagonal boron nitride (h-BN) to form a passivation layer 105, the passivation layer 105 including: a first layer 105a including hexagonal boron nitride (h-BN) and a second layer 105b including amorphous boron nitride (a-BN). The first layer 105a may not include amorphous boron nitride (a-BN).

[0121] For manufacturing Figure 2The method of the interconnect structure 100b shown in FIG. 1 comprises: forming a dielectric layer including amorphous boron nitride (a-BN) on a substrate; forming a conductive layer 103 on the dielectric layer; and converting the amorphous boron nitride (a-BN) present at the interface between the dielectric layer and the conductive layer 103 into hexagonal boron nitride (h-BN) to form a passivation layer 105, the passivation layer 105 comprising: a first layer 105a including hexagonal boron nitride (h-BN) and a second layer 105b including amorphous boron nitride (a-BN).

[0122] For manufacturing Figure 3 The method of the interconnect structure 100c shown in FIG. 1 comprises: forming a first dielectric layer including amorphous boron nitride (a-BN) on a substrate; forming a conductive layer 103 on the dielectric layer; forming a second dielectric layer including amorphous boron nitride (a-BN) on the conductive layer 103; and converting the amorphous boron nitride (a-BN) present at the interface between the first dielectric layer and the conductive layer 103 into hexagonal boron nitride (h-BN) and converting the amorphous boron nitride (a-BN) present at the interface between the second dielectric layer and the conductive layer 103 into hexagonal boron nitride (h-BN). The amorphous boron nitride (a-BN) at the position is converted into hexagonal boron nitride (h-BN) to form a first passivation layer 105-1 and a second passivation layer 105-2, the first passivation layer 105-1 includes: a first layer 105-1a including hexagonal boron nitride (h-BN) and a second layer 105-1b including amorphous boron nitride (a-BN), and the second passivation layer 105-2 includes: a first layer 105-2a including hexagonal boron nitride (h-BN) and a second layer 105-2b including amorphous boron nitride (a-BN). The first layers 105-1a and 105-2a may not include amorphous boron nitride (a-BN).

[0123] The conductive layer 103 and the dielectric layer of the interconnect structures 100a, 100b, and 100c may be formed by atomic layer deposition ("ALD"), chemical vapor deposition ("CVD"), or plasma enhanced CVD ("PECVD"), but the present disclosure is not limited thereto.

[0124] The process of converting amorphous boron nitride (a-BN) present at the interface between the dielectric layer (including the first dielectric layer and the second dielectric layer) and the conductive layer 103 into hexagonal boron nitride (h-BN) may include a process of locally applying energy to the amorphous boron nitride (a-BN) included in the dielectric layer.

[0125] The energy application process may include an annealing process, laser irradiation, or a combination thereof. The energy application process may be performed locally at an interface between the dielectric layer and the conductive layer, thereby minimizing damage to the device.

[0126] The annealing process may be a rapid thermal annealing (“RTA”) process, and may be performed at a temperature of about 800° C. to about 1000° C. for about 1 to about 10 minutes. For example, during the annealing process, the temperature may be greater than or equal to about 810° C., such as greater than or equal to about 820° C., greater than or equal to about 830° C., greater than or equal to about 840° C., or greater than or equal to about 850° C., and may be less than or equal to about 1000° C., such as less than or equal to about 990° C., less than or equal to about 980° C., less than or equal to about 970° C., less than or equal to about 960° C., less than or equal to about 950° C., less than or equal to about 940° C., less than or equal to about 930° C., less than or equal to about 920° C., less than or equal to about 910° C., or less than or equal to about 900° C. Within the above range, amorphous boron nitride (a-BN) present at the interface between the dielectric layer and the conductive layer may be easily converted into hexagonal boron nitride (h-BN).

[0127] The laser irradiation may be performed by locally irradiating the interface between the dielectric layer and the conductive layer with a laser having a wavelength range of about 100 nm to about 1000 nm. The wavelength range of the laser may be greater than or equal to about 100 nm, for example, greater than or equal to about 200 nm, greater than or equal to about 300 nm, greater than or equal to about 400 nm, or greater than or equal to about 500 nm, and may be less than or equal to about 1000 nm, for example, less than or equal to about 950 nm, or less than or equal to about 900 nm. Within the above range, amorphous boron nitride (a-BN) present at the interface between the dielectric layer and the conductive layer may be easily converted into hexagonal boron nitride (h-BN).

[0128] Through the above-mentioned local energy application process, the amorphous boron nitride (a-BN) included in the dielectric layer is used as a precursor material, and the metal included in the conductive layer acts as a catalyst, so that the amorphous boron nitride (a-BN) present at the interface between the dielectric layer and the conductive layer is converted into hexagonal boron nitride (h-BN). As a result, a first layer including hexagonal boron nitride (h-BN) is formed at the interface between the dielectric layer and the conductive layer, which constitutes a passivation layer. By applying local energy at the interface between the dielectric layer and the conductive layer, a first layer including hexagonal boron nitride (h-BN) can be formed as a continuous layer on the surface in contact with the conductive layer. The first layer may be a single layer of h-BN or a multilayer in which 2 to 5 single layers are stacked. This can effectively suppress or reduce grain boundary scattering and / or surface roughness scattering effects.

[0129] The interconnect structures 100a, 100b, 100c, 200a, 200b, 200c, 200d, 200e, 200f, and 300 described above may provide electronic devices. For example, the electronic devices may include semiconductor devices, in which case the interconnect structures 100a, 100b, 100c, 200a, 200b, 200c, 200d, 200e, 200f, and 300 may be applied to the back end of line (BEOL) structure of the semiconductor devices. The semiconductor devices may include at least one of transistors, capacitors, diodes, or resistors. In addition, the interconnect structures 100a, 100b, 100c, 200a, 200b, 200c, 200d, 200e, 200f, and 300 may be applied to a variety of electronic devices.

[0130] In the following, reference will be made to Fig.11 and 12 An electronic device including the above interconnect structure is described.

[0131] Fig.11 and 12 is a cross-sectional view of an electronic device according to some example embodiments.

[0132] refer to Fig.11 In an embodiment, the electronic device 700a may be formed of a transistor connected to the data storage DS. The electronic device 700a may include a substrate SUB and an oxide dielectric layer 710. The conductive layer 103 and the passivation layer 1053 exist inside the trench of the oxide dielectric layer 710. The conductive layer 103 and the passivation layer 1053 may have the same Figure 6 The same structure as shown in . Fig.11 The conductive layer and passivation layer can Figure 4 , 5 and any one of the arrangements of the structures shown in 7 to 9.

[0133] The gate insulating layer 770 is disposed on the oxide dielectric layer 710. On the gate insulating layer 770, the source electrode 751 and the drain electrode 752 are arranged to be spaced apart from each other. The conductive layer 103 may be configured to operate as a gate of the electronic device 700a.

[0134] The electronic device 700a may further include an insulating layer 785, such as silicon oxide, covering the source 751, the gate insulating layer 770, and the drain 752, and a data storage DS (such as a capacitor) may be on the insulating layer 785. A contact 775 including a conductive material such as a metal or a metal alloy may connect the data storage DS and the drain 752.

[0135] refer to Fig.12 In an embodiment, the electronic device 700b and Fig.11The electronic device 700a shown in FIG. 7 is different in that the gate insulating layer 770, the contact 775, the source 751, the drain 752, and the data storage DS are omitted. In addition, the oxide dielectric layer 710 includes two trenches spaced apart from each other, and each of the trenches is spaced apart from the other. Figure 6 That is, each of the trenches may include a conductive layer 103 and a passivation layer 1053 formed therein.

[0136] Upper conductive layer 790 is formed on oxide dielectric layer 710 and contacts the upper surface of conductive layer 103 in each interconnect structure so that the interconnect structures can be electrically connected to each other. Upper conductive layer 790 may include a conductive material such as a metal, a metal alloy, or a doped semiconductor. Fig.12 The conductive layer and passivation layer can be Figure 4 , 5 and any one of the arrangements of the structures shown in 7 to 9.

[0137] Hereinafter, the embodiments are described in more detail with reference to examples. However, the following examples are for illustrative purposes only and do not limit the scope of the claims.

[0138] Example 1: Fabrication of a stacked structure for testing

[0139] The SiO 2 Borazine was deposited on a Si (thickness: 100 nm) / Si (thickness: 725 micrometers (μm)) substrate for 25 minutes to form an amorphous boron nitride film (dielectric layer, average thickness: 4.5 nm). Molybdenum was sputtered onto the dielectric layer to form a conductive layer having a thickness of 200 nm. Then, rapid thermal annealing (RTA) was performed at 815° C. for 4 minutes to convert amorphous boron nitride (a-BN) present at the interface between the conductive layer and the dielectric layer into hexagonal boron nitride (h-BN) to form a passivation layer, thereby manufacturing a stacked structure for testing.

[0140] Example 2: Fabrication of a stacked structure for testing

[0141] A stacked structure was manufactured in the same manner as in Example 1, except that the RTA process was performed at 900° C. for 5 minutes.

[0142] Example 3: Fabrication of a stacked structure for testing

[0143] A stacked structure was manufactured in the same manner as in Example 1, except that the RTA process was performed at 1000° C. for 1 minute.

[0144] Comparative Example 1

[0145] An amorphous boron nitride thin film (dielectric layer, average thickness: 4.5 nm) was formed by depositing borazine on a Si (thickness: 525 μm) substrate using an ICP-CVD process at 400° C. for 25 minutes, and then rapid thermal annealing (RTA) was performed at 900° C. for 5 minutes.

[0146] In order to confirm the formation of hexagonal boron nitride (h-BN) in the stacked structures according to Examples 1 to 3, Raman spectra were obtained after removing molybdenum and are shown in FIG. Fig.13 For comparison, the Raman spectrum of the stacked structure according to Comparative Example 1 is also shown. Fig.13 : is a graph showing the results of Raman spectroscopy evaluation to confirm the formation of hexagonal boron nitride (h-BN) in the structures according to Examples 1 to 3 and Comparative Example 1.

[0147] refer to Fig.13 , a peak (1372 cm -1 ), while this peak was not observed in Comparative Example 1. Thus, it can be confirmed that in the stacked structures according to Examples 1 to 3, hexagonal boron nitride (h-BN) converted from the amorphous boron nitride (a-BN) of the dielectric layer is formed.

[0148] While the disclosure has been described in connection with what are presently considered to be practical example embodiments, it will be understood that the invention is not limited to the disclosed embodiments, but on the contrary is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

[0149] <Description of symbols>

[0150] 100a, 100b, 100c, 200a, 200b, 200c, 200d, 200e, 200f, 300: interconnection structure

[0151] 101, SUB: substrate 103: conductive layer

[0152] 105, 105-1, 105-2, 1051, 1052, 1053: passivation layer

[0153] 105a, 105-1a, 105-2a, 1051a, 1052a, 1053a: First floor

[0154] 105b, 105-1b, 105-2b, 1051b, 1052b, 1053b: Second layer

[0155] 700a, 700b: electronic device 710: oxide dielectric layer

[0156] 770: Gate insulation layer 751: Source

[0157] 752: Drain DS: Data storage

[0158] 785: Insulation layer 790: Upper conductive layer

Claims

1. An interconnection structure comprising: Base, a conductive layer on the substrate, and a passivation layer in contact with the conductive layer, The passivation layer includes: a first layer including hexagonal boron nitride (h-BN) having a hexagonal crystal structure and a second layer including amorphous boron nitride (a-BN), and The first layer is in contact with the conductive layer.

2. The interconnect structure according to claim 1, wherein The passivation layer is disposed on at least one of an upper surface or a lower surface of the conductive layer.

3. The interconnect structure according to claim 1, wherein The conductive layer includes metal, metal alloy, conductive compound, or a combination thereof.

4. The interconnect structure according to claim 3, wherein The metal includes a transition metal, a Group 2A metal, a Group 3A (Group 13) metal, or a combination thereof.

5. The interconnect structure according to claim 1, wherein The conductive layer includes copper (Cu), ruthenium (Ru), aluminum (Al), cobalt (Co), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), chromium (Cr), rhodium (Rh), iridium (Ir), palladium (Pd), osmium (Os), gold (Au), niobium (Nb), vanadium (V), scandium (Sc), erbium (Er), lanthanum (La), or a combination thereof.

6. The interconnect structure according to claim 1, wherein The conductive layer has a thickness greater than or equal to 0.1 nanometers (nm) and less than or equal to 10 nm, and the passivation layer has a thickness greater than or equal to 0.1 nm and less than or equal to 30 nm.

7. The interconnect structure of claim 1, wherein The thickness ratio of the conductive layer to the passivation layer is in the range of 1:0.01 to 1:

3.

8. The interconnect structure of claim 1, wherein Hexagonal boron nitride (h-BN) included in the first layer is derived from amorphous boron nitride (a-BN) included in the second layer.

9. The interconnect structure of claim 1, wherein Hexagonal boron nitride (h-BN) included in the first layer forms a van der Waals bond with a material constituting the conductive layer.

10. The interconnect structure of claim 1, wherein The first layer has a thickness greater than or equal to 0.1 nm and less than or equal to 3 nm, and the second layer has a thickness greater than or equal to 0.5 nm and less than or equal to 25 nm.

11. The interconnect structure of claim 1, wherein A thickness ratio of the first layer to the second layer is in a range of 1:1.5 to 1:

8.

12. The interconnect structure of claim 1, wherein The substrate includes a dielectric layer having a trench structure defined therein, The conductive layer fills the interior of the trench structure, and The passivation layer is disposed on the upper surface of the conductive layer; or The substrate includes a dielectric layer having a trench structure defined therein, The conductive layer fills the interior of the trench structure, and The passivation layer is disposed on the lower surface and the side surface of the conductive layer; or The substrate includes a dielectric layer having a trench structure defined therein, The conductive layer fills the interior of the trench structure, and The passivation layer surrounds the entirety of the conductive layer.

13. A method for manufacturing an interconnect structure as claimed in any one of claims 1 and 3 to 11, comprising: forming a conductive layer on a substrate; forming a dielectric layer including amorphous boron nitride (a-BN) on the conductive layer; as well as Amorphous boron nitride (a-BN) present at an interface between the dielectric layer and the conductive layer is converted into hexagonal boron nitride (h-BN) to form a passivation layer, the passivation layer comprising: a first layer comprising hexagonal boron nitride (h-BN) and a second layer comprising amorphous boron nitride (a-BN).

14. A method for manufacturing an interconnect structure as claimed in any one of claims 1 and 3 to 11, comprising: forming a dielectric layer including amorphous boron nitride (a-BN) on a substrate; forming a conductive layer on the dielectric layer; as well as Amorphous boron nitride (a-BN) present at an interface between the dielectric layer and the conductive layer is converted into hexagonal boron nitride (h-BN) to form a passivation layer, the passivation layer comprising: a first layer comprising hexagonal boron nitride (h-BN) and a second layer comprising amorphous boron nitride (a-BN).

15. The method of claim 13 or 14, wherein The passivation layer is formed by locally applying energy to amorphous boron nitride (a-BN) included in the dielectric layer to convert it into hexagonal boron nitride (h-BN) included in the first layer.

16. An electronic device comprising the interconnection structure according to any one of claims 1 to 12.

17. The electronic device of claim 16, wherein The electronic device is a transistor, a capacitor, a diode, or a resistor.

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