Test structure and gate line width roughness test method

Abstract

The invention relates to the technical field of semiconductor manufacturing, and provides a test structure and a gate line width roughness test method. The test structure comprises a test active region and a test grid located on the test active region; the test active region comprises a test source electrode and a test drain electrode, and the test source electrode and the test drain electrode are located on the two sides of the test grid electrode respectively; the test grid is provided with a corresponding grid design pattern, the grid design pattern extends along the first direction, and the grid design pattern has different width dimensions along the second direction. The grid design patterns of the test structure have different width dimensions, and the line width roughness of the test grid can be adjusted in a single variable manner on the premise of ensuring that the overall average line width of the test grid is fixed by scaling the local width dimensions of the grid design patterns, so that a basis is provided for the manufacturing process of the grid.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a test structure and a gate line width roughness test method. Background Art

[0002] In the field of semiconductor manufacturing, with the development of technology, the size of semiconductor devices is getting smaller and smaller, while the complexity is getting higher and higher. In order to monitor the manufacturing process of semiconductor devices and ensure the reliability of semiconductor devices, it is usually necessary to design a test key (test structure) during the tape-out (trial production) process. Test key is a test unit added to a fixed position on the wafer during the chip manufacturing process to monitor whether the chip manufacturing process is healthy and whether the device performance is normal.

[0003] Usually, the test key and the semiconductor device in the wafer are manufactured in the same semiconductor process, and the test key and the semiconductor device have a corresponding relationship with each other. Each layer of interconnection lines in the semiconductor device corresponds to the test line located at the same layer in the test structure, and each plug in the semiconductor device corresponds to the test plug located at the same layer in the test structure. Since the test structure and the semiconductor device are prepared in the same process and have a corresponding relationship with each other, the performance of the semiconductor device in the wafer can be obtained by detecting the performance of the test structure.

[0004] Polysilicon gate is an important structure that controls the opening and closing of MOS (Metal Oxide Semiconductor) devices. The line width of polysilicon gate will affect the electrical parameters of MOS devices. Due to the limitations of photolithography technology and fluctuations in manufacturing process parameters in the chip manufacturing process, the line width of polysilicon gate will be uneven or the surface will be uneven, which will lead to negative effects such as unstable device current characteristics, threshold voltage drift, and increased leakage current.

[0005] In the prior art, the line width of the polysilicon gate is biased to obtain device electrical data of different polysilicon gate line widths, so that the influence of the overall line width of the polysilicon gate on the electrical data can be analyzed. Figure 1 This is a schematic diagram of the structure of the overall pull-off comparison of the line width of the polysilicon gate. Figure 1As shown, by pulling the line width of the polysilicon gate 100 as a whole, the electrical data of devices with different line widths are obtained, so that only the influence of the overall line width can be analyzed. In fact, due to the differences in the line width roughness (LineWidth Roughness, referred to as LWR) of the polysilicon gate, even devices with the same overall line width exhibit different electrical properties. Due to the lack of means to monitor the line width roughness, it is impossible to analyze the source of the electrical difference, and thus it is impossible to make an effective evaluation of the line width roughness of the polysilicon gate, so that the line width roughness of the polysilicon gate measured online cannot match the final electrical results. In addition, due to the bottleneck of lithography technology and the instability of the manufacturing process, the corresponding line width roughness value of the polysilicon gate and the corresponding electrical feedback data can only be passively obtained after the manufacturing is completed, which cannot meet the needs of DOE (Design of Experiments) experiment to control a single variable. Summary of the invention

[0006] In order to solve the above technical defects, the present invention provides a test structure and a gate line width roughness test method.

[0007] A first aspect of the present invention provides a test structure, comprising: a test active region and a test gate located on the test active region;

[0008] The test active area includes a test source and a test drain, and the test source and the test drain are respectively located on both sides of the test gate;

[0009] The test gate has a corresponding gate design pattern, the gate design pattern extends along a first direction, and the gate design pattern has different width dimensions along a second direction.

[0010] In an embodiment of the present invention, the gate design pattern includes: an adjustment portion; the adjustment portion includes a plurality of recessed portions and a plurality of raised portions;

[0011] Each of the recessed portions has a first width dimension along the second direction, and each of the raised portions has a second width dimension along the second direction.

[0012] In the embodiment of the present invention, the first width dimensions of the plurality of recessed portions are all the same; and the second width dimensions of the plurality of raised portions are all the same.

[0013] In an embodiment of the present invention, the gate design pattern further includes: a main body portion connected to the adjustment portion along a first direction; the concave portion of the adjustment portion is concave relative to the main body portion, and the convex portion of the adjustment portion is convex relative to the main body portion.

[0014] In the embodiment of the present invention, the main body has a third width dimension along the second direction;

[0015] The difference between the third width dimension of the main body portion and the first width dimension of each recessed portion is equal;

[0016] The difference between the second width dimension of each protrusion and the third width dimension of the main body is equal.

[0017] In the embodiment of the present invention, each recessed portion has a first length dimension along the first direction, and each raised portion has a second length dimension along the first direction;

[0018] The sum of the first length dimensions of the plurality of recessed portions is equal to the sum of the second length dimensions of the plurality of raised portions.

[0019] In the embodiment of the present invention, the first length dimensions of the plurality of recessed portions are all the same; and the second length dimensions of the plurality of raised portions are all the same.

[0020] In the embodiment of the present invention, the plurality of recessed portions and the plurality of raised portions are alternately arranged in sequence along the first direction.

[0021] In the embodiment of the present invention, the plurality of recessed portions and the plurality of raised portions are arranged in a wave form along the first direction.

[0022] In the embodiment of the present invention, the test structure further includes: a first test board and a second test board, the first test board is electrically connected to the test source, and the second test board is electrically connected to the test drain.

[0023] A second aspect of the present invention provides a gate line width roughness testing method, comprising:

[0024] Providing a plurality of the above test structures;

[0025] The width size of the gate design pattern corresponding to the test gate of each test structure is adjusted differently to obtain different gate line width roughness;

[0026] Conducting electrical testing on the adjusted test structure to obtain electrical testing data corresponding to different gate line width roughnesses;

[0027] According to the electrical property test data corresponding to different gate line width roughnesses, the correlation between the electrical property test data and the gate line width roughnesses is obtained.

[0028] In the embodiment of the present invention, the gate design pattern corresponding to the test gate of the test structure includes: an adjustment portion; the adjustment portion includes a plurality of recessed portions and a plurality of raised portions;

[0029] Each of the recessed portions has a first width dimension along the second direction, and each of the raised portions has a second width dimension along the second direction.

[0030] In the embodiment of the present invention, the gate design pattern corresponding to the test gate of the test structure further includes: a main body portion connected to the adjustment portion along the first direction; and the main body portion has a third width dimension along the second direction.

[0031] In an embodiment of the present invention, different adjustments are made to the width dimensions of the gate design patterns corresponding to the test gates of each test structure, including: adjusting the first width dimension of the recessed portion and the second width dimension of the raised portion in the gate design patterns corresponding to the test gates of each test structure, so that the difference between the third width dimension of the main portion of each gate design pattern and the first width dimension of the recessed portion is different, and the difference between the second width dimension of the raised portion and the third width dimension of the main portion of each gate design pattern is different.

[0032] In an embodiment of the present invention, different adjustments are made to the width dimensions of the gate design patterns corresponding to the test gates of each test structure, including: different adjustments are made to the number of recessed portions and the number of raised portions in the gate design patterns corresponding to the test gates of each test structure, so that the number of recessed portions and the number of raised portions of each gate design pattern are different, so that the gate line width roughness of each test structure changes differently.

[0033] The gate design pattern of the test structure of the present invention has different width sizes. The width size of the local gate design pattern can be scaled, and the line width roughness of the test gate can be adjusted by a single variable under the premise of ensuring a certain overall average line width of the test gate. During the test process, the electrical test data of the test structure can be matched with the line width roughness of the test gate with a strong correlation, providing a basis for the manufacturing process of the gate.

[0034] Other features and advantages of the technical solution of the present invention will be described in detail in the specific implementation section below. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0036] Figure 1 This is a schematic diagram of the structure for overall pull-off comparison of the line width of the polysilicon gate;

[0037] Figure 2 is a schematic diagram of a test structure provided by an embodiment of the present invention;

[0038] Figure 3 yes Figure 2 Schematic diagram of the cross section along line AA;

[0039] Figure 4 is a schematic diagram of a gate design pattern corresponding to a test gate of a test structure provided in Embodiment 1 of the present invention;

[0040] Figure 5 is a schematic diagram of a gate design pattern corresponding to a test gate of a test structure provided in Embodiment 2 of the present invention;

[0041] Figure 6 is a schematic diagram of a gate design pattern corresponding to a test gate of a test structure provided in a third embodiment of the present invention;

[0042] Figure 7 is a flow chart of a gate line width roughness testing method provided by an embodiment of the present invention;

[0043] Figure 8 Schematic diagram of the comparison of different gate design patterns in the gate line width roughness test method provided by the embodiment of the present invention Figure 1 ;

[0044] Fig. 9 Schematic diagram of the comparison of different gate design patterns in the gate line width roughness test method provided by the embodiment of the present invention Figure 2 .

[0045] Description of Reference Numerals

[0046] 100-polysilicon gate,

[0047] 20- Test structure,

[0048] 200-test active area, 201-test gate, 202-test source, 203-test drain,

[0049] 204-first test board, 205-second test board,

[0050] 206-first conductive plug, 207-second conductive plug,

[0051] 300-gate design graphics,

[0052] 3001-adjustment part, 3001a-recessed part, 3001b-raised part, 3002-main body. DETAILED DESCRIPTION

[0053] In order to make the technical solutions and advantages of the embodiments of the present invention more clearly understood, the exemplary embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0054] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0055] In the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", "connected" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0056] As described in the background technology, in the prior art, the electrical data of devices with different line widths are obtained by pulling the line width of the polysilicon gate as a whole, so that only the influence of the overall line width can be analyzed. In fact, due to the differences in the line width roughness (LWR) of the polysilicon gate, even devices with the same overall line width exhibit different electrical properties. Due to the lack of means to monitor the line width roughness, it is impossible to analyze the source of the electrical difference, and thus it is impossible to make an effective evaluation of the line width roughness of the polysilicon gate, so that the line width roughness of the polysilicon gate measured online cannot match the final electrical results. In addition, due to the bottleneck of lithography technology and the instability of the manufacturing process, the corresponding line width roughness value of the polysilicon gate and the corresponding electrical feedback data can only be passively obtained after the manufacturing is completed, which cannot meet the needs of DOE experiments to control a single variable.

[0057] In view of the above problems, an embodiment of the present invention provides a test structure, in which the gate design pattern of the test structure has different width sizes, so the width size of the local gate design pattern can be scaled, and the line width roughness of the test gate can be adjusted by a single variable under the premise of ensuring a certain overall average line width of the test gate. During the test process, the electrical test data of the test structure can be matched with the line width roughness of the test gate with a strong correlation, providing a basis for the manufacturing process of the gate.

[0058] like Figure 2 and Figure 3 As shown, the test structure 20 provided by the embodiment of the present invention includes: a test active area 200 on a substrate (not shown) and a test gate 201 located on the test active area 200, and the test gate 201 spans the test active area 200. The test gate 201 has a corresponding gate design pattern. There are multiple test sources 202 and multiple test drains 203 in the test active area 200, and the multiple test sources 202 and the multiple test drains 203 are respectively located on opposite sides of the test gate 201. The test source 202 is electrically connected to the first test board 204 through the first conductive plug 206, and the test drain 203 is electrically connected to the second test board 205 through the second conductive plug 207.

[0059] Figure 4 Schematic diagram of a gate design pattern corresponding to a test gate of a test structure provided in Embodiment 1 of the present invention. Figure 4 As shown, in the first embodiment, the gate design pattern 300 corresponding to the test gate 201 extends along the first direction X, and the gate design pattern 300 has different width dimensions along the second direction Y, and the first direction X is perpendicular to the second direction Y. Along the first direction X, the gate design pattern 300 includes: an adjustment portion 3001 and a main body portion 3002, and the adjustment portion 3001 has different width dimensions along the second direction Y. Along the first direction X, the adjustment portion 3001 includes a plurality of recessed portions 3001a and a plurality of raised portions 3001b. Along the second direction Y, each recessed portion 3001a has a first width dimension W1, and each raised portion 3001b has a second width dimension W2. The first width dimension W1 of the recessed portion and the second width dimension W2 of the raised portion can be adjusted, for example, they can be enlarged or reduced. The main body portion 3002 is connected to the adjustment portion 3001 along the first direction X, and the main body portion 3002 has a third width dimension W3 along the second direction Y. The recessed portion 3001a is recessed relative to the main body portion 3002, and the raised portion 3001b is raised relative to the main body portion 3002. Specifically, the recessed portion 3001a is recessed based on the main body portion 3002 toward a direction close to the main body portion 3002, and the raised portion 3001b is raised based on the main body portion 3002 toward a direction away from the main body portion 3002. The main body portion 3002 is a pattern corresponding to the original design of the test gate 201.

[0060] Since the gate design pattern 300 has different width dimensions along the second direction Y, the width dimension of the local gate design pattern can be scaled to adjust the line width roughness of the test gate 201 with a single variable while ensuring that the overall average line width of the test gate 201 is constant. In the subsequent test process, the electrical test data of the test structure 20 obtained by feedback can be matched with the line width roughness of the test gate 201 with a strong correlation, providing a basis for the manufacturing process of the test gate 201.

[0061] It should be noted that, in this embodiment, only one side of the gate design pattern 300 is scaled, and the other side remains original, so as to facilitate controlling the stability of the overall line width of the test gate 201 .

[0062] It should be noted that the test structure 20 is usually manufactured in the same semiconductor process as the semiconductor device in the wafer, and the test structure 20 and the semiconductor device have a mutual correspondence. Each layer of interconnection lines in the semiconductor device corresponds to the test line located at the same layer in the test structure 20, and each plug in the semiconductor device corresponds to the test plug located at the same layer in the test structure 20. Since the test structure and the semiconductor device are prepared in the same process and have a mutual correspondence, the performance of the semiconductor device in the wafer can be obtained by detecting the performance of the test structure. The performance of the semiconductor device in the wafer is reflected by the test structure, which avoids the damage to the semiconductor device in the wafer. Since the test structure is only suitable for testing the performance of the semiconductor device in the wafer, and will not be finally made into a product for actual use, in order to make the test structure not occupy the area of ​​the semiconductor device that is actually put into practical use in the wafer, the test structure can be formed in the cutting road area of ​​the wafer. After the test is completed, the test structure will also be damaged during the process of cutting the wafer.

[0063] In the embodiment, along the first direction X, each recessed portion 3001a has a first length dimension L1, each raised portion 3001b has a second length dimension L2, and the sum of the first length dimensions L1 of all recessed portions 3001a is equal to the sum of the second length dimensions L2 of all raised portions 3001b.

[0064] In this embodiment, the first length dimensions L1 of all the recessed portions 3001a are equal; and the second length dimensions L2 of all the raised portions 3001b are equal.

[0065] In this embodiment, the first width dimension W1 of all the recessed portions 3001a is equal; the second width dimension W2 of all the raised portions 3001b is equal. The main body 3002 has a third width dimension W3 along the second direction Y. The difference between the third width dimension W3 of the main body and the first width dimension W1 of the recessed portion is the first width difference ΔW1. The difference between the second width dimension W2 of the raised portion and the third width dimension W3 of the main body is the second width difference ΔW2. The third width dimension of the main body is equal to the difference between the first width dimension of each recessed portion (the first width difference ΔW1), and the difference between the second width dimension of each raised portion and the third width dimension of the main body (the second width difference ΔW2) is equal. The first width difference ΔW1 is equal to the second width difference ΔW2. For example, the third width dimension W3 may be 0.06 micrometers, the first width dimension W1 may be 0.057 micrometers, the second width dimension W2 may be 0.063 micrometers, and the corresponding first width difference ΔW1 and second width difference ΔW2 may both be 0.003 micrometers.

[0066] In this embodiment, a plurality of recessed portions 3001a and a plurality of raised portions 3001b are arranged alternately in sequence along the first direction X.

[0067] In an optional embodiment, the material of the test gate 201 is polysilicon. The material of the substrate is silicon, and may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0068] Figure 5 Schematic diagram of a gate design pattern corresponding to a test gate of a test structure provided in Embodiment 2 of the present invention. Figure 5 As shown, in the second embodiment, the gate design pattern 300 corresponding to the test gate 201 only includes the adjustment part 3001. Along the first direction X, the adjustment part 3001 includes: a plurality of recessed parts 3001a and a plurality of raised parts 3001b. Along the second direction Y, each recessed part 3001a has a first width dimension W1, and each raised part 3001b has a second width dimension W2, and the first width dimension W1 of the recessed part and the second width dimension W2 of the raised part can be adjusted. Along the first direction X, each recessed part 3001a has a first length dimension L1, and each raised part 3001b has a second length dimension L2, and the sum of the first length dimensions L1 of all recessed parts 3001a is equal to the sum of the second length dimensions L2 of all raised parts 3001b.

[0069] In the second embodiment, since the gate design pattern 300 does not have a main body portion 3002, the recessed portion 3001a and the raised portion 3001b need to be recessed or raised based on an auxiliary line S parallel to the first direction X. The spacing dimension between the recessed portion 3001a and the auxiliary line S is a first width difference ΔW1, and the spacing dimension between the auxiliary line S and the raised portion 3001b is a second width difference ΔW2.

[0070] Figure 6 Schematic diagram of a gate design pattern corresponding to a test gate of a test structure provided in Embodiment 3 of the present invention. Figure 6 As shown, in the third embodiment, the gate design pattern 300 corresponding to the test gate 201 includes an adjustment portion 3001 and a main body portion 3002, and the adjustment portion 3001 includes a plurality of recessed portions 3001a and a plurality of raised portions 3001b. Each recessed portion 3001a has a first width dimension W1 along the second direction, and each raised portion 3001b has a second width dimension W2 along the second direction. The main body portion 3002 is connected to the adjustment portion 3001 along the first direction X, and the main body portion 3002 has a third width dimension W3 along the second direction Y. The recessed portion 3001a is recessed relative to the main body portion 3002, and the raised portion 3001b is raised relative to the main body portion 3002. The first width dimensions W1 of each recessed portion 3001a are not completely equal, and the second width dimensions W2 of each raised portion 3001b are not completely equal. The main body portion 3002 has a third width dimension W3 along the second direction Y. The difference between the third width dimension W3 of the main body and the first width dimension W1 of the concave portion is a first width difference ΔW1. The difference between the second width dimension W2 of the convex portion and the third width dimension W3 of the main body is a second width difference ΔW2. The concave portions and the convex portions are arranged in a wave form along the first direction X.

[0071] In the third embodiment, since the second width dimensions W2 of all the protrusions 3001b are not completely equal, the corresponding first width difference ΔW1 is a plurality, and the second width difference ΔW2 is also a plurality, but each first width difference ΔW1 has a second width difference ΔW2 equal to it. By arranging the plurality of recessed portions 3001a and the plurality of protrusions 3001b in a wave form, the gate design pattern is more consistent with the outer contour morphology of the test gate after actual etching, and it is easier to make the expected outer contour morphology of the test gate in the process of exposure and development based on the gate design pattern.

[0072] The embodiment of the present invention also provides a gate line width roughness test method based on the test structure of the above embodiment. Figure 7 As shown, the gate line width roughness testing method of the embodiment of the present invention comprises the following steps:

[0073] S701, providing multiple test structures;

[0074] S702, adjusting the width size of the gate design pattern corresponding to the test gate of each test structure in different ways to obtain different gate line width roughness;

[0075] S703, performing electrical testing on the adjusted test structure to obtain electrical testing data corresponding to different gate line width roughnesses;

[0076] S704, comparing electrical test data corresponding to different gate line width roughnesses, matching the electrical test data with the measured value of the gate line width roughness, and obtaining a correlation between the electrical test data and the gate line width roughness according to the electrical test data corresponding to different gate line width roughnesses.

[0077] In the test structures provided in the above-mentioned embodiments 1 and 3, the gate design pattern corresponding to the test gate includes an adjustment portion and a main body portion. The adjustment portion 3001 includes a plurality of recessed portions 3001a and a plurality of raised portions 3001b. Each recessed portion 3001a has a first width dimension W1 along the second direction, and each raised portion 3001b has a second width dimension W2 along the second direction. The main body portion 3002 is connected to the adjustment portion 3001 along the first direction X, and the main body portion 3002 has a third width dimension W3 along the second direction. The difference between the third width dimension W3 of the main body portion and the first width dimension W1 of the recessed portion is the first width difference ΔW1. The difference between the second width dimension W2 of the raised portion and the third width dimension W3 of the main body portion is the second width difference ΔW2.

[0078] In the test structure provided in the second embodiment, the gate design pattern corresponding to the test gate only includes the adjustment part. The adjustment part 3001 includes a plurality of recessed parts 3001a and a plurality of raised parts 3001b. Each recessed part 3001a has a first width dimension W1 along the second direction, and each raised part 3001b has a second width dimension W2 along the second direction.

[0079] In the above step S702, the local width dimension of the gate design pattern is scaled. For the test structures of the above embodiments 1 and 3, the first width dimension W1 of the concave portion and the second width dimension W2 of the convex portion in the gate design pattern corresponding to the test gate of each test structure are adjusted differently, so that the first width difference ΔW1 (the difference between the third width dimension W3 and the first width dimension W1) of each gate design pattern is different, and the second width difference ΔW2 (the difference between the second width dimension W2 and the third width dimension W3) is different. Under the premise of ensuring that the overall average line width of the test gate is constant, the line width roughness of the test gate is adjusted by a single variable, so that the gate line width roughness of each test structure changes differently, thereby obtaining different gate line width roughness.

[0080] In a specific example, referring to Figure 8 , taking the two test structures of the first embodiment as an example, the protrusions 3001b in the gate design patterns of the two test structures are stretched to different degrees in the Y direction, that is, corresponding to different gate line width roughness. For example, the third width dimension W3 of one gate design pattern is 0.06 microns, the first width dimension W1 is 0.057 microns, and the second width dimension W2 is 0.063 microns, and the corresponding first width difference ΔW1 and second width difference ΔW2 are both 0.003 microns; the third width dimension W3 of another gate design pattern 300 is also 0.06 microns, the first width dimension W1 is 0.055 microns, and the second width dimension W2 is 0.065 microns, and the corresponding first width difference ΔW1 and second width difference ΔW2 are both 0.005 microns.

[0081] It should be noted that, since only the line width roughness of the test gate is used as the only control variable during the test process, the adjustment between the corresponding different gate design patterns can only be associated with the line width roughness. Under the premise of ensuring that the overall average line width of the test gate is certain, the areas of different gate design patterns need to be kept equal. In addition, in order to obtain a strong correlation between the electrical test data and the line width roughness of the test gate, the adjustment of different gate design patterns must also comply with the principle of a single variable. In this example, the single variable between different gate design patterns is the width difference.

[0082] It should be noted that, during the test process, a test structure of a gate design pattern that has not undergone any line width scaling may also be used as a reference.

[0083] In another specific example, referring to Fig. 9 , taking the two test structures of the third embodiment as an example, the recessed portions 3001a and the raised portions 3001b in the gate design patterns of the two test structures are stretched to different degrees in the X direction, or the number of the recessed portions 3001a and the number of the raised portions 3001b are adjusted differently, so that the number of the recessed portions 3001a and the number of the raised portions 3001b of each gate design pattern are different, so that the gate line width roughness of each test structure changes differently. For example, the number of the recessed portions 3001a and the number of the raised portions 3001b of one gate design pattern are both m; the number of the recessed portions 3001a and the number of the raised portions 3001b of the other gate design pattern are both (m+n). In this example, the single variable between different gate design patterns is the number of the raised portions and the number of the recessed portions.

[0084] In the above step S702, for the test structure of the above embodiment 2, different adjustments are made to the first width dimension W1 of the recessed portion and the second width dimension W2 of the raised portion in the gate design pattern corresponding to the test gate of each test structure, so that the gate line width roughness of each test structure changes differently.

[0085] In the above step S704, the electrical test data corresponding to different gate line width roughness are compared, and the electrical test data is matched with the gate line width roughness to obtain the correlation between the electrical test data and the gate line width roughness. Based on the relationship between the line width roughness of the test gate in each test structure and the electrical test data, a mathematical model is fitted to determine the influence of the gate line width roughness on the electrical properties, providing a basis for the manufacturing process of the test gate.

[0086] The optional embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the technical concept of the embodiments of the present invention, a variety of simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all belong to the protection scope of the embodiments of the present invention. It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction, and as long as the combination does not violate the concept of the embodiments of the present invention, it should also be regarded as the content disclosed in the embodiments of the present invention.

Claims

1. A test structure, characterized in that: include: A test active region and a test gate located on the test active region; The test active area includes a test source and a test drain, and the test source and the test drain are respectively located on both sides of the test gate; The test gate has a corresponding gate design pattern, the gate design pattern extends along a first direction, and the gate design pattern has different width dimensions along a second direction.

2. The test structure according to claim 1, characterized in that: The gate design pattern includes: an adjustment part; The adjusting portion includes a plurality of recessed portions and a plurality of raised portions; Each of the recessed portions has a first width dimension along the second direction, and each of the raised portions has a second width dimension along the second direction.

3. The test structure according to claim 2, characterized in that: The first width dimensions of the plurality of recessed portions are all the same; the second width dimensions of the plurality of raised portions are all the same.

4. The test structure according to claim 2, characterized in that: The gate design pattern further includes: a main body portion connected to the adjustment portion along a first direction; The concave portion of the adjusting portion is concave relative to the main body portion, and the convex portion of the adjusting portion is convex relative to the main body portion.

5. The test structure according to claim 4, characterized in that: The body portion has a third width dimension along the second direction; The difference between the third width dimension of the main body portion and the first width dimension of each recessed portion is equal; The difference between the second width dimension of each protrusion portion and the third width dimension of the main body portion is equal.

6. The test structure according to claim 2 or 4, characterized in that: Each recessed portion has a first length dimension along the first direction, and each raised portion has a second length dimension along the first direction; The sum of the first length dimensions of the plurality of recessed portions is equal to the sum of the second length dimensions of the plurality of raised portions.

7. The test structure according to claim 6, characterized in that: The first length dimensions of the plurality of recessed portions are all the same; the second length dimensions of the plurality of raised portions are all the same.

8. The test structure according to claim 2, characterized in that: The plurality of recessed portions and the plurality of raised portions are alternately arranged in sequence along the first direction.

9. The test structure according to claim 2, characterized in that: The plurality of recessed portions and the plurality of raised portions are arranged in a wave form along a first direction.

10. The test structure according to claim 1, characterized in that: Also includes: A first test board and a second test board, wherein the first test board is connected to the test source, and the second test board is connected to the test drain.

11. A gate line width roughness testing method, characterized in that: include: Providing a plurality of test structures, wherein the test structure is the test structure according to claim 1; The width size of the gate design pattern corresponding to the test gate of each test structure is adjusted differently to obtain different gate line width roughness; Conducting electrical testing on the adjusted test structure to obtain electrical testing data corresponding to different gate line width roughnesses; According to the electrical test data corresponding to different gate line width roughnesses, the correlation between the electrical test data and the gate line width roughness is obtained.

12. The gate line width roughness testing method according to claim 11, characterized in that: The gate design pattern corresponding to the test gate of the test structure includes: an adjustment part; The adjusting portion includes a plurality of recessed portions and a plurality of raised portions; Each of the recessed portions has a first width dimension along the second direction, and each of the raised portions has a second width dimension along the second direction.

13. The gate line width roughness testing method according to claim 12, characterized in that: The gate design pattern corresponding to the test gate of the test structure further includes: a main body portion connected to the adjustment portion along the first direction; and the main body portion has a third width dimension along the second direction.

14. The gate line width roughness testing method according to claim 13, characterized in that: Different adjustments are made to the width size of the gate design pattern corresponding to the test gate of each test structure, including: The first width dimension of the recessed portion and the second width dimension of the raised portion in the gate design pattern corresponding to the test gate of each test structure are adjusted respectively, so that the difference between the third width dimension of the main portion of each gate design pattern and the first width dimension of the recessed portion is different, and the difference between the second width dimension of the raised portion and the third width dimension of the main portion of each gate design pattern is different.

15. The gate line width roughness testing method according to claim 12, characterized in that: Different adjustments are made to the width size of the gate design pattern corresponding to the test gate of each test structure, including: The number of recessed portions and the number of raised portions in the gate design pattern corresponding to the test gate of each test structure are adjusted differently, so that the number of recessed portions and the number of raised portions of each gate design pattern are different, so that the gate line width roughness of each test structure changes differently.

Images