Wafer structure capable of preventing electromagnetic interference

Abstract

The invention relates to a wafer structure capable of preventing electromagnetic interference, which is a wafer processing stage structure and is provided with a digital processing unit area, and the digital processing unit area is provided with a digital processing unit, an insulating layer, a conductive layer and a plurality of information link points. The insulating layer and the information link points are arranged on the upper surface of the digital processing unit, the conductive layer is coated on the upper surface of the insulating layer, and when electromagnetic interference is transmitted through the conductive layer, the conductive layer can absorb the electromagnetic interference.

Description

Technical Field

[0001] The invention relates to a wafer structure, in particular to a structure in which a conductive coating is added on a digital processing unit to isolate electromagnetic interference from adjacent analog processing units, which is a wafer processing stage structure. Background Art

[0002] First, semiconductor devices are generally manufactured using two complex processes, such as a front-end process and a back-end process, each of which may involve thousands of steps; wherein the front-end process involves forming a plurality of dies on the surface of a semiconductor wafer, and each die is typically identical and includes a circuit formed by electrically connected active and passive components; in addition, the back-end process involves singulating the individual dies in the finished wafer and packaging the dies to provide structural support and environmental isolation.

[0003] One of the main purposes of semiconductor manufacturing is to produce smaller semiconductor devices. Smaller devices typically consume less power, have higher performance and can be manufactured in large quantities more efficiently. In addition, smaller semiconductor devices have a smaller footprint that can be expected to be used in smaller end products. Smaller die size can be achieved by improving the front-end process to produce dies with smaller and higher density active and passive components. The back-end process can produce semiconductor device packages with a smaller footprint by improving electrical interconnects and packaging materials.

[0004] Another major goal of semiconductor manufacturing is to produce semiconductor devices with higher performance. The performance improvement of the device can be achieved by forming active components that can operate at higher speeds. In high-frequency applications such as radio frequency (RF) wireless communications, integrated passive components are often incorporated into the semiconductor device; however, high-frequency electrical devices generate or are susceptible to external electromagnetic interference (EMI) and radio frequency interference (RFI), which can interfere with their electrical operation.

[0005] Electromagnetic interference (EMI) is a serious and challenging problem for most electronic components or systems. Since EMI usually interrupts, reduces or limits the effective performance of all circuits of electronic components or electronic systems, electronic components or systems need to have effective EMI protection to ensure effective and safe operation.

[0006] Regarding electromagnetic interference, there are several patents as follows:

[0007] U.S. Patent No. 15 / 175,992 discloses a semiconductor package device and a method for manufacturing the same. According to an embodiment of the disclosure, the semiconductor package device includes a carrier, a first antenna, a second antenna, a package body, and a first shield. The carrier has an antenna region and a component region. The first antenna is formed on the antenna region. The second antenna extends from the antenna region to above the first antenna. The second antenna is electrically connected to the first antenna. The package body includes a first portion covering the component region and a second portion covering the antenna region. The first shield is conformally formed on the first portion of the package body and exposes the second portion of the package body.

[0008] U.S. Patent No. 13 / 493,576 discloses a semiconductor package including a shielding member that connects a plurality of conductive members configured on a wafer. The plurality of conductive members are configured to respectively surround a plurality of microstructure members on the wafer, and these microstructure members are located in a plurality of recesses formed by the conductive members to provide a better shielding effect. The shielding member and the plurality of conductive members have the function of shielding electromagnetic interference. A method for forming a semiconductor package includes the following steps. A semiconductor wafer having a plurality of sub-units is provided, at least one microstructure member is disposed in each sub-unit, and the microstructure member is electrically connected to the semiconductor wafer. A plurality of conductive members are formed on the semiconductor wafer, each conductive member surrounds the microstructure member and forms a plurality of recesses, and the microstructure member is in the recess. A shielding member is configured on the conductive member to enclose the microstructure member in the recess.

[0009] U.S. Patent No. 15 / 674,218 discloses an integrated circuit device for protecting a circuit from transient electrical events. An integrated circuit device includes a first bipolar junction transistor and a second bipolar junction transistor cross-coupled to the first bipolar junction transistor to operate as a first semiconductor controlled rectifier, wherein the base of the first bipolar junction transistor is connected to a collector of the second bipolar junction transistor, and a base of the second bipolar junction transistor is connected to an emitter or a collector of the first bipolar junction transistor. The integrated circuit device additionally includes a trigger device having a first diode, the first diode having a cathode connected to the base of the first bipolar junction transistor. The integrated circuit device further includes a third bipolar junction transistor cross-coupled to the second bipolar junction transistor to operate as a second semiconductor controlled rectifier, wherein the third bipolar junction transistor has a collector connected to the collector of the second bipolar junction transistor, and a base connected to the collector of the second bipolar junction transistor.

[0010] Taiwan Patent TW201608694 discloses a method comprising forming an RF field effect transistor in an active layer of a semiconductor on insulator wafer. The semiconductor on insulator wafer has a buried insulator side and an active layer side. The method further comprises bonding a second wafer to the active layer side of the semiconductor on insulator wafer. The method further comprises forming a shielding layer for a semiconductor device. The shielding layer comprises a conductive material. The method further comprises coupling the RF field effect transistor to a circuit comprising an RF element. The method further comprises singulating the RF field effect transistor, the RF element and the shielding layer into die. The shielding layer is located between a substrate of the RF element and the RF field effect transistor.

[0011] However, in the semiconductor field, electromagnetic interference problems are mostly dealt with in the back-end process, which increases the size of the packaged product. How to reduce electromagnetic interference problems in the finished product in the front-end process without affecting the cost and related processes will require more consideration in the front-end process. Summary of the invention

[0012] In view of the above problems, the present invention provides a wafer structure for preventing electromagnetic interference, which mainly uses a conductive layer to replace the traditional wafer electromagnetic interference protection structure to achieve the effect of significantly reducing the cost of the electromagnetic interference structure.

[0013] Therefore, the main purpose of the present invention is to provide a wafer structure that prevents electromagnetic interference, and constructs an insulating layer on a digital processing unit to achieve the purpose of quickly constructing a conductive layer.

[0014] Another object of the present invention is to provide a wafer structure that prevents electromagnetic interference, with through holes penetrating the conductive layer and the insulating layer, so as to be electrically connected to the outside world while maintaining electromagnetic interference.

[0015] Another object of the present invention is to provide a wafer structure that prevents electromagnetic interference, so that the insulating wall can avoid interference from the conductive layer and provide the circuit conduction required by the digital processing unit.

[0016] Another object of the present invention is to provide a wafer structure that prevents electromagnetic interference and integrates an analog signal transmitting unit to reduce the size of the structure during subsequent packaging.

[0017] To achieve the above-mentioned purpose, the present invention provides a wafer structure for preventing electromagnetic interference, which is a wafer processing stage structure, characterized in that it includes: a digital processing unit area, the digital processing unit area has a digital processing unit, an insulating layer, a conductive layer and multiple information connection points, the insulating layer and each of the information connection points are arranged on an upper surface of the digital processing unit, and the conductive layer is coated on the upper surface of the insulating layer, when electromagnetic interference is transmitted through the conductive layer, the conductive layer can absorb the electromagnetic interference.

[0018] In the technical solution of the present invention, the digital processing unit region has at least one ground connection point, and the ground connection point is electrically connected to the digital processing unit.

[0019] The digital processing unit area has a plurality of through holes, and each of the through holes penetrates the conductive layer and the insulating layer.

[0020] The invention also comprises an analog processing unit area, wherein an analog processing unit in the analog processing unit area is electrically connected to the digital processing unit.

[0021] The digital processing unit region has a plurality of insulating walls, and each of the insulating walls is arranged at a junction between each of the through holes and the conductive layer.

[0022] The analog processing unit area has an analog signal transmitting unit and an analog receiving unit, and the analog signal transmitting unit and the analog receiving unit are electrically connected to the analog processing unit respectively.

[0023] The digital processing unit area has a plurality of electrical connection areas, each of which is filled in each of the through holes, so that each of the electrical connection areas can be electrically connected to each of the information connection points in the digital processing unit area.

[0024] By adopting the above technical solution, compared with the conventional technology, the present invention has the following effects: (1) using a conductive layer to replace the traditional wafer electromagnetic interference protection structure to significantly reduce the cost of the electromagnetic interference structure; (2) constructing an insulating layer on the digital processing unit to achieve the purpose of quickly constructing the conductive layer; (3) integrating the analog signal transmission unit to reduce the size of the structure during subsequent packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a first schematic diagram of a first embodiment of the present invention;

[0026] Figure 2a is a second schematic diagram of the first embodiment of the present invention;

[0027] Figure 2b is a third schematic diagram of the first embodiment of the present invention;

[0028] Figure 3 is a first schematic diagram of a second embodiment of the present invention;

[0029] Figure 4 It is a second schematic diagram of the second embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, features and effects of the present invention more clearly understood, the preferred embodiments of the present invention are specifically listed below:

[0031] like Figure 1 , Figure 2a and Figure 2b The figure shows a first embodiment of a wafer structure for preventing electromagnetic interference provided by the present invention. Figure 1 As shown, a wafer structure for preventing electromagnetic interference includes: a digital processing unit area 1, the digital processing unit area 1 has a digital processing unit 10, an insulating layer 11, a conductive layer 12 and a plurality of information connection points 13, an upper surface 101 of the digital processing unit 10 is provided with the insulating layer 11 and the information connection points 13, and the conductive layer 12 is coated on the upper surface 111 of the insulating layer 11.

[0032] Specifically, the main function of the digital processing unit area 1 is to provide support and basic protection for the digital processing unit 10, and includes electrical input and electrical output parts; the digital processing unit 10 refers to the function of digital signal processing (DSP), which is a unit dedicated to processing digital signals; in addition, the insulating layer 11 is an insulating material, and its main function is to isolate electrical conduction and provide basic protection for the digital processing unit 10; the conductive layer 12 can include various materials and can be formed at various stages in the process of manufacturing semiconductor devices. Usually, the conductive layer 12 can be made of any conductive material, for example, the conductive layer 12 can be pure metal, such as copper, tungsten, molybdenum, metal alloy or metal silicide, etc. The conductive layer 12 has the function of preventing electromagnetic interference from the outside and between the upper and lower layers, and the conductive layer 12 can export waste heat, thereby averaging the overall temperature and reducing the temperature of the hot spots in the digital processing unit 10; the function of the information connection point 13 is to provide electrical connection between various electronic components and the outside world.

[0033] Generally speaking, the digital processing unit area 10 is as follows Figure 1 As shown, there is at least one ground connection point 14, which is electrically connected to the digital processing unit 1; the ground connection point 14 is the ground wire during circuit design, and the ground wire is widely used as a reference point for potential, providing a reference potential for the entire circuit, with the ground line voltage being 0V to unify the potential of the entire circuit.

[0034] As shown above, the digital processing unit area 10 is as follows Figure 2a It is shown that it has a plurality of through holes 15 , and each through hole 15 penetrates the conductive layer 12 and the insulating layer 11 .

[0035] Specifically, the through hole 15 mainly functions to expose the information connection point 13 and the ground connection point 14 buried under the conductive layer 12 and the insulating layer 11 to the outside, so as to facilitate subsequent processes.

[0036] Then, if Figure 2bAs shown, the digital processing unit area 1 also has a plurality of insulating walls 16, each insulating wall 16 is arranged at the junction of each through hole 15 and the conductive layer 12; and, the digital processing unit area has a plurality of electrical connection areas 17, each electrical connection area 17 is filled in each through hole 15, so that each electrical connection area 17 can electrically conduct each information connection point 13 of the digital processing unit area 1.

[0037] Generally speaking, the insulating wall 16 mainly prevents the conductive layer 12 from being electrically connected to the electrical connection area 17, and protects the electrical connection area 17 from being directly contacted by the conductive layer 12; each electrical connection area 17 has a colloid with fixed objects and conductive properties, which solidifies after qualitative change and maintains the fixed objects and conductive properties.

[0038] Please refer to Figure 3 FIG. 2 shows a second embodiment of a wafer structure for preventing electromagnetic interference according to the present invention. The main difference between the second embodiment and the first embodiment is that the second embodiment has an analog processing unit area 2 .

[0039] like Figure 3 As shown, an analog processing unit area 2 is added on one side of a digital processing unit area 1, and an analog processing unit 20 in the analog processing unit area 2 is electrically connected to the digital processing unit 10; wherein the analog processing unit area 2 has an analog signal transmitting unit 21 and an analog receiving unit 22, and the analog signal transmitting unit 21 and the analog receiving unit 22 are electrically connected to the analog processing unit 20 respectively.

[0040] Specifically, the main function of the analog processing unit area 2 is to provide support and basic protection for the analog processing unit 20, and includes electrical input and electrical output parts; the analog processing unit 20 refers to analog signal processing (Analog Signal Processing), which refers to any signal processing process that uses analog processing methods for continuous analog signals. It is a unit that specializes in processing analog signals; the analog signal transmitting unit 21 is a basic output unit for transmitting and transmitting analog signals, and the analog receiving unit 22 is a basic input unit for receiving and transmitting analog signals.

[0041] In fact, both the analog signal transmitting unit 21 and the analog receiving unit 22 will generate electromagnetic interference (EMI) to the digital processing unit 10. Therefore, the conductive layer 12 can prevent interference from the outside and between the upper and lower layers. The conductive layer 12 has effective electromagnetic interference protection to ensure that the digital processing unit 10 can operate effectively and safely.

[0042] like Figure 4As shown, the digital processing unit area 1 also has a plurality of insulating walls 16, each insulating wall 16 is arranged at the junction of each through hole 15 and the conductive layer 12; and, the digital processing unit area has a plurality of electrical connection areas 17, each electrical connection area 17 is filled in each through hole 15, so that each electrical connection area 17 can electrically conduct each information connection point 13 of the digital processing unit area 1.

[0043] Therefore, the efficacy of the present invention is different from that of general wafer structures, and is truly a first in semiconductor electromagnetic interference prevention and non-packaging structures, meeting the requirements of invention patents.

[0044] It needs to be reiterated that the above is only a preferred embodiment of the present invention. Any equivalent changes made by applying the present invention specification, patent protection scope or drawings are still within the technical scope protected by the present invention. Therefore, the patent protection scope of the present invention shall be based on the definition of the scope of the claims.

Claims

1. A wafer structure for preventing electromagnetic interference, which is a wafer processing stage structure, characterized in that The invention comprises: a digital processing unit area, wherein the digital processing unit area has a digital processing unit, an insulating layer, a conductive layer and a plurality of information connection points; the insulating layer and the information connection points are arranged on an upper surface of the digital processing unit, and the conductive layer is coated on the upper surface of the insulating layer; when electromagnetic interference is transmitted through the conductive layer, the conductive layer can absorb the electromagnetic interference.

2. The wafer structure for preventing electromagnetic interference according to claim 1, characterized in that: The digital processing unit region has at least one ground connection point, and the ground connection point is electrically connected to the digital processing unit.

3. The wafer structure for preventing electromagnetic interference according to claim 1, characterized in that: The digital processing unit area has a plurality of through holes, and each of the through holes penetrates the conductive layer and the insulating layer.

4. The wafer structure for preventing electromagnetic interference according to claim 1, wherein: The invention also comprises an analog processing unit area, wherein an analog processing unit in the analog processing unit area is electrically connected to the digital processing unit.

5. The wafer structure for preventing electromagnetic interference according to claim 3, characterized in that: The digital processing unit region has a plurality of insulating walls, and each of the insulating walls is arranged at a junction between each of the through holes and the conductive layer.

6. The wafer structure for preventing electromagnetic interference according to claim 4, characterized in that: The analog processing unit area has an analog signal transmitting unit and an analog receiving unit, and the analog signal transmitting unit and the analog receiving unit are electrically connected to the analog processing unit respectively.

7. The wafer structure for preventing electromagnetic interference according to claim 5, characterized in that: The digital processing unit area has a plurality of electrical connection areas, each of which is filled in each of the through holes, so that each of the electrical connection areas can be electrically connected to each of the information connection points in the digital processing unit area.

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