Semiconductor integrated circuit device and power supply device

Abstract

The invention provides a semiconductor integrated circuit device and a power supply device. The semiconductor integrated circuit device is configured to be used as a part of a power supply device, and includes: an error amplifier configured to output an error voltage according to a difference between a feedback voltage based on an output voltage of the power supply device and a reference voltage; a first switching element and a second switching element connected in series; a first controller configured to control a switching operation of the first switching element and the second switching element based on the error voltage; an output transistor; a second controller configured to linearly control the output transistor based on the error voltage; and a first terminal configured such that a connection node between the first switching element and the second switching element and an output terminal of the output transistor are both connected to the first terminal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based upon and claims the benefit of priority from Japanese patent application No. 2023-166336, filed on September 27, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a semiconductor integrated circuit device and a power supply device. Background Art

[0004] The semiconductor integrated circuit device disclosed in patent document 1 includes: a first error amplifier, which outputs a first error voltage based on the error between a feedback voltage and a reference voltage; a second error amplifier, which outputs a second error voltage based on the error between the feedback voltage and the reference voltage; a first switching element and a second switching element connected in series; a first controller, which controls the switching action of the first switching element and the second switching element based on the first error voltage; an output transistor; and a second controller, which linearly controls the output transistor based on the second error voltage.

[0005] The semiconductor integrated circuit device disclosed in Patent Document 1 can be switched between being used as a part of a switching power supply device and being used as a part of a linear power supply device.

[0006] Prior art literature

[0007] Patent Literature

[0008] Patent Document 1: Japanese Patent Application Publication No. 2005-130622 Summary of the invention

[0009] However, in the semiconductor integrated circuit device disclosed in Patent Document 1, a circuit related to a switching power supply device and a circuit related to a linear power supply device are completely separately configured, resulting in poor area efficiency.

[0010] The semiconductor integrated circuit device disclosed in the present specification is configured to be used as a part of a power supply device, and includes: an error amplifier, which is configured to output an error voltage based on the difference between a feedback voltage based on the output voltage of the power supply device and a reference voltage; a first switching element and a second switching element connected in series; a first controller, which is configured to control the switching action of the first switching element and the second switching element based on the error voltage; an output transistor; a second controller, which is configured to linearly control the output transistor based on the error voltage; and a first terminal, which is configured so that the connection node between the first switching element and the second switching element and the output terminal of the output transistor are both connected to the first terminal.

[0011] A power supply device disclosed in the present invention includes a substrate and a semiconductor integrated circuit device embedded in the substrate and configured as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention.

[0013] Figure 1 is a diagram showing a schematic structure of a semiconductor integrated circuit device according to a reference example.

[0014] Figure 2 is a diagram showing a schematic structure of a switching power supply device according to a reference example.

[0015] Figure 3 is a diagram showing a schematic structure of a linear power supply device according to a reference example.

[0016] Figure 4 is a diagram showing a schematic structure of a semiconductor integrated circuit device according to a first embodiment.

[0017] Figure 5 It is an external perspective view of the semiconductor integrated circuit device according to the first embodiment.

[0018] Figure 6 : is a diagram showing a schematic structure of a switching power supply device according to a first embodiment.

[0019] Figure 7 : is a diagram showing a schematic structure of a linear power supply device according to a first embodiment.

[0020] Figure 8 is a diagram showing a configuration example of a phase compensation circuit.

[0021] Fig. 9 is a diagram showing a schematic structure of a semiconductor integrated circuit device according to a second embodiment.

[0022] Fig.10 is a diagram showing a schematic structure of a semiconductor integrated circuit device according to a third embodiment. DETAILED DESCRIPTION

[0023] Reference will now be made in detail to various embodiments, examples of which are illustrated in the accompanying drawings. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other cases, well-known methods, processes, systems, and components are not described in detail in order to avoid unnecessarily obscuring aspects of the various embodiments.

[0024] In this specification, the term MOSFET (Metal Oxide Semiconductor Field Effect Transistor) refers to a field effect transistor having a gate structure consisting of at least three layers of "a layer made of a conductor or semiconductor (such as polysilicon) having a low resistance value", "an insulating layer", and "a P-type, N-type or intrinsic semiconductor layer". That is, the gate structure of MOSFET is not limited to a three-layer structure of metal, oxide, and semiconductor.

[0025] In this specification, the term "reference voltage" refers to a voltage that is constant under ideal conditions, but actually refers to a voltage that may slightly fluctuate due to temperature changes and the like.

[0026] <Semiconductor Integrated Circuit Device According to Reference Example>

[0027] Figure 1 is a diagram showing a schematic structure of a semiconductor integrated circuit device according to a reference example. Figure 1 The semiconductor integrated circuit device 100 shown in the figure includes a terminal IN, a terminal SW, a terminal OUT, and a terminal GND. The terminal IN is configured to receive an input voltage V IN The terminal GND is a terminal configured to be connected to a ground potential outside the semiconductor integrated circuit device 100 .

[0028] The semiconductor integrated circuit device 100 further includes an output stage circuit MM, an error amplifier 11, a phase compensation circuit 12, a slope voltage generation circuit 13, a comparator 14, a clock signal generation circuit 15, a logic circuit 16, a drive circuit 17, and resistors R1 and R2.

[0029] The output stage circuit MM includes a transistor M1 configured as a P-channel MOSFET and a transistor M2 configured as an N-channel MOSFET. The transistors M1 and M2 are a pair of switching elements connected in series between the terminal IN and the terminal GND. When the transistors M1 and M2 are switched, the input voltage V IN The switching voltage V SW Appears at terminal SW. Transistor M1 is set at a higher potential side than transistor M2. In other words, transistor M2 is set at a lower potential side than transistor M1. Specifically, the source of transistor M1 is connected to terminal IN. The drain of transistor M1 and the drain of transistor M2 are commonly connected to terminal SW. The source of transistor M2 is connected to terminal GND.

[0030] The gate signals G1 and G2 are provided as drive signals to the gates of transistors M1 and M2, respectively, and transistors M1 and M2 are turned on and off in response to the gate signals G1 and G2. When the gate signal G1 is at a low level, transistor M1 is turned on, and when the gate signal G1 is at a high level, transistor M1 is turned off. When the gate signal G2 is at a high level, transistor M2 is turned on, and when the gate signal G2 is at a low level, transistor M2 is turned off. Basically, transistors M1 and M2 are alternately turned on and off, but transistors M1 and M2 can both be kept in the off state. That is, the state of the output stage circuit MM is one of an output high state, an output low state, and a Hi-Z state (high impedance state).

[0031] The error amplifier 11 is a current output transconductance amplifier. The error amplifier 11 has an inverting input terminal, a non-inverting input terminal, and an output terminal. The inverting input terminal of the error amplifier 11 receives a feedback voltage V FB . Feedback voltage V FB The output voltage V received at the terminal OUT is obtained by resistors R1 and R2. OUT The voltage obtained by dividing the voltage.

[0032] Predetermined reference voltage V REF is supplied to the non-inverting input terminal of the error amplifier 11. The reference voltage V REF is a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generating circuit (not shown) in the semiconductor integrated circuit device 100. The output terminal of the error amplifier 11 is connected to the wiring WR11.

[0033] The error amplifier 11 generates a voltage V according to the feedback voltage FB and reference voltage V REF The difference between the two is output from its output terminal as a current signal I11, which is converted into a current signal according to the feedback voltage V FB and reference voltage V REF The difference between the two generates an error voltage V in the wiring WR11. ERR The charge caused by the current signal I11 is input and output with respect to the wiring WR11. Specifically, when the feedback voltage V FB Lower than the reference voltage V REF When the feedback voltage V FB Higher than the reference voltage V REF When the feedback voltage V FBand the absolute value of the difference from the reference voltage V REF increases, and the magnitude of the current caused by the current signal I11 also increases.

[0034] The phase compensation circuit 12 is provided between the wiring WR11 and the inverting input terminal of the error amplifier 11 to receive the current signal I11 as an input to compensate for the phase of the error voltage V ERR . The phase compensation circuit 12 includes a series circuit of a capacitor 12a and a resistor 12b. Specifically, one end of the capacitor 12a is connected to the inverting input terminal of the error amplifier 11, the other end of the capacitor 12a is connected to one end of the resistor 12b, and the other end of the resistor 12b is connected to the wiring WR11. By appropriately setting the capacitance value of the capacitor 12a and the resistance value of the resistor 12b, the phase of the error voltage V ERR can be compensated and oscillation of the output feedback loop can be prevented.

[0035] The ramp voltage generation circuit 13 generates and outputs a ramp voltage V SLP . The ramp voltage V SLP is a sawtooth voltage synchronized with the clock signal S1.

[0036] The comparator 14 has an inverting input terminal for receiving the voltage V1, a non-inverting input terminal for receiving the voltage V2, and an output terminal. The voltage V1 is a first comparison voltage, and the voltage V2 is a second comparison voltage. The comparator 14 compares the voltage V1 and the voltage V2, and outputs a signal S2 indicating the comparison result (hereinafter referred to as the comparison result signal S2) from its output terminal. The comparison result signal S2 is a binary signal adopting a high or low signal level. When "V2 > V1" is satisfied (i.e., when the voltage V2 is higher than the voltage V1), the comparator 14 outputs a high-level comparison result signal S2, and when "V2 < V1" is satisfied (i.e., when the voltage V1 is higher than the voltage V2), the comparator 14 outputs a low-level comparison result signal S2. When "V2 = V1" is satisfied, the comparison result signal S2 is at a high level or a low level.

[0037] In the semiconductor integrated circuit device 100, the error voltage V ERR is used as the voltage V1. That is, the inverting input terminal of the comparator 14 is connected to the wiring WR11 to receive the error voltage V ERR as the voltage V1. In the semiconductor integrated circuit device 100, the ramp voltage V SLP is used as the voltage V2. That is, the non-inverting input terminal of the comparator 14 receives the ramp voltage V SLP as the voltage V2.

[0038] The clock signal generation circuit 15 generates and outputs a clock signal S1 having a predetermined frequency f PWM .

[0039] The logic circuit 16 generates and outputs a control signal S3 based on the clock signal S1 and the comparison result signal S2. The control signal S3 is a binary signal that takes a high or low signal level.

[0040] The driving circuit 17 provides gate signals G1 and G2 to the gates of the transistors M1 and M2 , respectively, in response to the control signal S3 , thereby turning on or off the transistors M1 and M2 , respectively.

[0041] The logic circuit 16 and the drive circuit 17 constitute a drive control circuit CD that controls the output stage circuit MM based on the clock signal S1 and the comparison result signal S2.

[0042] The ramp voltage generating circuit 13, the comparator 14, the clock signal generating circuit 15 and the drive control circuit CD constitute a first controller, which is configured to generate a signal based on the error voltage V ERR To control the switching action of transistors M1 and M2.

[0043] The semiconductor integrated circuit device 100 further includes an output transistor Q7 provided between the terminal IN and the terminal OUT, and a transistor Q7 based on the feedback voltage V FB With reference voltage V REF The difference between them drives the output transistor Q7 which drives the drive.

[0044] The output transistor Q7 is a P-channel MOSFET. The source of the output transistor Q7 is connected to the terminal IN. The drain of the output transistor Q7 is connected to the terminal OUT.

[0045] The driver includes an error amplifier 21, a converter, a current amplifier, and a transistor Q6 constructed as a P-channel MOSFET.

[0046] The error amplifier 21 generates a voltage V according to the feedback voltage FB and reference voltage V REF The difference between the output error voltage. Feedback voltage V FB is supplied to the inverting input terminal of the error amplifier 21, and the reference voltage V REF is supplied to the non-inverting input terminal of the error amplifier 21. The power supply terminal of the error amplifier 21 is connected to the terminal IN.

[0047] The converter includes a transistor Q1 configured as a P-channel MOSFET, and converts a voltage into a current based on the output of the error amplifier 21. The gate of the transistor Q1 is connected to the output terminal of the error amplifier 21. The source of the transistor Q1 is connected to the terminal IN.

[0048] The current amplifier amplifies the output current of the transistor Q1. The current amplifier includes a constant current source 22, transistors Q2 and Q3 configured as P-channel MOSFETs, and transistors Q4 and Q5 configured as N-channel MOSFETs.

[0049] A first terminal of the constant current source 22 is connected to the drain of the transistor Q1 , and a second terminal of the constant current source 22 is connected to the terminal GND.

[0050] Transistors Q2 and Q3 constitute a current source type current mirror circuit. The sources of transistors Q2 and Q3 are connected to terminal IN. The gates of each of transistors Q2 and Q3 and the drain of transistor Q2 are connected to the first end of the constant current source 22. The mirror ratio (the size of the output side transistor relative to the size of the input side transistor) of the current mirror circuit formed by transistors Q2 and Q3 is M. In order to prevent the pole of the current mirror circuit formed by transistors Q2 and Q3 from shifting to a low frequency band as much as possible, M may be 5 or less, and specifically, 3 or less.

[0051] Transistors Q4 and Q5 constitute a current mirror circuit of a current sink type. The drain of transistor Q4 and the gates of each of transistors Q4 and Q5 are connected to the drain of transistor Q3. The source of each of transistors Q4 and Q5 is connected to terminal GND. The mirror ratio (the size of the output side transistor relative to the size of the input side transistor) of the current mirror circuit formed by transistors Q4 and Q5 is N. In order to prevent the pole of the current mirror circuit formed by transistors Q4 and Q5 from shifting to a low frequency band as much as possible, N may be 5 or less, and specifically, 3 or less.

[0052] The output current I5 of the current amplifier (drain current of transistor Q5) is expressed by the following formula using the drain current I1 of transistor Q1, the constant current Ic output from the constant current source, and the mirror ratios M and N:

[0053] I5 = M × N × (Ic - I1).

[0054] The transistor Q6 configured as a P-channel MOSFET is provided between the current amplifier and the output transistor Q7. The transistor Q6 is paired with the output transistor Q7 to form a current source type current mirror circuit. The mirror ratio (the size of the output transistor relative to the size of the input transistor) of the current mirror circuit formed by the transistor Q6 and the output transistor Q7 is 1.

[0055] The gates of the transistor Q6 and the output transistor Q7 and the drain of the transistor Q6 are connected to the drain of the transistor Q5. The source of the transistor Q6 is connected to the terminal IN.

[0056] The converter, the current amplifier, and the transistor Q6 constitute a second controller configured to linearly control the output transistor Q7 based on the error voltage output from the error amplifier 21 .

[0057] Figure 2 is a diagram showing a schematic structure of a switching power supply device according to a reference example. Figure 2 The switching power supply device shown includes a substrate 201 , a semiconductor integrated circuit device 100 mounted on the substrate 201 , an inductor L1 mounted on the substrate 201 , and an output capacitor C1 mounted on the substrate 201 .

[0058] exist Figure 2 In the switching power supply device shown, the first controller is in an enabled state, and the second controller is in a disabled state.

[0059] The substrate 201 has wiring patterns P1 to P4. The wiring patterns P1 to P4 are made of a conductive material such as copper foil, aluminum foil, etc. The wiring pattern P1 is a wiring pattern for electrically connecting the terminal SW and the first end of the inductor L1. The wiring pattern P2 is a wiring pattern for electrically connecting the second end of the inductor L1 and the first end of the output capacitor C1. The wiring pattern P3 is a wiring pattern for electrically connecting the second end of the output capacitor C1 and the terminal GND. The wiring pattern P4 is a wiring pattern for electrically connecting the wiring pattern P2 and the terminal OUT.

[0060] The wiring patterns P1 and P2 are wide wiring patterns that allow a large current to flow. On the other hand, since the wiring pattern P4 only needs to transmit voltage information, the wiring pattern P4 is a narrow wiring pattern.

[0061] Figure 3 is a diagram showing a schematic structure of a linear power supply device according to a reference example. Figure 3 The linear power supply device shown includes a substrate 202 , a semiconductor integrated circuit device 100 mounted on the substrate 202 , and an output capacitor C1 mounted on the substrate 202 .

[0062] exist Figure 3 In the linear power supply apparatus shown, the first controller is in a disabled state and the second controller is in an enabled state.

[0063] The substrate 202 has wiring patterns P5 and P6. The wiring patterns P5 and P6 are made of a conductive material such as copper foil, aluminum foil, etc. The wiring pattern P5 is a wiring pattern for electrically connecting the terminal OUT and the first end of the output capacitor C1. The wiring pattern P6 is a wiring pattern for electrically connecting the second end of the output capacitor C1 and the terminal GND.

[0064] The wiring pattern P5 is a wide wiring pattern that allows a large current to flow.

[0065] As described above, the wiring pattern of the substrate 201 used when the semiconductor integrated circuit device 100 is used as a part of the switching power supply device is different from the wiring pattern of the substrate 201 used when the semiconductor integrated circuit device 100 is used as a part of the linear power supply device. That is, when the semiconductor integrated circuit device 100 is used as a part of the power supply device, the substrate for the switching power supply device and the substrate for the linear power supply device cannot be made common. Therefore, when the semiconductor integrated circuit device 100 is used as a part of the power supply device, it is necessary to spend time and effort to prepare the substrate for the switching power supply device and the substrate for the linear power supply device.

[0066] <First Embodiment>

[0067] Figure 4 is a diagram showing a schematic structure of a semiconductor integrated circuit device according to a first embodiment. Figure 4 The semiconductor integrated circuit device 101 shown in FIG. Figure 1 The semiconductor integrated circuit device 100 shown is different in that the semiconductor integrated circuit device 101 does not include the error amplifier 21, the output terminal of the error amplifier 11 is connected to the gate of the transistor Q1, and the drain of the output transistor Q7 is connected to the terminal SW. In other respects, Figure 4 The semiconductor integrated circuit device 101 shown basically has the same Figure 1 The configuration of the semiconductor integrated circuit device 100 shown is the same configuration.

[0068] Figure 5 1 is an external perspective view of a semiconductor integrated circuit device 101. The semiconductor integrated circuit device 101 is an electronic component that includes a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) for accommodating the semiconductor chip, and a plurality of external terminals exposed from the housing to the outside of the semiconductor integrated circuit device 101. The semiconductor integrated circuit device 101 is formed by sealing the semiconductor chip in a housing (package) made of resin. Figure 5 The number of external terminals of the semiconductor integrated circuit device 101 and the type of housing of the semiconductor integrated circuit device 101 shown are merely examples and can be arbitrarily designed.

[0069] exist Figure 4 , only the terminal IN, the terminal SW, the terminal OUT, and the terminal GND are shown as a part of the plurality of external terminals provided on the semiconductor integrated circuit device 101. However, other external terminals (eg, an enable terminal, a communication terminal, etc.) are also provided on the semiconductor integrated circuit device 101.

[0070] In the semiconductor integrated circuit device 101, the first controller configured to perform switching control and the second controller configured to perform linear control are both based on the error voltage V ERR Control is performed, which makes it possible to reduce the number of error amplifiers. Therefore, the area efficiency of the semiconductor integrated circuit device 101 can be improved compared with the area efficiency of the semiconductor integrated circuit device 100.

[0071] Since the semiconductor integrated circuit device 101 includes the terminal SW configured such that the connection node between the transistors M1 and M2 and the drain of the output transistor Q7 are connected to the terminal SW, a substrate for a switching power supply device and a substrate for a linear power supply device can be commonly used.

[0072] Figure 6 : is a diagram showing a schematic structure of a switching power supply device according to a first embodiment. Figure 6 The switching power supply device shown includes a substrate 201 , a semiconductor integrated circuit device 100 mounted on the substrate 201 , an inductor L1 mounted on the substrate 201 , and an output capacitor C1 mounted on the substrate 201 .

[0073] exist Figure 6 In the switching power supply device shown, the first controller is in an enabled state, and the second controller is in a disabled state.

[0074] The substrate 201 has wiring patterns P1 to P4. The wiring patterns P1 to P4 are made of a conductive material such as copper foil, aluminum foil, etc. The wiring pattern P1 electrically connects the terminal SW and the first end of the inductor L1. The wiring pattern P2 electrically connects the second end of the inductor L1 and the first end of the output capacitor C1. The wiring pattern P3 electrically connects the second end of the output capacitor C1 and the terminal GND. The wiring pattern P4 electrically connects the wiring pattern P2 and the terminal OUT.

[0075] The wiring patterns P1 and P2 are wide wiring patterns that allow a large current to flow. On the other hand, since the wiring pattern P4 only needs to transmit voltage information, the wiring pattern P4 is a narrow wiring pattern.

[0076] Figure 7 : is a diagram showing a schematic structure of a linear power supply device according to a first embodiment. Figure 7 The linear power supply device shown includes a substrate 201, a semiconductor integrated circuit device 100 mounted on the substrate 201, a conductor D1 mounted on the substrate 201, and an output capacitor C1 mounted on the substrate 201. The conductor D1 is a discrete component having a resistance value of approximately 0 ohms.

[0077] exist Figure 7In the linear power supply apparatus shown, the first controller is in a disabled state and the second controller is in an enabled state.

[0078] The substrate 201 has wiring patterns P1 to P4. The wiring patterns P1 to P4 are made of a conductive material such as copper foil, aluminum foil, etc. The wiring pattern P1 electrically connects the terminal SW and the first end of the conductor D1. The wiring pattern P2 electrically connects the second end of the conductor D1 and the first end of the output capacitor C1. The wiring pattern P3 electrically connects the second end of the output capacitor C1 and the terminal GND. The wiring pattern P4 electrically connects the wiring pattern P2 and the terminal OUT.

[0079] The wiring patterns P1 and P2 are wide wiring patterns that allow a large current to flow. On the other hand, since the wiring pattern P4 only needs to transmit voltage information, the wiring pattern P4 is a narrow wiring pattern.

[0080] As described above, when the semiconductor integrated circuit device 101 is used as a part of a power supply device, the substrate for the switching power supply device and the substrate for the linear power supply device can be shared. Therefore, when the semiconductor integrated circuit device 101 is used as a part of a power supply device, it is not necessary to spend time and effort to prepare the substrate for the switching power supply device and the substrate for the linear power supply device.

[0081] In addition, at the stage of evaluating whether to use the semiconductor integrated circuit device 101 as part of a switching power supply device or as part of a linear power supply, it is desirable that the substrate for the switching power supply device and the substrate for the linear power supply can be shared as described above.

[0082] However, after completing the above evaluation and determining whether the semiconductor integrated circuit device 101 will be used as part of a switching power supply device or a linear power supply device, a substrate dedicated to a switching power supply device or a substrate dedicated to a linear power supply device can be manufactured.

[0083] The substrate dedicated to the switching power supply device may have a structure in which, for example, a wiring pattern having an inductor component having a first end electrically connected to the terminal SW via the wiring pattern P1 and a second end electrically connected to the wiring pattern P2 is added to the substrate 201. Therefore, the inductor L1 as a discrete component becomes unnecessary.

[0084] The substrate dedicated to the linear power supply device may have a structure in which, for example, a wiring pattern having no inductor component, which has a first end electrically connected to the terminal SW via the wiring pattern P1 and a second end electrically connected to the wiring pattern P2, is added to the substrate 201. Therefore, the conductor D1 as a discrete component becomes unnecessary. The expression "having no inductor component" also includes the case where the inductor component is so small that it can be considered to be zero.

[0085] Figure 8 1 is a diagram showing a configuration example of the phase compensation circuit 12 . Figure 8 The phase compensation circuit 12 of the structural example shown includes a corresponding Figure 4 The capacitor 12a shown includes a plurality of capacitors and a plurality of switches, and includes a corresponding Figure 4 The semiconductor integrated circuit device 101 includes a plurality of resistors and a plurality of switches of the resistor 12b shown. The semiconductor integrated circuit device 101 includes a register 18 and a switch controller 19. The register 18 stores the settings of the phase compensation circuit 12, specifically, stores the on / off settings of each switch in the phase compensation circuit 12. The switch controller 19 controls the on / off of each switch in the phase compensation circuit 12 based on the settings of the phase compensation circuit 12 stored in the register 18.

[0086] Since the number of error amplifiers is reduced, it is not necessary to provide the register 18 and the switch controller 19 for each error amplifier. Therefore, the area efficiency of the circuit portion related to the phase compensation circuit 12 can be improved.

[0087] <Second Embodiment>

[0088] Fig. 9 is a diagram showing a schematic structure of a semiconductor integrated circuit device according to a second embodiment. Fig. 9 The semiconductor integrated circuit device 102 shown is Figure 4 The semiconductor integrated circuit device 101 shown is different in that the semiconductor integrated circuit device 102 includes a switch SW1 and a switch controller ( Fig. 9 ), but otherwise has the same Figure 4 The semiconductor integrated circuit device 101 shown has basically the same structure.

[0089] The switch SW1 turns on and off the short circuit between the gate and the source of the output transistor Q7. The switch SW1 is, for example, a P-channel MOSFET.

[0090] When the semiconductor integrated circuit device 102 is used as a part of a switching power supply device, the first controller is in an enabled state, the second controller is in a disabled state, and the switch SW1 is turned on. As a result, the gate and source of the output transistor Q7 are short-circuited by the switch SW1. Therefore, the output transistor Q7 can be prevented from being turned on due to the charging of the parasitic capacitance between the gate and source of the output transistor Q7.

[0091] When the semiconductor integrated circuit device 102 is used as a part of a linear power supply device, the first controller is in a disabled state, the second controller is in an enabled state, and the switch SW1 is turned off.

[0092] <Third Embodiment>

[0093] Fig.10 is a diagram showing a schematic structure of a semiconductor integrated circuit device according to a third embodiment. Fig.10 The semiconductor integrated circuit device 103 shown is Figure 4 The semiconductor integrated circuit device 101 shown is different in that the semiconductor integrated circuit device 103 includes a switch SW2 and a switch SW3 and a switch controller ( Fig.10 ), but otherwise has the same Figure 4 The semiconductor integrated circuit device 101 shown has basically the same structure.

[0094] The switch SW2 is provided between the source of the transistor Q6 and the source of the output transistor Q7. The switch SW2 is, for example, a P-channel MOSFET.

[0095] The switch SW3 is provided between the gate of the transistor Q6 and the terminal GND. The switch SW3 is, for example, an N-channel MOSFET.

[0096] When the semiconductor integrated circuit device 103 is used as a part of a switching power supply device, the first controller is in an enabled state, the second controller is in a disabled state, the switch SW2 is turned on, and the switch SW3 is turned off.

[0097] When the semiconductor integrated circuit device 103 is used as a part of a linear power supply device, the first controller is in a disabled state, the second controller is in an enabled state, the switch SW2 is turned on, and the switch SW3 is turned off.

[0098] When the output transistor Q7 of the semiconductor integrated circuit device 103 is used as a load switch, the first controller is in a disabled state, the second controller is in an enabled state, the switch SW2 is turned off, and the switch SW3 is turned on. Since the switch SW2 is turned off, the gate of the output transistor Q7 is prevented from being clamped to the threshold voltage of the transistor Q6. In addition, since the switch SW3 is turned on, the ground voltage is supplied to the gate of the output transistor Q7. As a result, the output transistor Q7 is fully turned on. Therefore, the output transistor Q7 can be used as a load switch.

[0099] <Others>

[0100] In addition to the above-mentioned embodiments, various modifications may be made to the configuration of the present invention without departing from the spirit of the present invention. The above-mentioned embodiments should be considered to be exemplary and non-restrictive in all aspects. The technical scope of the present invention is defined by the claims rather than the above description of the embodiments, and should be understood to include all modifications that are equivalent to the claims in meaning and scope.

[0101] For example, a diode having an anode connected to the terminal GND and a cathode connected to the drain of the transistor M1 may be used instead of the transistor M2. When the diode is used instead of the transistor M2, the first controller controls the voltage of the terminal SW by switching the transistor M1, thereby controlling the on / off switching of the diode.

[0102] In addition, for example, the transistor M1 may be an N-channel MOSFET. When the transistor M1 is an N-channel MOSFET, a bootstrap circuit may be provided in the power supply device.

[0103] For example, in the above-described embodiment, the semiconductor integrated circuit device has built-in resistors R1 and R2, but the resistors R1 and R2 may be externally connected to the semiconductor integrated circuit device. In addition, the power supply device may have a configuration without the resistors R1 and R2, and the feedback voltage V FB Can be the output voltage V of the power supply device OUT itself, rather than the output voltage V OUT The partial pressure.

[0104] <Notes>

[0105] A supplementary note regarding the present invention will be provided in which a specific configuration example is shown in the above-mentioned embodiment.

[0106] A semiconductor integrated circuit device (101, 102, 103) of the present invention is configured to be used as a part of a power supply device, comprising: an error amplifier (11) configured to output an error voltage based on a difference between a feedback voltage based on an output voltage of the power supply device and a reference voltage; a first switching element (M1) and a second switching element (M2) connected in series; a first controller (13, 14, 15, CD) configured to control switching actions of the first switching element and the second switching element based on the error voltage; an output transistor (Q7); a second controller (Q1 to Q6, 22) configured to linearly control the output transistor based on the error voltage; and a first terminal (SW) configured so that a connection node between the first switching element and the second switching element and an output terminal of the output transistor are both connected to the first terminal (first structure).

[0107] According to the semiconductor integrated circuit device of the first structure, the first controller configured to perform switch control and the second controller configured to perform linear control both perform control based on the same error voltage. Therefore, the number of error amplifiers can be reduced. As a result, the area efficiency of the semiconductor integrated circuit device can be improved.

[0108] In addition, since the semiconductor integrated circuit device of the first structure includes a first terminal, which is configured so that the connection node between the first switching element and the second switching element and the output terminal of the output transistor are both connected to the first terminal, the substrate for the switching power supply device and the substrate for the linear power supply device can be shared.

[0109] The semiconductor integrated circuit device of the first structure may further include a phase compensation circuit (12) configured to perform phase compensation on the error amplifier (second structure).

[0110] The semiconductor integrated circuit device of the first structure or the second structure may further include a first switch (SW1) configured to turn on and off a short circuit between a gate and a source of the output transistor (third structure).

[0111] The semiconductor integrated circuit device of any one of the first structure to the third structure may also include: a field effect transistor (Q6) which is paired with the output transistor to form a current mirror circuit; and a second switch (SW2) which is arranged between the source of the field effect transistor and the source of the output transistor (fourth structure).

[0112] The semiconductor integrated circuit device of the fourth structure may further include a third switch (SW3) provided between the gate of the field effect transistor and the second terminal (GND) configured to receive a ground voltage (fifth structure).

[0113] The semiconductor integrated circuit device of the fifth structure can have a first operation mode in which the second switch is turned on and the third switch is turned off, and a second operation mode in which the second switch is turned off and the third switch is turned on (sixth structure).

[0114] A power supply device of the present invention includes: a substrate (201); and a semiconductor integrated circuit device (seventh structure) of any one of the first structure to the sixth structure mounted on the substrate.

[0115] The power supply device of the seventh structure further includes a wiring pattern having an inductor (L1) mounted on the substrate and electrically connected to the first terminal, or having an inductor component formed on the substrate and electrically connected to the first terminal (eighth structure).

[0116] The power supply device of the seventh structure further includes a wiring pattern having a conductor (D1) mounted on the substrate and electrically connected to the first terminal, or does not have an inductor component formed on the substrate and electrically connected to the first terminal (ninth structure).

[0117] Although specific embodiments have been described, these embodiments are presented only by way of example and are not intended to limit the scope of the present invention. In fact, the embodiments described herein may be embodied in various other forms. In addition, various omissions, substitutions and changes may be made to the forms of the embodiments described herein without departing from the spirit of the present invention. The accompanying claims and their equivalents are intended to cover such forms or variations that will fall within the scope and spirit of the present invention.

[0118] Description of Reference Numerals

[0119] 11, 21: Error amplifier

[0120] 12: Phase compensation circuit

[0121] 12a: Capacitor

[0122] 12b: Resistor

[0123] 13: Ramp voltage generation circuit

[0124] 14: Comparator

[0125] 15: Clock signal generation circuit

[0126] 16: Logic Circuit

[0127] 17: Driving circuit

[0128] 18: Register

[0129] 19: Switch Controller

[0130] 22: Constant current source

[0131] 100 to 103: Semiconductor integrated circuit devices

[0132] 201, 202: Substrate

[0133] C1: Output capacitor

[0134] CD: drive control circuit

[0135] D1: Conductor

[0136] L1: Inductor

[0137] M1, M2, Q1 to Q6: transistors

[0138] Q7: Output transistor

[0139] R1, R2: Resistors

[0140] IN, SW, OUT, GND: terminals

[0141] P1 to P6: Wiring pattern

[0142] SW1 to SW3: first to third switches.

Claims

1. A semiconductor integrated circuit device configured to be used as a part of a power supply device, comprising: an error amplifier configured to output an error voltage based on a difference between a feedback voltage based on an output voltage of the power supply device and a reference voltage; a first switching element and a second switching element connected in series; a first controller configured to control switching operations of the first switching element and the second switching element based on the error voltage; Output transistor; a second controller configured to linearly control the output transistor based on the error voltage; as well as A first terminal configured such that a connection node between the first switching element and the second switching element and an output terminal of the output transistor are both connected to the first terminal. 2 . The semiconductor integrated circuit device according to claim 1 , further comprising a phase compensation circuit configured to perform phase compensation on the error amplifier.

3. The semiconductor integrated circuit device according to claim 1, further comprising a first switch configured to turn on and off a short circuit between a gate and a source of the output transistor.

4. The semiconductor integrated circuit device according to claim 1, further comprising: a field effect transistor paired with the output transistor to form a current mirror circuit; as well as A second switch is provided between a source of the field effect transistor and a source of the output transistor. 5 . The semiconductor integrated circuit device according to claim 4 , further comprising a third switch provided between the gate of the field effect transistor and a second terminal configured to receive a ground voltage.

6. The semiconductor integrated circuit device according to claim 5, having a first operation mode in which the second switch is turned on and the third switch is turned off, and A second operation mode in which the second switch is off and the third switch is on.

7. A power supply device, comprising: substrate; as well as The semiconductor integrated circuit device according to any one of claims 1 to 6, wherein the semiconductor integrated circuit device is mounted on the substrate. 8 . The power supply device according to claim 7 , further comprising a wiring pattern having an inductor mounted on the substrate and electrically connected to the first terminal, or having an inductor component formed on the substrate and electrically connected to the first terminal.

9. The power supply device according to claim 7, further comprising a wiring pattern having a conductor mounted on the substrate and electrically connected to the first terminal, or having no inductor component formed on the substrate and electrically connected to the first terminal.

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