System and method for zero voltage detection in resonant pole inverter

Abstract

Embodiments of the present disclosure relate to systems and methods for zero voltage detection in resonant pole inverters. A zero voltage detection device may include: a voltage divider scaling down a first voltage to a second voltage; a comparator that compares the second voltage to one or more voltage thresholds and outputs an estimate of a first set of signals indicative of a moment when the first voltage approaches zero voltage, the one or more voltage thresholds configured to compensate for a time delay from the voltage divider; a trigger acquiring the first set of signals and outputting a second set of signals to control a switching operation of the switching device; and a control system that acquires the second set of signals during a defined time window and forces the switching device to turn on at the end of the defined time window if the second set of signals is not detected to limit the turn-on loss.

Description

Technical Field

[0001] The present disclosure relates to the field of inverters. More specifically, the present disclosure relates to a system and method for zero voltage detection in a soft switching inverter. Background Art

[0002] Conventional inverters provide AC voltage from a DC power source. For example, an inverter may be included in an uninterruptible power supply or an adjustable speed drive to provide an AC voltage from a power source. To synthesize the AC voltage, the inverter uses a pulse width modulation (PWM) technique that involves switching power semiconductor devices on and off at a certain switching frequency. To enable operation at high switching frequencies with high efficiency, the inverter may employ a soft switching technique that is based on switching semiconductor devices on or off when the voltage across the semiconductor is zero volts. Summary of the invention

[0003] Soft switching devices often utilize auxiliary circuits to provide zero voltage switching during commutation events. The auxiliary circuits can reduce switching losses compared to conventional inverters by enabling zero voltage switching (ZVS) during each switching cycle. In order to achieve proper ZVS turn-on, an estimate of when the voltage across the main switching device reaches zero must be determined.

[0004] Conventional methods perform zero voltage detection ("ZVD") by calculating the approximate time at which the voltage reaches zero volts based on one or more parameters observed at the inverter. However, this conventional method is sensitive to parameter deviations, temperature, and other variables that may negatively affect ZVD. Other conventional methods may utilize auxiliary circuits to perform ZVD. However, due to the fast switching frequency required by the inverter and the sensitivity of the auxiliary circuit to noise, accurately detecting the zero volt moment may be challenging. Specifically, conventional auxiliary circuits perform ZVD by scaling down the voltage of the inverter, which amplifies the effects of noise in the auxiliary circuit and may result in erroneous detection of the zero volt moment. In addition, although a common solution may be to introduce a noise filter in the auxiliary circuit, this proposed solution may cause delays, resulting in higher turn-on losses and may result in electromagnetic interference. Delays and noise in the auxiliary circuit may result in missing the zero volt moment, which will stop the commutation process at the inverter due to the lack of a ZVD signal received from the auxiliary circuit.

[0005] In some embodiments, a device for performing zero voltage detection (ZVD) includes a voltage divider, a comparator, a trigger, and a control system, wherein the voltage divider is configured to scale down a first voltage to a second voltage, the comparator compares the second voltage with one or more voltage thresholds and outputs a first set of signals indicating an estimate of the moment when the first voltage is close to zero voltage, the one or more voltage thresholds are configured to compensate for time delays from the voltage divider, the trigger is configured to acquire the first set of signals and output a second set of signals to control the switching operation of a switching device, the control system is configured to acquire the second set of signals during a defined time window, and if the second set of signals is not detected, the control system forces the switching device to turn on at the end of the defined time window to limit turn-on losses.

[0006] In some embodiments, the voltage divider includes a resistor voltage divider and a capacitive voltage divider, the resistor voltage divider includes one or more resistors connected in series, and the capacitive voltage divider includes one or more capacitors connected in series, each of the one or more capacitors is connected in parallel with each of the one or more resistors.

[0007] In some embodiments, the resistor divider defines the second voltage during steady state operation, the capacitor divider defines the second voltage during voltage transitions, and a voltage ratio of the resistor divider is substantially equal to a voltage ratio of the capacitor divider.

[0008] In some embodiments, the device further comprises a damping resistor configured to reduce electromagnetic noise at the device to reduce turn-on losses.

[0009] In some embodiments, the one or more voltage thresholds include a first voltage threshold and a second voltage threshold.

[0010] In some embodiments, the comparator includes a first comparator and a second comparator, the first comparator generates a first signal as an output based on a comparison between the second voltage and a first voltage threshold, the second comparator generates a second signal as an output based on a comparison between the second voltage and a second voltage threshold, the first group of signals includes the first signal and the second signal and represents an estimate of the zero voltage moment.

[0011] In some embodiments, the flip-flop includes a first logic gate device and a second logic gate device, an output of the first logic gate device and an output of the second logic gate device being connected to an input of the other of the first logic gate device and the second logic gate device.

[0012] In some embodiments, the control system acquires the second set of signals and controls the on / off switching of the cycling switching device.

[0013] In some embodiments, the first set of signals is not affected by electrical noise in the second voltage.

[0014] In some embodiments, a system includes one or more switching devices, a ZVD device associated with each switching device, and a control system, the ZVD device including a voltage divider and a trigger, the voltage divider including a resistor voltage divider and a capacitor voltage divider, the resistor voltage divider including one or more resistors connected in series, the capacitor voltage divider including one or more capacitors connected in series, the voltage divider scales down a first voltage to a second voltage, a comparator compares the second voltage with one or more voltage thresholds determined based on an expected zero voltage moment, and the comparator outputs a first set of signals indicating an estimate of the second voltage approaching the zero voltage moment to compensate for a time delay from the voltage divider, the trigger acquires the first set of signals and outputs a second set of signals to control the switching operation of the corresponding switching device, the control system is configured to acquire the second set of signals during a defined time window, and if the second set of signals is not detected, the control system forces the switching device to turn on at the end of the defined time window to limit turn-on losses.

[0015] In some embodiments, the system further includes a damping resistor configured to reduce electromagnetic noise at the device to reduce turn-on losses.

[0016] In some embodiments, each of the one or more capacitors is connected in parallel with each of the one or more resistors, the resistor divider defines the second voltage during steady-state operation, and the capacitor divider defines the second voltage during voltage transitions, and a voltage ratio of the resistor divider is substantially equal to a voltage ratio of the capacitor divider.

[0017] In some embodiments, the comparator includes a first comparator and a second comparator, the first comparator compares the second voltage with a first voltage threshold and generates as an output a first ZVD signal representing an estimate of the zero voltage moment of the second voltage, the second comparator compares the second voltage with a second voltage threshold and generates as an output a second ZVD signal representing an estimate of the zero voltage moment of the second voltage, and the one or more voltage thresholds include the first voltage threshold and the second voltage threshold.

[0018] In some embodiments, the flip-flop includes a first logic gate device and a second logic gate device, and the outputs of the first logic gate device and the second logic gate device are connected to the input of the other of the first logic gate device and the second logic gate device, and the second set of signals is configured to cycle the on / off of the switch device based on the first set of signals.

[0019] In some embodiments, the control system acquires the second set of signals and controls the on / off switching of the cycling switching device.

[0020] In some embodiments, the first set of signals is not affected by electrical noise in the second voltage.

[0021] In some embodiments, a method includes obtaining a first voltage applied to a switching device as an input through a zero voltage detection (ZVD) device, scaling down the first voltage to a second voltage within a time delay through the ZVD device, comparing the second voltage with one or more voltage thresholds through the ZVD device and generating a first set of signals as output indicating an estimate of a moment when the first voltage is close to zero volts, generating a second set of signals as output through the ZVD device based on the first set of signals to cycle the switching device on / off, and forcing the switching device to turn on through the ZVD device to limit turn-on losses if the second set of signals is not detected at the end of a defined time window, the one or more voltage thresholds being configured to compensate for the time delay.

[0022] In some embodiments, the method further includes damping the first voltage by the ZVD device to reduce electromagnetic noise in the first voltage and reduce turn-on losses at the ZVD device.

[0023] In some embodiments, comparing the second voltage with one or more voltage thresholds and generating a first set of signals as outputs also includes: comparing the second voltage with a first voltage threshold by a first comparator and generating a first signal as an output, and comparing the second voltage with a second voltage threshold by a second comparator and generating a second signal as an output, the one or more voltage thresholds including a first voltage threshold and a second voltage threshold, and the second set of signals output by the ZVD device are based on the first signal and the second signal.

[0024] In some embodiments, generating a second set of signals as outputs based on the first set of signals to cycle the on / off state of the switching device further comprises: acquiring the first signal as input at the first logic gate device, acquiring the second signal as input at the second logic gate device, and acquiring the second set of signals as outputs from the first logic gate device through a control system, and controlling the on / off cycle of the switching device based on the second set of signals, the output of the first logic gate device further comprising another input to the second logic gate device, and the output of the second logic gate device further comprising another input to the first logic gate device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Some embodiments of the present disclosure are described herein with reference to the accompanying drawings by way of example only. With specific reference now to the accompanying drawings in detail, it should be emphasized that the embodiments shown are only examples and are used to illustrate embodiments of the present disclosure. In this regard, the description in conjunction with the accompanying drawings makes it clear to those skilled in the art how to practice the embodiments of the present disclosure.

[0026] Figure 1 A schematic diagram illustrating a non-limiting example of a system according to some embodiments;

[0027] Figure 2 is a diagram showing a method according to some embodiments Figure 1 A block diagram of a non-limiting example of a system;

[0028] Figure 3 is a block diagram illustrating another non-limiting example of a system according to some embodiments;

[0029] Figure 4 is a diagram showing a method according to some embodiments Figure 1 A schematic diagram of a non-limiting example embodiment of a portion of a system;

[0030] Figure 5 A graphical representation of the operation of a system according to some embodiments is shown;

[0031] Figure 6 a second graphical representation illustrating a non-limiting example of a system that facilitates zero voltage detection in accordance with some embodiments; and

[0032] Figure 7 A flow chart of a method according to some embodiments is shown. DETAILED DESCRIPTION

[0033] Among the benefits and improvements that have been disclosed, other objects and advantages of the present disclosure will become apparent through the following description in conjunction with the accompanying drawings. Detailed embodiments of the present disclosure are disclosed herein; however, it should be understood that the disclosed embodiments are merely illustrative of the disclosure that can be embodied in various forms. In addition, each example given with respect to the various embodiments of the present disclosure is illustrative and not restrictive.

[0034] Various embodiments of the present disclosure relate to systems, devices, and methods of auxiliary circuits capable of performing zero voltage detection ("ZVD") in soft switching circuits. The auxiliary circuit may also be referred to as an auxiliary resonant commutated pole ("ARCP") inverter system. The auxiliary circuit may include one or more ZVD systems or devices configured to acquire current signals directed to switching devices in the ARCP inverter system, and may perform operations, including performing ZVD based on the current signals measured at the switching devices. As a result of performing the ZVD operation, the ZVD system may acquire the current signal and may output a gate signal to operate the switching device in a zero voltage switching ("ZVS") mode. In this regard, the ZVD system of the present disclosure may be capable of controlling the switching operation of the corresponding switching devices in the ARCP inverter system while achieving a high switching frequency. The ZVD system may also include one or more electrical components therein, the one or more electrical components being configured to provide improved noise immunity while reducing ZVD circuit losses in transition to minimize circuit delays and provide improved tolerance for missed zero volt moments to limit turn-on losses.

[0035] Figure 1 A schematic diagram of a non-limiting example of a system 100 is shown in accordance with some embodiments.

[0036] System 100 is an ARCP inverter system including an inverter branch 102. System 100 and inverter branch 102 may be capable of being used in multiple applications requiring high frequency switching operations. Inverter branch 102 may be a soft switching inverter and include switching devices 106a and switching devices 106b connected in series across inverter branch 102 (e.g., across a bus of inverter branch 102). Hereinafter, switching devices 106a and switching devices 106b may be collectively referred to as switching devices 106. System 100 also includes a zero voltage detection (ZVD) device 108 associated with each respective switching device in switching device 106. Inverter branch 102 may also include a resonant circuit 104 (e.g., an LC resonant circuit).

[0037] The system 100 may include a ZVD device 108a connected to the inverter branch 102 at the switching device 106a and a ZVD device 108b connected to the inverter branch 102 at the switching device 106b. The ZVD device 108a and the ZVD device 108b may be collectively referred to as the ZVD device 108 hereinafter. The ZVD device 108 may be electrically connected to the inverter branch 102 adjacent to the corresponding switching device 106 to measure a voltage (e.g., a first voltage) to the switching device 106. In addition, each ZVD device 108 may be electrically connected to the corresponding switching device 106 to control the switching operation of the switching device 106, for example, based on the voltage measured at the inverter branch 102, in response to a gate control signal provided as an output by the ZVD device 108 to control the switching device 106 to be turned on and off.

[0038] In some embodiments, the ZVD device 108 may be electrically connected to the inverter branch 102 at the cathode of the switching device 106 to measure the current at the corresponding switching device 106 and perform ZVD based on the measured current signal. In some embodiments, the ZVD device 108 may calculate the voltage at the cathode of the ZVD device 108 based on the measured current. Based on the voltage measured at the corresponding switching device 106, and in response to estimating the voltage ZVI, the ZVD device 108 may generate a second set of signals as outputs. In some embodiments, the second set of signals may be gate control signals, and the gate control signals may be sent to the gate of the switching device 106 to cycle the switching device 106 on or off. In some embodiments, the ZVD device 108 may also be connected to the gate of the corresponding switching device 106 to cause the switching device 106 to cycle on or off based on the voltage measured at the cathode of the switching device 106.

[0039] The ZVD devices 108 enable the inverter branches 102 and the switching devices 106 to perform high switching frequency operations. In this regard, each ZVD device 108 acquires a current signal measured from the inverter branch 102 at the corresponding switching device 106, and controls the switching operation of the corresponding switching device 106 based on an estimate of when the voltage determined based on the current approaches the zero voltage moment, as will be further described herein. The ZVD device 108 estimates the zero voltage moment by acquiring a voltage from the inverter branch 102 at the switching device 106, scaling the voltage down to a second voltage, comparing the second voltage to one or more voltage thresholds and generating as output a first set of signals (ZVD signals) indicating an estimate of the moment when the voltage at the inverter branch 102 approaches the zero voltage moment, and generating as output a second set of signals (gate control signals) by the ZVD device 108 based on the first set of signals, the second set of signals being configured to cause the switching device 106 to turn on / off to avoid missing the zero voltage moment.

[0040] According to some embodiments, the switching device 106 may be a solid-state switching device (SSSD) capable of high switching frequency operation. In some embodiments, the switching device 106 may be a bidirectional switching device 106. According to some embodiments, the bidirectional switching device 106 may include, but is not limited to, an insulated gate bipolar transistor (IGBT), a metal oxide silicon field effect transistor (MOSFET), a bipolar junction transistor (BJT), a junction gate field effect transistor (JFET), other semiconductor devices, or any combination thereof. In some embodiments, the switching device 106 may be an IGBT. In other embodiments, the switching device 106 may be a SiC MOSFET. It should be understood by those of ordinary skill in the art that the type of SSSD of the switching device 106 is not intended to be limiting and may include any one of a plurality of SSSDs according to the present disclosure.

[0041] According to some embodiments, inverter branch 102 may include switching device 110a and switching device 110b. Switching device 110a and switching device 110b may be connected in an anti-series configuration at resonant circuit 104. In some embodiments, switching device 110a and switching device 110b may be located between inductor 182 and node 184, which node 184 connects the anode of switching device 106a to the cathode of switching device 106b. In another embodiment, switching device 110 may be located between inductor 182 and node 186, and inductor 182 is located between node 184 and switching device 110.

[0042] The inverter branch 102 may include one or more other circuits and / or components that enable the inverter branch 102 to perform operations according to the present disclosure. It should be understood by those of ordinary skill in the art that the inverter branch 102 described in the present disclosure is not intended to be limiting, and the inverter branch 102 may include other components not described herein that enable the inverter branch 102 to perform fast frequency switching operations.

[0043] Figure 2 is a diagram showing a method according to some embodiments Figure 1 1 is a block diagram of a non-limiting example of a system 100. A ZVD device 108 is electrically connected to an inverter branch 102 and a control system 112. In some embodiments, the ZVD device 108 is electrically connected to the inverter branch 102 at the cathode of the switching device 106 of the inverter branch 102. The ZVD device 108 includes a voltage divider 114, a comparator circuit 116, and a trigger circuit 118. The ZVD device 108 performs ZVD based on the following: obtaining a voltage V1 measured at the switching device 106 of the inverter branch 102 and generating a set of signals (e.g., gate control signals) configured to control the switching operation of the switching device 106 based on the voltage as an output.

[0044] In this regard, based on the moment when the voltage measured by the ZVD device 108 at the switching device 106 is close to zero voltage, the ZVD device 108 can output a turn-on signal (e.g., a gate signal) to cause the switching device 106 to cycle on, thereby promoting the switching device 106 to avoid missing the zero voltage moment of the voltage of the inverter branch 102 at the switching device 106 and enabling the inverter branch 102 to use the switching device 106 to perform high-frequency switching operations.

[0045] The ZVD device 108 includes a voltage divider 114. The voltage divider 114 obtains a voltage (e.g., a first voltage) from the inverter branch 102, and scales down the voltage and outputs a second voltage. In some embodiments, the voltage may be a voltage obtained at the cathode of the corresponding switching device 106 of the inverter branch 102. Since the voltage of the inverter branch 102 is scaled down to the second voltage, the trigger 118 may introduce a time delay at the second voltage that lags behind the voltage of the inverter branch 102.

[0046] The ZVD device 108 includes a comparator circuit 116. The comparator circuit 116 compares the second voltage from the voltage divider 114 with one or more voltage thresholds and outputs a first set of signals (e.g., ZVD signals). The one or more voltage thresholds are configured to compensate for the time delay caused by the voltage divider 114 scaling down the voltage of the inverter branch 102 to the second voltage. In this regard, the comparator circuit 116 compares the second voltage with one or more voltage thresholds rather than the expected voltage thresholds to account for the time delay caused by scaling down the voltage to the second voltage using the voltage divider 114. Based on the comparison, the comparator circuit 116 sends a first set of signals indicating the moment when the voltage at the inverter branch 102 and the switching device 106 is close to zero voltage.

[0047] The comparator circuit 116 obtains the second voltage from the voltage divider 114, and compares the second voltage with one or more voltage thresholds and generates a first set of signals as output. The first set of signals output by the comparator circuit 116 is an estimate by the ZVD device 108 of the time when the voltage obtained from the inverter branch 102 is close to zero voltage, and the estimate takes into account the time delay of the voltage divider 114 caused by scaling down the first voltage to the second voltage. In addition, the first set of signals output by the comparator circuit 116 is highly unaffected by noise that may affect the second voltage. This enables the ZVD device 108 to estimate the zero voltage moment at the inverter branch 102, and based on the estimate, the ZVD device 108 controls the on / off of the cycling switch device 106 with an optimal voltage threshold that takes into account the time delay from the voltage divider 114.

[0048] The ZVD device 108 includes a trigger 118. The trigger 118 obtains a first set of signals (e.g., ZVD signals) from the comparator circuit 116 and generates a second set of signals (e.g., gate control signals) as outputs based on a comparison of a second voltage with one or more voltage thresholds. Based on the first set of signals (which may indicate a voltage approaching a zero voltage moment and which may be generated based on a comparison of the second voltage with respect to one or more voltage thresholds), the trigger 118 outputs a second set of signals to cycle the switching device 106 in the inverter branch 102 on or off. In some embodiments, the trigger circuit 118 may be a set-reset (SR) trigger circuit.

[0049] Figure 3 is a block diagram illustrating another non-limiting example of a system 100 according to some embodiments.

[0050] The ZVD device 108 may be electrically connected to the switching device 106 in the inverter branch 102. In some embodiments, the inverter branch 102 may include one or more of the switching devices 106, and for each of the switching devices 106 in the inverter branch 102, the system 100 may include the ZVD device 108. According to some embodiments, the ZVD device 108 may include a control system 112, a voltage divider 114, a comparator circuit 116, a trigger 118, and a damping circuit 120. It should be understood by those skilled in the art that the ZVD device 108 may include one or more components, including but not limited to the control system 112, the voltage divider 114, the comparator circuit 116, the trigger 118, the damping circuit 120, other components and / or circuits, or any combination thereof. It should be understood by those skilled in the art that the ZVD device 108 may include one or more other components and / or circuits for enabling the ZVD device 108 to perform zero voltage detection according to the present disclosure.

[0051] The ZVD device 108 may include a damping circuit 120. The damping circuit 120 may be located between the input terminal of the ZVD device 108 and the voltage divider 114. The damping circuit 120 is configured to reduce noise in the ZVD device 108 that may be caused by electromagnetic interference (EMI) and / or electromagnetic noise. By reducing the noise in the ZVD device 108, the damping circuit 120 reduces the turn-on loss by reducing the possibility that the ZVD device 108 misses or fails to detect the zero voltage moment due to fluctuations that may occur in the ZVD device 108 due to noise. In some embodiments, the comparator circuit 116 may include the damping circuit 120. In other embodiments, the voltage divider 114 may include the damping circuit 120.

[0052] In some embodiments, the ZVD device 108 may include a control system 112. The control system 112 may obtain a second set of signals, such as a gate signal, from the trigger 118, and the control system 112 may control the cycling of the switching devices 106 in the inverter branch 102. In some embodiments, the control system 112 may also obtain a current or voltage measurement signal from the inverter branch 102.

[0053] Figure 4 is a diagram showing a method according to some embodiments Figure 1 Schematic diagram of a non-limiting example embodiment of a ZVD device 108 in FIG.

[0054] The ZVD device 108 includes a damping circuit 120. The damping circuit 120 includes a damping resistor 122. The damping resistor 122 reduces noise in the ZVD device 108 that may be caused by electromagnetic interference. By reducing the noise in the ZVD device 108, the damping resistor 122 reduces the possibility of the ZVD device 108 missing or not detecting the zero voltage moment due to voltage fluctuations in the ZVD device 108 due to such noise to reduce the turn-on loss. The damping resistor 122 can be located between the input terminal of the ZVD device 108 and the voltage divider 114. In some embodiments, the voltage divider 114 can include the damping resistor 122. In other embodiments, the comparator circuit 116 can include the damping resistor 122.

[0055] The ZVD device 108 includes a voltage divider 114. The voltage divider 114 includes a resistor divider 124 and a capacitive divider 126. The resistor divider 124 includes one or more resistors 128 connected in series. The capacitive divider 126 includes one or more capacitors 130 connected in series. In addition, according to some embodiments, the resistor divider 124 can be connected in parallel with the capacitive divider 126. In some embodiments, each resistor 128 in the resistor divider 124 can be connected in parallel with a corresponding capacitor 130 in the capacitive divider 126. It should be understood by those of ordinary skill in the art that the specific configuration of the voltage divider 114 is not intended to be limiting in accordance with the present disclosure, and based on the desired operating characteristics of the ZVD device 108, the voltage divider 114 can include one or more resistors 128 and one or more capacitors 130.

[0056] In the voltage divider 114, the voltage across the resistor divider 124 can be effectively equal to the voltage across the capacitor divider 126, so that the voltage ratio between the resistor divider 124 and the capacitor divider 126 is effectively equal. This enables the voltage divider 114 to operate so that the resistor divider 124 defines the second voltage during steady-state operation, and the capacitor divider 126 defines the second voltage during voltage transition. In some embodiments, the voltage ratio between the resistor divider 124 and the capacitor divider 126 can be equal to 1. In other embodiments, the voltage ratio between the resistor divider 124 and the capacitor divider 126 can be effectively equal to 1. In other embodiments, the voltage ratio between the resistor divider 124 and the capacitor divider 126 can be approximately equal to 1. However, in some embodiments, the second voltage output by the voltage divider 114 may not exceed the comparator maximum input voltage.

[0057] To improve noise immunity and reduce ZVD circuit losses, the resistor divider 124 and the capacitor divider 126 can each be configured to include a high impedance value. According to some embodiments, the voltage divider 114 can be configured such that the resistor divider 124 includes a large total equivalent resistance, while the capacitor divider 126 includes a low capacitance. In addition, in order to minimize / reduce the effect of parasitic capacitance on the voltage divider 114, the total capacitance of the capacitor divider 126 can be configured to be greater than the parasitic capacitance in the voltage divider 114 and the ZVD device 108.

[0058] The ZVD device 108 includes a comparator circuit 116. The comparator circuit 116 compares the second voltage with the first voltage threshold and the second voltage threshold, and outputs a corresponding ZVD signal as a result of the comparison. In some embodiments, the comparator circuit 116 can compare the second voltage with the first voltage threshold and output a first ZVD signal based on the comparison. In addition, in some embodiments, the comparator circuit 116 can compare the second voltage with the second voltage threshold and output a second ZVD signal based on the comparison. In some embodiments, the first group of signals includes a first ZVD signal and a second ZVD signal. In some embodiments, the comparator circuit 116 can be a high-speed comparator. In other embodiments, the comparator circuit 116 can be an ultra-fast comparator.

[0059] According to some embodiments, the comparator circuit 116 may include a comparator 132 and a comparator 134. The comparator 132 (e.g., a first comparator) outputs a first ZVD signal based on a comparison of the second voltage with the first voltage threshold by the comparator 132. For example, in some embodiments, when the second voltage is greater than the first voltage threshold, the comparator 132 outputs a value of 1, and when the second voltage is less than the first voltage threshold, the comparator 132 outputs a value of 0. The comparator 134 (e.g., a second comparator) outputs a second ZVD signal based on a comparison of the second voltage with the second voltage threshold by the comparator 134. For example, in some embodiments, when the second voltage threshold is greater than the second voltage, the comparator 134 outputs a value of 1, and when the second voltage threshold is less than the second voltage, the comparator 134 outputs a value of 0.

[0060] In the ZVD device 108, the first voltage threshold and the second voltage threshold can be set at the comparator circuit 116 using the low power supply voltage 136. In some embodiments, the low power supply voltage 136 can be a 12V power supply voltage. In addition, according to some embodiments, the comparator circuit 116 can include a second resistor divider 138, which enables the comparator circuit 116 to generate the first voltage threshold and the second voltage threshold from the low power supply voltage 136. The low power supply voltage 136 and the second resistor divider 138 can be configured to set the first voltage threshold and the second voltage threshold at the comparator circuit 116, and the voltage threshold can take into account the time delay caused by scaling down the voltage from the inverter branch 102 to the second voltage, and is an estimate of the expected zero voltage moment at the inverter branch 102. In some embodiments, one or more voltage thresholds can be based on the voltage at the low power supply voltage 136. In other embodiments, one or more voltage thresholds can also be based on the resistance at the second resistor divider 138.

[0061] In addition, the first voltage threshold and the second voltage threshold correspond to optimal voltage thresholds configured to trigger the switching device 106 to turn on based on a second voltage cycle relative to the first voltage threshold and the second voltage threshold to minimize the turn-on loss of the ZVD device 108. In some embodiments, the control system 112 can determine the first voltage threshold and the second voltage threshold at the ZVD device 108, and can be based on the time delay caused by the voltage divider 114 scaling down the voltage measured at the inverter branch 102 and the corresponding switching device 106. It should be understood by those of ordinary skill in the art that the voltage of the low power supply voltage 136 is not limiting, and the voltage of the low power supply voltage 136 can be greater than or less than 12V.

[0062] The one or more voltage thresholds at the ZVD device 108 compensate for the time delay caused by scaling down the first voltage from the inverter branch 102 to the second voltage. If the ZVD device 108 is to output a second set of signals, such as gate signals, because the second voltage is at or near the expected zero voltage moment, then by the time the ZVD device 108 outputs the second set of signals to trigger the switch device 106 to turn on, the actual voltage at the inverter branch 102 will have passed the zero volt moment, thereby causing turn-on losses at the corresponding switch device 106. For example, the ZVD device 108 sending the second set of signals based on the expected voltage threshold can cause the switch device 106 to cycle on after the zero voltage moment. In order to account for the time delay introduced by scaling down the voltage to the second voltage, the ZVD device 108 estimates the one or more voltage thresholds using the one or more voltage thresholds, which enables the ZVD device 108 to output signals to trigger the switch device 106 to turn on / off at the optimal voltage.

[0063] The trigger circuit 118 may be electrically connected to the comparator circuit 116. The trigger circuit 118 obtains a first set of signals from the comparator circuit 116 and outputs a second set of signals to the control system 112 and / or the corresponding ZVD device 108. The trigger circuit 118 may include a logic gate device 140 and a logic gate device 142. The trigger circuit 118 may include one or more different types of gate devices, including but not limited to an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, other logic gate devices, or any combination thereof. In some embodiments, the logic gate device 140 and the logic gate device 142 may each be a NOR gate. It should be understood by those of ordinary skill in the art that the trigger circuit 118, the logic gate device 140, the logic gate device 142, and / or other components of the ZVD device 108 may include one or more gate devices, each of which is any of a plurality of different types of logic gate devices, and may be arranged in any of a plurality of configurations to enable the ZVD device 108 to perform a ZVD operation according to the present disclosure.

[0064] like Figure 4 As shown, the output of comparator 132 is connected to the input of logic gate device 140, and the output of comparator 134 is connected to the input of logic gate device 142. In addition, the outputs of comparator 132 and comparator 134 can be connected to the input of the other of comparators 132 and 134. In addition, the output of comparator 132 can output a second set of signals to control the ZVD device 108 to cycle on and off based on the voltage of inverter branch 102 approaching an optimal voltage threshold, which corresponds to the value of the second voltage relative to the first voltage threshold of comparator 132 and relative to the second voltage threshold of comparator 134.

[0065] In addition, the output provided by the logic gate device 140 based on the first set of signals controls the switching of the corresponding switch device 106. For example, the second voltage is greater than the first voltage threshold and the second voltage threshold causes the comparator 132 to output a value of 1 to the logic gate device 140 and causes the comparator 134 to output a value of 0 to the logic gate device 142, thereby causing the flip-flop 118 to output a gate control signal with a value of 1, and causing the switch device 106 to cycle on. In another example, the second voltage is less than the first voltage threshold and the second voltage threshold causes the comparator 132 to output a value of 0 to the logic gate device 140 and causes the comparator 134 to output a value of 1 to the logic gate device 142, thereby causing the comparator 132 at the flip-flop circuit 118 to output a second signal or a second set of signals with a value of 0, which causes the switch device 106 to cycle off. It should be understood by a person of ordinary skill in the art that, in accordance with the present disclosure, the specific configuration of the trigger 118 is not intended to be limiting, and the ZVD device 108 may include any of a number of other components capable of controlling a gate signal output from the ZVD device 108 as a result of comparing the second voltage from the voltage divider 114 to one or more voltage thresholds.

[0066] The system 100 and / or the ZVD device 108 may include a control system 112. The control system 112 performs one or more operations according to the present disclosure, which may include obtaining a second set of signals from a trigger circuit 118 of the ZVD device 108, and based on the second set of signals, controlling the switching operation of the switching device 106 as a result of zero volt detection performed by the ZVD device 108. In some embodiments, the ZVD device 108 may include the control system 112. In other embodiments, the control system 112 may be electrically connected to the inverter branch 102 and / or the ZVD device 108 to monitor one or more parameters of the inverter branch 102 and / or the ZVD device 108. In other embodiments, the control system 112 may be included in the inverter branch 102.

[0067] According to some embodiments, the control system 112 may be configured to obtain the gate control signal output by the trigger circuit 118, and the control system 112 may control the cyclic operation of the switching device 106. In some embodiments, the control system 112 may be electrically communicatively connected to the ZVD device 108a and the ZVD device 108b, such as Figure 1As shown, the control system 112 may obtain a second set of signals corresponding to the gate control signals from the ZVD device 108a and / or the ZVD device 108b, and the control system 112 may control the switch device 106a or the switch device 106b, respectively, based on the signals obtained from the corresponding ZVD device 108. In other embodiments, the system 100 may include a control system 112a (not shown) connected to the ZVD device 108a, the control system 112a may control the on / off cycle of the switch device 106a based on the signals obtained from the ZVD device 108a, and the system 100 may include a second control system 112b (not shown) connected to the ZVD device 108b, the control system 112b may control the on / off cycle of the switch device 106b based on the signals obtained from the ZVD device 108b.

[0068] The control system 112 may be configured to control the operation of the ZVD device 108, including the timing of the ZVD device 108. In some embodiments, the control system 112 may control the ZVD device 108 so that the trigger circuit 118 may obtain a ZVD signal corresponding to the turn-on gate signal from the comparator circuit 116 within a defined time window. In some embodiments, the control system 112 may be configured to detect a first ZVD signal and / or a second ZVD signal (e.g., a value of 1) from the comparator circuit 116 within a defined time window. If the control system 112 does not detect the first ZVD signal and the second ZVD signal (e.g., a value of 1) within the defined time window, the control system 112 may force the corresponding switching device 106 to cycle on or off so that the operation of the soft-switching inverter branch 102 is not interrupted by the missed turn-on.

[0069] The time window may be defined to start during the period of the voltage transition from the first voltage to the second voltage to ensure that the gate control signal is sent to the switching device 106 at a low turn-on voltage and to tolerate missed zero crossings. In some embodiments, the time window may be defined to start when the first voltage begins to transition to the second voltage at the voltage divider 114 and end before the first voltage reaches an excessively high value in its natural oscillation. In other embodiments, the time window may be defined to start at the end of a defined period of boost time to charge one or more capacitors of the LC resonant circuit 104.

[0070] The control system 112 may trigger cycling of the switching device 106 during a defined time window. If the ZVD device 108 does not detect a zero voltage crossing at the end of the time window, in some embodiments, the control system 112 may force the switching device 106 to turn on so that the operation of the inverter branch 102 is not interrupted by missing the zero crossing and failing to turn on the switching device 106. In addition, since the defined time window ends at a low device voltage, turn-on losses at the inverter branch 102 may be limited.

[0071] Figure 5 A graphical representation 200 of the operation of the ZVD device 108 is shown in accordance with some embodiments.

[0072] Voltage 150 represents a first voltage measured at the switch device 106 on the inverter branch 102 and obtained by the ZVD device 108. Voltage 152 represents a second voltage that is a scaled-down version of the voltage 150 at the ZVD device 108 based on the voltage divider 114. Figure 5 As shown, there is a delay Δt between voltage 150 and voltage 152, which corresponds to the delay caused by scaling down the first voltage to the second voltage. For example, the delay of scaling down voltage 150 to voltage 152 may be 45ns. The time delay is the result of ZVD device 108 scaling down first voltage 150 to second voltage 152 to reduce noise in ZVD device 108. In some embodiments, voltage divider 114 may also scale down first voltage 150 to second voltage 152 so that second voltage 152 does not exceed the maximum voltage of comparator circuit 116, thereby reducing the possibility of damage to comparator circuit 116 by the second voltage.

[0073] In order to avoid voltage incompatibility between the resistor divider 124 and the capacitor divider 126, the voltage ratio Nr of the resistor divider 124 and the voltage ratio Nc of the capacitor divider 126 should be equal or substantially equal (e.g., the voltage ratio is 1), so that N=Nr=Nc=R2 / (R1+R2)=C1 / (C1+C2) (where R1 is the equivalent resistor 124a, R2 is the equivalent resistor 124b, C1 is the equivalent resistor 130a, and C2 is the equivalent resistor 130b). The combined voltage divider 114 operates so that the resistor divider 124 defines the second voltage 152 in a steady state and the capacitor divider 126 defines the second voltage 152 during a voltage transition.

[0074] exist Figure 5 The threshold 154 is related to the second voltage threshold V th- The corresponding optimization threshold, such as Figure 4By implementing an optimized threshold voltage, the switch device 106 can be cycled on / off according to a timing that takes into account the time delay caused by the ZVD device 108, rather than cycling the switch device 106 on / off when the voltage reaches the expected zero voltage (which may result in a missed zero voltage moment and turn-on losses).

[0075] The ZVD device 108 and the comparator circuit 116 send a first set of signals (e.g., ZVD signals) that indicate an estimate of when the first voltage approaches zero voltage and take into account the time delay caused by the voltage divider 114. The first set of signals is configured to enable the trigger circuit 118 to trigger the switching device 106 to cycle on / off based on a comparison of the second voltage 152 relative to one or more voltage thresholds (e.g., the second voltage 152 relative to the first voltage threshold and the second voltage threshold).

[0076] The control system 112 may define the value of one or more voltage thresholds. In some embodiments, the control system 112 may define one or more voltage thresholds based on an expected voltage threshold. In some embodiments, the first voltage threshold may be an expected voltage threshold upper limit, and the second voltage threshold may be an expected voltage threshold lower limit. In other embodiments, the first voltage threshold may be a threshold during a positive phase of the input voltage, and the second voltage threshold may be a threshold during a negative phase of the input voltage. In still other embodiments, the first voltage threshold may be a threshold during a negative phase of the input voltage, and the second voltage threshold may be a threshold during a positive phase of the input voltage. When the input voltage approaches a zero voltage moment during each of the corresponding positive and negative phases, the ZVD device 108 may cause the trigger circuit 118 to output a gate control signal to the switching device 106 to cycle on / off based on a second voltage trigger relative to the one or more voltage thresholds. Figure 4 In the example embodiment shown, Rt1 and Rt2 define a first voltage threshold (for Vth+), and Rt3 and Rt4 define a second voltage threshold (for Vth-).

[0077] Figure 6 A second graphical representation 300 of a non-limiting example of a system 100 that facilitates zero voltage detection in accordance with some embodiments is shown.

[0078] The figure shows a transition from switching device 106a to switching device 106b at inverter branch 102, where PWM1 and PWM2 correspond to the original PWM signals of inverter branch 102, Dce1 corresponds to the output signal of ZVD device 108a, and Dce2 corresponds to the output signal of ZVD device 108b, for example, as shown in FIG. Figure 4As shown, the signal ZV_H output by the trigger circuit 118. G1 corresponds to the gate control signal of the switching device 106a, G2 corresponds to the gate control signal of the switching device 106b, Ga1 corresponds to the PWM gate signal of the switching device 110a, and Ga2 corresponds to the PWM gate signal of the switching device 110b. In addition, T_w1 corresponds to the dead time between PWM1 and PWM2, T_bst1 corresponds to the rise time for establishing the current in the resonant inductor 182 before the voltage transition, T_w2 corresponds to the waiting time window for the gate signal to cycle to turn on the switching device 106b before the control system 112 forces the switching device 106b to be turned on to reduce the turn-on loss, and T_w3 corresponds to the waiting time for allowing the switching device 110a to be turned off.

[0079] refer to Figure 6 , the switch device 106b is forced to turn on using the gate control signal G2 at the end of the time window T_w2. The time window T_w2 starts in the transition and ends before the voltage at the switch device 106b reaches too high an oscillation. The switch device 106b is triggered to turn on at the end of T_w2. According to some embodiments, if the ZVD device 108 misses the zero crossing and does not turn on the switch device 106b at the end of T_w2, the ZVD device 108 and / or the control system 112 force the switch device 106b to turn on so that the operation of the inverter branch 102 is not interrupted. In addition, since T_w2 is defined to end at a low voltage, the turn-on loss is limited. In some embodiments, the ZVD device 108 can define a time window during the voltage transition to ensure a low turn-on voltage and enable the ZVD device 108 to limit the turn-on loss. In other embodiments, the control system 112 can define a time window during the voltage transition.

[0080] Figure 7 A flow chart of a method 400 is shown according to some embodiments.

[0081] At 402, the method 400 includes obtaining as input a first voltage applied to the switching device 106. In addition, the ZVD device 108 can be electrically connected to the inverter branch 102 and / or the switching device 106. In some embodiments, the ZVD device 108 can be electrically connected to the inverter branch 102 at a cathode of the switching device 106. In some embodiments, the ZVD device 108 can also control a cycling operation of the switching device 106 based on the measured first voltage.

[0082] In some embodiments, the method 400 includes damping the first voltage to reduce EMI and electromagnetic noise in the ZVD device 108 and reducing turn-on losses at the ZVD device. In some embodiments, the ZVD device 108 can obtain the first voltage from the inverter branch 102 and can damp the voltage to reduce EMI and noise in the first voltage. In some embodiments, the ZVD device can include a damping circuit 120, the damping circuit 120 including a damping resistor 122 to reduce EMI and electromagnetic noise in the first voltage. In some embodiments, the damping circuit 120 can be located between the inverter branch 102 and the voltage divider 114. The damping circuit 120 damps the first voltage before it passes through the voltage divider 114 in the ZVD device 108.

[0083] At 404, the method 400 includes scaling down the first voltage to the second voltage within the time delay. In some embodiments, the ZVD device 108 may include a voltage divider 114. In addition, the voltage divider 114 may include a resistor divider 124. The resistor divider 124 may include one or more resistors 128 connected in series with other resistors 128. In other embodiments, the voltage divider 114 may also include a capacitive divider 126. The capacitive divider 126 may include one or more capacitors 130 connected in series with other capacitors 130. In some embodiments, the voltage divider 114 may include a resistor divider 124 connected in parallel with the capacitive divider 126, wherein the one or more resistors 128 are connected in series, the one or more capacitors 130 are connected in series, and each resistor 128 is connected in parallel to a capacitor 130 in the one or more capacitors 130.

[0084] Scaling the first voltage down to the second voltage may also include outputting the second voltage having a voltage ratio that may be substantially equal to 1 through the voltage divider 114, thereby reducing parasitic capacitance in the ZVD device 108. In addition, the capacitive voltage divider 126 may be configured such that the capacitance is higher than any parasitic capacitance at the ZVD device 108 and / or the voltage divider 114. In some embodiments, scaling the first voltage down to the second voltage by the voltage divider 114 also includes outputting the second voltage so as not to exceed a maximum voltage tolerance of the comparator 116.

[0085] At 406, method 400 includes comparing the second voltage to one or more voltage thresholds and generating an estimated first set of signals (ZVD signals) indicating the moment when the first voltage is close to zero voltage as output. The estimation is based on comparing the second voltage to one or more voltage thresholds. In some embodiments, comparing the second voltage to one or more voltage thresholds and generating a first set of signals as output includes comparing the second voltage to a first voltage threshold and generating a first signal as output, and comparing the second voltage to a second voltage threshold and generating a second signal as output. The one or more voltage thresholds include a first voltage threshold and a second voltage threshold, and the second set of signals output by the ZVD device is determined based on the first signal and the second signal.

[0086] In some embodiments, the ZVD device includes a comparator 116 that compares the second voltage to one or more voltage thresholds, e.g. Figure 4 The comparator circuit 116 is shown. In some embodiments, the comparator may include a comparator 132 that compares the second voltage with the first voltage threshold and generates a first signal as an output, and may include a comparator 134 that compares the second voltage with the second voltage threshold and generates a second signal as an output. In some embodiments, the method 400 may include determining a first voltage threshold and a second voltage threshold based on the low level input voltage 136, wherein the first voltage threshold and the second voltage threshold are set based on the low power supply voltage 136 and are configured to take into account the time delay introduced by the voltage divider 114 to scale down the first voltage to the second voltage, so that the ZVD device 108 reduces the turn-on loss at the switching device 106.

[0087] Based on the comparison, each of the comparators 132 and 134 outputs a first set of signals (e.g., ZVD signals) corresponding to a true value (e.g., 1) or a false value (e.g., 0) based on the corresponding comparison. For example, the comparator 132 outputs a value of 1, and the comparator 134 outputs a value of 0, indicating that the second voltage is greater than the first voltage threshold and the second voltage threshold. In another example, when the first voltage approaches zero, the second voltage may drop below the first voltage threshold and the second voltage threshold, and the comparator 132 outputs a value of 0 and the comparator 134 outputs a value of 1, and the first set of signals output by the comparator circuit 116 thereby indicates the moment when the first voltage approaches zero voltage based on the second voltage.

[0088] The value of one or more voltage thresholds may correspond to an optimized voltage threshold determined based on an expected voltage threshold (which is used when the first voltage is expected to reach zero voltage moment), while compensating for the time delay caused by scaling down the voltage. In some embodiments, comparing the second voltage to the one or more voltage thresholds also includes determining one or more voltage thresholds to compensate for the time delay caused by the voltage divider 114 scaling down the first voltage to the second voltage. In some embodiments, the optimized voltage threshold may be a predefined value. In other embodiments, the control system 112 may define one or more voltage thresholds based on the expected voltage threshold. In other embodiments, the ZVD device 108 may be configured with one or more voltage thresholds as inputs so that when the second voltage reaches one or more voltage thresholds instead of the expected zero volt moment, the ZVD device 108 triggers the switch device 106 to cycle on / off.

[0089] At 408, method 400 includes generating a second set of signals as outputs based on the first set of signals to cycle the switching device 106 on / off. In some embodiments, the second set of signals may be gate control signals to cycle the switching device 106 on / off based on the first set of signals and the time when the first voltage approaches zero volts. For example, in some embodiments, the second set of signals may be on signals to cycle the switching device 106 on based on the time when the first voltage approaches zero voltage.

[0090] In some embodiments, the ZVD device 108 may include a trigger circuit 118, such as Figure 4 The flip-flop circuit 118 shown. The flip-flop circuit 118 may include a logic gate device 140 and a logic gate device 142. In addition, the flip-flop circuit 118 may be connected to the output of the comparator circuit 116 to obtain the first set of signals as input. In some embodiments, the output of the comparator 132 may be connected to the logic gate device 140 as an input, and the output of the comparator 134 may be connected to the logic gate device 142 as an input. In addition, the output of the logic gate device 140 corresponds to the output of the ZVD device 108, and the output of the logic gate device 140 may also be connected to the input of the logic gate device 142, and the output of the logic gate device 142 is connected to the input of the logic gate device 140.

[0091] According to some embodiments, the flip-flop circuit 118 obtains a first set of signals from the comparator circuit 116 and provides a second set of signals as outputs based on the inputs. In some embodiments, the logic gate device 140 obtains the first ZVD signal from the comparator 132, and the logic gate device 142 obtains the second ZVD signal from the comparator 134, and the method 400 includes the logic gate device 140 outputting the second set of signals (e.g., gate signals) to cycle the switching device 106 on / off. In some implementations, the flip-flop 118 can be an SR flip-flop circuit that turns the switching device 106 on / off based on the ZVD signal obtained as an input from the comparator 116.

[0092] In some embodiments, generating the second set of signals as outputs based on the first set of signals to cycle the on / off of the switch device 106 further includes: obtaining the first signal as input by the logic gate device 140 and obtaining the second signal as input by the logic gate device 142. In addition, in some embodiments, generating the second set of signals further includes: obtaining the second set of signals as outputs from the logic gate device 140, and controlling the on / off cycle of the switch device 106 based on the second set of signals.

[0093] In some embodiments, generating the second set of signals includes: the logic gate device 140 provides a first gate control signal as an output to cycle the switch device 106 from the first state to the second state in response to the second voltage being greater than the first voltage threshold and the second voltage threshold, and provides a second gate signal as an output to cycle the switch device 106 from the second state to the first state in response to the second voltage being less than the first voltage threshold or the second voltage threshold. In some embodiments, the second voltage being less than the first voltage threshold and the second voltage threshold may cause the ZVD device 108 to output the second set of signals to cycle the switch device 106 on, and the second voltage being greater than the first voltage threshold and the second voltage threshold may cause the ZVD device 108 to output the second set of signals to cycle the switch device 106 off. In other embodiments, the second voltage being greater than the first voltage threshold and the second voltage threshold may cause the ZVD device 108 to output the second set of signals to cycle the switch device on, and the second voltage being less than the first voltage threshold and the second voltage threshold may cause the ZVD device 108 to output the second set of signals to cycle the switch device 106 off.

[0094] At 410, the method 400 includes forcing the switching device 106 to turn on if the second set of signals is not detected at the end of the defined time window to limit turn-on losses. In some embodiments, the method 400 may include defining a time window when the second set of signals for cycling the switching device 106 on is configured to be detected from the ZVD device 108. In this regard, in some embodiments, the method 400 may include cycling the switching device 106 on by the control system 112 to limit turn-on losses and enable the inverter branch 102 to continue to operate without interruption if the second set of signals configured to turn the switching device 106 on is not detected at the end of the defined time window.

[0095] All prior patents and publications cited herein are incorporated by reference in their entirety.

[0096] Throughout the specification and claims, unless the context clearly dictates otherwise, the following terms have the meanings explicitly associated herein. The phrases "in one embodiment," "in an embodiment," and "in some embodiments" used herein do not necessarily refer to the same (multiple) embodiment, although it may refer to the same (multiple) embodiment. In addition, the phrases "in another embodiment" and "in some other embodiments" used herein do not necessarily refer to different embodiments, although it may refer to different embodiments. All embodiments of the present disclosure are intended to be combined without departing from the scope or spirit of the present disclosure.

[0097] As used herein, the term "based on" is not exclusive and allows for being based on other factors not described unless the context clearly dictates otherwise. In addition, throughout the specification, the meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on"

[0098] As used herein, the term "between" does not necessarily need to be directly disposed next to other elements. Generally speaking, this term refers to a configuration in which something is sandwiched between two or more other things. At the same time, the term "between" can describe something that is directly next to two opposing things. Therefore, in any one or more of the embodiments disclosed herein, a particular structural component disposed between two other structural elements may be:

[0099] being disposed directly between two other structural elements so that the particular structural component is in direct contact with the two other structural elements;

[0100] being disposed directly adjacent to only one of the two other structural elements such that the particular structural component is in direct contact with only one of the two other structural elements;

[0101] indirectly disposed beside only one of the two other structural elements, such that the particular structural component is not in direct contact with only one of the two other structural elements, and there is another element juxtaposing the particular structural component and one of the two other structural elements;

[0102] indirectly disposed between two other structural elements, such that a particular structural component is not in direct contact with the two other structural elements, and other features may be disposed between them; or

[0103] Any combination thereof.

[0104] As used herein, "embedded" means that a first material is distributed in a second material.

[0105] All aspects

[0106] Various aspects are described below. It should be understood that any one or more of the features recited in the following (multiple) aspects may be combined with any one or more (multiple) other aspects.

[0107] Aspect 1. A device for performing zero voltage detection (ZVD), comprising:

[0108] Voltage divider,

[0109] wherein the voltage divider is configured to scale down the first voltage to a second voltage;

[0110] Comparator,

[0111] wherein the comparator compares the second voltage to one or more voltage thresholds and outputs a first set of signals indicative of an estimate of a time when the first voltage is close to zero voltage, the one or more voltage thresholds being configured to compensate for a time delay from the voltage divider;

[0112] trigger,

[0113] wherein the trigger is configured to acquire the first group of signals and output a second group of signals to control the switching operation of the switching device; and

[0114] Control systems,

[0115] The control system is configured to acquire the second set of signals during a defined time window, and if the second set of signals is not detected, the control system forces the switching device to turn on at the end of the defined time window to limit turn-on losses.

[0116] Aspect 2. The device according to aspect 1, wherein the voltage divider comprises:

[0117] Resistor voltage divider, including:

[0118] one or more resistors connected in series, and

[0119] Capacitive voltage divider, including:

[0120] One or more capacitors connected in series,

[0121] Each of the one or more capacitors is connected in parallel with each of the one or more resistors.

[0122] Aspect 3. The device according to aspect 2,

[0123] wherein the resistor divider defines the second voltage during steady-state operation,

[0124] wherein the capacitive voltage divider defines the second voltage during a voltage transition, and

[0125] The voltage ratio of the resistor voltage divider is substantially equal to the voltage ratio of the capacitor voltage divider.

[0126] Aspect 4. The device according to any one of the preceding aspects further comprises:

[0127] Damping resistor,

[0128] The damping resistor is configured to reduce electromagnetic noise at the device to reduce turn-on losses.

[0129] Aspect 5. The device according to any one of the preceding aspects, wherein the one or more voltage thresholds include:

[0130] a first voltage threshold, and

[0131] A second voltage threshold.

[0132] Aspect 6. The apparatus according to aspect 5, wherein the comparator comprises:

[0133] The first comparator,

[0134] wherein the first comparator generates a first signal as an output based on a comparison between the second voltage and the first voltage threshold, and

[0135] The second comparator,

[0136] wherein the second comparator generates a second signal as an output based on a comparison between the second voltage and the second voltage threshold,

[0137] The first set of signals includes the first signal and the second signal and represents an estimate of the zero volt instant.

[0138] Aspect 7. The device according to any one of the preceding aspects, wherein the trigger comprises:

[0139] a first logic gate device, and

[0140] The second logic gate device,

[0141] Wherein the output of the first logic gate device and the output of the second logic gate device are connected to the input of the other of the first logic gate device and the second logic gate device.

[0142] Aspect 8. The device according to any one of the preceding aspects, wherein the control system acquires the second set of signals and controls the on / off cycle of the switching device.

[0143] Aspect 9. The apparatus according to any one of the preceding aspects, wherein the first set of signals is not affected by electrical noise in the second voltage.

[0144] Aspect 10. A system comprising:

[0145] one or more switching devices;

[0146] A ZVD device, associated with each switching device and comprising:

[0147] Voltage divider, including:

[0148] Resistor voltage divider, including:

[0149] one or more resistors connected in series, and

[0150] Capacitive voltage divider, including:

[0151] One or more capacitors connected in series,

[0152] wherein the voltage divider scales down the first voltage to a second voltage, the comparator,

[0153] wherein the comparator compares the second voltage to one or more voltage thresholds determined based on an expected zero voltage instant, and the comparator outputs a first set of signals indicative of an estimate of the instant at which the second voltage approaches zero voltage to compensate for a time delay from the voltage divider; and

[0154] trigger,

[0155] wherein the trigger acquires the first group of signals and outputs a second group of signals to control the switching operation of the corresponding switching device; and

[0156] Control systems,

[0157] The control system is configured to acquire the second set of signals during a defined time window, and if the second set of signals is not detected, the control system forces the switching device to turn on at the end of the defined time window to limit turn-on losses.

[0158] Aspect 11. The system according to aspect 10, further comprising:

[0159] Damping resistor,

[0160] The damping resistor is configured to reduce electromagnetic noise at the device to reduce turn-on losses.

[0161] Aspect 12. The system according to aspect 10 or 11,

[0162] wherein each of the one or more capacitors is connected in parallel with each of the one or more resistors,

[0163] wherein the resistor divider defines the second voltage during steady state operation and the capacitor divider defines the second voltage during voltage transitions, and a voltage ratio of the resistor divider is substantially equal to a voltage ratio of the capacitor divider.

[0164] Aspect 13. The system according to aspect 10, 11 or 12, wherein the comparator comprises:

[0165] The first comparator,

[0166] wherein the first comparator compares the second voltage with a first voltage threshold and generates as output a first ZVD signal representing an estimate of the zero voltage instant of the second voltage, and

[0167] The second comparator,

[0168] wherein the second comparator compares the second voltage with a second voltage threshold and generates as output a second ZVD signal representing an estimate of the zero voltage instant of the second voltage,

[0169] The one or more voltage thresholds include the first voltage threshold and the second voltage threshold.

[0170] Aspect 14. The system according to aspect 10, 11, 12 or 13, wherein the trigger comprises:

[0171] The first logic gate device,

[0172] a second logic gate device, and

[0173] wherein the outputs of the first logic gate device and the second logic gate device are connected as inputs to the input of the other of the first logic gate device and the second logic gate device,

[0174] The second set of signals is configured to cycle the on / off switching of the switching device based on the first set of signals.

[0175] Aspect 15. The system according to aspect 10, 11, 12, 13 or 14, wherein the control system acquires the second set of signals and controls the on / off cycle of the switching device.

[0176] Aspect 16. The system of aspect 10, 11, 12, 13, 14 or 15, wherein the first set of signals is not affected by electrical noise in the second voltage.

[0177] Aspect 17. A method comprising:

[0178] obtaining a first voltage applied to the switching device as an input through a zero voltage detection (ZVD) device;

[0179] scaling down the first voltage to a second voltage within a time delay by the ZVD device;

[0180] comparing, by the ZVD device, the second voltage to one or more voltage thresholds and generating as output a first set of signals indicative of an estimate of when the first voltage approaches zero volts;

[0181] generating, by the ZVD device, a second set of signals as outputs based on the first set of signals to cycle the switching device on / off; and

[0182] If the second set of signals is not detected at the end of the defined time window, forcing the switching device to turn on by the ZVD device to limit turn-on losses;

[0183] Wherein the one or more voltage thresholds are configured to compensate for the time delay.

[0184] Aspect 18. The method according to aspect 17 further includes:

[0185] The first voltage is damped by the ZVD device to reduce electromagnetic noise in the first voltage and reduce turn-on losses at the ZVD device.

[0186] Aspect 19. The method according to aspect 17 or 18, wherein comparing the second voltage to the one or more voltage thresholds and generating the first set of signals as output further comprises:

[0187] comparing the second voltage with a first voltage threshold by a first comparator and generating a first signal as an output,

[0188] comparing the second voltage with a second voltage threshold by a second comparator and generating a second signal as an output, and

[0189] wherein the one or more voltage thresholds include the first voltage threshold and the second voltage threshold,

[0190] The second set of signals output by the ZVD device is based on the first signal and the second signal.

[0191] Aspect 20. The method according to aspect 19, wherein generating the second set of signals as outputs to cycle the switching device on / off based on the first set of signals further comprises:

[0192] obtaining the first signal as input at a first logic gate device,

[0193] obtaining the second signal as input at a second logic gate device, and

[0194] acquiring the second group of signals as outputs from the first logic gate device through a control system, and controlling the on / off cycle of the switch device based on the second group of signals,

[0195] The output of the first logic gate device further includes another input to the second logic gate device, and the output of the second logic gate device further includes another input to the first logic gate device.

[0196] It should be understood that changes in detail, especially in the materials of construction employed and the shapes, sizes and arrangements of parts may be made without departing from the scope of the present disclosure. The specification and described embodiments are examples, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A device for performing zero voltage detection ZVD, comprising: Voltage divider, wherein the voltage divider is configured to scale down the first voltage to a second voltage; Comparator, wherein the comparator compares the second voltage to one or more voltage thresholds and outputs a first set of signals, the first set of signals indicating an estimate of a time when the first voltage is close to zero voltage, the one or more voltage thresholds being configured to compensate for a time delay from the voltage divider; trigger, wherein the trigger is configured to acquire the first group of signals and output a second group of signals to control the switching operation of the switching device; as well as Control systems, The control system is configured to acquire the second set of signals during a defined time window, and if the second set of signals is not detected, the control system forces the switching device to turn on at the end of the defined time window to limit turn-on losses.

2. The apparatus of claim 1 , wherein the voltage divider comprises: Resistor voltage divider, including: one or more resistors connected in series, and Capacitive voltage divider, including: One or more capacitors connected in series, Each of the one or more capacitors is connected in parallel with each of the one or more resistors.

3. The device according to claim 2, wherein the resistor divider defines the second voltage during steady-state operation, wherein the capacitive voltage divider defines the second voltage during a voltage transition, and The voltage ratio of the resistor voltage divider is substantially equal to the voltage ratio of the capacitor voltage divider.

4. The apparatus according to claim 1, further comprising: Damping resistor, The damping resistor is configured to reduce electromagnetic noise at the device to reduce turn-on losses.

5. The apparatus of claim 1 , wherein the one or more voltage thresholds include: a first voltage threshold, and The second voltage threshold.

6. The apparatus of claim 5, wherein the comparator comprises: The first comparator, wherein the first comparator generates a first signal as an output based on a comparison between the second voltage and the first voltage threshold, and The second comparator, wherein the second comparator generates a second signal as an output based on a comparison between the second voltage and the second voltage threshold, The first group of signals includes the first signal and the second signal and represents an estimation of the zero voltage instant.

7. The apparatus of claim 1, wherein the trigger comprises: a first logic gate device, and The second logic gate device, The output of the first logic gate device and the output of the second logic gate device are each connected to the input of the other of the first logic gate device and the second logic gate device.

8. The apparatus according to claim 1, wherein the control system acquires the second group of signals and controls the on / off cycle of the switching device.

9. The apparatus of claim 1, wherein the first set of signals is not affected by electrical noise in the second voltage.

10. A system comprising: one or more switching devices; One or more ZVD devices, each ZVD device being associated with a switching device and comprising: Voltage divider, including: Resistor voltage divider, including: one or more resistors connected in series, and Capacitive voltage divider, including: One or more capacitors connected in series, wherein the voltage divider scales down the first voltage to a second voltage, Comparator, wherein the comparator compares the second voltage to one or more voltage thresholds determined based on an expected zero voltage instant, and the comparator outputs a first set of signals to compensate for a time delay from the voltage divider, the first set of signals indicating an estimate of an instant when the second voltage is close to zero voltage; and trigger, wherein the trigger acquires the first group of signals and outputs a second group of signals to control the switching operation of the switching device; and Control systems, The control system is configured to acquire the second set of signals during a defined time window, and if the second set of signals is not detected, the control system forces the switching device to turn on at the end of the defined time window to limit turn-on losses.

11. The system according to claim 10, further comprising: Damping resistor, The damping resistor is configured to reduce electromagnetic noise at the ZVD device to reduce turn-on loss.

12. The system according to claim 10, wherein each of the one or more capacitors is connected in parallel with each of the one or more resistors, wherein the resistor divider defines the second voltage during steady state operation and the capacitor divider defines the second voltage during voltage transitions, and a voltage ratio of the resistor divider is substantially equal to a voltage ratio of the capacitor divider.

13. The system of claim 10, wherein the comparator comprises: The first comparator, wherein the first comparator compares the second voltage with a first voltage threshold and generates as output a first ZVD signal representing an estimate of the zero voltage instant of the second voltage, and The second comparator, wherein the second comparator compares the second voltage with a second voltage threshold and generates as output a second ZVD signal representing an estimate of the zero voltage instant of the second voltage, The one or more voltage thresholds include the first voltage threshold and the second voltage threshold.

14. The system of claim 10, wherein the trigger comprises: a first logic gate device, and The second logic gate device, wherein the outputs of the first logic gate device and the second logic gate device are connected as inputs to the input of the other of the first logic gate device and the second logic gate device, The second set of signals is configured to cycle the on / off switching of the switching device based on the first set of signals.

15. The system of claim 10, wherein the control system acquires the second set of signals and controls the on / off cycling of the switching device.

16. The system of claim 10, wherein the first set of signals is not affected by electrical noise in the second voltage.

17. A method comprising: Obtaining a first voltage applied to the switching device as input through a zero voltage detection ZVD device; scaling down the first voltage to a second voltage within a time delay by the ZVD device; comparing, by the ZVD device, the second voltage to one or more voltage thresholds and generating as output a first set of signals, the first set of signals indicating an estimate of when the first voltage is close to zero volts; generating, by the ZVD device, a second set of signals as outputs based on the first set of signals to cycle the switching device on / off; as well as If the second set of signals is not detected at the end of the defined time window, forcing the switching device to turn on by the ZVD device to limit turn-on losses; Wherein the one or more voltage thresholds are configured to compensate for the time delay.

18. The method according to claim 17, further comprising: The first voltage is damped by the ZVD device to reduce electromagnetic noise in the first voltage and reduce turn-on losses at the ZVD device.

19. The method of claim 17, wherein comparing the second voltage to the one or more voltage thresholds and generating the first set of signals as output further comprises: comparing the second voltage with a first voltage threshold by a first comparator and generating a first signal as an output, and comparing the second voltage with a second voltage threshold by a second comparator and generating a second signal as an output, wherein the one or more voltage thresholds include the first voltage threshold and the second voltage threshold, The second set of signals output by the ZVD device is based on the first signal and the second signal.

20. The method of claim 19, wherein generating the second set of signals as outputs to cycle the switching device on / off based on the first set of signals further comprises: obtaining the first signal as input at a first logic gate device, obtaining the second signal as input at a second logic gate device, and acquiring the second group of signals as outputs from the first logic gate device through a control system, and controlling the on / off cycle of the switch device based on the second group of signals, The output of the first logic gate device also includes another input to the second logic gate device, and the output of the second logic gate device includes another input to the first logic gate device.

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