Intelligent power module driving device

Abstract

The invention relates to the technical field of intelligent power modules, in particular to an intelligent power module driving device. Comprising a power chip; the first driving electrode of the driving chip is connected with the gate electrode of the power chip, and the second driving electrode of the driving chip is connected with the emitting electrode of the power chip; the wireless signal receiving part is used for collecting a wireless signal to obtain an original driving signal; the Schmidt trigger filtering part is used for performing waveform conversion on the original driving signal and outputting an initial square wave signal; the logic level conversion part is used for carrying out edge switching on the trigger signal and outputting a square wave signal; the driving part is used for converting the square wave signal into a driving signal and outputting the driving signal to a gate pole of the power chip; according to the invention, the transmission of the wireless driving signal is realized through the wireless signal receiving part, and the problems in the prior art that the bonding wires for transmitting the driving signal are more, the wires are easy to collapse and break, the module is easy to scrap and the like are solved.

Description

Technical Field

[0001] The present invention relates to the technical field of intelligent power modules, and in particular to an intelligent power module driving device. Background Art

[0002] Intelligent Power Module (IPM) is a power drive product that combines power electronics and integrated circuit technology. It is mainly composed of IGBT chips, diode chips and driver ICs. The driver chip generally integrates protection circuits to control undervoltage protection, over-temperature protection and over-current protection.

[0003] The application of IPM is generally to solder the PIN (pin) of the module to the PCB board, and the MCU transmits the signal to the driver chip inside the module through the line to control the switch of the module. The driver chip is generally soldered on the frame, and the PAD (pin pad) and PIN are connected with a wire to obtain the signal received by the PIN. The driver chip and IGBT also need to be bonded to transmit the voltage to the IGBT to control the switch of the IGBT.

[0004] The existing IPM needs to connect the module pins, driver chips and IGBT chips through bonding wires. Since the driver chip has more functions, more wires need to be bonded. On average, a driver IC with integrated protection circuit requires 12 wires, which makes the process complicated, time-consuming and labor-intensive. Using wires with lower hardness is prone to wire collapse and breakage in subsequent process links, while using wires with higher hardness is easy to damage the chip. As long as there is a problem with one bonding wire, the entire module will be scrapped, which has a great impact on the production yield and is also prone to hidden problems when customers use it. Summary of the invention

[0005] The purpose of the present invention is to provide an intelligent power module driving device to solve the above technical problems;

[0006] The technical problem solved by the present invention can be achieved by adopting the following technical solutions:

[0007] An intelligent power module driving device, comprising:

[0008] Power chip;

[0009] A driving chip, wherein a first driving electrode of the driving chip is connected to a gate electrode of the power chip, and a second driving electrode of the driving chip is connected to an emitter electrode of the power chip, and the driving chip comprises:

[0010] A wireless signal receiving unit, used for collecting wireless signals to obtain original driving signals;

[0011] A Schmitt trigger filter unit, connected to the wireless signal receiving unit, for performing waveform conversion on the original driving signal and outputting a preliminary square wave signal;

[0012] A logic level conversion unit, connected to the Schmitt trigger filter unit, for edge switching the trigger signal and outputting a square wave signal;

[0013] A driving unit, connected to the logic level conversion unit, configured to convert the square wave signal into a driving signal and output it to the gate of the power chip;

[0014] An overcurrent protection unit, wherein the input side of the overcurrent protection unit is connected to the emitter current of the power chip, and the output side of the overcurrent protection unit is connected to the logic level conversion unit, and is used to output a protection signal for controlling the power chip to shut down according to the emitter current of the power chip.

[0015] Preferably, the power chip is connected to the copper sheet by solder paste, the driving pole of the driving chip is printed with bumps, and the driving chip is mounted on the power chip in an inverted manner;

[0016] The driving chip is integrated with an on-chip antenna, and the wireless signal is received via the on-chip antenna.

[0017] Preferably, the wireless signal receiving unit includes:

[0018] A first capacitor, wherein a first end of the first capacitor is connected to the wireless signal, and a second end of the first capacitor is grounded;

[0019] a first inductor, wherein a first end of the first inductor is connected to a first end of the first capacitor, and a second end of the first inductor is connected to a second end of the first capacitor;

[0020] a first resistor, wherein a first end of the first resistor is connected to the wireless signal, and a second end of the first resistor is grounded;

[0021] a second resistor, a first end of the second resistor being connected to the wireless signal;

[0022] a second capacitor, wherein a first end of the second capacitor is connected to a second end of the second resistor;

[0023] a third capacitor, wherein a first end of the third capacitor is connected to the second end of the second capacitor, and a second end of the third capacitor is grounded;

[0024] a third resistor, wherein a first end of the third resistor is connected to a second end of the second resistor, and a second end of the third resistor is connected to a first end of the third capacitor;

[0025] a first diode, wherein an anode of the first diode is connected to a second end of the second resistor;

[0026] a fourth capacitor, wherein a first end of the fourth capacitor is connected to the cathode of the first diode, and a second end of the fourth capacitor is connected to the second end of the third capacitor;

[0027] a first transistor, wherein the base of the first transistor is connected to the cathode of the first diode, and the collector of the first transistor serves as the output of the wireless signal receiving unit;

[0028] a fourth resistor, wherein a first end of the fourth resistor is connected to the base of the first transistor, and a second end of the fourth resistor is connected to the collector of the first transistor;

[0029] a fifth resistor, wherein a first end of the fifth resistor is connected to the emitter of the first transistor, and a second end of the fifth resistor is grounded;

[0030] A fifth capacitor, wherein a first end of the fifth capacitor is connected to the emitter of the first transistor, and a second end of the fifth capacitor is connected to the second end of the fifth resistor.

[0031] Preferably, the wireless signal receiving unit further includes:

[0032] a sixth resistor, a first end of the sixth resistor being connected to the collector of the first transistor;

[0033] a seventh resistor, wherein a first end of the seventh resistor is connected to the base of the first transistor, and a second end of the seventh resistor is connected to the second end of the fifth resistor;

[0034] a second diode, wherein a cathode of the second diode is connected to a second end of the sixth resistor;

[0035] a third diode, wherein a cathode of the third diode is connected to an anode of the second diode, and an anode of the third diode is grounded;

[0036] a fourth diode, wherein a cathode of the fourth diode is connected to the second end of the sixth resistor;

[0037] a fifth diode, wherein a cathode of the fifth diode is connected to an anode of the fourth diode, and an anode of the fifth diode is connected to an anode of the third diode;

[0038] a sixth capacitor, wherein a first end of the sixth capacitor is connected to an anode of the second diode;

[0039] A coil, a first end of the coil is connected to the second end of the sixth capacitor, a second end of the coil is connected to the anode of the fourth diode, and the coil is used to output a supply voltage.

[0040] Preferably, the Schmitt trigger filter unit includes:

[0041] A second transistor, wherein the base of the second transistor is connected to the output end of the wireless signal receiving unit;

[0042] an eighth resistor, wherein a first end of the eighth resistor is connected to the collector of the second transistor, and a second end of the eighth resistor is connected to a positive potential signal;

[0043] a ninth resistor, wherein a first end of the ninth resistor is connected to the emitter of the second transistor, and a second end of the ninth resistor is grounded;

[0044] a tenth resistor, a first end of the tenth resistor being connected to the collector of the second transistor;

[0045] an eleventh resistor, a first end of the eleventh resistor being connected to the second end of the tenth resistor, and a second end of the eleventh resistor being grounded;

[0046] a third triode, wherein the base of the third triode is connected to the second end of the tenth resistor, and the emitter of the third triode is connected to the emitter of the second triode;

[0047] A twelfth resistor, wherein a first end of the twelfth resistor is connected to the collector of the third transistor, and a second end of the twelfth resistor is connected to the positive potential signal.

[0048] Preferably, the Schmitt trigger filter unit further includes:

[0049] a thirteenth resistor, a first end of the thirteenth resistor being connected to the collector of the third transistor;

[0050] a first MOS transistor, wherein the drain of the first MOS transistor is connected to the second end of the thirteenth resistor, the source of the first MOS transistor is connected to a first power supply voltage, and the gate of the first MOS transistor is the output end of the Schmitt trigger filter unit, outputting the preliminary square wave signal;

[0051] a second MOS transistor, wherein a drain of the second MOS transistor is connected to the second end of the thirteenth resistor, a source of the second MOS transistor is grounded, and a gate of the second MOS transistor is connected to the gate of the first MOS transistor;

[0052] a third MOS tube, wherein a gate of the third MOS tube is connected to the second end of the thirteenth resistor, a drain of the third MOS tube is connected to the gate of the first MOS tube, and a source of the third MOS tube is connected to the first power supply voltage;

[0053] a fourth MOS tube, wherein a gate of the fourth MOS tube is connected to the second end of the thirteenth resistor, a source of the fourth MOS tube is connected to the source of the second MOS tube, and a drain of the fourth MOS tube is connected to the gate of the second MOS tube.

[0054] Preferably, the logic level conversion unit includes:

[0055] a fourteenth resistor, a first end of the fourteenth resistor being connected to the output end of the Schmitt trigger filter unit;

[0056] A first comparator, wherein a first input terminal of the first comparator is connected to the second end of the fourteenth resistor, and a second input terminal of the first comparator is connected to a reference signal;

[0057] An edge trigger, wherein an input end of the edge trigger is connected to an output end of the first comparator;

[0058] An AND gate, wherein the first input end of the AND gate is connected to the output end of the edge trigger, the second output end of the AND gate is connected to the protection signal, and the output end of the AND gate serves as the output end of the logic level conversion unit to output the square wave signal.

[0059] Preferably, the driving unit comprises:

[0060] a fifth MOS transistor, wherein a gate of the fifth MOS transistor is connected to an output end of the logic level conversion unit, and a source of the fifth MOS transistor is connected to a second power supply voltage;

[0061] a sixth MOS tube, wherein a gate of the sixth MOS tube is connected to the gate of the fifth MOS tube, a drain of the sixth MOS tube is connected to the drain of the fifth MOS tube, and a source of the sixth MOS tube is grounded;

[0062] a seventh MOS tube, wherein a source of the seventh MOS tube is connected to the source of the fifth MOS tube, and a gate of the seventh MOS tube is connected to the drain of the fifth MOS tube;

[0063] an eighth MOS tube, wherein a gate of the eighth MOS tube is connected to the gate of the seventh MOS tube, and a source of the eighth MOS tube is connected to the source of the sixth MOS tube;

[0064] A fifteenth resistor, a first end of the fifteenth resistor is connected to the drain of the seventh MOS tube, and a second end of the fifteenth resistor is the output end of the driving unit and is connected to the gate of the power chip to output the driving signal;

[0065] a sixteenth resistor, wherein a first end of the sixteenth resistor is connected to a second end of the fifteenth resistor, and a second end of the sixteenth resistor is connected to a drain of the eighth MOS tube;

[0066] A seventeenth resistor, wherein a first end of the seventeenth resistor is connected to the second end of the fifteenth resistor, and a first end of the seventeenth resistor is connected to the source of the eighth MOS tube.

[0067] Preferably, the overcurrent protection unit includes:

[0068] an eighteenth resistor, a first end of the eighteenth resistor being connected to the emitter of the power chip;

[0069] a nineteenth resistor, a first end of the nineteenth resistor being connected to the second end of the eighteenth resistor;

[0070] a seventh capacitor, wherein a first end of the seventh capacitor is connected to a first end of the nineteenth resistor, and a second end of the seventh capacitor is connected to a second end of the nineteenth resistor;

[0071] a twentieth resistor, a first end of the twentieth resistor being connected to the second end of the eighteenth resistor, and a second end of the twentieth resistor being grounded;

[0072] a second comparator, wherein a first input terminal of the second comparator is connected to a first terminal of the 20th resistor, and a second input terminal of the second comparator is connected to a threshold signal;

[0073] A filter, wherein an input end of the filter is connected to an output end of the second comparator;

[0074] A NOR gate, wherein a first input terminal of the NOR gate is connected to an output terminal of the filter;

[0075] An RS trigger, wherein the S end of the RS trigger is connected to the output end of the filter, the R end of the RS trigger is connected to the output end of the NOR gate, and the output end of the RS trigger is the output end of the overcurrent protection unit to output the protection signal;

[0076] A NOT gate, wherein the input end of the NOT gate is connected to the output end of the RS trigger, and the output end of the NOT gate is connected to the second input end of the NOR gate.

[0077] Preferably, a transparent packaging shell is provided on the outer sides of the power chip and the driver chip.

[0078] Beneficial effects of the present invention: Due to the adoption of the above technical scheme, the present invention realizes the transmission of wireless driving signals through the wireless signal receiving unit, thereby solving the problems in the prior art of having many bonding wires for transmitting driving signals, being prone to wire collapse and breakage, and easily causing the module to be scrapped. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] Figure 1 A logic block diagram of an intelligent power module driving device in an embodiment of the present invention;

[0080] Figure 2 Schematic diagram of the external structure of the intelligent power module in an embodiment of the present invention;

[0081] Figure 3 A schematic diagram of the internal structure of a driver chip in an embodiment of the present invention;

[0082] Figure 4 A circuit diagram of a wireless signal receiving unit in an embodiment of the present invention;

[0083] Figure 5 A circuit diagram of a Schmitt trigger filter unit in an embodiment of the present invention;

[0084] Figure 6 is a circuit diagram of a logic level conversion unit in an embodiment of the present invention;

[0085] Figure 7 is a circuit diagram of a driving unit in an embodiment of the present invention;

[0086] Figure 8 4 is a circuit diagram of an overcurrent protection unit in an embodiment of the present invention. DETAILED DESCRIPTION

[0087] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0088] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0089] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0090] An intelligent power module driving device, such as Figures 1 to 3 As shown, including,

[0091] Power chip 1;

[0092] A driving chip 2, wherein a first driving electrode 27 of the driving chip 2 is connected to a gate electrode of the power chip 1, and a second driving electrode 28 of the driving chip 2 is connected to an emitter electrode of the power chip 1. The driving chip 2 comprises:

[0093] A wireless signal receiving unit 21 is used to collect wireless signals to obtain original driving signals;

[0094] The Schmitt trigger filter unit 22 is connected to the wireless signal receiving unit 21 and is used to perform waveform conversion on the original driving signal and output a preliminary square wave signal;

[0095] The logic level conversion unit 23 is connected to the Schmitt trigger filter unit 22 and is used to perform edge switching on the trigger signal and output a square wave signal;

[0096] The driving unit 24 is connected to the logic level conversion unit 23 and is used to convert the square wave signal into a driving signal and output it to the gate of the power chip 1;

[0097] The overcurrent protection unit 25 has an input side connected to the emitter current of the power chip 1 , and an output side connected to the logic level conversion unit 23 , which is used to output a protection signal for controlling the power chip 1 to shut down according to the emitter current of the power chip 1 .

[0098] Specifically, the present invention proposes an intelligent power module (IPM) driving structure that can be wirelessly activated, including a driving chip 2 and a power chip 1. In the present invention, the power chip 1 is an IGBT chip;

[0099] The present invention realizes the transmission of wireless driving signals through the wireless signal receiving unit 21, thereby solving the problems in the prior art of having many bonding wires for transmitting driving signals, which easily lead to wire collapse and disconnection, and the module being easily scrapped.

[0100] In a preferred embodiment, the power chip 1 is connected to the copper sheet by solder paste, the driving pole of the driving chip 2 is printed with bumps, and the driving chip 2 is mounted on the power chip 1 by facing down;

[0101] An on-chip antenna 26 is integrated on the driver chip 2 , and wireless signals are received via the on-chip antenna 26 .

[0102] Specifically, the power chip 1 of the present invention is soldered to the copper sheet using solder paste as solder.

[0103] The driver chip 2 is mounted on the power chip 1 through flip-chip technology by making bumps on the driver electrode, and is contacted with the gate and emitter of the power chip 1 through reflow soldering with solder. The driver electrode of the driver chip 2 and the overcurrent protection circuit are connected to the gate D2 electrode and the emitter, and the insulating layer of other areas is made of polymer material.

[0104] In addition to the problems of the background technology, the prior art also has the problem of creepage static electricity between pins, especially the spacing between the driving pins is smaller, and the ability to withstand static electricity is also weaker. The driving chip 2 of the present invention integrates an on-chip antenna 26, including a wireless signal receiving circuit, a Schmitt trigger and filtering circuit, a driving circuit, an overcurrent protection circuit, etc., which can effectively solve the problems of many bonding wires, easy collapse and breakage of wires, easy scrapping of modules, and static electricity between driving pins.

[0105] In a preferred embodiment, Figure 4 As shown, the wireless signal receiving unit 21 includes:

[0106] A first capacitor C1, a first end of the first capacitor C1 is connected to the wireless signal, and a second end of the first capacitor C1 is grounded;

[0107] A first inductor L1, wherein a first end of the first inductor L1 is connected to a first end of the first capacitor C1, and a second end of the first inductor L1 is connected to a second end of the first capacitor C1;

[0108] A first resistor R1, a first end of the first resistor R1 is connected to the wireless signal, and a second end of the first resistor R1 is grounded;

[0109] A second resistor R2, a first end of the second resistor R2 is connected to the wireless signal;

[0110] A second capacitor C2, a first end of the second capacitor C2 is connected to a second end of the second resistor R2;

[0111] A third capacitor C3, a first end of the third capacitor C3 is connected to the second end of the second capacitor C2, and a second end of the third capacitor C3 is grounded;

[0112] a third resistor R3, wherein a first end of the third resistor R3 is connected to a second end of the second resistor R2, and a second end of the third resistor R3 is connected to a first end of a third capacitor C3;

[0113] A first diode D1, wherein an anode of the first diode D1 is connected to a second end of a second resistor R2;

[0114] a fourth capacitor C4, wherein a first end of the fourth capacitor C4 is connected to the cathode of the first diode D1, and a second end of the fourth capacitor C4 is connected to the second end of the third capacitor C3;

[0115] A first transistor T1, wherein the base of the first transistor T1 is connected to the cathode of the first diode D1, and the collector of the first transistor T1 serves as the output of the wireless signal receiving unit 21;

[0116] a fourth resistor R4, wherein a first end of the fourth resistor R4 is connected to the base of the first transistor T1, and a second end of the fourth resistor R4 is connected to the collector of the first transistor T1;

[0117] a fifth resistor R5, wherein a first end of the fifth resistor R5 is connected to the emitter of the first transistor T1, and a second end of the fifth resistor R5 is grounded;

[0118] A fifth capacitor C5 , wherein a first end of the fifth capacitor C5 is connected to the emitter of the first transistor T1 , and a second end of the fifth capacitor C5 is connected to the second end of the fifth resistor R5 .

[0119] In a preferred embodiment, the wireless signal receiving unit 21 further includes:

[0120] a sixth resistor R6, wherein a first end of the sixth resistor R6 is connected to the collector of the first transistor T1;

[0121] a seventh resistor R7, wherein a first end of the seventh resistor R7 is connected to the base of the first transistor T1, and a second end of the seventh resistor R7 is connected to the second end of the fifth resistor R5;

[0122] a second diode D2, wherein a cathode of the second diode D2 is connected to a second end of the sixth resistor R6;

[0123] a third diode D3, wherein a cathode of the third diode D3 is connected to an anode of the second diode D2, and an anode of the third diode D3 is grounded;

[0124] a fourth diode D4, wherein a cathode of the fourth diode D4 is connected to a second end of the sixth resistor R6;

[0125] a fifth diode D5, wherein a cathode of the fifth diode D5 is connected to an anode of the fourth diode D4, and an anode of the fifth diode D5 is connected to an anode of the third diode D3;

[0126] a sixth capacitor C6, wherein a first end of the sixth capacitor C6 is connected to an anode of the second diode D2;

[0127] The coil L2 has a first end connected to the second end of the sixth capacitor C6 , a second end connected to the anode of the fourth diode D4 , and the coil L2 is used to output a supply voltage.

[0128] Specifically, the driver chip 2 of the present invention integrates an on-chip antenna 26, a first capacitor C1 and a first inductor L1 form a resonant circuit, a first resistor R1, a second resistor R2, a third resistor R3, a second capacitor C2 and a third capacitor C3 are connected for impedance matching; a first diode D1 and a fourth capacitor C4 are connected for detection;

[0129] The seventh resistor R7 in the present invention is an adjustable resistor, and low-pass filtering is performed through the fourth resistor R4, the seventh resistor R7, the first transistor T1, the fifth capacitor C5 and the fifth resistor R5;

[0130] In the present invention, the power supply voltage is obtained by magnetic coupling of the coil L2, and the subsequent positive potential signal, the first power supply voltage VDD, the second power supply voltage VCC, the reference signal Ref1, and the threshold signal Ref2 are all generated by voltage conversion of the power supply voltage.

[0131] In a preferred embodiment, Figure 5 As shown, the Schmitt trigger filter unit 22 includes:

[0132] A second transistor T2, the base of which is connected to the output end of the wireless signal receiving unit 21;

[0133] an eighth resistor R8, wherein a first end of the eighth resistor R8 is connected to the collector of the second transistor T2, and a second end of the eighth resistor R8 is connected to a positive potential signal;

[0134] a ninth resistor R9, wherein a first end of the ninth resistor R9 is connected to the emitter of the second transistor T2, and a second end of the ninth resistor R9 is grounded;

[0135] a tenth resistor R10, wherein a first end of the tenth resistor R10 is connected to the collector of the second transistor T2;

[0136] an eleventh resistor R11, a first end of the eleventh resistor R11 is connected to the second end of the tenth resistor R10, and a second end of the eleventh resistor R11 is grounded;

[0137] a third triode T3, wherein the base of the third triode T3 is connected to the second end of the tenth resistor R10, and the emitter of the third triode T3 is connected to the emitter of the second triode T2;

[0138] A twelfth resistor R12 , a first end of the twelfth resistor R12 is connected to the collector of the third transistor T3 , and a second end of the twelfth resistor R12 is connected to the positive potential signal.

[0139] In a preferred embodiment, the Schmitt trigger filter unit 22 further includes:

[0140] A thirteenth resistor R13, a first end of the thirteenth resistor R13 is connected to the collector of the third transistor T3;

[0141] A first MOSFET Q1, a drain of the first MOSFET Q1 is connected to the second end of the thirteenth resistor R13, a source of the first MOSFET Q1 is connected to a first power supply voltage, and a gate of the first MOSFET Q1 is an output end of the Schmitt trigger filter unit 22, outputting a preliminary square wave signal;

[0142] a second MOSFET Q2, wherein the drain of the second MOSFET Q2 is connected to the second end of the thirteenth resistor R13, the source of the second MOSFET Q2 is grounded, and the gate of the second MOSFET Q2 is connected to the gate of the first MOSFET Q1;

[0143] a third MOSFET Q3, wherein a gate of the third MOSFET Q3 is connected to the second end of the thirteenth resistor R13, a drain of the third MOSFET Q3 is connected to the gate of the first MOSFET Q1, and a source of the third MOSFET Q3 is connected to the first power supply voltage;

[0144] The fourth MOSFET Q4 has a gate connected to the second end of the thirteenth resistor R13, a source connected to the source of the second MOSFET Q2, and a drain connected to the gate of the second MOSFET Q2.

[0145] Specifically, the Schmitt trigger filter unit 22 is used to output the original drive signal as a preliminary square wave signal, wherein the waveform of the original drive signal is connected in series with the base of the second transistor T2, and the collector of the second transistor T2 is connected in series with the eighth resistor R8 to the positive potential signal, and the positive potential signal in the present invention is 5V;

[0146] The emitter of the second transistor T2 is connected in series with the ninth resistor R9 to the ground, and the collector of the second transistor T2 is connected in series with the tenth resistor R10 and the eleventh resistor R11 to the ground.

[0147] The tenth resistor R10 and the eleventh resistor R11 are connected to the base of the third transistor T3 , the emitter of the third transistor T3 and the second transistor T2 share an emitter, and the third collector is connected in series with the twelfth resistor R12 to a high potential signal.

[0148] At the same time, the collector of the third triode T3 is connected in series with the thirteenth resistor R13 to the drain of the first MOSFET Q1, the second MOSFET Q2, the gate of the third MOSFET Q3, and the fourth MOSFET Q4. The gates of the first MOSFET Q1 and the second MOSFET Q2 are connected to the drain of the third MOSFET Q3 and the fourth MOSFET Q4. The sources of the first MOSFET Q1 and the third MOSFET Q3 are connected to the first power supply voltage, and the sources of the second MOSFET Q2 and the fourth MOSFET Q4 are grounded. When the input potential exceeds the upper threshold, the collector of the third triode T3 is high; when the input is lower than the lower threshold, the collector of the third triode T3 is low, and the upper and lower thresholds have hysteresis. The high and low levels of the output are shaped and filtered into square waves by the first MOSFET Q1, the second MOSFET Q2, the third MOSFET Q3, and the fourth MOSFET Q4.

[0149] In a preferred embodiment, Figure 6 As shown, the logic level conversion unit 23 includes:

[0150] A fourteenth resistor R14, a first end of the fourteenth resistor R14 is connected to the output end of the Schmitt trigger filter unit 22;

[0151] A first comparator A1, wherein a first input terminal of the first comparator A1 is connected to a second end of a fourteenth resistor R14, and a second input terminal of the first comparator A1 is connected to a reference signal Ref1;

[0152] An edge trigger D1, wherein an input end of the edge trigger D1 is connected to an output end of the first comparator A1;

[0153] AND gate D2, a first input terminal of AND gate D2 is connected to the output terminal of edge trigger D1, a second input terminal of AND gate D2 is connected to the protection signal, and an output terminal of AND gate D2 serves as an output terminal of logic level conversion unit 23 to output a square wave signal.

[0154] Specifically, the logic level conversion unit 23 is an edge-triggered logic conversion circuit, the first end of the fourteenth resistor R14 serves as the first input end of the logic level conversion unit 23 connected to the output end of the Schmitt trigger filter unit 22, and the second input end of the AND gate D2 serves as the second input end of the logic level conversion unit 23 connected to the overcurrent protection unit 25.

[0155] Since there are still noises in the square wave after the Schmitt trigger shaping, a relatively perfect square wave signal is obtained by setting a logic level conversion unit 23, and the fourteenth resistor R14, the first comparator A1 and the set reference signal Ref1 are compared. In order to prevent the chip from being interfered by other components of the circuit during application and to make the driving signal more stable, the signal needs to pass through the edge trigger D1, so that the signal output will only change when the high and low level edges are switched, otherwise the signal maintains the original level. The output of the overcurrent protection circuit and the signal processed by the edge trigger D1 are output to the driving pole circuit after passing through the AND gate D2. If the voltage sampled by the overcurrent protection unit 25 is higher than the reference signal Ref1, a level will be output and a new level will be obtained through the AND gate D2 to control the power chip 1 to turn off.

[0156] In a preferred embodiment, Figure 7 As shown, the driving unit 24 includes:

[0157] a fifth MOSFET Q5, wherein the gate of the fifth MOSFET Q5 is connected to the output end of the logic level conversion unit 23, and the source of the fifth MOSFET Q5 is connected to a second power supply voltage VCC;

[0158] a sixth MOSFET Q6, wherein the gate of the sixth MOSFET Q6 is connected to the gate of the fifth MOSFET Q5, the drain of the sixth MOSFET Q6 is connected to the drain of the fifth MOSFET Q5, and the source of the sixth MOSFET Q6 is grounded;

[0159] A seventh MOSFET Q7, wherein a source of the seventh MOSFET Q7 is connected to a source of the fifth MOSFET Q5, and a gate of the seventh MOSFET Q7 is connected to a drain of the fifth MOSFET Q5;

[0160] an eighth MOSFET Q8, wherein the gate of the eighth MOSFET Q8 is connected to the gate of the seventh MOSFET Q7, and the source of the eighth MOSFET Q8 is connected to the source of the sixth MOSFET Q6;

[0161] A fifteenth resistor R15, a first end of the fifteenth resistor R15 is connected to the drain of the seventh MOS tube Q7, and a second end of the fifteenth resistor R15 is an output end of the driving unit 24 connected to the gate of the power chip 1 to output a driving signal;

[0162] a sixteenth resistor R16, wherein a first end of the sixteenth resistor R16 is connected to a second end of the fifteenth resistor R15, and a second end of the sixteenth resistor R16 is connected to a drain of the eighth MOS tube Q8;

[0163] The seventeenth resistor R17 has a first end connected to the second end of the fifteenth resistor R15 and a first end connected to the source of the eighth MOSFET Q8.

[0164] Specifically, further, the circuit of the driving unit 24 is located in the driving chip 2 and includes a driving electrode, the input square wave signal is connected to the gates of the fifth MOS tube Q5 and the sixth MOS tube Q6 of the driving unit 24, and the drains of the fifth MOS tube Q5 and the sixth MOS tube Q6 are connected to the gates of the seventh MOS tube Q7 and the eighth MOS tube Q8;

[0165] The sources of the fifth MOSFET Q5 and the seventh MOSFET Q7 are connected to the second power supply voltage VCC, and the sources of the sixth MOSFET Q6 and the eighth MOSFET Q8 are connected to the reference 0 potential;

[0166] The source of the eighth MOSFET Q8 is connected in series with the seventeenth resistor R17 and the fifteenth resistor R15 to the drain of the seventh MOSFET Q7. Meanwhile, the fifteenth resistor R15 and the sixteenth resistor R16 are connected in series with the drain of the eighth MOSFET Q8.

[0167] The circuit output end of the driving unit 24 is connected to the gate of the power chip 1 , and the sources of the sixth MOSFET Q6 and the eighth MOSFET Q8 are connected to the emitter of the power chip 1 .

[0168] In a preferred embodiment, Figure 8 As shown, the overcurrent protection unit 25 includes:

[0169] An eighteenth resistor R18, a first end of the eighteenth resistor R18 is connected to the emitter of the power chip 1;

[0170] a nineteenth resistor R19, wherein a first end of the nineteenth resistor R19 is connected to a second end of the eighteenth resistor R18;

[0171] a seventh capacitor C7, wherein a first end of the seventh capacitor C7 is connected to a first end of a nineteenth resistor R19, and a second end of the seventh capacitor C7 is connected to a second end of the nineteenth resistor R19;

[0172] a twentieth resistor R20, a first end of the twentieth resistor R20 is connected to the second end of the eighteenth resistor R18, and a second end of the twentieth resistor R20 is grounded;

[0173] A second comparator A2, wherein a first input terminal of the second comparator A2 is connected to a first end of a twentieth resistor R20, and a second input terminal of the second comparator A2 is connected to a threshold signal Ref2;

[0174] A filter F1, wherein an input end of the filter F1 is connected to an output end of the second comparator A2;

[0175] A NOR gate D3, wherein a first input terminal of the NOR gate D3 is connected to an output terminal of the filter F1;

[0176] RS trigger D4, the S end of the RS trigger D4 is connected to the output end of the filter F1, the R end of the RS trigger D4 is connected to the output end of the NOR gate D3, and the output end of the RS trigger D4 is the output end of the overcurrent protection unit 25 to output a protection signal;

[0177] The NOT gate D5, the input end of the NOT gate D5 is connected to the output end of the RS trigger D4, and the output end of the NOT gate D5 is connected to the second input end of the NOR gate D3.

[0178] Specifically, the eighteenth resistor R18 of the overcurrent protection unit 25 is a sampling resistor, through which the overcurrent protection unit 25 is connected to the emitter of the power chip 1, and the nineteenth resistor R19 and the seventh capacitor C7 play a filtering function, which is compared with the set threshold signal Ref2 by the second comparator A2, connected in series with the filter F1, and connected to the logic level conversion unit 23 after passing through the NOR gate D3, the NOT gate D5, and the RS trigger D4. If the current is too large and the sampled voltage is greater than the threshold signal Ref2, the power chip 1 is turned off to play a protective role.

[0179] In a preferred embodiment, a transparent packaging shell is provided on the outer sides of the power chip 1 and the driver chip 2 .

[0180] Specifically, the use of a transparent packaging shell can realize the transmission of optical coupling signals, and can also replace the bonding wire signal transmission method of the prior art. At the same time, the use of a transparent packaging shell facilitates the viewing and detection of the working status of the chip in the packaging shell.

[0181] The above description is only a preferred embodiment of the present invention, and does not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. An intelligent power module driving device, characterized in that: include, Power chip (1); A driving chip (2), wherein a first driving electrode (27) of the driving chip (2) is connected to a gate electrode of the power chip (1), and a second driving electrode (28) of the driving chip (2) is connected to an emitter electrode of the power chip (1), and the driving chip (2) comprises: A wireless signal receiving unit (21), used for collecting wireless signals to obtain original driving signals; A Schmitt trigger filter unit (22), connected to the wireless signal receiving unit (21), is used to perform waveform conversion on the original drive signal and output a preliminary square wave signal; A logic level conversion unit (23), connected to the Schmitt trigger filter unit (22), configured to perform edge switching on the trigger signal and output a square wave signal; A driving unit (24), connected to the logic level conversion unit (23), and used for converting the square wave signal into a driving signal and outputting it to the gate of the power chip (1); An overcurrent protection unit (25), wherein an input side of the overcurrent protection unit (25) is connected to the emitter current of the power chip (1), and an output side of the overcurrent protection unit (25) is connected to the logic level conversion unit (23), and is used to output a protection signal for controlling the power chip (1) to shut down according to the emitter current of the power chip (1).

2. The intelligent power module driving device according to claim 1, characterized in that: The power chip (1) is connected to the copper sheet by means of solder paste, a driving pole of the driving chip (2) is printed with a bump, and the driving chip (2) is mounted on the power chip (1) in an inverted manner; The driving chip (2) is integrated with an on-chip antenna (26), and the wireless signal is received via the on-chip antenna (26).

3. The intelligent power module driving device according to claim 1, characterized in that: The wireless signal receiving unit (21) comprises: a first capacitor (C1), wherein a first end of the first capacitor (C1) is connected to the wireless signal, and a second end of the first capacitor (C1) is grounded; a first inductor (L1), wherein a first end of the first inductor (L1) is connected to a first end of the first capacitor (C1), and a second end of the first inductor (L1) is connected to a second end of the first capacitor (C1); a first resistor (R1), wherein a first end of the first resistor (R1) is connected to the wireless signal, and a second end of the first resistor (R1) is grounded; a second resistor (R2), wherein a first end of the second resistor (R2) is connected to the wireless signal; a second capacitor (C2), wherein a first end of the second capacitor (C2) is connected to a second end of the second resistor (R2); a third capacitor (C3), wherein a first end of the third capacitor (C3) is connected to a second end of the second capacitor (C2), and a second end of the third capacitor (C3) is grounded; a third resistor (R3), wherein a first end of the third resistor (R3) is connected to a second end of the second resistor (R2), and a second end of the third resistor (R3) is connected to a first end of the third capacitor (C3); a first diode (D1), wherein an anode of the first diode (D1) is connected to a second end of the second resistor (R2); a fourth capacitor (C4), wherein a first end of the fourth capacitor (C4) is connected to the cathode of the first diode (D1), and a second end of the fourth capacitor (C4) is connected to the second end of the third capacitor (C3); a first transistor (T1), wherein the base of the first transistor (T1) is connected to the cathode of the first diode (D1), and the collector of the first transistor (T1) serves as the output of the wireless signal receiving unit (21); a fourth resistor (R4), wherein a first end of the fourth resistor (R4) is connected to the base of the first transistor (T1), and a second end of the fourth resistor (R4) is connected to the collector of the first transistor (T1); a fifth resistor (R5), wherein a first end of the fifth resistor (R5) is connected to the emitter of the first transistor (T1), and a second end of the fifth resistor (R5) is grounded; A fifth capacitor (C5), wherein a first end of the fifth capacitor (C5) is connected to the emitter of the first transistor (T1), and a second end of the fifth capacitor (C5) is connected to the second end of the fifth resistor (R5).

4. The intelligent power module driving device according to claim 3, characterized in that: The wireless signal receiving unit (21) further includes: a sixth resistor (R6), wherein a first end of the sixth resistor (R6) is connected to the collector of the first transistor (T1); a seventh resistor (R7), wherein a first end of the seventh resistor (R7) is connected to the base of the first transistor (T1), and a second end of the seventh resistor (R7) is connected to the second end of the fifth resistor (R5); a second diode (D2), wherein a cathode of the second diode (D2) is connected to a second end of the sixth resistor (R6); a third diode (D3), wherein a cathode of the third diode (D3) is connected to an anode of the second diode (D2), and an anode of the third diode (D3) is grounded; a fourth diode (D4), wherein a cathode of the fourth diode (D4) is connected to a second end of the sixth resistor (R6); a fifth diode (D5), wherein a cathode of the fifth diode (D5) is connected to an anode of the fourth diode (D4), and an anode of the fifth diode (D5) is connected to an anode of the third diode (D3); a sixth capacitor (C6), wherein a first end of the sixth capacitor (C6) is connected to an anode of the second diode (D2); A coil (L2), wherein a first end of the coil (L2) is connected to a second end of the sixth capacitor (C6), a second end of the coil (L2) is connected to an anode of the fourth diode (D4), and the coil (L2) is used to output a supply voltage.

5. The intelligent power module driving device according to claim 1, characterized in that: The Schmitt trigger filter unit (22) comprises: a second transistor (T2), wherein the base of the second transistor (T2) is connected to the output end of the wireless signal receiving unit (21); an eighth resistor (R8), wherein a first end of the eighth resistor (R8) is connected to the collector of the second transistor (T2), and a second end of the eighth resistor (R8) is connected to a positive potential signal; a ninth resistor (R9), wherein a first end of the ninth resistor (R9) is connected to the emitter of the second transistor (T2), and a second end of the ninth resistor (R9) is grounded; a tenth resistor (R10), wherein a first end of the tenth resistor (R10) is connected to the collector of the second transistor (T2); an eleventh resistor (R11), a first end of the eleventh resistor (R11) being connected to the second end of the tenth resistor (R10), and a second end of the eleventh resistor (R11) being grounded; a third triode (T3), wherein a base of the third triode (T3) is connected to the second end of the tenth resistor (R10), and an emitter of the third triode (T3) is connected to the emitter of the second triode (T2); A twelfth resistor (R12), wherein a first end of the twelfth resistor (R12) is connected to the collector of the third transistor (T3), and a second end of the twelfth resistor (R12) is connected to the positive potential signal.

6. The intelligent power module driving device according to claim 5, characterized in that: The Schmitt trigger filter unit (22) further includes: a thirteenth resistor (R13), wherein a first end of the thirteenth resistor (R13) is connected to the collector of the third transistor (T3); a first MOSFET (Q1), wherein the drain of the first MOSFET (Q1) is connected to the second end of the thirteenth resistor (R13), the source of the first MOSFET (Q1) is connected to a first power supply voltage (VDD), and the gate of the first MOSFET (Q1) is the output end of the Schmitt trigger filter unit (22) for outputting the preliminary square wave signal; a second MOSFET (Q2), wherein a drain of the second MOSFET (Q2) is connected to the second end of the thirteenth resistor (R13), a source of the second MOSFET (Q2) is grounded, and a gate of the second MOSFET (Q2) is connected to the gate of the first MOSFET (Q1); a third MOSFET (Q3), wherein a gate electrode of the third MOSFET (Q3) is connected to the second end of the thirteenth resistor (R13), a drain electrode of the third MOSFET (Q3) is connected to the gate electrode of the first MOSFET (Q1), and a source electrode of the third MOSFET (Q3) is connected to the first power supply voltage (VDD); a fourth MOSFET (Q4), wherein a gate electrode of the fourth MOSFET (Q4) is connected to the second end of the thirteenth resistor (R13), a source electrode of the fourth MOSFET (Q4) is connected to the source electrode of the second MOSFET (Q2), and a drain electrode of the fourth MOSFET (Q4) is connected to the gate electrode of the second MOSFET (Q2).

7. The intelligent power module driving device according to claim 1, characterized in that: The logic level conversion unit (23) comprises: a fourteenth resistor (R14), wherein a first end of the fourteenth resistor (R14) is connected to an output end of the Schmitt trigger filter unit (22); A first comparator (A1), wherein a first input terminal of the first comparator (A1) is connected to a second terminal of the fourteenth resistor (R14), and a second input terminal of the first comparator (A1) is connected to a reference signal (Ref1); An edge trigger (D1), wherein an input end of the edge trigger (D1) is connected to an output end of the first comparator (A1); An AND gate (D2), wherein a first input end of the AND gate (D2) is connected to an output end of the edge trigger (D1), a second output end of the AND gate (D2) is connected to the protection signal, and an output end of the AND gate (D2) serves as an output end of the logic level conversion unit (23) to output the square wave signal.

8. The intelligent power module driving device according to claim 1, characterized in that: The driving unit (24) comprises: a fifth MOS transistor (Q5), wherein a gate electrode of the fifth MOS transistor (Q5) is connected to an output end of the logic level conversion unit (23), and a source electrode of the fifth MOS transistor (Q5) is connected to a second power supply voltage (VCC); a sixth MOSFET (Q6), wherein a gate electrode of the sixth MOSFET (Q6) is connected to a gate electrode of the fifth MOSFET (Q5), a drain electrode of the sixth MOSFET (Q6) is connected to a drain electrode of the fifth MOSFET (Q5), and a source electrode of the sixth MOSFET (Q6) is grounded; a seventh MOS transistor (Q7), wherein a source electrode of the seventh MOS transistor (Q7) is connected to a source electrode of the fifth MOS transistor (Q5), and a gate electrode of the seventh MOS transistor (Q7) is connected to a drain electrode of the fifth MOS transistor (Q5); an eighth MOS transistor (Q8), wherein a gate electrode of the eighth MOS transistor (Q8) is connected to a gate electrode of the seventh MOS transistor (Q7), and a source electrode of the eighth MOS transistor (Q8) is connected to a source electrode of the sixth MOS transistor (Q6); a fifteenth resistor (R15), wherein a first end of the fifteenth resistor (R15) is connected to the drain of the seventh MOS tube (Q7), and a second end of the fifteenth resistor (R15) is an output end of the driving unit (24) connected to the gate of the power chip (1) to output the driving signal; a sixteenth resistor (R16), wherein a first end of the sixteenth resistor (R16) is connected to a second end of the fifteenth resistor (R15), and a second end of the sixteenth resistor (R16) is connected to a drain of the eighth MOS transistor (Q8); A seventeenth resistor (R17), wherein a first end of the seventeenth resistor (R17) is connected to the second end of the fifteenth resistor (R15), and a first end of the seventeenth resistor (R17) is connected to the source of the eighth MOS tube (Q8).

9. The intelligent power module driving device according to claim 1, characterized in that: The overcurrent protection unit (25) comprises: an eighteenth resistor (R18), a first end of the eighteenth resistor (R18) being connected to the emitter of the power chip (1); a nineteenth resistor (R19), wherein a first end of the nineteenth resistor (R19) is connected to a second end of the eighteenth resistor (R18); a seventh capacitor (C7), wherein a first end of the seventh capacitor (C7) is connected to a first end of the nineteenth resistor (R19), and a second end of the seventh capacitor (C7) is connected to a second end of the nineteenth resistor (R19); a twentieth resistor (R20), wherein a first end of the twentieth resistor (R20) is connected to a second end of the eighteenth resistor (R18), and a second end of the twentieth resistor (R20) is grounded; A second comparator (A2), wherein a first input terminal of the second comparator (A2) is connected to a first terminal of the second resistor (R20), and a second input terminal of the second comparator (A2) is connected to a threshold signal (Ref2); A filter (F1), wherein an input end of the filter (F1) is connected to an output end of the second comparator (A2); A NOR gate (D3), wherein a first input end of the NOR gate (D3) is connected to an output end of the filter (F1); An RS trigger (D4), wherein the S end of the RS trigger (D4) is connected to the output end of the filter (F1), the R end of the RS trigger (D4) is connected to the output end of the NOR gate (D3), and the output end of the RS trigger (D4) is the output end of the overcurrent protection unit (25) to output the protection signal; A NOT gate (D5), wherein the input end of the NOT gate (D5) is connected to the output end of the RS trigger (D4), and the output end of the NOT gate (D5) is connected to the second input end of the NOR gate (D3).

10. The intelligent power module driving device according to claim 1, characterized in that: A transparent packaging shell is provided on the outer sides of the power chip (1) and the driving chip (2).

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