A method for dynamically improving the driving of a wave by a circuit

Abstract

The application belongs to the technical field of circuit, and discloses a method for dynamically improving wave driving of a circuit, wherein an MCU carries out loop operation, and updates and loads loop operation results of driving, determines a circuit structure, and thus determines a time t required for driving update, and the timing of driving update is ahead of the timing of driving loading by t. The application has the beneficial effects that: the interrupt request function of the main timer of the control chip is utilized to make the update timing of LLC driving ahead of the loading timing, to accelerate the driving response speed; compared with the traditional driving update mode, LLC driving can respond to update faster, and the driving update strategy driving can complete the update one period ahead, and the strategy has the advantages of increasing loop phase margin and reducing driving response delay.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a method for dynamically improving circuit-driven waveform generation. Background Technology

[0002] Driven by global digital transformation, the server industry has experienced significant growth in recent years. With the rapid development of cloud computing and AI technologies, the demand for data processing and computing power in servers is constantly increasing. GPU servers, with their powerful computing capabilities, require significantly more power to operate; for example, a server equipped with eight GPUs can consume up to 6 kilowatts per hour. As AI technology advances, the dynamic response of GPUs to server power supplies is becoming increasingly stringent. Under large dynamic output loads, the output voltage often fails to meet dynamic specifications due to the untimely response of LLC drives. Therefore, the untimely response of LLC drives under these dynamic conditions is a problem that needs to be addressed in this technical field.

[0003] Therefore, it is necessary to provide a method for dynamically improving circuit drive waveform generation to solve the problem of untimely LLC drive response under dynamic output conditions. Summary of the Invention

[0004] This invention discloses a method for dynamically improving circuit drive waveform generation, relating to the field of DC / DC power conversion, and particularly to a method for dynamically improving drive waveform generation, which can effectively solve the technical problems involved in the background art.

[0005] To achieve the above objectives, the technical solution of the present invention is as follows:

[0006] A method for dynamically improving circuit-driven waveform generation includes the following steps:

[0007] S1. The circuit is equipped with an MCU, which performs loop calculations and updates and loads the loop calculation results to the driver.

[0008] S2. Determine the circuit structure to determine the time t required for the drive update;

[0009] S3, the driver update occurs t earlier than the driver loading time.

[0010] Specifically, this invention discloses a dynamic improvement drive waveform generation strategy applicable to LLC, addressing the problem of slow response speed in traditional drive update methods, which leads to output voltage failure to meet dynamic specifications under dynamic load conditions. Traditional drive update methods involve simultaneous loading and updating, while the proposed method prioritizes updating before loading. Compared to traditional methods, LLC drives respond to updates much faster, offering advantages such as increased loop phase margin and reduced drive response delay. Utilizing the interrupt request function of the control chip's master timer, the LLC drive update timing is advanced before loading, accelerating drive response speed. This description uses a half-bridge LLC circuit as an example; this strategy can be applied to other switching power supply topologies, such as full-bridge LLC and PFC topologies. The time by which the update timing precedes the loading timing is 0.6µs in this example; actual applications will require adjustment based on the time needed for drive configuration updates.

[0011] As a preferred improvement of the present invention: in step S2, the time t required for driving the update is positively correlated with the number of switching transistors in the circuit, which can be measured by an oscilloscope or obtained through experiments.

[0012] As a preferred improvement of the present invention, the circuit includes, but is not limited to, LLC circuits and PFC circuits.

[0013] As a preferred improvement of the present invention, the loop operation includes, but is not limited to, voltage loop and current loop.

[0014] As a preferred improvement of the present invention: the timing of the drive loading is related to the loop operation frequency, and the drive loading is performed at the end of the loop operation cycle.

[0015] As a preferred improvement of the present invention: the circuit is a half-bridge LLC circuit, which includes a power supply. The positive terminal of the power supply is connected to the drain of MOSFET Q1. The source of MOSFET Q1 is connected to the drain of MOSFET Q2 and one end of inductor Lr. The negative terminal of the power supply is connected to the source of MOSFET Q2 and one end of capacitor Cr. The other end of inductor Lr is connected to one end of inductor Lm and pin 1 of transformer T. The other end of capacitor Cr is connected to the other end of inductor Lm and pin 2 of transformer T. Pin 6 of transformer T is connected to the source of MOSFET Q3. The drain of MOSFET Q3 is connected to the drain of MOSFET Q4 and one end of capacitor Cout. Pin 5 of transformer T is connected to pin 4 of transformer T and the other end of capacitor Cout. Pin 3 of transformer T is connected to the source of MOSFET Q4. Capacitor Cout is connected to the load.

[0016] As a preferred improvement of the present invention, t is 0.6 microseconds.

[0017] The beneficial effects of this invention are as follows:

[0018] The timing of the driver update is t earlier than the timing of the driver loading. The main timer interrupt of the controller can be triggered earlier, that is, the driver register is updated earlier, ensuring that the driver updates the loop operation result in the next cycle, improving the phase margin of one frequency cycle. In summary, the driver update strategy proposed in this invention can complete the update one cycle earlier, improve the loop response phase margin, and increase the dynamic response. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0020] Figure 1 A schematic diagram of the process driven by existing methods;

[0021] Figure 2 This is a schematic diagram of the driving process of a method for dynamically improving circuit driving wave generation according to the present invention;

[0022] Figure 3 This is a schematic diagram of a half-bridge LLC circuit. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0024] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indication will also change accordingly.

[0025] Furthermore, in this invention, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0026] In this invention, unless otherwise explicitly specified and limited, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0027] Furthermore, the technical solutions of the various embodiments of the present invention can be combined with each other, but only if they are feasible for those skilled in the art. If the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.

[0028] This invention provides a method for dynamically improving circuit drive waveform generation, comprising the following steps: S1, the circuit is equipped with an MCU, the MCU performs loop calculations, and updates and loads the results of the loop calculations on the drive; S2, the circuit structure is determined, thereby determining the time t required for drive update; S3, the timing of drive update is t earlier than the timing of drive loading.

[0029] In step S2, the time t required for the drive update is positively correlated with the number of switching transistors in the circuit. This can be determined by measuring with an oscilloscope or through experiments. The number of switching transistors determines the amount of data to be updated, which in turn determines the update time. This can be determined based on the specific circuit structure used. The circuit includes, but is not limited to, LLC circuits and PFC circuits, and the loop operation includes, but is not limited to, voltage loops and current loops. The timing of the drive loading is related to the loop operation frequency; the drive loading occurs at the end of the loop operation cycle.

[0030] LLC (Resonant Circuit) and SR (Synchronous Rectifier) ​​driver updates depend on the microcontroller's settings for driver update and load timing. The driver update timing is a time period during which the driver register values ​​are updated. The load timing acts like a switch; when triggered, the driver updates according to the driver register values. The length of the update timing depends on the complexity of the driver configuration. It's crucial to select an appropriate update timing, ensuring the driver register values ​​are completely updated before loading. If driver loading occurs within the update timing, some driver registers will be overwritten, leading to inconsistencies before and after loading and potentially causing driver reliability issues.

[0031] like Figure 3The circuit described herein is a reference circuit. The circuit is a half-bridge LLC circuit, which includes a power supply. The positive terminal of the power supply is connected to the drain of MOSFET Q1. The source of MOSFET Q1 is connected to the drain of MOSFET Q2 and one end of inductor Lr. The negative terminal of the power supply is connected to the source of MOSFET Q2 and one end of capacitor Cr. The other end of inductor Lr is connected to one end of inductor Lm and pin 1 of transformer T. The other end of capacitor Cr is connected to the other end of inductor Lm and pin 2 of transformer T. Pin 6 of transformer T is connected to the source of MOSFET Q3. The drain of MOSFET Q3 is connected to the drain of MOSFET Q4 and one end of capacitor Cout. Pin 5 of transformer T is connected to pin 4 of transformer T and the other end of capacitor Cout. Pin 3 of transformer T is connected to the source of MOSFET Q4. Capacitor Cout is connected to the load. The time t is 0.6 microseconds. It should be further noted that any other components used to achieve the above effects should fall within the inventive concept of this invention and should be protected within the scope of this invention.

[0032] The update timing of LLC and SR drivers is determined by the interrupt trigger timing of the microcontroller's main timer, which is determined by the interrupt request setting. When the interrupt request is set to REP (i.e., the cycle position; in traditional driver update methods, the driver update and load timings are consistent, making configuration simple), the interrupt trigger timing of the main timer is determined by the LLC frequency of the loop operation. Currently, the update timing is set to CMP4 (the driver update method proposed in this invention, with an advance load timing of 0.6us). The interrupt trigger timing of the main timer is determined by the CMP4 setting value, which is updated in real time. This invention modifies the interrupt request setting of the microcontroller's main timer from REP to CMP4, setting the CMP4 value to 0.6us before the LLC cycle position. The driver load timing is set to the LLC frequency, allowing the main timer interrupt to trigger 0.6us earlier, thus achieving an advance load timing update of the driver register by 0.6us. This ensures that the driver updates the loop operation result in the next cycle, improving the phase margin by one frequency cycle.

[0033] Taking the LLC and SR drivers being updated from 50kHz to 100kHz as an example, Figure 1The master timer interrupt request is set to REP. In the first cycle, the LLC frequency is 50kHz. At the end of the first cycle, the LLC and SR driver update and loading times occur simultaneously. Since driver register updates take time, the driver register has not yet been updated to 100kHz. Therefore, at the end of the first cycle, the driver is still loaded at 50kHz. In the second cycle, the LLC and SR driver frequencies are still 50kHz. At the end of the second cycle, the LLC and SR driver registers have been updated to 100kHz. Therefore, at the end of the second cycle, the driver is loaded at 100kHz. In the third cycle, the LLC and SR driver frequencies are 100kHz.

[0034] Figure 2 The master timer interrupt request is set to CMP4. In the first cycle, the LLC frequency is 50kHz. The master timer interrupt is triggered 0.6µs before the end of the first cycle to update the LLC and SR driver registers to 100kHz. In this example, the LLC and SR driver registers can be updated in 0.6µs. At the end of the first cycle, the LLC and SR driver frequencies are loaded to 100kHz, and the LLC and SR driver frequencies can be updated to 100kHz in the second cycle. Compared with traditional driver update methods, the driver update strategy proposed in this invention can complete the update one cycle earlier, improving the loop response phase margin and increasing dynamic response.

[0035] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. Other modifications can be easily made by those skilled in the art. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A method for dynamically improving circuit-driven waveform generation, characterized in that, Includes the following steps: S1. The circuit is equipped with an MCU, which performs loop calculations and updates and loads the loop calculation results to the driver. S2. Determine the circuit structure to determine the time t required for the drive update; S3, the driver update occurs t earlier than the driver loading time.

2. The method for dynamically improving circuit-driven waveform generation according to claim 1, characterized in that: In step S2, the time t required for the drive update is positively correlated with the number of switching transistors in the circuit, which can be measured by an oscilloscope or obtained through experiments.

3. The method for dynamically improving circuit-driven waveform generation according to claim 1, characterized in that: The circuit includes an LLC circuit and a PFC circuit.

4. The method for dynamically improving circuit-driven waveform generation according to claim 1, characterized in that: The loop operation includes a voltage loop and a current loop.

5. The method for dynamically improving circuit-driven waveform generation according to claim 1, characterized in that: The timing of the drive loading is related to the loop operation frequency; the drive loading is performed at the end of the loop operation cycle.

6. The method for dynamically improving circuit-driven waveform generation according to claim 1, characterized in that: The circuit is a half-bridge LLC circuit. The half-bridge LLC circuit includes a power supply. The positive terminal of the power supply is connected to the drain of MOSFET Q1. The source of MOSFET Q1 is connected to the drain of MOSFET Q2 and one end of inductor Lr. The negative terminal of the power supply is connected to the source of MOSFET Q2 and one end of capacitor Cr. The other end of inductor Lr is connected to one end of inductor Lm and pin 1 of transformer T. The other end of capacitor Cr is connected to the other end of inductor Lm and pin 2 of transformer T. Pin 6 of transformer T is connected to the source of MOSFET Q3. The drain of MOSFET Q3 is connected to the drain of MOSFET Q4 and one end of capacitor Cout. Pin 5 of transformer T is connected to pin 4 of transformer T and the other end of capacitor Cout. Pin 3 of transformer T is connected to the source of MOSFET Q4. Capacitor Cout is connected to the load.

7. The method for dynamically improving circuit-driven waveform generation according to claim 6, characterized in that: The value of t is 0.6 microseconds.

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