Voltage doubling circuit, voltage doubling circuit module and high-voltage power supply

Abstract

The invention provides a voltage doubling circuit, a voltage doubling circuit module and a high-voltage power supply. The voltage doubling circuit comprises: a full-bridge rectifier module, wherein the full-bridge rectifier module comprises a first rectifier bridge arm and a second rectifier bridge arm; and the voltage-multiplying module comprises a first voltage-multiplying unit and a second voltage-multiplying unit. Wherein the output end of the first rectifier bridge arm is electrically connected with the input end of the first voltage-multiplying unit, and the output end of the second rectifier bridge arm is electrically connected with the input end of the second voltage-multiplying unit.

Description

Technical Field

[0001] The present disclosure relates to the technical field of high-voltage power supplies, and more specifically, to a voltage doubling circuit, a voltage doubling circuit module, and a high-voltage power supply. Background Art

[0002] The high voltage boost ratio voltage doubler circuit is a key core component of the high voltage power supply. It uses a transformer and a charge pump to increase the input voltage to multiple times. The transformation ratio of the high-frequency transformer and the number of stages of the charge pump circuit directly determine the output voltage level of the high voltage DC power supply. Symmetrical voltage doubler circuits are widely used due to their simple structure and high voltage boost ratio, but their output voltage ripple is large and their load capacity is poor. They face great challenges in applications that require high output voltage stability. Summary of the invention

[0003] In view of this, embodiments of the present disclosure provide a voltage doubling circuit, a voltage doubling circuit module, and a high voltage power supply.

[0004] One aspect of the present disclosure provides a voltage doubling circuit, comprising:

[0005] A full-bridge rectifier module, the full-bridge rectifier module comprising a first rectifier bridge arm and a second rectifier bridge arm; and

[0006] A voltage doubling module, the voltage doubling module comprising a first voltage doubling unit and a second voltage doubling unit,

[0007] The output end of the first rectifying bridge arm is electrically connected to the input end of the first voltage doubling unit, and the output end of the second rectifying bridge arm is electrically connected to the input end of the second voltage doubling unit.

[0008] According to an embodiment of the present disclosure, the full-bridge rectifier module further includes a first input terminal and a second input terminal;

[0009] The first rectifier bridge arm comprises a first connection end, a third connection end and a first output end, the first connection end and the third connection end of the first rectifier bridge arm are respectively connected to the first input end and the second input end of the full-bridge rectifier module, and the first output end of the first rectifier bridge arm is electrically connected to the input end of the first voltage doubling unit; and

[0010] The second rectifier bridge arm includes a fourth connection end, a sixth connection end and a second output end. The fourth connection end and the sixth connection end of the second rectifier bridge arm are respectively connected to the first input end and the second input end of the full-bridge rectifier module. The second output end of the second rectifier bridge arm is electrically connected to the input end of the second voltage doubling unit.

[0011] According to an embodiment of the present disclosure, the voltage doubling circuit further includes:

[0012] A transformer, the transformer comprising a primary side and a secondary side, the two ends of the primary side are respectively configured to be connected to the two ends of the AC power supply, and the two ends of the secondary side are respectively configured to be connected to the first input end and the second input end of the full-bridge rectifier module; and

[0013] A load, one end of the load is electrically connected to the output end of the first voltage doubling unit, and the other end of the load is electrically connected to the output end of the second voltage doubling unit.

[0014] According to an embodiment of the present disclosure, the first rectifier bridge arm further includes a first diode, a second diode, and a second connection terminal, the anode of the first diode is electrically connected to the first connection terminal, the cathode of the first diode and the cathode of the second diode are both electrically connected to the second connection terminal, and the anode of the second diode is electrically connected to the third connection terminal; and

[0015] The second rectifier bridge arm also includes a third diode, a fourth diode and a fifth connection terminal, the cathode of the third diode is electrically connected to the fourth connection terminal, the anode of the third diode and the anode of the fourth diode are both electrically connected to the fifth connection terminal, and the cathode of the fourth diode is electrically connected to the sixth connection terminal.

[0016] According to an embodiment of the present disclosure, the full-bridge rectifier module also includes a first capacitor, a first plate of the first capacitor is electrically connected to the second connection end of the first rectifier bridge arm, and a second plate of the first capacitor is electrically connected to the fifth connection end of the second rectifier bridge arm.

[0017] According to an embodiment of the present disclosure, the first output end of the first rectifier bridge arm includes a first sub-output end, a second sub-output end and a third sub-output end, the first sub-output end is electrically connected to the first connection end, the second sub-output end is electrically connected to the second connection end, and the third sub-output end is electrically connected to the third connection end;

[0018] The first voltage doubling unit includes p-stage cascaded first voltage doubling subunits, each stage of the first voltage doubling subunits includes a fourth input terminal, a fifth input terminal, a sixth input terminal, a fourth output terminal, a fifth output terminal and a sixth output terminal, respectively.

[0019] Among them, the fourth input terminal, the fifth input terminal and the sixth input terminal of the first-stage first voltage doubling subunit are electrically connected to the first sub-output terminal, the second sub-output terminal and the third sub-output terminal of the first rectifier bridge arm, respectively, and the fourth input terminal, the fifth input terminal and the sixth input terminal of the i+1-th stage first voltage doubling subunit are electrically connected to the fourth output terminal, the fifth output terminal and the sixth output terminal of the i-th stage first voltage doubling subunit, respectively, wherein i is a positive integer greater than or equal to 1 and less than or equal to p-1, and p is a positive integer greater than or equal to 2.

[0020] According to an embodiment of the present disclosure, the second output end of the second rectifier bridge arm includes a fourth sub-output end, a fifth sub-output end and a sixth sub-output end, the fourth sub-output end is electrically connected to the fourth connection end, the fifth sub-output end is electrically connected to the fifth connection end, and the sixth sub-output end is electrically connected to the sixth connection end;

[0021] The second voltage doubling unit includes m stages of cascaded second voltage doubling sub-units, each stage of the second voltage doubling sub-units includes a seventh input terminal, an eighth input terminal, a ninth input terminal, a seventh output terminal, an eighth output terminal and a ninth output terminal, respectively.

[0022] Among them, the seventh input terminal, the eighth input terminal and the ninth input terminal of the first-stage second voltage doubling sub-unit are electrically connected to the fourth sub-output terminal, the fifth sub-output terminal and the sixth sub-output terminal of the second rectifier bridge arm, respectively, and the seventh input terminal, the eighth input terminal and the ninth input terminal of the j+1-th stage second voltage doubling sub-unit are electrically connected to the seventh output terminal, the eighth output terminal and the ninth output terminal of the j-th stage second voltage doubling sub-unit, respectively, wherein j is a positive integer greater than or equal to 1 and less than or equal to m-1, and m is a positive integer greater than or equal to 2.

[0023] According to an embodiment of the present disclosure, the fifth output terminal of the p-th stage first voltage doubling subunit is electrically connected to one end of the load; and

[0024] The eighth output terminal of the m-th stage second voltage doubling subunit is electrically connected to the other end of the load.

[0025] According to an embodiment of the present disclosure, the number of cascaded first voltage doubling subunits included in the first voltage doubling unit is equal to the number of cascaded second voltage doubling subunits included in the second voltage doubling unit.

[0026] According to an embodiment of the present disclosure, the i-th level first voltage doubling subunit includes an eleventh capacitor, a twenty-first capacitor, a thirty-first capacitor, an eleventh diode, a twenty-first diode, a thirty-first diode and a forty-first diode, where i is a positive integer greater than or equal to 1,

[0027] The first electrode plate of the eleventh capacitor is electrically connected to the fourth input terminal of the i-th first voltage doubling subunit, and the second electrode plate of the eleventh capacitor is electrically connected to the fourth output terminal of the i-th first voltage doubling subunit;

[0028] The first electrode plate of the twenty-first capacitor is electrically connected to the fifth input terminal of the i-th first voltage doubling subunit, and the second electrode plate of the twenty-first capacitor is electrically connected to the fifth output terminal of the i-th first voltage doubling subunit;

[0029] The first electrode plate of the thirty-first capacitor is electrically connected to the sixth input terminal of the i-th first voltage doubling subunit, and the second electrode plate of the thirty-first capacitor is electrically connected to the sixth output terminal of the i-th first voltage doubling subunit;

[0030] The cathode of the eleventh diode is electrically connected to the fourth output terminal of the i-th first voltage doubling subunit, and the anode of the eleventh diode is electrically connected to the fifth input terminal of the i-th first voltage doubling subunit;

[0031] An anode of the twenty-first diode is electrically connected to the fourth output terminal of the i-th first voltage doubling subunit, and a cathode of the twenty-first diode is electrically connected to the fifth output terminal of the i-th first voltage doubling subunit;

[0032] an anode of the thirty-first diode is electrically connected to the fifth input terminal of the i-th first voltage doubling subunit, and a cathode of the thirty-first diode is electrically connected to the sixth output terminal of the i-th first voltage doubling subunit; and

[0033] The cathode of the forty-first diode is electrically connected to the fifth output terminal of the i-th first voltage doubling subunit, and the anode of the forty-first diode is electrically connected to the sixth output terminal of the i-th first voltage doubling subunit.

[0034] According to an embodiment of the present disclosure, the structure of the transformer is a center-tap-free structure.

[0035] According to an embodiment of the present disclosure, the voltage boost ratio of the voltage doubler circuit is as shown in the following formula:

[0036] ratio=V out / V in =2N(2m+1), where ratio represents the voltage boost ratio of the voltage doubler circuit, V out represents the voltage value of the DC voltage output by the voltage doubler circuit, V in represents the equivalent voltage value of the AC voltage input by the AC power supply, 2N represents the transformation ratio of the transformer, and m represents the number of stages of the first voltage doubling unit and the second voltage doubling unit.

[0037] Another aspect of the present disclosure provides a voltage doubling circuit module, which includes a voltage doubling circuit as described in any one of the above items.

[0038] Yet another aspect of the present disclosure provides a high-voltage power supply, wherein the high-voltage power supply comprises: an AC power supply; and the voltage doubling circuit module as described above.

[0039] One or more of the above embodiments have the following beneficial effects:

[0040] (1) It has the advantage of small voltage drop loss, so it is suitable for occasions with high requirements on output voltage stability;

[0041] (2) The output voltage drop loss is small under different load conditions, with better voltage regulation performance, and can be used in high voltage and high power applications;

[0042] (3) The high-frequency transformer used does not require an intermediate tap structure, so it has the advantages of simple structure and high reliability;

[0043] (4) The dynamic adjustment performance of the output voltage is better than that of the conventional symmetrical voltage doubler circuit, so it is suitable for applications with high requirements on dynamic characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0045] Figure 1A is a structural block diagram of a high voltage power supply according to an exemplary embodiment of the present disclosure, Figure 1B is a structural block diagram of a voltage doubling circuit module according to an exemplary embodiment of the present disclosure;

[0046] Figure 2 is a schematic diagram of a conventional symmetrical voltage doubling circuit according to an exemplary embodiment of the present disclosure;

[0047] Figure 3 is based on Figure 2 A schematic diagram of a charging process of a conventional symmetrical voltage doubler circuit;

[0048] Figure 4 is based on Figure 2 A schematic diagram of another charging process of a conventional symmetrical voltage doubler circuit;

[0049] Figure 5 is based on Figure 2 A schematic diagram of a discharge process of a conventional symmetrical voltage doubler circuit;

[0050] Figure 6 is a structural block diagram of a voltage doubling circuit according to an exemplary embodiment of the present disclosure;

[0051] Figure 7 is a schematic diagram of a voltage doubling circuit according to an exemplary embodiment of the present disclosure;

[0052] Fig. 8A is a partial circuit diagram of a voltage doubling circuit according to an exemplary embodiment of the present disclosure, wherein a first rectifying bridge arm and a first voltage doubling unit are shown; Figure 8Bis a partial circuit diagram of a voltage doubling circuit according to an exemplary embodiment of the present disclosure, wherein a second rectifier bridge arm and a second voltage doubling unit are shown;

[0053] Fig. 9 is based on Figure 7 A schematic diagram of a charging process of a voltage doubling circuit of an exemplary embodiment;

[0054] Fig.10 is based on Figure 7 A schematic diagram of another charging process of a voltage doubling circuit of an exemplary embodiment;

[0055] Fig.11 is based on Figure 7 A schematic diagram of a discharge process of a voltage doubler circuit of an exemplary embodiment of the present invention; and

[0056] Figures 12A-12C Schematic diagrams comparing the dynamic characteristics of a voltage doubler circuit according to an embodiment of the present disclosure and a conventional symmetrical voltage doubler circuit.

[0057] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the sizes of the overall / local structures or the overall / local areas may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0058] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0059] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of the features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0060] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0061] First, some of the terms involved in this application are defined as follows:

[0062] Voltage doubler circuit: The main function of the voltage doubler circuit is to rectify and boost the high-frequency AC voltage to obtain the DC high voltage required by the next stage, which mainly includes diodes with higher reverse peak voltage and capacitors with higher withstand voltage. For example, in an electronic circuit, when the voltage required by the next stage is an integer multiple higher than that of the previous stage and the required current is not very large, a voltage doubler circuit can be used.

[0063] Charge pump: A DC-DC converter that uses capacitors as energy storage elements and is often used to generate an output voltage greater than the input voltage, or to generate a negative output voltage. For example, a charge pump may include multiple cascaded voltage doubling units.

[0064] Voltage ripple: Voltage ripple is the AC component in a DC voltage. The DC voltage should be a fixed value, but in many cases it is obtained by rectifying and filtering the AC voltage. Due to unclean filtering, there will be residual AC components. Even if it is powered by a battery, ripples will be generated due to load fluctuations.

[0065] An embodiment of the present disclosure provides a voltage doubling circuit, comprising:

[0066] A transformer, the transformer comprising a primary side and a secondary side, wherein two ends of the primary side are respectively configured to be connected to two ends of an AC power source;

[0067] A full-bridge rectifier module, the full-bridge rectifier module includes a first input end and a second input end, the first input end and the second input end of the full-bridge rectifier module are respectively configured to connect the two ends of the secondary side; the full-bridge rectifier module also includes a first rectifier bridge arm and a second rectifier bridge arm, the first rectifier bridge arm includes a first connection end, a third connection end and a first output end, the first connection end and the third connection end of the first rectifier bridge arm are respectively connected to the first input end and the second input end of the full-bridge rectifier module; the second rectifier bridge arm includes a fourth connection end, a sixth connection end and a second output end, the fourth connection end and the sixth connection end of the second rectifier bridge arm are respectively connected to the first input end and the second input end of the full-bridge rectifier module;

[0068] A voltage doubling module, the voltage doubling module comprising a first voltage doubling unit and a second voltage doubling unit, the input end of the first voltage doubling unit is electrically connected to the first output end of the first rectifier bridge arm, and the input end of the second voltage doubling unit is electrically connected to the second output end of the second rectifier bridge arm; and

[0069] A load, one end of the load is electrically connected to the output end of the first voltage doubling unit, and the other end of the load is electrically connected to the output end of the second voltage doubling unit.

[0070] By adopting a hybrid structure of full-bridge rectification and voltage-doubling rectification cascade, the number of voltage-doubling circuit cascades is reduced, the voltage-step-up ratio of the circuit is improved, and the number of capacitors in a single voltage-doubling unit (such as the first voltage-doubling unit or the second voltage-doubling unit) can be reduced, thereby improving the circuit's load capacity and dynamic response performance. In addition, the transformer can adopt a conventional non-center-tapped transformer, which has a simple structure, can simplify the structure of the entire circuit, and reduce costs.

[0071] Figure 1A is a structural block diagram of a high voltage power supply according to an exemplary embodiment of the present disclosure, Figure 1B is a structural block diagram of a voltage doubling circuit module according to an exemplary embodiment of the present disclosure; Figure 2 is a schematic diagram of a conventional symmetrical voltage doubling circuit according to an exemplary embodiment of the present disclosure, Figure 3 is based on Figure 2 A schematic diagram of a charging process of a conventional symmetrical voltage doubler circuit in FIG. Figure 4 is based on Figure 2 Schematic diagram of another charging process of the conventional symmetrical voltage doubler circuit in. Figure 5 is based on Figure 2 Schematic diagram of a discharge process of a conventional symmetrical voltage doubler circuit.

[0072] For example, in the embodiments of the present disclosure, referring to Figure 1A , a high-voltage power supply 1000 is provided. The high-voltage power supply 1000 may include an AC power supply 100 and a voltage doubling circuit module 500. The voltage doubling circuit module 500 may include an AC signal input terminal Vac and a signal output terminal Vo. The AC power supply 100 is electrically connected to the AC signal input terminal Vac of the voltage doubling circuit module 500, and can provide a high-frequency AC voltage signal to the voltage doubling circuit module 500. The voltage doubling circuit module 500 can rectify and boost the received high-frequency AC voltage signal to obtain the DC high voltage required by the subsequent stage. In other words, the signal output terminal Vo of the voltage doubling circuit module 500 can output a DC high-voltage signal to the outside.

[0073] For example, refer to Figure 1B The voltage doubling circuit module 500 may include a voltage doubling circuit 200. The voltage doubling circuit 200 in the voltage doubling circuit module 500 may rectify and boost an AC voltage to obtain a high-voltage DC voltage.

[0074] For example, Figure 2 A conventional voltage doubling circuit 200 having a symmetrical structure is shown.

[0075] In the related art, refer to Figure 2The conventional symmetrical voltage multiplier circuit 200 includes a transformer T and an n-stage voltage multiplier unit VMC, where n is greater than or equal to 1. The transformer T is a transformer with a center tap. The n-stage voltage multiplier unit VMC includes a first-stage voltage multiplier unit VMC1, a second-stage voltage multiplier unit VMC2, ..., an n-th-stage voltage multiplier unit VMC n . Each stage of the voltage doubling unit can be electrically connected in parallel with the voltage doubling unit of the next stage, thereby forming a multi-stage voltage doubling unit. By increasing the number of stages of the n-stage voltage doubling unit VMC, the voltage value of the DC high voltage output by the voltage doubling circuit 200 can be increased, thereby meeting the application scenario requiring a higher voltage. By electrically connecting the center tap of the transformer T to the center point of the input end of the n-stage voltage doubling unit VMC, the center point of the input end of the n-stage voltage doubling unit VMC (for example, the second node N2) maintains a constant potential.

[0076] It should be noted that the "center tap" here refers to a termination form used in power transformers, mainly used in input windings and output windings. The center tap method is used in the input winding, which is to extract the midpoint of the input winding as the center point, and then form two branches by connecting this center point to the ground or other reference potential. These two branches can be connected to different power supply voltages respectively, so that the center point potential can be kept constant when the input voltage changes.

[0077] The conventional symmetrical voltage doubler circuit 200 further includes a load Ro. The load Ro may be a load with a relatively high withstand voltage, and the signal output terminal Vo of the voltage doubler circuit 200 may be electrically connected to both ends of the load Ro. That is, the voltage outputted by the signal output terminal Vo of the voltage doubler circuit 200 may be equal to the voltage across both ends of the load Ro.

[0078] In the conventional symmetrical voltage multiplier circuit 200, the voltage multiplier units of each stage may have the same circuit structure. Taking the first-stage voltage multiplier unit VMC1 as an example, the first-stage voltage multiplier unit VMC1 may include a capacitor C1_1, a capacitor C2_1, a capacitor C3_1, a diode D1_1, a diode D2_1, a diode D3_1, and a diode D4_1. For example, the diode D1_1, the diode D2_1, the diode D3_1, and the diode D4_1 may be diodes with a higher reverse peak voltage. The capacitor C1_1, the capacitor C2_1, and the capacitor C3_1 may be capacitors with a higher withstand voltage.

[0079] Exemplarily, the first plate of the capacitor C1_1, the cathode of the diode D1_1, and the anode of the diode D3_1 are all electrically connected to the first node N1.

[0080] Exemplarily, the anode of the diode D1_1, the first plate of the capacitor C2_1, and the anode of the diode D2_1 are all electrically connected to the second node N2.

[0081] Exemplarily, the cathode of the diode D3_1, the second plate of the capacitor C2_1, and the cathode of the diode D4_1 are all electrically connected to the third node N3.

[0082] Exemplarily, the cathode of the diode D2_1, the anode of the diode D4_1, and the first plate of the capacitor C3_1 are all electrically connected to the fourth node N4.

[0083] Exemplarily, the second plate of capacitor C1_1 (eg Figure 2 As shown, the left plate of capacitor C1_1) and the second plate of capacitor C3_1 (as shown Figure 2 As shown, the left plate of capacitor C3_1 is electrically connected to the second node N2. For example, the second plate of capacitor C1_1 and the second plate of capacitor C3_1 can be electrically connected to the second node N2 through a transformer T.

[0084] The following will be combined Figure 3-Figure 5 The working process of a conventional symmetrical voltage doubler circuit is briefly described.

[0085] For example, in one cycle, the working process of the conventional symmetrical voltage doubler circuit may include four processes, of which two are charging processes and two are discharging processes. The working process of the first-stage voltage doubler unit VMC1 will be taken as an example for description.

[0086] During the first charging process, refer to Figure 3 , the AC signal inputted by the AC signal input terminal Vac is in the positive half cycle, the current I1 flows through the capacitor C1_1, the diode D3_1 and the capacitor C2_1 in sequence; and the current I2 flows through the diode D2_1 and the capacitor C3_1 in sequence. The current I1 and the current I2 can be currents of substantially equal magnitude and the same direction. This process can charge the capacitors C1_1, C2_1 and C3_1.

[0087] In the second charging process, refer to Figure 4 , the AC signal inputted by the AC signal input terminal Vac is in the negative half cycle, the current I3 flows through the diode D1_1 and the capacitor C1_1 in sequence; and the current I4 flows through the capacitor C3_1, the diode D4_1 and the capacitor C2_1 in sequence. The current I3 and the current I4 can be currents of substantially equal magnitude and the same direction. This process can charge the capacitors C1_1, C2_1 and C3_1.

[0088] Combined with reference Figure 3 and Figure 4, the current I1 and the current I4 can be currents of substantially equal magnitude and opposite directions. The charging direction of the capacitor C1_1 in the positive half cycle is opposite to that in the negative half cycle, so the charges on the capacitor plate of the capacitor C1_1 can offset or neutralize each other in the two charging processes (e.g., the first charging process and the second charging process), so that the accumulated voltage stored in the capacitor C1_1 is small.

[0089] Similarly, the charging direction of capacitor C3_1 in the positive half cycle is opposite to that in the negative half cycle, so the charges on the capacitor plate of capacitor C3_1 can offset or neutralize each other in two charging processes (such as the first charging process and the second charging process), so that the accumulated voltage stored in capacitor C3_1 is smaller.

[0090] Continue to combine references Figure 3 and Figure 4 , the charging direction of capacitor C2_1 in the positive half cycle is the same as that in the negative half cycle. Figure 3 The intermediate current I1 flows into the second plate of the capacitor C2_1 (the plate on the right side of the capacitor C2_1 ), and then flows out from the first plate of the capacitor C2_1 (the plate on the left side of the capacitor C2_1 ). Figure 4 The current I4 flows into the second plate of the capacitor C2_1 and then flows out from the first plate of the capacitor C2_1. That is, the charging direction of the capacitor C2_1 in the positive half cycle is the same as that in the negative half cycle, so that the capacitor C2_1 can store a higher voltage in a complete cycle.

[0091] Exemplarily, the charging process of each level of the n-level voltage multiplier unit VMC is substantially the same as the charging process of the first-level voltage multiplier unit VMC1. Therefore, in a complete cycle, the capacitor C2_1 and the capacitors C2_2, ..., and C2_n can all store a relatively high voltage.

[0092] Exemplarily, the two discharge processes of the voltage doubler circuit may correspond to the two charging processes respectively. That is, the two discharge processes of the voltage doubler circuit may correspond to the positive half cycle and the negative half cycle of the AC power supply respectively. Since the charging processes of capacitor C2_1 and capacitor C2_2, ..., capacitor C2_n in the positive half cycle and the negative half cycle of the AC power supply are substantially the same, the equivalent circuits of the two discharge processes of the voltage doubler circuit may be substantially the same. For example, referring to Figure 5 , the discharge circuit of the voltage doubler circuit can be equivalent to: capacitor C2_1 and capacitor C2_2, ..., capacitor C2_n are connected in series and then connected to load Ro, providing a higher voltage output for load Ro. By increasing the number of n-stage voltage doubler units VMC, the voltage doubler circuit can provide a higher DC voltage.

[0093] The conventional symmetrical voltage doubler circuit 200 is composed of n cascaded voltage doubler units, and the transformer ratio is 1:N:N. Then, the voltage boost ratio of the conventional symmetrical voltage doubler circuit under no-load condition is 2Nn. A higher voltage boost ratio can be achieved by adjusting the transformer ratio N and the number of voltage doubler units n.

[0094] The inventor has found through research that in a conventional symmetrical voltage doubler circuit, when under load, the capacitors of each voltage doubler unit will produce a certain voltage drop, resulting in a decrease in the final output voltage. o , the frequency of the input voltage signal is f s , the equivalent voltage value of the input AC voltage is V ac , the capacitance value of each voltage doubling unit is the same and is C, then the output voltage of the conventional symmetrical voltage doubling circuit under load is:

[0095] (1)

[0096] From the above formula, we can see that as the output current I o The output voltage V of the conventional symmetrical voltage doubler circuit increases o1 The voltage is reduced, resulting in a decrease in load capacity, so it is often used in high-voltage and low-power applications. In addition, in conventional symmetrical voltage doubler circuits, the secondary side of the transformer T requires a center tap structure, which is complex and difficult to design, and is not conducive to insulation design and circuit structure design in practical applications.

[0097] At least one embodiment of the present disclosure provides a voltage doubling circuit. By combining a rectifier bridge and two cascaded voltage doubling units, the voltage step-up ratio of the circuit can be improved, while reducing the number of stages of a single cascaded voltage doubling unit, reducing the number of voltage doubling capacitors, and improving the circuit's load capacity and dynamic response performance. At the same time, the transformer can use a conventional non-center-tapped transformer, which has a simple structure, can simplify the structure of the entire circuit, and reduce costs.

[0098] Figure 6 is a structural block diagram of a voltage doubling circuit according to an exemplary embodiment of the present disclosure.

[0099] For example, refer to Figure 6 , an embodiment of the present disclosure provides a voltage doubling circuit 200. The voltage doubling circuit 200 may include: a transformer T, a full-bridge rectifier module ADC, a voltage doubling module VM and a load Ro.

[0100] The transformer T may include a primary side T1 and a secondary side T2 , and two ends of the primary side T1 are respectively configured to be connected to two ends of an AC power source.

[0101] Exemplarily, the structure of the transformer T may be a structure without a center tap. The structure of a transformer without a center tap is simple, which can simplify the structure of the entire circuit and reduce costs.

[0102] Exemplarily, the full-bridge rectifier module ADC may include a first input terminal Vi1 and a second input terminal Vi2. The first input terminal Vi1 and the second input terminal Vi2 of the full-bridge rectifier module are respectively configured to connect two ends of the secondary side T2.

[0103] The full-bridge rectifier module ADC may also include a first rectifier bridge arm ADC1 and a second rectifier bridge arm ADC2. The first rectifier bridge arm ADC1 includes a first connection terminal ADC11, a third connection terminal ADC13 and a first output terminal VAo1. The first connection terminal ADC11 and the third connection terminal ADC13 of the first rectifier bridge arm ADC1 are respectively connected to the first input terminal Vi1 and the second input terminal Vi2 of the full-bridge rectifier module ADC. In other words, the first connection terminal ADC11 and the third connection terminal ADC13 of the first rectifier bridge arm ADC1 are respectively connected to the two ends of the secondary side T2 of the transformer, and the secondary side T2 of the transformer can provide an AC voltage signal for the first rectifier bridge arm ADC1.

[0104] The second rectifier bridge arm ADC2 includes a fourth connection terminal ADC24, a sixth connection terminal ADC26 and a second output terminal VAo2. The fourth connection terminal ADC24 and the sixth connection terminal ADC26 of the second rectifier bridge arm ADC2 are respectively connected to the first input terminal Vi1 and the second input terminal Vi2 of the full-bridge rectifier module ADC. In other words, the fourth connection terminal ADC24 and the sixth connection terminal ADC26 of the second rectifier bridge arm ADC2 can also be respectively connected to the two ends of the secondary side T2 of the transformer, and the secondary side T2 of the transformer can provide an AC voltage signal for the second rectifier bridge arm ADC2.

[0105] Exemplarily, the voltage doubling module VM may include a first voltage doubling unit VM1 and a second voltage doubling unit VM2. The input terminal VMi1 of the first voltage doubling unit VM1 is electrically connected to the first output terminal VAo1 of the first rectifier bridge arm ADC1, and the input terminal VMi2 of the second voltage doubling unit VM2 is electrically connected to the second output terminal VAo2 of the second rectifier bridge arm ADC2. Through such a design, the full-bridge rectifier module ADC can transmit the AC voltage signal provided by the secondary side T2 of the transformer to the first voltage doubling unit VM1 and the second voltage doubling unit VM2, respectively.

[0106] Exemplarily, one end of the load Ro is electrically connected to the output end VMo1 of the first voltage doubling unit VM1 , and the other end of the load Ro is electrically connected to the output end VMo2 of the second voltage doubling unit VM2 .

[0107] Exemplarily, the full-bridge rectifier module ADC may further include a storage unit ADC3. For example, the storage unit ADC3 may include a capacitor.

[0108] The load Ro, the first voltage doubler unit VM1, and the second voltage doubler unit VM2 can form a series path through the full-bridge rectifier module ADC, so that the voltages stored in the first voltage doubler unit VM1, the second voltage doubler unit VM2, and the full-bridge rectifier module ADC can be applied to both ends of the load Ro together to provide a high-voltage DC voltage for the load Ro.

[0109] Figure 7 is a schematic diagram of a voltage doubling circuit according to an exemplary embodiment of the present disclosure, Fig. 8A is a partial circuit diagram of a voltage doubling circuit according to an exemplary embodiment of the present disclosure, wherein a first rectifying bridge arm and a first voltage doubling unit are shown; Figure 8B is a partial circuit diagram of a voltage doubling circuit according to an exemplary embodiment of the present disclosure, in which a second rectifier bridge arm and a second voltage doubling unit are shown.

[0110] For example, in the embodiments of the present disclosure, referring to Figure 7 The full-bridge rectifier module ADC includes a first input terminal Vi1 and a second input terminal Vi2. The first input terminal Vi1 and the second input terminal Vi2 of the full-bridge rectifier module are respectively configured to connect two ends of the secondary side T2.

[0111] The full-bridge rectifier module ADC may further include a first rectifier bridge arm ADC1 and a second rectifier bridge arm ADC2.

[0112] The first rectifying bridge arm ADC1 may include a first connection terminal ADC11, a third connection terminal ADC13 and a first output terminal VAo1. The first connection terminal ADC11 and the third connection terminal ADC13 of the first rectifying bridge arm ADC1 are respectively connected to the first input terminal Vi1 and the second input terminal Vi2 of the full-bridge rectifier module ADC. The first output terminal VAo1 of the first rectifying bridge arm ADC1 is electrically connected to the input terminal VMi1 of the first voltage doubling unit VM1.

[0113] The first rectifier bridge arm ADC1 may further include a first diode D1, a second diode D2, and a second connection terminal ADC12. The anode of the first diode D1 is electrically connected to the first connection terminal ADC11, the cathode of the first diode D1 and the cathode of the second diode D2 are both electrically connected to the second connection terminal ADC12, and the anode of the second diode D2 is electrically connected to the third connection terminal ADC13.

[0114] The second rectifier bridge arm ADC2 includes a fourth connection terminal ADC24, a sixth connection terminal ADC26, and a second output terminal VAo2. The fourth connection terminal ADC24 and the sixth connection terminal ADC26 of the second rectifier bridge arm ADC2 are respectively connected to the first input terminal Vi1 and the second input terminal Vi2 of the full-bridge rectifier module ADC. The second output terminal VAo2 of the second rectifier bridge arm ADC2 is electrically connected to the input terminal VMi2 of the second voltage doubling unit VM2.

[0115] The second rectifier bridge arm ADC2 further includes a third diode D3, a fourth diode D4 and a fifth connection terminal ADC25. The cathode of the third diode D3 is electrically connected to the fourth connection terminal ADC24, the anode of the third diode D3 and the anode of the fourth diode D4 are both electrically connected to the fifth connection terminal ADC25, and the cathode of the fourth diode D4 is electrically connected to the sixth connection terminal ADC26.

[0116] For example, in conjunction with reference Figure 6 and Figure 7 The full-bridge rectifier module ADC may further include a storage unit ADC3, which may include a first capacitor C1. The first plate of the first capacitor C1 is electrically connected to the second connection terminal ADC12 of the first rectifier bridge arm ADC1, and the second plate of the first capacitor C1 is electrically connected to the fifth connection terminal ADC25 of the second rectifier bridge arm ADC2.

[0117] For example, refer to Fig. 8A The first output terminal VAo1 of the first rectifying bridge arm ADC1 may include a first sub-output terminal VAo11, a second sub-output terminal VAo12, and a third sub-output terminal VAo13. The first sub-output terminal VAo11 is electrically connected to the first connection terminal ADC11, the second sub-output terminal VAo12 is electrically connected to the second connection terminal ADC12, and the third sub-output terminal VAo13 is electrically connected to the third connection terminal ADC13.

[0118] For example, in conjunction with reference Figure 7 and Fig. 8A The first voltage doubling unit VM1 includes p-stage cascaded first voltage doubling subunits. For example, the first voltage doubling unit VM1 includes a first-stage first voltage doubling subunit VMC a1 , the second stage first voltage multiplier unit VMC a2 , ..., the first voltage multiplier unit VMC of the pth level ap Each level of the first voltage doubling subunit includes a fourth input terminal, a fifth input terminal, a sixth input terminal, a fourth output terminal, a fifth output terminal and a sixth output terminal. The fourth output terminal, the fifth output terminal and the sixth output terminal of the first voltage doubling subunit of the previous level are electrically connected to the fourth input terminal, the fifth input terminal and the sixth input terminal of the first voltage doubling subunit of the next level, respectively, so as to realize a p-level cascade.

[0119] For example, in conjunction with reference Figure 7 and Fig. 8A , the first stage first voltage multiplier unit VMC a1 The fourth input terminal VI 14 , the fifth input terminal VI 15 and the sixth input terminal VI 16The first voltage doubling subunit VMC is electrically connected to the first output terminal VAo11, the second output terminal VAo12 and the third output terminal VAo13 of the first rectifying bridge arm ADC1. a(i+1) The fourth input terminal VI (i+1)4 , the fifth input terminal VI (i+1)5 and the sixth input terminal VI (i+1)6 Respectively with the first voltage multiplier unit VMC of the i-th level ai The fourth output terminal VO i4 , the fifth output terminal VO i5 and the sixth output terminal VO i6 Wherein, i is a positive integer greater than or equal to 1 and less than or equal to p-1, and p is a positive integer greater than or equal to 2.

[0120] For example, in conjunction with reference Figure 7 and Figure 8B The second output terminal VAo2 of the second rectifying bridge arm ADC2 may include a fourth sub-output terminal VAo24, a fifth sub-output terminal VAo25, and a sixth sub-output terminal VAo26. The fourth sub-output terminal VAo24 is electrically connected to the fourth connection terminal ADC24, the fifth sub-output terminal VAo25 is electrically connected to the fifth connection terminal ADC25, and the sixth sub-output terminal VAo26 is electrically connected to the sixth connection terminal ADC26.

[0121] For example, in conjunction with reference Figure 7 and Figure 8B The second voltage doubling unit VM2 includes m-stage cascaded second voltage doubling subunits. For example, the second voltage doubling unit VM2 may include a first-stage second voltage doubling subunit VMC. b1 , the second stage second voltage multiplier unit VMC b2 , ..., the mth level second voltage multiplier unit VMC bm Each level of the second voltage doubling subunit includes a seventh input terminal, an eighth input terminal, a ninth input terminal, a seventh output terminal, an eighth output terminal and a ninth output terminal. The seventh output terminal, the eighth output terminal and the ninth output terminal of the second voltage doubling subunit of the previous level are electrically connected to the seventh input terminal, the eighth input terminal and the ninth input terminal of the second voltage doubling subunit of the next level, respectively, so as to realize m-level cascade.

[0122] For example, in conjunction with reference Figure 7 and Figure 8B , the first stage second voltage multiplier unit VMC b1 The seventh input terminal VI 17 , the eighth input terminal VI 18 and the ninth input terminal VI 19The seventh input terminal VI of the second voltage doubling sub-unit of the j+1th stage is electrically connected to the fourth sub-output terminal VAo24, the fifth sub-output terminal VAo25 and the sixth sub-output terminal VAo26 of the second rectifying bridge arm ADC2. (j+1)7 , the eighth input terminal VI (j+1)8 and the ninth input terminal VI (j+1)9 and the seventh output terminal VO of the second voltage doubling subunit of the jth stage, respectively. j7 , the eighth output terminal VO j8 and the ninth output terminal VO j9 Wherein, j is a positive integer greater than or equal to 1 and less than or equal to m-1, and m is a positive integer greater than or equal to 2.

[0123] For example, continue to refer to Figure 7 , the first voltage multiplier unit VMC of the pth level ap The fifth output terminal VO p5 The m-th level second voltage multiplier unit VMC is electrically connected to one end of the load Ro. bm The eighth output terminal VO m8 The other end of the load Ro is electrically connected. That is, the first voltage multiplication subunit VMC of the pth stage can be ap The fifth output terminal VO p5 As the output terminal VMo1 of the first voltage doubling unit VM1, the mth level second voltage doubling subunit VMC bm The eighth output terminal VO m8 Serves as the output terminal VMo2 of the second voltage doubling unit VM2.

[0124] Exemplarily, the first voltage doubling unit VM1 and the second voltage doubling unit VM2 may each include a symmetrical voltage doubling circuit. Figure 2 The n-stage voltage multiplying units VMC in the conventional symmetrical voltage multiplying circuit shown have the same or similar structure.

[0125] For example, refer to Figure 7 The first voltage doubling unit VM1 may include p-stage cascaded first voltage doubling sub-units, where p is a positive integer greater than or equal to 2. Each stage of the first voltage doubling sub-units may have the same circuit structure.

[0126] For example, in conjunction with reference Figure 2 and Fig. 8A The structure of the first voltage doubling subunit in the first voltage doubling unit VM1 can be the same as Figure 2 The structures of the first-stage voltage multiplying unit VMC1 in the n-stage voltage multiplying units VMC in the conventional symmetrical voltage multiplying circuit shown are the same.

[0127] For example, refer to Fig. 8A , the first voltage multiplier unit VMC of the i-th levelai An eleventh capacitor C may be included a1-i 、The twenty-first capacitor C a2-i 、The thirty-first capacitor C a3-i 11th diode D a1-i 、The twenty-first diode D a2-i 、The thirty-first diode D a3-i and the forty-first diode D a4-i , i is a positive integer greater than or equal to 1.

[0128] For example, the eleventh capacitor C a1-i The first electrode plate and the first voltage multiplication subunit VMC of the i-th stage ai The fourth input terminal VI i4 Electrical connection, eleventh capacitor C a1-i The second plate and the first voltage multiplication subunit VMC of the i-th stage ai The fourth output terminal VO i4 Electrical connection.

[0129] Exemplarily, the twenty-first capacitor C a2-i The first electrode plate and the first voltage multiplication subunit VMC of the i-th stage ai The fifth input terminal VI i5 Electrical connection, the twenty-first capacitor C a2-i The second plate and the first voltage multiplication subunit VMC of the i-th stage ai The fifth output terminal VO i5 Electrical connection.

[0130] Exemplarily, the thirty-first capacitor C a3-i The first electrode plate and the first voltage multiplication subunit VMC of the i-th stage ai The sixth input terminal VI i6 Electrical connection, the thirty-first capacitor C a3-i The second plate and the first voltage multiplication subunit VMC of the i-th stage ai The sixth output terminal VO i6 Electrical connection.

[0131] For example, the eleventh diode D a1-i The cathode and the first voltage multiplier unit VMC of the i-th stage ai The fourth output terminal VO i4 Electrical connection, eleventh diode D a1-i The anode and the first voltage multiplier unit VMC of the i-th stage ai The fifth input terminal VI i5 Electrical connection.

[0132] Exemplarily, the twenty-first diode D a2-i The anode and the first voltage multiplier unit VMC of the i-th stage ai The fourth output terminal VOi4 Electrical connection, the twenty-first diode D a2-i The cathode and the first voltage multiplier unit VMC of the i-th stage ai The fifth output terminal VO i5 Electrical connection.

[0133] Exemplarily, the thirty-first diode D a3-i The anode and the first voltage multiplier unit VMC of the i-th stage ai The fifth input terminal VI i5 Electrical connection, the thirty-first diode D a3-i The cathode and the first voltage multiplier unit VMC of the i-th stage ai The sixth output terminal VO i6 Electrical connection.

[0134] Exemplarily, the forty-first diode D a4-i The cathode and the first voltage multiplier unit VMC of the i-th stage ai The fifth output terminal VO i5 Electrical connection, forty-first diode D a4-i The anode and the first voltage multiplier unit VMC of the i-th stage ai The sixth output terminal VO i6 Electrical connection.

[0135] In some embodiments, the second voltage doubling unit VM2 may include m stages of cascaded second voltage doubling sub-units, where m is a positive integer greater than or equal to 2. Each stage of the second voltage doubling sub-units may have the same circuit structure.

[0136] For example, in combination Fig. 8A and Figure 8B The circuit structure of the second voltage doubling subunit in the second voltage doubling unit VM2 may be similar to the circuit structure of the first voltage doubling subunit in the first voltage doubling unit VM1. For example, the j-th level second voltage doubling subunit may also include three capacitors C b1-j , C b2-j and C b3-j And four diodes D b1-j , D b2-j , D b3-j and D b4-j .

[0137] The circuit structure of the first voltage doubling subunit in the first voltage doubling unit VM1 is different in that: Figure 8B The positive and negative electrodes of the four diodes of the second voltage doubling subunit in the second voltage doubling unit VM2 are connected to Fig. 8A The positive and negative poles of the four diodes of the first voltage doubling sub-unit in the first voltage doubling unit VM1 are in opposite directions.

[0138] For example, the capacitor C b1-jThe first plate and the j-th second voltage multiplier unit VMC bj The seventh input terminal VI j7 Electrical connection, capacitor C b1-j The second plate and the j-th second voltage multiplying subunit VMC bj The seventh output terminal VO j7 Electrical connection.

[0139] For example, the capacitor C b2-j The first plate and the j-th second voltage multiplier unit VMC bj The eighth input terminal VI j8 Electrical connection, capacitor C b2-j The second plate and the j-th second voltage multiplying subunit VMC bj The eighth output terminal VO j8 Electrical connection.

[0140] For example, the capacitor C b3-j The first plate and the j-th second voltage multiplier unit VMC bj The ninth input terminal VI j9 Electrical connection, capacitor C b3-j The second plate and the j-th second voltage multiplying subunit VMC bj The ninth output terminal VO j9 Electrical connection.

[0141] For example, the diode D b1-j The anode and the j-th second voltage multiplier unit VMC bj The seventh output terminal VO j7 Electrical connection, diode D b1-j The cathode and the j-th second voltage multiplier unit VMC bj The eighth input terminal VI j8 Electrical connection.

[0142] For example, the diode D b2-j The cathode and the j-th second voltage multiplier unit VMC bj The seventh output terminal VO j7 Electrical connection, diode D b2-j The anode and the j-th second voltage multiplier unit VMC bj The eighth output terminal VO j8 Electrical connection.

[0143] For example, the diode D b3-j The cathode and the j-th second voltage multiplier unit VMC bj The eighth input terminal VI j8 Electrical connection, diode D b3-j The anode and the j-th second voltage multiplier unit VMC bj The ninth output terminal VOj9 Electrical connection.

[0144] For example, the diode D b4-j The anode and the j-th second voltage multiplier unit VMC bj The eighth output terminal VO j8 Electrical connection, diode D b4-j The cathode and the j-th second voltage multiplier unit VMC bj The ninth output terminal VO j9 Electrical connection.

[0145] It should be noted that, although the embodiments of the present disclosure show that the first voltage doubling subunit in the first voltage doubling unit includes three capacitors and four diodes, and the embodiments of the present disclosure show that the second voltage doubling subunit in the second voltage doubling unit includes three capacitors and four diodes, the embodiments of the present disclosure are not limited thereto. In the embodiments of the present disclosure, the first voltage doubling subunit and the second voltage doubling subunit can adopt various voltage doubling circuit structure designs known in the art.

[0146] In some embodiments, the number of cascaded first voltage doubling subunits included in the first voltage doubling unit VM1 may be equal to the number of cascaded second voltage doubling subunits included in the second voltage doubling unit VM2. Figure 7 In the illustrated embodiment, the first voltage doubling unit VM1 includes p-stage cascaded first voltage doubling sub-units, and the second voltage doubling unit VM2 includes m-stage cascaded second voltage doubling sub-units, where P may be equal to m.

[0147] Through such a design, the charging and discharging efficiencies of the first voltage doubling unit VM1 and the second voltage doubling power source VM2 can be made more consistent, thereby improving the charging and discharging efficiency of the overall voltage doubling module.

[0148] Fig. 9 is based on Figure 7 A schematic diagram of a charging process of a voltage doubler circuit of an exemplary embodiment, Fig.10 is based on Figure 7 A schematic diagram of another charging process of a voltage doubler circuit of an exemplary embodiment, Fig.11 is based on Figure 7 A schematic diagram of a discharge process of a voltage doubler circuit of an exemplary embodiment.

[0149] In some embodiments, the first voltage doubling unit VM1 may include n-stage cascaded first voltage doubling subunits, and the second voltage doubling unit VM2 may include n-stage cascaded second voltage doubling subunits. The charging process of the voltage doubling circuit 200 may include a positive half-cycle charging process and a negative half-cycle charging process.

[0150] For example, for the charging process of the positive half cycle, refer to Fig. 9 , in the full-bridge rectifier module, the current I0-1 It flows in from the first input terminal Vi1 of the full-bridge rectifier module ADC, flows through the first diode D1, the first capacitor C1 and the fourth diode D4 in sequence, and finally flows into the second input terminal Vi2 of the full-bridge rectifier module ADC. a1-1 It flows in from the first input terminal Vi1 of the full-bridge rectifier module ADC and flows through the capacitor C a1-1 、Diode D a2-1 , capacitor C a2-1 、Diode D a3-1 , capacitor C a3-1 , and finally flows into the second input terminal Vi2 of the full-bridge rectifier module ADC. By analogy, the current I an-1 It flows in from the first input terminal Vi1 of the full-bridge rectifier module ADC and flows through the capacitor C a1-n 、Diode D a2-n , capacitor C a2-n 、Diode D a3-n , capacitor C a3-n , and finally flows into the second input terminal Vi2 of the full-bridge rectifier module ADC. In the second voltage doubling unit, the current I b1-1 It flows in from the first input terminal Vi1 of the full-bridge rectifier module ADC and flows through the capacitor C b1-1 、Diode D b1-1 , capacitor C b2-1 、Diode D b4-1 , capacitor C b3-1 , and finally flows into the second input terminal Vi2 of the full-bridge rectifier module ADC. By analogy, the current I bn-1 It flows in from the first input terminal Vi1 of the full-bridge rectifier module ADC and flows through the capacitor C b1-n 、Diode D b1-n , capacitor C b2-n 、Diode D b4-n , capacitor C b3-n , and finally flows into the second input terminal Vi2 of the full-bridge rectifier module ADC.

[0151] For example, for the charging process of the negative half cycle, refer to Fig.10 , in the full-bridge rectifier module, the current I 0-2 The current I flows from the second input terminal Vi2 of the full-bridge rectifier module ADC, flows through the second diode D2, the first capacitor C1 and the third diode D3 in sequence, and finally flows into the first input terminal Vi1 of the full-bridge rectifier module ADC. a1-2 It flows in from the second input terminal Vi2 of the full-bridge rectifier module ADC and flows through the capacitor C a3-1 、Diode D a4-1 , capacitor C a2-1 、Diode D a1-1 , capacitor Ca1-1 , and finally flows into the first input terminal Vi1 of the full-bridge rectifier module ADC. By analogy, the current I an-2 It flows in from the second input terminal Vi2 of the full-bridge rectifier module ADC and flows through the capacitor C a3-n 、Diode D a4-n , capacitor C a2-n 、Diode D a1-n , capacitor C a1-n , and finally flows into the first input terminal Vi1 of the full-bridge rectifier module ADC. In the second voltage doubling unit, the current I b1-2 It flows in from the second input terminal Vi2 of the full-bridge rectifier module ADC and flows through the capacitor C b3-1 、Diode D b3-1 , capacitor C b2-1 、Diode D b2-1 , capacitor C b1-1 , and finally flows into the first input terminal Vi1 of the full-bridge rectifier module ADC. By analogy, the current I bn-2 It flows in from the second input terminal Vi2 of the full-bridge rectifier module ADC and flows through the capacitor C b3-n 、Diode D b3-n , capacitor C b2-n 、Diode D b2-n , capacitor C b1-n , and finally flows into the first input terminal Vi1 of the full-bridge rectifier module ADC.

[0152] In some embodiments, the full-bridge rectifier module ADC, the first voltage doubling unit VM1 and the second voltage doubling unit VM2 can be symmetrically designed. Fig. 9 and Fig.10 , current I a1-1 and I a1-2 It can be a current of substantially equal magnitude and opposite direction. an-1 and I an-2 It can be a current of substantially equal magnitude and opposite direction. b1-1 and I b1-2 It can be a current of substantially equal magnitude and opposite direction. bn-1 and I bn-2 The currents may be substantially equal in magnitude and opposite in direction.

[0153] Therefore, during the charging process, the capacitor C a1-1 ,…,C a1-n , capacitor C a3-1 ,…,C a3-n , capacitor C b1-1 ,…,C b1-n and capacitor C b3-1 ,…,C b3-nThe current direction in the positive half cycle is opposite to the current direction in the negative half cycle. That is to say, in a complete charging cycle, the capacitor C a1-1 ,…,C a1-n , capacitor C a3-1 ,…,C a3-n , capacitor C b1-1 ,…,C b1-n and capacitor C b3-1 ,…,C b3-n The multiple capacitors will basically not accumulate charge during the charging process.

[0154] Capacitor C a2-1 ,…,C a2-n and capacitor C b2-1 ,…,C b2-n And the first capacitor C1 in the full-bridge rectifier module ADC has the same current direction in the positive half cycle as in the negative half cycle. Therefore, in a complete charging cycle, the capacitor C a2-1 ,…,C a2-n and capacitor C b2-1 ,…,C b2-n And the first capacitor C1 in the full-bridge rectifier module ADC can store more charges, thereby providing a higher DC output voltage for the load Ro.

[0155] During the discharge process, the equivalent circuit of the voltage doubler circuit can be referred to Fig.11 , capacitor C a2-1 ,…,C a2-n and the first capacitor C1 and the capacitor C b2-1 ,…,C b2-n After the series connection, the load Ro is connected in series. Therefore, in the voltage doubling circuit of the embodiment of the present disclosure, when the first voltage doubling unit VM1 includes n-stage cascaded first voltage doubling subunits, and the second voltage doubling unit VM2 includes n-stage cascaded second voltage doubling subunits, the voltage boost ratio of the voltage doubling circuit is as follows:

[0156] ratio=V out / V ac =2N(2n+1),

[0157] Among them, ratio represents the voltage boost ratio of the voltage doubler circuit, V out Indicates the voltage value of the DC voltage output by the voltage doubler circuit, V ac It represents the equivalent voltage value of the AC voltage input by the AC power supply, 2N represents the transformation ratio of the transformer, and n represents the number of stages of the first voltage doubling unit and the second voltage doubling unit.

[0158] In order to distinguish from a conventional symmetrical voltage doubler circuit, the voltage doubler circuit according to the embodiment of the present disclosure is referred to as a novel voltage doubler circuit hereinafter.

[0159] Compared with the conventional symmetrical voltage doubler circuit, in the novel voltage doubler circuit of the embodiment of the present disclosure, when Figure 7 The number of stages of the first voltage doubling unit VM1 and the second voltage doubling unit VM2 shown in FIG. Figure 2 When the number of stages of the voltage multiplier units VMC in the conventional symmetrical voltage multiplier circuit shown is n, the voltage boost ratio of the novel voltage multiplier circuit in the embodiment of the present disclosure is 2N(2n+1), which is more than twice the voltage boost ratio (2Nn) of the conventional symmetrical voltage multiplier circuit.

[0160] Through such a design, the overall boost ratio of the voltage doubler circuit can be greatly improved while ensuring that the number of stages of a single cascade voltage doubler unit does not increase.

[0161] Based on this, if the same boost ratio as that of a conventional symmetrical voltage doubler circuit needs to be achieved, the number of stages of the first voltage doubler unit VM1 and the second voltage doubler unit VM2 may be less than 1 / 2 of the number of stages of the voltage doubler unit VMC in the conventional symmetrical voltage doubler circuit.

[0162] For example, the number of stages of the first voltage multiplier unit VM1 and the second voltage multiplier unit VM2 is m, and at this time, the voltage boost ratio of the novel voltage multiplier circuit of the embodiment of the present disclosure is 2N(2m+1). When the number of stages of the voltage multiplier unit VMC of the conventional symmetrical voltage multiplier circuit is n, the voltage boost ratio of the conventional symmetrical voltage multiplier circuit is 2Nn.

[0163] Assuming that the voltage boost ratio of the novel voltage doubler circuit of the embodiment of the present disclosure is equal to the voltage boost ratio of the conventional symmetrical voltage doubler circuit, that is, 2N(2m+1)=2Nn, then m=(n-1) / 2. Therefore, the number of stages of the first voltage doubler unit and the second voltage doubler unit can be reduced by the voltage doubler circuit of the embodiment of the present disclosure.

[0164] For example, in conjunction with reference Figure 7 and Figure 9-11 In the charging mode, the voltage doubling capacitors (e.g., capacitor C a2-1 ,…,C a2-n and capacitor C b2-1 ,…,C b2-n ) are charged in parallel; in the discharge mode, each voltage doubling capacitor is discharged in series. Since there is no series charging and parallel discharge circuit in the full-bridge rectifier module ADC, there is no voltage drop under load, so the voltage loss under load can be reduced.

[0165] In the novel voltage doubling circuit of the embodiment of the present disclosure, return to reference Figure 7 , when the number of stages of the first voltage doubling unit VM1 and the second voltage doubling unit VM2 are both m, assuming that the current flowing through the load Ro is Io, the total voltage drop of the subsequent m-stage voltage doubling units is:

[0166] (2)

[0167] Among them, △V oa represents the total voltage drop of the m-level first voltage-doubling subunits of the first voltage-doubling unit VM1, △V ob It represents the total voltage drop of m-stage second voltage doubling sub-units of the second voltage doubling unit VM2.

[0168] Assuming that the transformation ratio of the transformer T is 2N, the output voltage of the novel voltage doubling circuit of the embodiment of the present disclosure is:

[0169] (3)

[0170] For a conventional symmetrical voltage doubler rectifier circuit, in order to achieve the same boost ratio, the number of secondary stages is n=2m+1. Combined with reference formula (1), the output voltage when the load current is Io is:

[0171] (4)

[0172] By comparing formula (3) and formula (4), it can be found that as the number of circuit levels increases, the output voltage drop loss of the new voltage doubler circuit provided by the embodiment of the present disclosure is greatly reduced compared with the conventional symmetrical voltage doubler circuit. Therefore, the new voltage doubler circuit provided by the embodiment of the present disclosure has better load capacity and output voltage adjustment performance, and is particularly suitable for applications with relatively high power.

[0173] Figures 12A-12C Schematic diagrams comparing the dynamic characteristics of a novel voltage doubler circuit according to an embodiment of the present disclosure and a conventional symmetrical voltage doubler circuit.

[0174] The above two circuits are compared and analyzed with the help of a design embodiment. The main parameters of the design embodiment are shown in Table 1, which shows the simulation waveforms of the two circuits under different load conditions (0.5kW, 2kW, 5kW).

[0175] Table 1 Main parameters of the circuit of the design example

[0176] parameter Numeric Input voltage 100V Input voltage frequency 100kHz No-load output voltage 6kV Rated Power 5kW Voltage doubler capacitor 200nF

[0177] Exemplarily, a conventional symmetrical voltage doubler circuit adopts a three-stage voltage doubler with a transformer ratio of 1:10:10; the novel voltage doubler circuit of the embodiment of the present disclosure adopts a full-bridge rectification and a one-stage voltage doubler with a transformer ratio of 1:20.

[0178] For example, Figures 12A-12C The simulation waveforms of the two circuits under different load conditions (0.5kW, 2kW, 5kW) are shown respectively, where V o1 is the output voltage of a conventional symmetrical voltage doubler circuit, V o2is the output voltage of the novel voltage doubler circuit of the embodiment of the present disclosure, V ac is the input AC voltage. Fig. 12A The rated power is 0.5kW. Fig. 12B The rated power is 2kW, Fig. 12C The rated power in the circuit is 5kW. By comparison, we can see that as the rated power increases, the output voltage V o1 The output voltage V of the novel voltage doubler circuit of the embodiment of the present disclosure is significantly reduced. o2 There was basically no decline.

[0179] It can be seen from this that as the output load increases, the output voltage drop of the conventional symmetrical voltage doubler circuit increases significantly, while the voltage drop of the new voltage doubler circuit in the embodiment of the present invention is much smaller than that of the conventional symmetrical voltage doubler rectifier circuit. Therefore, the new voltage doubler circuit in the embodiment of the present invention is suitable for occasions with high requirements on the stability of the output voltage.

[0180] The voltage doubler circuit of the embodiment of the present disclosure has a small output voltage drop loss under different load conditions, has better voltage regulation performance, and can be applied to high voltage and high power applications.

[0181] For example, in the novel voltage doubler circuit of the embodiment of the present disclosure, since the full-bridge rectifier circuit does not have a series charging and parallel discharging operation mode, its dynamic characteristics are better than those of a conventional symmetrical voltage doubler circuit. Figures 12A-12C The transient response time of the novel voltage doubler circuit of the embodiment of the present disclosure is about 0.07ms, which is shorter than the transient response time of the conventional symmetrical voltage doubler circuit (about 0.3ms). Therefore, the novel voltage doubler circuit of the embodiment of the present disclosure has better dynamic characteristics and is suitable for application scenarios with high requirements for dynamic characteristics.

[0182] For example, return to reference Figure 1A The embodiment of the present disclosure further provides a high voltage power supply 1000. The high voltage power supply 1000 may include the voltage doubling circuit 200 provided in any of the above embodiments. It should be understood that the high voltage power supply 1000 has the same beneficial effects as the voltage doubling circuit 200 provided in the above embodiments.

[0183] Those skilled in the art can understand that the embodiments described above are exemplary and can be improved by those skilled in the art. The structures described in various embodiments can be freely combined without causing conflicts in structure or principle.

[0184] After describing the preferred embodiments of the present disclosure in detail, those skilled in the art can clearly understand that various changes and modifications can be made without departing from the scope and spirit of the appended claims, and the present disclosure is not limited to the implementation methods of the exemplary embodiments listed in the specification.

Claims

1. A voltage doubling circuit, characterized in that: include: A full-bridge rectifier module, the full-bridge rectifier module comprising a first rectifier bridge arm and a second rectifier bridge arm; and A voltage doubling module, the voltage doubling module comprising a first voltage doubling unit and a second voltage doubling unit, The output end of the first rectifying bridge arm is electrically connected to the input end of the first voltage doubling unit, and the output end of the second rectifying bridge arm is electrically connected to the input end of the second voltage doubling unit.

2. The voltage doubling circuit according to claim 1, wherein: The full-bridge rectifier module also includes a first input terminal and a second input terminal; The first rectifier bridge arm comprises a first connection end, a third connection end and a first output end, the first connection end and the third connection end of the first rectifier bridge arm are respectively connected to the first input end and the second input end of the full-bridge rectifier module, and the first output end of the first rectifier bridge arm is electrically connected to the input end of the first voltage doubling unit; and The second rectifier bridge arm includes a fourth connection end, a sixth connection end and a second output end. The fourth connection end and the sixth connection end of the second rectifier bridge arm are respectively connected to the first input end and the second input end of the full-bridge rectifier module. The second output end of the second rectifier bridge arm is electrically connected to the input end of the second voltage doubling unit.

3. The voltage doubling circuit according to claim 2, wherein: The voltage doubling circuit further includes: A transformer, the transformer comprising a primary side and a secondary side, the two ends of the primary side are respectively configured to be connected to the two ends of the AC power supply, and the two ends of the secondary side are respectively configured to be connected to the first input end and the second input end of the full-bridge rectifier module; and A load, one end of the load is electrically connected to the output end of the first voltage doubling unit, and the other end of the load is electrically connected to the output end of the second voltage doubling unit.

4. The voltage doubling circuit according to claim 3, wherein: The first rectifier bridge arm further includes a first diode, a second diode and a second connection terminal, the anode of the first diode is electrically connected to the first connection terminal, the cathode of the first diode and the cathode of the second diode are both electrically connected to the second connection terminal, and the anode of the second diode is electrically connected to the third connection terminal; and The second rectifier bridge arm also includes a third diode, a fourth diode and a fifth connection terminal, the cathode of the third diode is electrically connected to the fourth connection terminal, the anode of the third diode and the anode of the fourth diode are both electrically connected to the fifth connection terminal, and the cathode of the fourth diode is electrically connected to the sixth connection terminal.

5. The voltage doubling circuit according to claim 4, wherein: The full-bridge rectifier module also includes a first capacitor, a first plate of the first capacitor is electrically connected to the second connection end of the first rectifier bridge arm, and a second plate of the first capacitor is electrically connected to the fifth connection end of the second rectifier bridge arm.

6. The voltage doubling circuit according to claim 4 or 5, wherein: The first output end of the first rectifier bridge arm includes a first sub-output end, a second sub-output end and a third sub-output end, the first sub-output end is electrically connected to the first connection end, the second sub-output end is electrically connected to the second connection end, and the third sub-output end is electrically connected to the third connection end; The first voltage doubling unit includes p-stage cascaded first voltage doubling subunits, each stage of the first voltage doubling subunits includes a fourth input terminal, a fifth input terminal, a sixth input terminal, a fourth output terminal, a fifth output terminal and a sixth output terminal, respectively. Among them, the fourth input terminal, the fifth input terminal and the sixth input terminal of the first-stage first voltage doubling subunit are electrically connected to the first sub-output terminal, the second sub-output terminal and the third sub-output terminal of the first rectifier bridge arm, respectively, and the fourth input terminal, the fifth input terminal and the sixth input terminal of the i+1-th stage first voltage doubling subunit are electrically connected to the fourth output terminal, the fifth output terminal and the sixth output terminal of the i-th stage first voltage doubling subunit, respectively, wherein i is a positive integer greater than or equal to 1 and less than or equal to p-1, and p is a positive integer greater than or equal to 2.

7. The voltage doubling circuit according to claim 6, wherein: The second output end of the second rectifier bridge arm includes a fourth sub-output end, a fifth sub-output end and a sixth sub-output end, the fourth sub-output end is electrically connected to the fourth connection end, the fifth sub-output end is electrically connected to the fifth connection end, and the sixth sub-output end is electrically connected to the sixth connection end; The second voltage doubling unit includes m stages of cascaded second voltage doubling sub-units, each stage of the second voltage doubling sub-units includes a seventh input terminal, an eighth input terminal, a ninth input terminal, a seventh output terminal, an eighth output terminal and a ninth output terminal, respectively. Among them, the seventh input terminal, the eighth input terminal and the ninth input terminal of the first-stage second voltage doubling sub-unit are electrically connected to the fourth sub-output terminal, the fifth sub-output terminal and the sixth sub-output terminal of the second rectifier bridge arm, respectively, and the seventh input terminal, the eighth input terminal and the ninth input terminal of the j+1-th stage second voltage doubling sub-unit are electrically connected to the seventh output terminal, the eighth output terminal and the ninth output terminal of the j-th stage second voltage doubling sub-unit, respectively, wherein j is a positive integer greater than or equal to 1 and less than or equal to m-1, and m is a positive integer greater than or equal to 2.

8. The voltage doubling circuit according to claim 7, wherein: The fifth output terminal of the p-th stage first voltage doubling subunit is electrically connected to one end of the load; and The eighth output terminal of the m-th stage second voltage doubling subunit is electrically connected to the other end of the load.

9. The voltage doubling circuit according to claim 8, wherein: The number of cascaded first voltage doubling subunits included in the first voltage doubling unit is equal to the number of cascaded second voltage doubling subunits included in the second voltage doubling unit.

10. The voltage doubling circuit according to any one of claims 6 to 9, wherein: The i-th level first voltage doubling subunit includes an eleventh capacitor, a twenty-first capacitor, a thirty-first capacitor, an eleventh diode, a twenty-first diode, a thirty-first diode and a forty-first diode, i is a positive integer greater than or equal to 1, The first electrode plate of the eleventh capacitor is electrically connected to the fourth input terminal of the i-th first voltage doubling subunit, and the second electrode plate of the eleventh capacitor is electrically connected to the fourth output terminal of the i-th first voltage doubling subunit; The first electrode plate of the twenty-first capacitor is electrically connected to the fifth input terminal of the i-th first voltage doubling subunit, and the second electrode plate of the twenty-first capacitor is electrically connected to the fifth output terminal of the i-th first voltage doubling subunit; The first electrode plate of the thirty-first capacitor is electrically connected to the sixth input terminal of the i-th first voltage doubling subunit, and the second electrode plate of the thirty-first capacitor is electrically connected to the sixth output terminal of the i-th first voltage doubling subunit; The cathode of the eleventh diode is electrically connected to the fourth output terminal of the i-th first voltage doubling subunit, and the anode of the eleventh diode is electrically connected to the fifth input terminal of the i-th first voltage doubling subunit; An anode of the twenty-first diode is electrically connected to the fourth output terminal of the i-th first voltage doubling subunit, and a cathode of the twenty-first diode is electrically connected to the fifth output terminal of the i-th first voltage doubling subunit; an anode of the thirty-first diode is electrically connected to the fifth input terminal of the i-th first voltage doubling subunit, and a cathode of the thirty-first diode is electrically connected to the sixth output terminal of the i-th first voltage doubling subunit; and The cathode of the forty-first diode is electrically connected to the fifth output terminal of the i-th first voltage doubling subunit, and the anode of the forty-first diode is electrically connected to the sixth output terminal of the i-th first voltage doubling subunit.

11. The voltage doubling circuit according to claim 3, wherein: The transformer has a structure without a center tap.

12. The voltage doubling circuit according to claim 3, wherein: The voltage boost ratio of the voltage doubler circuit is shown in the following formula: ratio=V out / V in =2N(2m+1), where ratio represents the voltage boost ratio of the voltage doubler circuit, V out represents the voltage value of the DC voltage output by the voltage doubler circuit, V in represents the equivalent voltage value of the AC voltage input by the AC power supply, 2N represents the transformation ratio of the transformer, and m represents the number of stages of the first voltage doubling unit and the second voltage doubling unit.

13. A voltage doubling circuit module, characterized in that: The invention comprises a voltage doubling circuit as claimed in any one of claims 1 to 12.

14. A high voltage power supply, characterized in that: The high-voltage power supply comprises: an AC power supply; and a voltage doubling circuit module as claimed in claim 13.

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