Three-level energy storage converter and control method thereof

Abstract

The invention provides a three-level energy storage converter and a control method thereof, the alternating current side square wave of a three-phase bridge arm is sampled for N times in a switching period of a switching tube, and each sampling comprises the step of determining whether the relation between the alternating current side square wave of the three-phase bridge arm and the direct current side voltage meets a preset condition or not; based on a voltage sampling clock, counting the condition that the relation between the alternating-current side square wave and the direct-current side voltage of the three-phase bridge arm meets a preset condition, under the condition that a count value reaches a preset control parameter, after PWM control signals of all switching tubes are generated, setting dead time on the basis of PWM control signals corresponding to complementary switching tubes respectively, according to the scheme, the opportunity for generating the PWM control signal and setting the dead time is given. The scheme has better robustness and reliability for different modulation ratios, different dead time, high switching frequency and the like.

Description

Technical Field

[0001] The present application relates to the technical field of energy storage converters, and in particular to a three-level energy storage converter and a control method thereof. Background Art

[0002] As the core and key component of the energy storage system, the energy storage inverter realizes energy conversion and bidirectional flow between the energy storage battery and the power grid. It can convert direct current (DC) into alternating current (AC) or convert alternating current (AC) into direct current (DC) to meet the charging and discharging needs of the power grid for the energy storage system. It has high energy conversion efficiency to significantly reduce the operating cost of the energy storage system. It has precise power control capabilities to achieve rapid response and precise regulation of the energy storage system, improve the stability and reliability of the power system, and it has an intelligent energy management system to maximize the utilization of the energy storage system and minimize losses, thereby improving the economy and environmental protection of the entire power system. Therefore, the research on energy storage inverters can better meet the needs of the power system and optimize scheduling, which is of great significance for promoting the development of new energy and achieving environmental and social benefits.

[0003] By adding dead time to avoid the loss of the switch tube caused by the shoot-through phenomenon and reducing the reverse conduction loss, the output voltage and output current waveforms will be distorted. The following method can reduce the probability of deviation between the actual waveform and the expected waveform:

[0004] The immune algorithm compensates for the dead time effect: optimizes the space vector action time and vector sequence, and uses a specific space vector combination according to the load impedance characteristics to achieve a dead time-free effect.

[0005] Compensation for dead time effects based on current polarity adjustment strategy: The logic control circuit adjusts the duty cycle of the PWM signal according to the change in current flow direction to compensate for the voltage drop or increase caused by the dead time.

[0006] Harmonic separation compensation dead time influence: establish output voltage model including dead time effect, perform feed-forward voltage compensation according to mathematical model, inject calculated compensation component into modulation signal, reduce current harmonics caused by dead time effect, and improve system performance.

[0007] The above method is limited by the need for additional computing resources. As the computational complexity and real-time requirements increase, it is difficult to achieve the expected effect in high switching frequency scenarios. Summary of the invention

[0008] The present specification provides a three-level energy storage converter and a control method thereof to solve the problem that the existing method has a heavy computational load when processing the voltage waveform and current waveform distortion caused by the dead time and is difficult to apply to application scenarios with high switching frequencies.

[0009] To solve the above technical problems, the first aspect of the present specification provides a three-level energy storage converter, including: a three-phase bridge arm, each phase bridge arm including multiple switch tubes; a driving component, used to drive the switch tube to operate according to a PWM control signal; a bridge arm signal monitoring unit, used to sample the AC side square wave of the three-phase bridge arm N times within a switching cycle of the switch tube, each sampling includes determining whether the relationship between the AC side square wave and the DC side voltage of the three-phase bridge arm meets a predetermined condition, and N is a positive integer; a digital signal processing system, used to generate a PWM control signal according to a modulation wave signal, a carrier voltage signal, and a sampling result; wherein the method for generating the PWM control signal includes: counting the situation that the relationship between the AC side square wave and the DC side voltage of the three-phase bridge arm meets the predetermined condition based on a voltage sampling clock; when the count value reaches a preset control parameter, after generating the PWM control signal of each switch tube, setting a dead time based on the PWM control signals corresponding to the complementary switch tubes.

[0010] In some embodiments, the preset control parameter is obtained based on a normalized signal of the expected voltage signal, and the value range of the normalized signal of the expected voltage signal is [-1, 1].

[0011] In some embodiments, the count value is cleared and restarted in the following cases: when the expected voltage signal crosses zero and the PWM control signal of the corresponding switch tube indicates shutting down.

[0012] In some embodiments, each phase bridge arm in the three-phase bridge arm includes two groups of synchronous switch tubes, two switch tubes in the complementary switch tubes are respectively arranged in different groups, and the switch tubes in the synchronous switch tubes can be turned on and off at the same time; the method for generating a PWM control signal also includes: comparing the expected voltage signal and the carrier voltage signal to obtain a first voltage signal and a second voltage signal; wherein, if the expected voltage signal is positive, the first voltage signal takes a positive value, and the second voltage signal takes a negative value; if the expected voltage signal is negative, the first voltage signal takes a negative value, and the second voltage signal takes a positive value; according to the first voltage signal, the PWM control signals corresponding to the first group of synchronous switch tubes in the bridge arm are determined; according to the second voltage signal, the PWM control signals corresponding to the second group of synchronous switch tubes in the bridge arm are determined.

[0013] In some embodiments, each phase bridge arm in the three-phase bridge arm includes two groups of synchronous switch tubes, two switch tubes in the complementary switch tube are respectively arranged in different groups, and the switch tubes in the synchronous switch tube can be turned on and off at the same time; the bridge arm signal monitoring unit includes: a first sampling submodule, used to detect the situation that the relationship between the AC side square wave and the DC side voltage of the three-phase bridge arm meets the first predetermined subcondition; a second sampling submodule, used to detect the situation that the relationship between the AC side square wave and the DC side voltage of the three-phase bridge arm meets the second predetermined subcondition; the digital signal processing system also includes: a first counter, used to accumulate the sampling results of the first sampling submodule according to the voltage sampling clock; a first comparator, used to determine the Whether the counting result of a counter reaches a first preset control parameter; a first dead zone control unit, used to set the dead zone time based on the PWM control signals corresponding to the first group of synchronous switch tubes when the counting result of the first counter reaches the first preset control parameter; a second counter, used to accumulate the sampling results of the second sampling submodule according to the voltage sampling clock; a second comparator, used to determine whether the counting result of the second counter reaches the second preset control parameter; a second dead zone control unit, used to set the dead zone time based on the PWM control signals corresponding to the second group of synchronous switch tubes when the counting result of the second counter reaches the second preset control parameter.

[0014] In some embodiments, the first predetermined sub-condition includes: Uz≥0.25Udc, and / or, the second predetermined sub-condition includes: Uz≤-0.25Udc, wherein Uz is the AC side square wave of the three-phase bridge arm, and Udc is the DC side voltage of the three-phase bridge arm.

[0015] In some embodiments, the first sampling submodule includes a first resistor, a second resistor, a third resistor, a fourth resistor and a first comparator; wherein the DC side voltage is grounded through the first resistor and the second resistor in sequence, the AC side square wave is grounded through the third resistor and the fourth resistor in sequence, the second resistor and the fourth resistor are directly grounded, and the second resistor and the fourth resistor have the same value; the first input end of the first comparator is connected to the high potential end of the second resistor, and the second input end of the first comparator is connected to the high potential end of the fourth resistor; and / or, the second sampling submodule includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a second comparator; wherein the DC side voltage is grounded through the fifth resistor and the sixth resistor in sequence, the AC side square wave is grounded through the seventh resistor and the eighth resistor in sequence, the sixth resistor and the eighth resistor are directly grounded, and the sixth resistor and the eighth resistor have the same value; the first input end of the second comparator is connected to the high potential end of the sixth resistor, and the second input end of the second comparator is connected to the high potential end of the eighth resistor.

[0016] In some embodiments, the method for generating a PWM control signal further includes: detecting a balanced state of the terminal voltage of two balancing capacitors on the DC side of the three-phase bridge arm; and adjusting the size of the preset control parameter when the terminal voltage of the two balancing capacitors is unbalanced.

[0017] In some embodiments, the digital signal processing system includes: a capacitor voltage monitoring unit, used to detect the balance state of the terminal voltage of two balancing capacitors on the DC side of the three-bridge arm; a third counter, used to count the capacitor unbalanced state based on the capacitor sampling clock; the counting result of the third counter is used to adjust the size of the preset control parameter.

[0018] In some embodiments, the capacitance sampling clock is B times the voltage sampling clock, where B is a positive integer.

[0019] In some embodiments, the count value of the third counter is cleared and restarts counting in the following circumstances: the expected voltage signal crosses zero.

[0020] A second aspect of the present specification provides a control method for a three-level energy storage converter, the three-level energy storage converter comprising a three-phase bridge arm; the method comprising: sampling the AC side square wave of the three-phase bridge arm N times within a switching cycle of a switch tube in the three-phase bridge arm, each sampling comprising determining whether the relationship between the AC side square wave of the three-phase bridge arm and the DC side voltage meets a predetermined condition, wherein N is a positive integer; calculating a target voltage according to the sampled value, the target voltage being proportional to Uz / Udc, wherein Uz is the AC side square wave of the three-phase bridge arm, and Udc is the DC side voltage of the three-phase bridge arm; normalizing the target voltage and performing digitization processing; accumulating the digitized target voltage; and when the accumulation result reaches a preset control parameter, after generating a PWM control signal for each switch tube, setting a dead time based on the PWM control signals corresponding to the complementary switch tubes.

[0021] In some embodiments, the preset control parameter is obtained based on a normalized signal of the expected voltage signal, and the value range of the normalized signal of the expected voltage signal is [-1, 1].

[0022] In some embodiments, the method further includes: when the expected voltage signal passes through zero, clearing the accumulated result of the target voltage, and when the PWM control signal of the corresponding switch tube indicates shutdown, clearing the accumulated result of the target voltage.

[0023] In some embodiments, the target voltage is calculated by the following formula: t =Uz / 0.5Udc, where U′ t is the target voltage.

[0024] In some embodiments, the normalized result of the target voltage is digitized by the following formula:

[0025]

[0026] Among them, U t is the normalized result of the target voltage, For digital results.

[0027] In some embodiments, the method further includes: detecting a balanced state of the terminal voltage of two balancing capacitors on the DC side of the three-phase bridge arm; and adjusting the size of the preset control parameter when the terminal voltage of the two balancing capacitors is unbalanced.

[0028] In some embodiments, detecting the balance state of the terminal voltage of two balancing capacitors on the DC side of the three-phase bridge arm includes: detecting the capacitor voltage of a target point on the DC side of the three-phase bridge arm; two identical capacitors are connected in series and then in parallel on the DC side of the three-phase bridge arm, and the target point is located between the two identical capacitors; accordingly, when the terminal voltage of the two balancing capacitors is unbalanced, adjusting the size of the preset control parameter, including: when the capacitor voltage at the target point is greater than 0.5 times the voltage on the DC side of the three-phase bridge arm, controlling to increase or decrease the preset control parameter.

[0029] The three-level energy storage converter and control method thereof provided in this specification can obtain lower harmonic content and lower system loss under different modulation ratio conditions, making the output waveform closer to the ideal waveform and achieving better dead time compensation and capacitor voltage balance effect.

[0030] The three-level energy storage converter and control method thereof provided in this specification can obtain lower THD regardless of low switching frequency or high switching frequency, and achieve better dead time compensation and capacitor voltage balance effects.

[0031] The three-level energy storage converter and control method thereof provided in this specification have excellent performance under different dead time conditions, can not only ensure the balance of capacitor voltage, but also can well compensate for dead time and switch transient, and output a smooth, stable and balanced waveform.

[0032] The three-level energy storage converter and control method thereof provided in this specification are superior to other classic dead time compensation methods and capacitor voltage balancing methods under different working conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some implementation methods recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0034] Figure 1 A schematic diagram of a three-phase bridge arm of an energy storage converter;

[0035] Figure 2 A schematic diagram of the current direction of a working mode of the three-phase bridge arm of the energy storage converter;

[0036] Figure 3 A schematic diagram of the current direction of another working mode of the three-phase bridge arm of the energy storage converter;

[0037] Figure 4 A schematic diagram of the current direction of another working mode of the three-phase bridge arm of the energy storage converter;

[0038] Figure 5 A schematic diagram of a control method for an energy storage converter provided in this specification;

[0039] Figure 6 A structural schematic diagram of an energy storage converter provided in this specification;

[0040] Figure 7 A schematic diagram of a method for generating PWM control signals for a digital signal processing system of a three-level energy storage converter;

[0041] Figure 8 Another internal structure diagram of the digital signal processing system of the energy storage converter provided in this specification;

[0042] Fig. 9 Schematic diagram of another method for generating PWM control signals for a digital signal processing system of a three-level energy storage converter;

[0043] Fig.10 To preset control parameters and Accumulated value Schematic diagram of the measured results;

[0044] Fig.11 The output voltage waveform, output current waveform and capacitor voltage waveform when the modulation ratio is 0.25;

[0045] Fig.12 The output voltage waveform, output current waveform and capacitor voltage waveform when the modulation ratio is 0.76;

[0046] Fig.13 The output voltage waveform, output current waveform and capacitor voltage waveform when the modulation ratio is 0.96;

[0047] Fig.14 The output voltage waveform and capacitor voltage waveform at a switching frequency of 3kHz;

[0048] Fig.15 The output voltage waveform and capacitor voltage waveform at a switching frequency of 100kHz;

[0049] Fig.16 Output voltage waveform and capacitor voltage waveform at switching frequency 400kHz;

[0050] Fig.17 Output voltage waveform and capacitor voltage waveform when the dead time is 0.5μs;

[0051] Fig.18 Output voltage waveform and capacitor voltage waveform when the dead time is 1μs;

[0052] Fig.19 Output voltage waveform and capacitor voltage waveform when the dead time is 3μs;

[0053] Fig. 20 Schematic diagram of the difference between the control method provided in this manual and other classical methods under different modulation ratio conditions;

[0054] Fig.21 Schematic diagram of the difference between the control method provided in this manual and other classical methods under different switching frequency conditions;

[0055] Fig. 22 This is a schematic diagram of the differences between the control method provided in this manual and other classic methods under different dead time conditions. DETAILED DESCRIPTION

[0056] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0057] The three-level energy storage converter converts a DC signal into an AC signal, wherein the desired AC signal has three values: a positive level, a zero level, and a negative level. The three-level energy storage converter controls the switch tubes on each bridge arm in the three-phase bridge arm to realize the conversion of the AC signal into the DC signal. The three-phase bridge arm includes three bridge arms, each bridge arm corresponds to a phase of AC power, and each bridge arm is provided with at least 4 switch tubes. The three-level energy storage converter can be an NPC (Neutral Point Clamped) energy storage converter or an ANPC (Active Neutral Point Clamped) energy storage converter. The NPC energy storage converter usually performs midpoint clamping through a diode, while the ANPC usually performs midpoint clamping through a switch tube. This specification takes the NPC three-level energy storage converter as an example to illustrate the solution provided in this specification.

[0058] like Figure 1 As shown in the figure, the dotted frame is a three-phase bridge arm for AC-DC conversion, and the three-phase bridge arm includes three bridge arms, each of which is provided with four switch tubes (S x1 ~S x4 (x=a,b,c)) and 4 freewheeling diodes (D x1 ~D x4 (x=a,b,c)), and two diodes clamp the DC midpoint. The DC side power supply voltage is evenly divided by two capacitors. By controlling the on and off of the four switches on each phase bridge arm, the DC side output of the three-phase bridge arm can be controlled to output three different voltage levels, namely Udc / 2 (which can be expressed as 1 or P), 0 (which can be expressed as 0 or O), and -Udc / 2 (which can be expressed as -1 or N). Therefore, the switching function S of the NPC three-level three-phase bridge arm is x It can be expressed as:

[0059]

[0060] By controlling the on and off of the four switches on each phase bridge arm, different output levels can be obtained on the AC side of the three-phase bridge arm. The following takes phase a as an example to introduce and analyze the principle of outputting different levels.

[0061] (1) Working mode I, such as Figure 2 As shown, when the power switch tube S a1 , S a2 Open, S a3 , S a4 Turn off, that is, the switching function S a is 1, output high level (P), if the current is flowing out at this time, it will flow out from the positive pole of the DC power supply, through S a1 , S a2, flows to the load side; if the current is flowing in at this time, it will flow out from the load side and pass through D a2 , D a1 , flows to the positive pole of the DC power supply.

[0062] (2) Working mode II, such as Figure 3 As shown, when the power switch tube S a2 , S a3 Open, S a1 , S a4 Turn off, that is, the switching function S a is 0, the output is zero level (O). If the current is flowing out at this time, it will flow out from the DC side midpoint O and pass through D 1 , S a2 , flows to the load side, such as Figure 3 As shown in (a) in the figure; if the current is flowing in at this time, it will flow out from the load side and pass through S a3 , D 2 , flows to the DC side midpoint O, such as Figure 3 As shown in (b) in .

[0063] (3) Working mode III, such as Figure 4 As shown, when the power switch tube S a3 , S a4 Open, S a1 , S a2 Turn off, that is, the switching function S a =-1, output low level (N), if the current is flowing out at this time, it will flow out from the negative pole of the power supply and pass through D a4 , D a3 , flows to the load side, such as Figure 4 As shown in (a) in the figure; if the current is flowing in at this time, it will flow out from the load side and pass through S a3 , S a4 , flows to the negative pole of the power supply, such as Figure 4 As shown in (b) in .

[0064] From the above analysis, it can be seen that the phase voltages corresponding to the three levels of P, O, and N output by each phase bridge arm (that is, the voltage between each phase and the neutral point (or ground) in the three-phase power system) are Udc / 2, 0, and -Udc / 2, respectively, and the line voltage (that is, the voltage between any two phases in the three-phase power system) has five levels, namely Udc, Udc / 2, 0, -Udc / 2, and -Udc.

[0065] Uz is the voltage on the left side of the LC filter circuit, which is a square wave signal, that is, the actual output voltage of the three-phase bridge arm. Uac is the voltage on the right side of the LC filter circuit, that is, the voltage output to the power grid. The switching devices in the three-phase bridge arm are nonlinear elements, which makes the entire system have nonlinear characteristics. The high-frequency harmonics are filtered out by the LC filter, and the fundamental component (that is, the expected voltage signal) is allowed to pass, so that the effective value of the output voltage is mainly determined by the fundamental component, and the sine wave Uac is obtained for easy control, and the value of the fundamental component can be approximated by measuring the average value of the voltage within the cycle.

[0066] The expected voltage signal is the voltage signal expected to be output to the power grid. The expected voltage signal is usually compared with the carrier voltage signal to generate a PWM control signal for controlling each switch in the three-phase bridge arm. Assume that the modulation wave Umw is the result of normalizing the expected voltage signal to the value interval [-1,1]. Under ideal conditions (i.e., no dead time and switching loss), the on and off of the switch can be precisely controlled without delay and interference from nonlinear factors. Then the amplitude and shape of the modulation wave Umw will directly determine the amplitude and shape of the output voltage Uac, that is, the output voltage Uac is a proportional amplification of the modulation wave Umw.

[0067] In order to map the modulation wave Umw to the three-level, it is necessary to match the range of the modulation wave Umw with the voltage level that can actually be generated. Specifically, when the modulation wave Umw takes the value of -1, the expected output voltage is -0.5Udc; when the modulation wave Umw takes the value of 0, the expected output voltage is 0; when the modulation wave Umw takes the value of 1, the expected output voltage is 0.5Udc. Therefore, the proportional magnification is 0.5Udc, so it has the following relationship:

[0068]

[0069]

[0070]

[0071] It should be noted that the switching period Ts is the reciprocal of the switching frequency. Generally, the faster the switching frequency, the shorter the switching period. For example, the switching frequency in this solution can be set to 3kHz.

[0072] If U t =Uz / 0.5Udc(U t is a digital signal normalized to the range of [-1,1]), N is the number of intervals divided in each switching cycle Ts, then the modulation wave Umw can be expressed as:

[0073]

[0074] Among them, Δt is the length of each subinterval,

[0075] In digital modulation, by increasing the number of sampling points N, U t The integral of U t The sum of ) is approximated by the Riemann sum. When the number of sampling points is large enough, the Riemann sum can approximate the integral very accurately, that is: So we have the following formula:

[0076]

[0077]

[0078] Where N is the number of sampling points in a switching cycle, U t,i is the U of the i-th sampling point in a switching cycle t value.

[0079] U can be t,i To digitize:

[0080]

[0081] In a switching cycle Ts, if the sampling frequency is high enough (for example, the sampling frequency in this solution can be set to 12kHz), so that multiple samples can be taken in each cycle, then the count value It can be expressed as: Where N is the number of sampling points in each switching cycle, U t,i is the U of the i-th sampling point t Value, Δx i is the length of the subinterval between two sampling points.

[0082]

[0083] From the above analysis, we can see that when the count value When the target value N*Umw (where * represents a multiplication operation) is reached, it indicates that the average value of the output voltage waveform of the energy storage converter is close enough to the ideal value. At this time, generating a PWM control signal and setting the dead time can achieve the desired output voltage waveform.

[0084] Based on the above analysis, this specification provides a control method for a three-level energy storage converter. Figure 5 As shown, the method comprises the following steps:

[0085] S110: sampling the AC side square wave of the three-phase bridge arm N times within one switching cycle of the switch tube in the three-phase bridge arm, each sampling comprising determining whether the relationship between the AC side square wave and the DC side voltage of the three-phase bridge arm meets a predetermined condition, and N is a positive integer.

[0086] The three-phase bridge arm structure of the three-level energy storage converter can be as follows Figure 1 The NPC structure shown may also be an ANPC structure, and this specification does not limit the specific structural type of the three-phase bridge arm.

[0087] S120: Calculate a target voltage according to the sampled value, wherein the target voltage is proportional to Uz / Udc, wherein Uz is the AC side square wave of the three-phase bridge arm, and Udc is the DC side voltage of the three-phase bridge arm.

[0088] The target voltage can be the above U t Before normalization, it can also be U t According to U′ t =Uz / 0.5Udc to calculate the target voltage, where U′ t The target voltage Uz is the AC side square wave of the three-phase bridge arm.

[0089] The above U′ t With the above U t The difference is that U′ t The value range of U′ can exceed the following value range: [-1, 1], that is, t It may be the result of not performing normalization. t When U is the result of normalization, t '=U t .

[0090] S130: normalizing the target voltage and performing digital processing.

[0091] The result of normalizing the target voltage is the above U t , its value range is [-1, 1].

[0092] Digital processing refers to the t Converts to 0 or 1.

[0093] Specifically, in some embodiments, S130 may perform digital processing on the normalized result of the target voltage with reference to the above formula (5), that is, perform digital processing by the following formula:

[0094]

[0095] Among them, U t is the normalized result of the target voltage, For digital results.

[0096] S140: Accumulate the digitized target voltage.

[0097] That is, calculate the above

[0098] S150: When the accumulated result reaches the preset control parameter, after generating the PWM control signal of each switch tube, a dead time is set based on the PWM control signals corresponding to the complementary switch tubes.

[0099] If the accumulated result does not reach the preset control parameter, no PWM control signal may be generated and no dead time may be set. Of course, it is not excluded that in some embodiments, while adopting the control method provided in this specification, other methods are also superimposed, so it is also possible that in the embodiment, S150 is adopted, and a PWM control signal is generated and a dead time is set if the accumulated result does not reach the preset control parameter.

[0100] That is, in the count value When the preset control parameters are reached, after generating the PWM control signals of each switch tube in the three-phase bridge arm, the dead time is first set based on the PWM control signals corresponding to the complementary switch tubes, and then the PWM control signals of each switch tube with the set dead time are used to drive each switch tube to operate. When the preset control parameters are reached, the AC side output voltage of the energy storage converter (i.e., the voltage of the AC side square wave of the three-phase bridge arm after LC filtering and the voltage output to the grid) is close enough to the ideal value (i.e., reaches the ideal level state), and the switch state can be switched to output other levels. In the process of switching, in order to prevent the complementary switch tubes from being turned on at the same time, a dead time should be set for the PWM control signal of the complementary switch tube.

[0101] In the count value When the preset control parameters are not reached, it means that the AC side output voltage of the energy storage inverter (i.e., the voltage of the AC side square wave of the three-phase bridge arm after LC filtering and the voltage loaded to both ends of the load) has not reached the ideal level state, and the appropriate time to switch the switch state has not yet been reached. Therefore, there is no need to generate a new PWM control signal, and there is no need to set a dead time.

[0102] Complementary switches are two switches in one phase bridge arm that will not be turned on at the same time. If these two switches are turned on at the same time, the DC side will be short-circuited. Normally, before the dead time is increased, the PWM control signals of the complementary switches are complementary, that is, when one of the complementary switches is turned on, the other is turned off. After the dead time is increased, both switches are turned off during the dead time.

[0103] For example, Figure 1 As shown, each bridge arm of the three-phase bridge arm includes a first switch tube S of the upper bridge arm. x1 , the second switch tube S x2 , and the third switch tube S of the lower bridge arm x3 , the fourth switch tube S x4 , where x represents one of the phases a, b, and c, then the first switch tube S x1 and the third switch tube S x3 is a complementary switch tube, the second switch tube S x2 and the fourth switch tube S x4 A pair of complementary switching tubes can also be a pair of synchronous switching tubes.

[0104] The above preset control parameters may vary with time.

[0105] In some embodiments, the preset control parameter is obtained based on the normalized signal of the expected voltage signal, and the value range of the normalized signal of the expected voltage signal is [-1, 1]. The normalized signal of the expected voltage can be directly used as the preset control parameter; or the value of each moment can be adjusted based on the normalized signal of the expected voltage to obtain the preset control parameter. Accordingly, the PWM control signal of each switch tube can be determined based on the comparison result of the "normalized signal" of the expected voltage signal and the carrier voltage signal.

[0106] In a three-level energy storage converter, some switch tubes can be turned on and off at the same time. During control, these switch tubes can be grouped together for synchronous control, and two switch tubes in the complementary switch tubes can be grouped together in different groups. A PWM control signal for a first pair of synchronous switch tubes can be generated according to a preset control parameter corresponding to the positive half-cycle of an expected voltage signal, and a dead time can be set for the PWM control signal corresponding to each switch tube in the pair of synchronous switch tubes according to the preset control parameter corresponding to the positive half-cycle of the expected voltage signal; a PWM control signal for another pair of synchronous switch tubes can be generated according to a preset control parameter corresponding to the negative half-cycle of the expected voltage signal, and a dead time can be set for the PWM control signal corresponding to each switch tube in the pair of synchronous switch tubes according to the preset control parameter corresponding to the negative half-cycle of the expected voltage signal.

[0107] According to the preset control parameters, the dead time of the PWM control signal corresponding to each switch tube in the complementary switch tube can be specifically: when the PWM control signal of one switch tube in a pair of complementary switch tubes indicates shutdown, the dead time is set for the PWM control signal of the other switch tube in the complementary switch tube.

[0108] In some embodiments, when the expected voltage signal passes through zero, the accumulated result of the target voltage is cleared to zero, and when the PWM control signal of the corresponding switch tube indicates shutting down, the accumulated result of the target voltage is cleared to zero.

[0109] For example, Figure 8 As shown, one reset signal of the first counter and the second counter (i.e., the reset terminal R1 of the counter) comes from the expected voltage signal zero-crossing signal, and the other reset signal (i.e., the reset terminal R2 of the counter) comes from the inversion of the output of the first RS trigger, which is used to reset the falling edge of the output of the RS trigger, i.e., S x1 The falling edge of the PWM control signal (i.e., the PWM control signal indicates turning off the switch tube) resets the counter.

[0110] By setting the accumulated result of the target voltage to zero when the expected voltage signal passes through zero, it is possible to prevent the accumulated result of the previous cycle or the first half cycle of the expected voltage signal from affecting the corresponding switch tube from being turned off at the correct time in the current half cycle, for example, which may cause the corresponding switch tube to be turned off earlier.

[0111] After a switch is turned off, that is, during the dead time, the bridge arm will continue to output high voltage for a period of time due to the natural freewheeling characteristics of the diode. By setting the accumulated result of the target voltage to zero when the PWM control signal of the switch indicates shutdown, it is possible to avoid the count value in the dead time being used as the accumulated value in the previous counting cycle, and use it as the accumulated value in the next counting cycle. Since the switching frequency is generally high, the output waveform of the bridge arm in two adjacent switching cycles is basically the same. Therefore, the count value in the dead time is used as the accumulated value in the next counting cycle and is counted in advance.

[0112] Generally, no new PWM control signal is generated within the dead time. Therefore, it is meaningless to use the accumulated value within the dead time as the accumulated value in the previous counting cycle.

[0113] In some embodiments, the control method of the three-level energy storage converter further includes the following S160 and S170.

[0114] S160: Detect the balance state of the terminal voltage of two balancing capacitors on the DC side of the three-phase bridge arm.

[0115] In a midpoint clamped energy storage converter, a capacitor branch is usually provided at both ends of a three-phase bridge arm. Two identical capacitors are connected in series on the capacitor branch. These two capacitors are balancing capacitors.

[0116] In the equilibrium state, the terminal voltage of any balancing capacitor is 0.5Udc, where Udc is the DC side voltage of the three-phase bridge arm, and the potential between the two capacitors is zero potential.

[0117] like Figure 1 As shown, C 1 and C 2 is the balancing capacitor.

[0118] S170: When the terminal voltages of the two balancing capacitors are unbalanced, adjust the preset control parameters.

[0119] When the preset control parameter is obtained based on the normalized signal of the expected voltage signal (i.e., the preset control parameter is a sine wave), when the capacitor voltage is unbalanced, the duty cycle of the preset control parameter can be changed by adjusting the voltage amplitude of the expected voltage signal at each moment. Figure 1 The voltages of the capacitors C1 and C2 in the circuit can be used to calculate their voltage difference, and the expected voltage signal can be adjusted according to the positive or negative value of the voltage difference, that is, the duty cycle of the drive signal can be adjusted according to the positive or negative value of the voltage difference.

[0120] Combination Figure 1 and Figure 8 , when the voltage of capacitor C1 is higher than the voltage of capacitor C2, the amplitude of the expected voltage signal can be increased, and the time for the first comparator to output a high level increases. Because the expected voltage signal is higher than the triangular wave for a longer time, the duty cycle of the preset control parameter increases accordingly. Increasing the duty cycle will cause the switch tube associated with capacitor C1 to be turned on for a longer time, and more charge will flow through per unit time, thereby increasing the current flowing through capacitor C1 and accelerating its discharge efficiency, thereby reducing the voltage of capacitor C1. Vice versa. It can be seen that dynamically adjusting the amplitude of the expected voltage signal according to the voltage difference monitored in real time can ensure that the capacitor voltage remains balanced.

[0121] It should be noted that, when the preset control parameter is obtained based on the normalized signal of the expected voltage signal (ie, the preset control parameter is a sine wave), the PWM control signal of each switch tube can be Figure 8 The digital signal processing system in Figure 8 The schematic diagram of the generation process of the PWM control signal is not shown.

[0122] There are many ways to implement the control method of the three-level energy storage converter. This specification provides a three-level energy storage converter that can implement the control method. Figure 6 As shown, the energy storage converter includes: a three-phase bridge arm, a drive component, a bridge arm signal monitoring unit and a digital signal processing system.

[0123] Each phase bridge arm in the three-phase bridge arm includes a plurality of switch tubes. Each switch tube can be a high-frequency switch tube. The three-phase bridge arm can be Figure 1 The NPC type shown may also be an ANPC type. For example, the frequency of each switch tube may be 200kHz, 300kHz, or 400kHz, and the sampling frequency may be 3MHz.

[0124] Generally, the switching frequency of low-frequency switching tubes is from several kilohertz to tens of kilohertz, the switching frequency of medium-frequency switching tubes is from tens of kilohertz to hundreds of kilohertz, and the switching frequency of high-frequency switching tubes is from hundreds of kilohertz to several megahertz. The use of high-frequency switching tubes can reduce the size and weight of magnetic components and capacitors, thereby improving power density.

[0125] The driving component is used to drive the switch tube to operate according to the PWM control signal.

[0126] The bridge arm signal monitoring unit is used to sample the AC side square wave of the three-phase bridge arm N times within a switching cycle of the switch tube. Each sampling includes determining whether the relationship between the AC side square wave of the three-phase bridge arm and the DC side voltage meets a predetermined condition, and N is a positive integer.

[0127] The digital signal processing system is used to generate a PWM control signal according to the modulation wave, the carrier voltage signal and the sampling result.

[0128] The method for generating a PWM control signal includes: counting the situations where the relationship between the AC side square wave and the DC side voltage of the three-phase bridge arm meets the predetermined conditions based on the voltage sampling clock; when the count value reaches the preset control parameter, after generating the PWM control signal of each switch tube, setting the dead time based on the PWM control signals corresponding to the complementary switch tubes respectively.

[0129] The voltage sampling clock is designed so that the AC side square wave of the three-phase bridge arm is sampled N times within one switching cycle of the switch tube.

[0130] When the relationship between the AC side square wave and the DC side voltage of the three-phase bridge arm meets the predetermined condition, the result of counting the cases meeting the predetermined condition is the same as the result of S110 to S140 described above.

[0131] For the description of the preset control parameters, please refer to the description of the control method part.

[0132] In some embodiments, the preset control parameter is obtained based on a normalized signal of the expected voltage signal, and the value range of the normalized signal of the expected voltage signal is [-1, 1]. For details, please refer to the description of the control method part.

[0133] In some embodiments, the counter is cleared and restarts counting in the following cases: when the expected voltage signal crosses zero and the PWM control signal of the corresponding switch tube indicates shutting down. For details, please refer to the description of the control method section.

[0134] Some three-level energy storage converters have three sets of synchronous switching tubes in one phase bridge arm, and some three-level energy storage converters have two sets of synchronous switching tubes in one phase bridge arm. Whether it is two sets of synchronous switching tubes or three sets of synchronous switching tubes, they are determined based on the comparison result between the expected voltage signal and the carrier voltage signal, and the dead zone setting method of the complementary switching tube is similar.

[0135] The following uses the example of two sets of synchronous switch tubes in one phase bridge arm of a three-level energy storage converter to illustrate the three-level energy storage converter provided in this specification. Figure 7 As shown, in the digital signal processing system of such a three-level energy storage converter, a PWM control signal can be generated through the following S210 , S220 and S230 .

[0136] S210: Compare the expected voltage signal and the carrier voltage signal to obtain a first voltage signal and a second voltage signal; wherein, if the expected voltage signal is positive, the first voltage signal is positive and the second voltage signal is negative; if the expected voltage signal is negative, the first voltage signal is negative and the second voltage signal is positive.

[0137] In some embodiments, the preset control parameter is obtained based on the normalized signal of the expected voltage signal, that is, the preset control parameter is a sine wave, then the first voltage signal can be a signal with the same positive and negative signs as the normalized signal of the expected voltage signal, and the second voltage signal can be a signal with opposite positive and negative signs as the normalized signal of the expected voltage signal.

[0138] It should be noted that, when the preset control parameter is obtained based on the normalized signal of the expected voltage signal (ie, the preset control parameter is a sine wave), the PWM control signal of each switch tube can be Figure 8 The digital signal processing system generates Figure 8 The schematic diagram of the generation process of the PWM control signal is not shown.

[0139] The expected voltage signal may be generated by a digital signal processing system or may be input externally. The carrier voltage may be generated by a digital signal processing system or may be input externally.

[0140] The carrier voltage can be one triangle wave or two triangle waves. The frequency of the triangle wave can be the same as the switching frequency. In the case where the carrier voltage is one triangle wave, the value range of the triangle wave of one cycle can be [-A, A], where A is the amplitude of the expected voltage signal. In the case where the carrier voltage is two triangle waves, the value range of the first triangle wave can be [-A, 0], and the value range of the second triangle wave can be [0, A], and the two triangle waves have the same phase. The description of the carrier voltage is also applicable to the above control method.

[0141] S220: Determine PWM control signals corresponding to the first group of synchronous switch tubes in the bridge arm according to the first voltage signal.

[0142] S230: Determine PWM control signals corresponding to the second group of synchronous switch tubes in the bridge arm according to the second voltage signal.

[0143] The bridge arm signal monitoring unit includes: a first sampling submodule, a first counter, a first comparator, a first dead zone control unit, a second sampling submodule, a second counter, a second comparator, and a second dead zone control unit.

[0144] The first sampling submodule is used to detect the situation where the relationship between the AC side square wave and the DC side voltage of the three-phase bridge arm meets the first predetermined sub-condition.

[0145] The first counter is used to accumulate the sampling results of the first sampling submodule according to the voltage sampling clock.

[0146] The first comparator is used to determine whether the counting result of the first counter reaches a first preset control parameter.

[0147] The first dead zone control unit is used to set the dead zone time based on the PWM control signals respectively corresponding to the first group of synchronous switch tubes when the counting result of the first counter reaches the first preset control parameter.

[0148] The second sampling submodule is used to detect the situation where the relationship between the AC side square wave and the DC side voltage of the three-phase bridge arm meets the second predetermined sub-condition.

[0149] The second counter is used to accumulate the sampling results of the second sampling submodule according to the voltage sampling clock.

[0150] The second comparator is used to determine whether the counting result of the second counter reaches a second preset control parameter.

[0151] The second dead zone control unit is used to set the dead zone time based on the PWM control signals corresponding to the second group of synchronous switch tubes when the counting result of the second counter reaches the second preset control parameter.

[0152] The first predetermined sub-condition includes: Uz≥0.25Udc, and / or the second predetermined sub-condition includes: Uz≤-0.25Udc, wherein Uz is the AC side square wave of the three-phase bridge arm, and Udc is the DC side voltage of the three-phase bridge arm.

[0153] The first sampling submodule includes a first resistor, a second resistor, a third resistor, a fourth resistor and a first comparator; wherein the DC side voltage is grounded through the first resistor and the second resistor in sequence, the AC side square wave is grounded through the third resistor and the fourth resistor in sequence, the second resistor and the fourth resistor are directly grounded, and the values ​​of the second resistor and the fourth resistor are equal; the first input end of the first comparator is connected to the high potential end of the second resistor, and the second input end of the first comparator is connected to the high potential end of the fourth resistor.

[0154] The second sampling submodule includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a second comparator; wherein the DC side voltage is grounded through the fifth resistor and the sixth resistor in sequence, the AC side square wave is grounded through the seventh resistor and the eighth resistor in sequence, the sixth resistor and the eighth resistor are directly grounded, and the values ​​of the sixth resistor and the eighth resistor are equal; the first input end of the second comparator is connected to the high potential end of the sixth resistor, and the second input end of the second comparator is connected to the high potential end of the eighth resistor.

[0155] like Figure 1 and Figure 8 As shown, the x phase (x=a, b, c) includes the first switch tube S on the upper bridge arm. x1 , the second switch tube S x2 , and the third switch tube S of the lower bridge arm x3 , the fourth switch tube S x4 , where the first switch tube S x1 , the third switch tube S x3 is a set of synchronous switch tubes, the second switch tube S x2 , the fourth switch tube S x4 The first sampling submodule includes two R1, R2, and Ra1. The first switching tube S is controlled based on the sampling result of the first sampling submodule. x1 , the third switch tube S x3 The second sampling submodule includes two R1, R2, Ra2, and controls the second switch tube S based on the sampling result of the second sampling submodule x2 , the fourth switch tube S x4 .

[0156] Based on the sampling result of the first sampling submodule, the first switch tube S is controlled x1 , the third switch tube S x3 When the accumulated result reaches the first preset control parameter N*Umw, the first switch tube S is generated. x1 , the third switch tube S x3 Based on the sampling result of the second sampling submodule, the second switch tube S is controlled x2 , the fourth switch tube S x4When the accumulated result reaches the second preset control parameter -N*Umw, the second switch tube S is generated. x2 , the fourth switch tube S x4 The driving signal.

[0157] In some embodiments, the first sampling submodule compares the DC side voltage of the three-phase bridge arm and the AC side square wave of the three-phase bridge arm, and outputs a high level when Uz≥0.25Udc, wherein Uz is the AC side square wave of the three-phase bridge arm, and Udc is the DC side voltage of the three-phase bridge arm.

[0158] Specifically, the first sampling submodule includes a first resistor, a second resistor, a third resistor, a fourth resistor and a first comparator. The DC side voltage is grounded through the first resistor and the second resistor in turn, the AC side square wave is grounded through the third resistor and the fourth resistor in turn, the second resistor and the fourth resistor are directly grounded, and the second resistor and the fourth resistor have the same value. The first input end of the first comparator is connected to the high potential end of the second resistor, and the second input end of the first comparator is connected to the high potential end of the fourth resistor.

[0159] like Figure 8 As shown, the first resistor is R2, the second resistor is R1, the third resistor is Ra1, and the fourth resistor is R1, wherein the values ​​of the two R1 are the same. Where * represents the product operation.

[0160] By setting the first sampling submodule to output a high level when Uz≥0.25Udc, the anti-interference ability of the digital signal processing system can be improved, ensuring that when the output of the energy storage converter is close to its highest level, the duty cycle of the PWM control signal is adjusted in time, thereby accurately controlling the output voltage waveform of the energy storage converter. In this way, even if the DC voltage fluctuates, the present solution can correctly generate digital signals.

[0161] In some embodiments, the second sampling submodule compares the DC side voltage of the three-phase bridge arm and the AC side square wave of the three-phase bridge arm, and outputs a high level when Uz≤-0.25Udc, wherein Uz is the AC side square wave of the three-phase bridge arm, and Udc is the DC side voltage of the three-phase bridge arm.

[0162] Specifically, the second sampling submodule includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a second comparator. The DC side voltage is grounded through the fifth resistor and the sixth resistor in turn, the AC side square wave is grounded through the seventh resistor and the eighth resistor in turn, the sixth resistor and the eighth resistor are directly grounded, and the values ​​of the sixth resistor and the eighth resistor are equal. The first input end of the second comparator is connected to the high potential end of the sixth resistor, and the second input end of the second comparator is connected to the high potential end of the eighth resistor.

[0163] like Figure 8 As shown, the fifth resistor is R2, the sixth resistor is R1, the seventh resistor is Ra2, and the eighth resistor is R1, wherein the values ​​of the two R1 are the same. Where * represents the product operation.

[0164] By setting the second sampling submodule to output a high level when Uz≤-0.25Udc, the anti-interference ability of the digital signal processing system can be improved, ensuring that when the output of the energy storage converter is close to its minimum level, the duty cycle of the PWM control signal is adjusted in time, thereby accurately controlling the output voltage waveform of the energy storage converter. In this way, even if the DC voltage fluctuates, this solution can correctly generate digital signals.

[0165] In some embodiments, Figure 8 As shown, the digital signal processing system can be used to perform at least one of the following: generating a carrier voltage signal, comparing the expected voltage signal with the carrier voltage signal to obtain a modulated wave, generating a PWM control signal for each switch tube according to the comparison result, and setting a dead time on the PWM control signal of the complementary switch tube.

[0166] The digital signal processing system may include a first counter, a first comparator, an RS trigger, and a dead zone control unit.

[0167] The first counter is used to accumulate the sampling results of the bridge arm signal monitoring unit according to the voltage sampling clock.

[0168] The first comparator is used to compare the accumulation result of the first counter with a preset control parameter.

[0169] The RS trigger is used to generate a trigger signal for setting the dead time according to the switching clock of the switch tube.

[0170] The dead zone control unit is used to set a dead zone time for the PWM control signal corresponding to the complementary switch tube when a trigger signal is received.

[0171] like Figure 8 As shown, the output signal of the bridge arm signal monitoring unit is logically ANDed with the voltage sampling clock to realize the acquisition of the relationship between Uz and Udc at each voltage sampling moment in the switching cycle to determine whether it meets the predetermined conditions. The result of the logical AND is input into the first counter to calculate the cumulative result. The output of the first counter and the preset control parameter are input into the comparator together to compare whether the cumulative result reaches the preset control parameter.

[0172] The output of the comparator and the switching clock are connected to the RS trigger. The period of the switching clock is the same as the switching period of each switch tube. At the beginning of the switching period (i.e. the rising edge of the switching clock), the RS trigger is set and its output is high, which marks the beginning of a new period.

[0173] When the first preset control parameter is greater than 0, it means that the expected output voltage is in the positive half cycle. At this time, the output of the RS trigger triggers the dead zone control unit through the converter to set a dead zone time in the PWM control signal corresponding to the complementary switch tube, and then controls the corresponding complementary switch tube (for example, Figure 1 S x1 and S x3 ).

[0174] like Figure 2 As shown, when the bridge arm waveform is detected to be high (ie S x1 and S x2 On, S x3 and S x4 Off), that is, the accumulated result of the counter When the first counter is high, the first counter starts counting. When the value of the first counter is equal to the preset control parameter, the RS trigger is reset to output a low level, which results in the switch tube S being turned on after the dead time is set. x1 is turned off.

[0175] After the above process, the average value of the bridge arm output waveform can accurately match the modulation wave.

[0176] The first preset control parameter and the second preset control parameter are opposite numbers. When the first preset control parameter is greater than 0 and the second preset control parameter is less than 0, S x4 The PWM control signal is always at a low level to meet the modulation timing. x2 When conducting, S x4 They will not be turned on at the same time, thus avoiding the bridge arm being turned on directly (that is, the two switch tubes on the same bridge arm are turned on at the same time).

[0177] For example, Figure 8 As shown, one reset signal of the first counter and the second counter (i.e., the reset terminal R1 of the counter) comes from the expected voltage signal zero-crossing signal, and the other reset signal (i.e., the reset terminal R2 of the counter) comes from the inversion of the output of the first RS trigger, which is used to reset the falling edge of the output of the RS trigger, i.e., S x1 The falling edge of the PWM control signal (i.e., the PWM control signal indicates turning off the switch tube) resets the counter.

[0178] By setting the accumulated result of the target voltage to zero when the expected voltage signal passes through zero, it is possible to prevent the accumulated result of the previous cycle or the first half cycle of the expected voltage signal from affecting the corresponding switch tube from being turned off at the correct time in the current half cycle, for example, which may cause the corresponding switch tube to be turned off earlier.

[0179] After a switch is turned off, that is, during the dead time, the bridge arm will continue to output high voltage for a period of time due to the natural freewheeling characteristics of the diode. By setting the accumulated result of the target voltage to zero when the PWM control signal of the switch indicates shutdown, it is possible to avoid the count value in the dead time being used as the accumulated value in the previous counting cycle, and use it as the accumulated value in the next counting cycle. Since the switching frequency is generally high, the output waveform of the bridge arm in two adjacent switching cycles is basically the same. Therefore, the count value in the dead time is used as the accumulated value in the next counting cycle and is counted in advance.

[0180] Generally, no new PWM control signal is generated within the dead time. Therefore, it is meaningless to use the accumulated value within the dead time as the accumulated value in the previous counting cycle.

[0181] like Figure 3 As shown, when the switch tube S x1 After shutdown, due to the natural freewheeling of diode D1, the bridge arm continues to output high voltage, but this period cannot be counted in advance, so the count value in the dead time is used as the initial count value of the next switching cycle. Since the switching frequency is usually high, the output waveform of the bridge arm in two adjacent switching cycles is basically the same, so this method of generating the initial count value can ensure that the digital signal is fully counted in advance.

[0182] The above digital signal processing system is composed of only logic units, and thus can be implemented by utilizing internal resources of the digital signal processing system without requiring additional discrete devices, thereby being easy to integrate and reducing costs.

[0183] like Figure 8 As shown, an isolator can also be provided between the digital signal processing system and the driving component.

[0184] In some embodiments, Fig. 9 As shown, the digital signal processing system of the three-level energy storage converter can generate a PWM control signal through the following S210 to S250.

[0185] S210: Compare the expected voltage signal and the carrier voltage signal to obtain a first voltage signal and a second voltage signal; wherein, if the expected voltage signal is positive, the first voltage signal is positive and the second voltage signal is negative; if the expected voltage signal is negative, the first voltage signal is negative and the second voltage signal is positive.

[0186] S220: Determine PWM control signals corresponding to the first group of synchronous switch tubes in the bridge arm according to the first voltage signal.

[0187] S230: Determine PWM control signals corresponding to the second group of synchronous switch tubes in the bridge arm according to the second voltage signal.

[0188] For the above S210 to S230 , reference may be made to the above description.

[0189] S240: Detecting the balance state of the terminal voltages of the two balancing capacitors on the DC side of the three-phase bridge arm.

[0190] S250: When the terminal voltages of the two balancing capacitors are unbalanced, adjust the value of the preset control parameter, and further adjust the PWM control signal of each switch tube.

[0191] Capacitor voltage imbalance will cause voltage fluctuations on the DC side, active power fluctuations on the grid side, and severe current waveform distortion, which will reduce the service life of switching devices and affect the stability and energy conversion efficiency of the energy storage system. There are three main classic methods for solving the above problems in the prior art:

[0192] Space vector pulse width modulation method: The zero-axis control strategy is used to suppress the zero-sequence component of the output voltage and control the capacitor voltage balance, effectively suppressing the negative-sequence component caused by the unbalanced load, and the zero-axis loop control strategy is used to suppress the zero-sequence component and control the capacitor voltage balance.

[0193] Negative sequence voltage injection method: establish the relationship between the active power of each phase and the negative sequence voltage, calculate the negative sequence voltage in the dq coordinate system, and adjust the modulation wave of the output stage by negative sequence voltage injection, so as to achieve balanced control of the capacitor voltage.

[0194] Carrier pulse width modulation method: By obtaining the current synchronous carrier and the upper bridge arm voltage and lower bridge arm voltage on the DC side, the PWM carrier zero bias is adjusted and the corresponding control signal is calculated to achieve capacitor voltage balance.

[0195] The above method is difficult to achieve the expected effect in high switching frequency scenarios. The existing technology usually adopts independent solutions to deal with the dead zone compensation problem and the capacitor voltage imbalance problem, such as unilateral research on dead zone time compensation, or unilateral research on capacitor voltage balance, etc. In order to solve the dead zone compensation and capacitor voltage imbalance problems at the same time, two different solutions are required, which will increase the complexity of the system, increase the difficulty of maintenance and fault diagnosis, and reduce the response speed and real-time performance of the system. This specification provides a technical solution that can solve the above-mentioned dead zone compensation problem and capacitor voltage imbalance problem at the same time.

[0196] In some embodiments, Figure 8 As shown, the digital signal processing system includes a capacitor voltage monitoring unit and a third counter.

[0197] The capacitor voltage monitoring unit is used to detect the balance state of the terminal voltage of the two balancing capacitors on the DC side of the three bridge arms. The balance state may include that the terminal voltage of the first balancing capacitor is greater than the terminal voltage of the second balancing capacitor, the terminal voltage of the first balancing capacitor is less than the terminal voltage of the second balancing capacitor, and the terminal voltage of the first balancing capacitor is equal to the terminal voltage of the second balancing capacitor.

[0198] The third counter is used to count the capacitor unbalanced state based on the capacitor sampling clock; the counting result of the third counter is used to adjust the size of the preset control parameter.

[0199] Specifically, the counting result of the third counter can be used to adjust the magnitudes of the first preset control parameter and the second preset control parameter.

[0200] Furthermore, the capacitance sampling clock is B times the voltage sampling clock, where B is a positive integer. The value of B can be 4%M*P to 6%M*P, where M is the modulation ratio and P is the number of times the AC side square wave of the three-phase bridge arm is sampled in one switching cycle of the switch tube. Specifically, the value of B can be 5%M*P.

[0201] In some embodiments, detecting the balance state of the terminal voltage of two balancing capacitors on the DC side of the three-phase bridge arm includes: detecting the capacitor voltage of a target point on the DC side of the three-phase bridge arm; two identical capacitors are connected in series and then in parallel on the DC side of the three-phase bridge arm, and the target point is located between the two identical capacitors. Accordingly, in the case where the terminal voltage of the two balancing capacitors is unbalanced, adjusting the size of the preset control parameter includes: in the case where the capacitor voltage at the target point is greater than 0.5 times the voltage on the DC side of the three-phase bridge arm, controlling to increase or decrease the preset control parameter.

[0202] Specifically, the three-level energy storage converter also includes: a capacitor voltage acquisition module, which is used to sample the DC side voltage of the three-phase bridge arm and the AC side square wave of the three-phase bridge arm, and compare the DC side voltage of the three-phase bridge arm and the AC side square wave of the three-phase bridge arm, and output a high level when Uc2≤0.5Udc.

[0203] The capacitor voltage acquisition module includes a ninth resistor, a tenth resistor, an eleventh resistor, a twelfth resistor and a third comparator. The DC side voltage is grounded through the ninth resistor and the tenth resistor in turn, the AC side square wave is grounded through the eleventh resistor and the twelfth resistor in turn, the tenth resistor and the twelfth resistor are directly grounded, and the tenth resistor and the twelfth resistor have the same value. The first input end of the third comparator is connected to the high potential end of the tenth resistor, and the second input end of the third comparator is connected to the high potential end of the twelfth resistor.

[0204] like Figure 8As shown, the ninth resistor is R2, the tenth resistor is R1, the eleventh resistor is Rc2, and the twelfth resistor is R1, wherein the two R1s have the same value, Rc2=R1+2*R2, wherein * represents a product operation.

[0205] By setting the capacitor voltage acquisition module to output a high level when Uc2≤0.5Udc, the anti-interference ability of the digital signal processing system can be improved, so that the capacitor voltage unbalanced state can be correctly converted into a digital signal.

[0206] In some embodiments, the digital signal processing system is used to determine the generation timing of the switch tube drive signal according to the AC side square wave of the three-phase bridge arm, and generate a PWM control signal according to the modulation wave and the carrier voltage signal at the generation timing of the switch tube drive signal.

[0207] Wherein, the digital signal processing system includes: a third counter, the first input end of the third counter is connected to the output end of the capacitor voltage acquisition module, the second input end of the third counter is used to input the switching clock, and the output end of the third counter is used to adjust the amplitude of the preset control parameter.

[0208] The switching clock is input into the second input terminal of the third counter after being multiplied by B, where B is a positive number.

[0209] like Figure 8 As shown, U of the third counter represents an up-count input terminal, D represents a down-count input terminal, and R represents a reset terminal. The output terminal of the capacitor voltage acquisition module is connected to the up-count terminal of the third counter, and is connected to the down-count terminal of the third counter after passing through a NOT gate. The output terminal of the third counter is connected to a preset control parameter regulator (including a first preset control parameter regulator and a second preset control parameter regulator) for adjusting the amplitude of the preset control parameter.

[0210] In some embodiments, when the voltage signal is expected to pass through zero, the count value of the third counter is cleared. Figure 8 As shown, the reset signal of the third counter (ie, the reset terminal R of the counter) comes from the expected voltage signal zero-crossing signal.

[0211] The above three-level energy storage converter and control method can be understood by referring to each other.

[0212] The control method of the above three-level energy storage converter is verified by using an NPC (Neutral Point Clamped) type energy storage converter.

[0213] The simulation and experimental parameters are as follows: the rated voltage of the AC side is 690V, the rated voltage of the DC side is 1200V, 18 groups of 750uF capacitors are connected in parallel on the DC side, and the parallel capacitor groups are connected in series to form the neutral point of the DC side. The 18 groups of capacitors can be equivalent to a single capacitor of 13500uF. The inductance of the AC side inductor is 0.1mH, the switching frequency is 3.333kHz, the cutoff frequency of the low-pass filter of the simulation circuit is 2kHz, and the sampling frequency is 12kHz. The DC filter model is JEC002-466416028-2E3, and the AC filter model is JEC002-546500028-2E3.

[0214] The experimental verification and analysis are as follows:

[0215] Fig.10 To preset control parameters and Accumulated value Schematic diagram of the measured results. Among them, the black y1 is the preset control parameter and The non-overlapping part, gray y2 is It can be seen that the preset control parameters and Almost coincident, we can conclude Can accurately reflect changes in preset control parameters.

[0216] Fig.11 , Fig.12 and Fig.13 The output voltage waveform, output current waveform and capacitor voltage waveform are shown when the modulation ratio is 0.25, 0.76 and 0.96 respectively. The total harmonic distortion (THD) is 0.9%, 0.87% and 0.83% respectively, indicating that the method provided in this specification can obtain lower harmonic content and lower system loss under different modulation ratio conditions, making the output waveform closer to the ideal waveform, achieving better dead time compensation and capacitor voltage balance effect.

[0217] Fig.14 , Fig.15 and Fig.16 The output voltage waveform and capacitor voltage waveform are shown when the switching frequency is 3kHz, 100kHz, and 400kHz. It is not difficult to see from the experimental results that the method provided in this specification can obtain lower THD regardless of low switching frequency or high switching frequency, and can achieve better dead time compensation and capacitor voltage balance effect.

[0218] Fig.17 , Fig.18 and Fig.19The output voltage waveform and capacitor voltage waveform are shown when the dead time is 0.5μs, 1μs, and 3μs. It is not difficult to see from the experimental results that the method provided in this specification has excellent performance under different dead time conditions, not only can it ensure the balance of capacitor voltage, but also can well compensate for dead time and switch transients, obtain lower THD, and output smooth, stable, balanced, and pure waveforms. It shows that the method provided in this specification has high practicality and reliability in practical applications.

[0219] Fig. 20 , Fig.21 , Fig. 22 The differences between the control method provided in this specification (also referred to as this scheme) and other classical methods under different modulation ratio conditions, different switching frequency conditions, and different dead time conditions are compared and analyzed respectively.

[0220] Table 1 compares and analyzes the differences between the control method provided in this manual and other classical methods from a multi-dimensional perspective.

[0221] Table 1 Comparative analysis of methods for compensating dead time and balancing capacitor voltage

[0222]

[0223] It can be seen from Table 1 above that the control method provided in this specification performs well in terms of total harmonic distortion THD, switching frequency, computing power requirements, and flexibility, and has good robustness and reliability.

[0224] Although the present application has been described through embodiments, those skilled in the art will appreciate that there are many modifications and variations to the present application without departing from the spirit of the present application, and it is intended that the appended claims include these modifications and variations without departing from the spirit of the present application.

Claims

1. A three-level energy storage converter, characterized in that: include: Three-phase bridge arm, each phase bridge arm includes a plurality of switch tubes; A driving component, used to drive the switch tube to operate according to the PWM control signal; The bridge arm signal monitoring unit is used to sample the AC side square wave of the three-phase bridge arm N times within one switching cycle of the switch tube, and each sampling includes determining whether the relationship between the AC side square wave of the three-phase bridge arm and the DC side voltage meets a predetermined condition, where N is a positive integer; A digital signal processing system, used for generating a PWM control signal according to a modulation wave signal, a carrier voltage signal and a sampling result; The method of generating a PWM control signal includes: Based on the voltage sampling clock, counting the situations where the relationship between the AC side square wave and the DC side voltage of the three-phase bridge arm meets the predetermined condition; When the count value reaches the preset control parameter, after the PWM control signal of each switch tube is generated, the dead time is set based on the PWM control signals corresponding to the complementary switch tubes.

2. The three-level energy storage converter according to claim 1, characterized in that: The preset control parameter is obtained based on a normalized signal of the expected voltage signal, and the value range of the normalized signal of the expected voltage signal is [-1, 1].

3. The three-level energy storage converter according to claim 1, characterized in that: The count value is cleared and restarted in the following cases: when the expected voltage signal crosses zero and the PWM control signal of the corresponding switch tube indicates shutdown.

4. The three-level energy storage converter according to claim 1, characterized in that: Each phase bridge arm in the three-phase bridge arm includes two groups of synchronous switch tubes, two switch tubes in the complementary switch tubes are respectively arranged in different groups, and the switch tubes in the synchronous switch tubes can be turned on and off at the same time; The method of generating a PWM control signal further includes: The expected voltage signal and the carrier voltage signal are compared to obtain a first voltage signal and a second voltage signal; wherein, if the expected voltage signal is positive, the first voltage signal is positive and the second voltage signal is negative; if the expected voltage signal is negative, the first voltage signal is negative and the second voltage signal is positive; Determine the PWM control signals respectively corresponding to the first group of synchronous switch tubes in the bridge arm according to the first voltage signal; The PWM control signals respectively corresponding to the second group of synchronous switch tubes in the bridge arm are determined according to the second voltage signal.

5. The three-level energy storage converter according to claim 1, characterized in that: Each phase bridge arm in the three-phase bridge arm includes two groups of synchronous switch tubes, two switch tubes in the complementary switch tubes are respectively arranged in different groups, and the switch tubes in the synchronous switch tubes can be turned on and off at the same time; The bridge arm signal monitoring unit comprises: A first sampling submodule, used to detect the situation where the relationship between the AC side square wave and the DC side voltage of the three-phase bridge arm meets the first predetermined sub-condition; A second sampling submodule is used to detect the situation where the relationship between the AC side square wave and the DC side voltage of the three-phase bridge arm meets the second predetermined sub-condition; The digital signal processing system further comprises: A first counter, used to accumulate the sampling results of the first sampling submodule according to the voltage sampling clock; A first comparator, used to determine whether the counting result of the first counter reaches a first preset control parameter; A first dead zone control unit, used for setting a dead zone time based on the PWM control signals respectively corresponding to the first group of synchronous switch tubes when the counting result of the first counter reaches a first preset control parameter; A second counter, used to accumulate the sampling results of the second sampling submodule according to the voltage sampling clock; A second comparator, used to determine whether the counting result of the second counter reaches a second preset control parameter; The second dead zone control unit is used to set the dead zone time based on the PWM control signals respectively corresponding to the second group of synchronous switch tubes when the counting result of the second counter reaches the second preset control parameter.

6. The three-level energy storage converter according to claim 5, characterized in that: The first predetermined sub-condition includes: Uz≥0.25Udc, and / or the second predetermined sub-condition includes: Uz≤-0.25Udc, wherein Uz is the AC side square wave of the three-phase bridge arm, and Udc is the DC side voltage of the three-phase bridge arm.

7. The three-level energy storage converter according to claim 5, characterized in that: The first sampling submodule includes a first resistor, a second resistor, a third resistor, a fourth resistor and a first comparator; wherein the DC side voltage is grounded through the first resistor and the second resistor in sequence, the AC side square wave is grounded through the third resistor and the fourth resistor in sequence, the second resistor and the fourth resistor are directly grounded, and the second resistor and the fourth resistor have the same value; the first input end of the first comparator is connected to the high potential end of the second resistor, and the second input end of the first comparator is connected to the high potential end of the fourth resistor; and / or, The second sampling submodule includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor and a second comparator; wherein the DC side voltage is grounded through the fifth resistor and the sixth resistor in sequence, the AC side square wave is grounded through the seventh resistor and the eighth resistor in sequence, the sixth resistor and the eighth resistor are directly grounded, and the values ​​of the sixth resistor and the eighth resistor are equal; the first input end of the second comparator is connected to the high potential end of the sixth resistor, and the second input end of the second comparator is connected to the high potential end of the eighth resistor.

8. The three-level energy storage converter according to claim 1, characterized in that: The method of generating a PWM control signal further includes: Detecting the balance state of the terminal voltage of two balancing capacitors on the DC side of the three-phase bridge arm; When the terminal voltages of the two balancing capacitors are unbalanced, the magnitude of the preset control parameter is adjusted.

9. The three-level energy storage converter according to claim 8, characterized in that: The digital signal processing system comprises: A capacitor voltage monitoring unit is used to detect the balance state of the terminal voltage of two balancing capacitors on the DC side of the three bridge arms; The third counter is used to count the capacitor unbalanced state based on the capacitor sampling clock; the counting result of the third counter is used to adjust the size of the preset control parameter.

10. The three-level energy storage converter according to claim 9, characterized in that: The capacitance sampling clock is B times the voltage sampling clock, where B is a positive integer.

11. The three-level energy storage converter according to claim 10, characterized in that: In the following cases, the count value of the third counter is cleared and restarts counting: the expected voltage signal crosses zero.

12. A control method for a three-level energy storage converter, characterized in that: The three-level energy storage converter includes a three-phase bridge arm; the method includes: The AC side square wave of the three-phase bridge arm is sampled N times within one switching cycle of the switch tube in the three-phase bridge arm, and each sampling includes determining whether the relationship between the AC side square wave of the three-phase bridge arm and the DC side voltage meets a predetermined condition, and N is a positive integer; Calculate the target voltage according to the sampled value, the target voltage is proportional to Uz / Udc, where Uz is the AC side square wave of the three-phase bridge arm, and Udc is the DC side voltage of the three-phase bridge arm; Normalizing and digitizing the target voltage; Accumulating the digitized target voltage; When the accumulated result reaches the preset control parameter, after the PWM control signal of each switch tube is generated, the dead time is set based on the PWM control signals corresponding to the complementary switch tubes.

13. The method according to claim 12, characterized in that The preset control parameter is obtained based on a normalized signal of the expected voltage signal, and the value range of the normalized signal of the expected voltage signal is [-1, 1].

14. The method according to claim 12, characterized in that The method further includes: when the expected voltage signal passes through zero, clearing the accumulated result of the target voltage, and when the PWM control signal of the corresponding switch tube indicates shutdown, clearing the accumulated result of the target voltage.

15. The method according to claim 12, characterized in that The target voltage is calculated using the following formula: U′ t =Uz / 0.5Udc, where U′ t is the target voltage.

16. The method according to claim 12, characterized in that The normalized result of the target voltage is digitized by the following formula: Among them, U t is the normalized result of the target voltage, For digital results.

17. The method according to claim 12, characterized in that The method further comprises: Detecting the balance state of the terminal voltage of two balancing capacitors on the DC side of the three-phase bridge arm; When the terminal voltages of the two balancing capacitors are unbalanced, the magnitude of the preset control parameter is adjusted.

18. The method according to claim 17, characterized in that Detecting the balance state of the terminal voltage of two balancing capacitors on the DC side of the three-phase bridge arm, including: detecting the capacitor voltage of a target point on the DC side of the three-phase bridge arm; two identical capacitors are connected in series and then in parallel on the DC side of the three-phase bridge arm, and the target point is located between the two identical capacitors; Accordingly, when the terminal voltages of the two balancing capacitors are unbalanced, the size of the preset control parameter is adjusted, including: when the capacitor voltage at the target point is greater than 0.5 times the DC side voltage of the three-phase bridge arm, controlling to increase or decrease the preset control parameter.

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