Sigma-delta ADC downsampling digital filter floating point coefficient fixed-point unit design method

Abstract

The invention discloses a fixed-point unit design method for a floating-point coefficient of a sigma-delta ADC downsampling digital filter, which is realized in a full-digital manner and integrates optimal coding, hybrid coding combination and multiplication and addition operation optimization technologies based on a graph theory. By means of the hybrid coding method based on the graph theory, hardware resources of multiplication and addition operation are reduced, the operation speed is increased, and the area and power consumption are remarkably optimized while it is guaranteed that delay is slightly reduced. In addition, an optimized carry chain rearrangement algorithm is used, and the fan-out number of the adder and the connection efficiency are maximized. Compared with a traditional floating point coefficient fixed-point coding and adder method, the method can effectively achieve multiplication and addition operation optimization of a down-sampling filter in a digital module of the sigma-delta ADC, greatly reduces the power consumption delay product on the basis of keeping the areas similar, and improves the power consumption delay product. The comprehensive performance of the floating point coefficient fixed-point unit of the down-sampling digital filter is obviously enhanced, and the method is suitable for the multiplication and addition operation optimization of the down-sampling filter in a sigma-delta ADC (Analog to Digital Converter) digital module.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design, and specifically discloses a method for designing a floating-point coefficient fixed-point unit of a Σ-ΔADC downsampling digital filter. Background Art

[0002] Since hardware implementation requires fixed-point processing of the floating-point numbers of the digital filter model, the digital filter for Σ-ΔADC downsampling often includes modules such as integral-comb cascade filter, compensation filter, and half-band filter. Except for the integral-comb cascade filter, the coefficients of other filters such as compensation filter and half-band filter are non-integer. When the fixed-point bit width is determined, the hardware implementation overhead of different encoding algorithms is also different. The more non-zero numbers in the coefficients, the more addition operations are required during hardware implementation. In order to reduce hardware overhead, the traditional encoding algorithm must be optimized.

[0003] In digital system encoding, the most common methods include binary complement, inverse code, signed numerical representation, etc., among which binary encoding is the most widely used. According to statistics, when binary encoding is used, nearly half of the positions are zero. In order to reduce the number of non-zeros, the signed number encoding system adds -1 on the basis of 0 and 1. For signed number encoding, the proportion of non-zeros is reduced to one third. However, signed number encoding is not unique, so there is also an optimal regular signed CSD encoding based on the improvement of signed number algorithm.

[0004] Although the optimal regular signed CSD encoding can greatly reduce the number of non-zeros in the coefficients, thereby reducing the addition operations in the entire operation. However, in the optimal encoding, the coefficients are often factored and then the factors are implemented. Factoring the coefficients first and then performing the optimal regular signed CSD can more effectively reduce the number of required adders. For a set consisting of multiple constant coefficients, there are many ways to represent it through a graph. A series of intermediate variables can be generated by factoring. If the existing intermediate variables can be reused to generate other variables that have not been generated, then in the end the system not only has reduced overhead, but also improved speed.

[0005] The digital filter for Σ-ΔADC downsampling contains a variety of FIR filters. From the differential equation of FIR, it can be seen that it is essentially composed of a series of multiplication and addition operations. Therefore, optimizing the multiplication and addition operation is very useful for optimizing the coefficient solution process of the digital filter for Σ-ΔADC downsampling. For multiplication and addition operations, the simplest way is to use the hardwired Hardwired Multiply Adder that comes with the resource. Since these fixed resources are integrated with other basic logics, the resource utilization rate will be low when the tool is automatically implemented. Therefore, the multiplication and addition operation must be designed and optimized according to system requirements. The most commonly used optimization algorithm is to adopt a distributed idea, that is, to decompose binary data bit by bit. The data of the same bit at different times are reorganized, the results are stored in advance, and finally the final result is obtained by address reading and shift addition.

[0006] After distributed reorganization, all possible results can be obtained through pre-calculation, and the final number of additions is only related to the input bit width. However, this method has several shortcomings. First, this method consumes more ROM resources, and the resource consumption grows exponentially with the coefficient bit width. If a full parallel mode is to be achieved, such hardware overhead is unacceptable. Secondly, this method has advantages when implemented on FPGA because it has abundant embedded RAM, LUT and other resources. If it is to be implemented as an ASIC, then the advantages will no longer exist. Multiplication operations can be replaced by shift addition instead of multiplication, so there is no need for a dedicated multiplier.

[0007] There are two main directions for the optimization of addition. One is to correspond to the serial mode, focusing on low power consumption and low hardware overhead. The other is to correspond to the parallel mode, focusing on high speed and low latency, and the hardware overhead and power consumption requirements are relatively low. Common types include chain carry adder (Carry-Ripple Adder), carry jump adder (Carry-Skip Adder), carry select adder (Carry-Select Adder) and carry lookahead adder (Carry-Lookahead Adder). Among them, the carry ripple structure is the simplest, but because the previous carry calculation must be completed before it can be passed to the next level for use, the critical path is the longest, which is suitable for situations where the serial mode does not require high speed. In the full parallel mode, the speed requirement is high, and the carry propagation chain must be modified to shorten the time as much as possible. Whether it is carry selection or skipping, although the operation parallelism is improved to a certain extent and the critical path is reduced, it does not fundamentally eliminate the limitation of the level-by-level carry on the propagation chain.

[0008] By testing and comparing the number of gates, delay, area and power consumption required for different implementations of adders with the same bit size, it can be seen that the carry-lookahead adder can exchange more hardware overhead and power consumption for lower delay. Summary of the invention

[0009] The purpose of the present invention is to provide a coefficient solution method for a Σ-Δ ADC downsampling digital filter, so as to solve the above-mentioned shortcomings of large power consumption, large area, large delay in the process of solving the coefficient of the downsampling digital filter, and the defects of the working mode being limited and the application scope being small. To achieve the above purpose, the present invention adopts the following technical solutions:

[0010] The method for designing a fixed-point unit for floating-point coefficients of a Σ-Δ ADC downsampling digital filter comprises:

[0011] Optimal fixed-point encoding method and multiplication-addition operation optimization method; Among them,

[0012] The floating-point coefficients required by the Σ-ΔADC downsampling digital filter are input into the optimal fixed-point encoding method, and the optimal encoded fixed-point quantization parameters are output to obtain the optimal floating-point coefficient fixed-point unit structure. The multiplication and addition operation optimization method is used to optimize the operation unit structure in the floating-point coefficient fixed-point unit of the Σ-ΔADC downsampling digital filter.

[0013] The optimal fixed-point encoding method comprises:

[0014] Optimal coding method based on graph theory and hybrid coding combination method; among them,

[0015] The optimal coding method based on graph theory is connected with the hybrid coding combination method; the floating-point coefficients required by the Σ-ΔADC downsampling digital filter are input into the optimal coding method based on graph theory, and the optimized code is output; the optimized code output by the optimal coding method based on graph theory is input into the hybrid coding combination method, and finally the fixed-point quantization parameter of the optimal code is output.

[0016] The multiplication-addition operation optimization method comprises the following steps:

[0017] The first step is to replace the multiplication operation with shift addition;

[0018] The second step is to initialize the group generation signal and the group propagation signal according to the generation function and the transfer function;

[0019] The third step is to calculate the signal generated by each individual group and the signal propagated by the group;

[0020] The fourth step is to use the partial group pre-calculation in the Brent-Kung structure to generate odd carry;

[0021] The fifth step is to gradually reduce the number of additional PG units required in the subsequent Kogge-Stone structure;

[0022] Step 6, the last level uses the odd carry to calculate the even carry;

[0023] Step 7: Complete the calculation of local sum and carry output.

[0024] The optimal coding method based on graph theory comprises the following steps:

[0025] The first step is to initialize the input set A and the graph set B;

[0026] The second step is to make all elements of set A positive and singular;

[0027] The third step is to calculate the required additive cost of the coefficients in set A;

[0028] Step 4: Move the coefficients with a cost of 1 in set A to set B;

[0029] Step 5: Calculate the coefficients in set B that can produce a cost of 0;

[0030] Step 6: The generated coefficients are stored in set C and randomly added or subtracted;

[0031] Step 7: Move the coefficients with the value in set A to set B;

[0032] Step 8: Determine whether there are any coefficients to be moved into set B. If yes, return to step 5: calculate the coefficients in set B that can produce a cost of 0. If no, execute the subsequent process, i.e., step 9: determine whether set A is empty.

[0033] Step 9: Determine whether set A is empty: if so, end the entire code generation process and exit the loop; if not, execute step 10: add new auxiliary coefficients to set B;

[0034] Step 10: Add new auxiliary coefficients to set B.

[0035] The hybrid coding combination method comprises the following steps:

[0036] The first step is to compare the coding optimization effects of the two coding methods on the filter coefficients;

[0037] The second step is to determine whether the performance of graph theory coding is better than the best CSD coding: if so, then execute the third step: adopt the best coding based on graph theory; if not, then execute the fourth step: adopt the best regular signed CSD coding;

[0038] The third step is to use the optimal coding based on graph theory;

[0039] The fourth step is to use the best regular signed CSD encoding;

[0040] Step 5: The mixed coding is completed and the coding result is obtained.

[0041] The multiplication and addition operation optimization method uses carry chain rearrangement to optimize the maximum fan-out number and the number of connections, configures the logic level to be log2N+2, the maximum fan-out to be 2, and the number of connections to be 1;

[0042] Where N is the number of addition digits;

[0043] The multiplication operation is replaced by shift addition, and the multiplication and addition operation is realized by full addition operation;

[0044] Adding new auxiliary coefficients to the set B, if the intermediate coefficients are all related to each other, the optimal encoding result can be directly obtained, otherwise new auxiliary coefficients need to be added between the coefficients to establish a connection;

[0045] The above-mentioned judgment graph theory coding performance is better than the best CSD coding, the coding optimization result based on graph theory is compared with the result of using the best regular signed CSD coding, and the best coding result of the two is adopted;

[0046] The adding of new auxiliary coefficients only considers the case of adding an additional variable, and the other cases are not processed.

[0047] Compared with the prior art, the present invention has the following technical effects:

[0048] 1. The number of adders required for the fixed-point unit of the floating-point coefficient of the down-sampling digital filter is significantly reduced, and the number of adders on the critical path is also reduced. This reduces the hardware resource overhead and improves the operation speed of the fixed-point unit of the floating-point coefficient.

[0049] 2. The optimal fixed-point encoding method significantly improves the area and power consumption of the floating-point coefficient fixed-point unit while slightly reducing the latency.

[0050] 3. The multiplication-addition optimization algorithm with optimized carry chain rearrangement method is used to achieve the optimal improvement of the maximum fan-out number and the number of connections of the adder in the floating-point coefficient fixed-point unit, which is significantly improved compared with the three typical addition acceleration structures when the power consumption is the same.

[0051] 4. Compared with the traditional floating-point coefficient fixed-point encoding and adder method, the optimized digital filter floating-point coefficient fixed-point unit design method greatly reduces the power consumption delay product of the integrated circuit while the area used remains almost unchanged, and improves the overall performance of the downsampling digital filter floating-point coefficient fixed-point unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A flowchart of an optimal coding method based on graph theory for a design method of a floating-point coefficient fixed-point unit for a Σ-Δ ADC downsampling digital filter provided in an embodiment of the present invention;

[0053] Figure 2 A flow chart of a hybrid coding combination method for a design method of a floating-point coefficient fixed-point unit for a Σ-Δ ADC downsampling digital filter provided by an embodiment of the present invention;

[0054] Figure 3 A flow chart of a multiplication-addition operation optimization method for a Σ-Δ ADC downsampling digital filter floating-point coefficient fixed-point unit design method provided in an embodiment of the present invention;

[0055] Figure 4 A flow chart of an overall optimization design method for a method for designing a floating-point coefficient fixed-point unit for a Σ-Δ ADC downsampling digital filter provided by an embodiment of the present invention; DETAILED DESCRIPTION

[0056] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0057] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0058] The present invention is further described in detail below with reference to specific embodiments.

[0059] See also Figure 1 , where the optimal encoding method based on graph theory is generated as follows:

[0060] The first step is to initialize the input set A and the graph set B;

[0061] The second step is to convert all elements of set A into positive singular numbers: that is, convert the input coefficient set A into positive singular numbers, that is, divide each coefficient in the input coefficient set A by the greatest divisor of the power of 2 to obtain positive singular numbers of each coefficient and rewrite the set A;

[0062] The third step is to calculate the required addition cost of the coefficients in set A: that is, to delete the powers of 2 and the number of repetitions in the positive odd-numbered input coefficient set A, and then calculate the required addition cost of each coefficient, that is, the number of additions required;

[0063] Step 4: Move the coefficients with a cost of 1 in set A to set B: that is, move the coefficients with an addition cost of 1 obtained in step 3 to set B, and delete the coefficients in set A.

[0064] The fifth step is to calculate the coefficients in set B that can produce a cost of 0: that is, calculate the power of 2 of the coefficients in graph set B;

[0065] Step 6: Store the generated coefficients in set C, and perform random addition and subtraction: store the coefficients calculated in step 5 in set C, and perform an addition and subtraction operation on two random coefficients in set C;

[0066] Step 7: Move the coefficients with the value in set A to set B: that is, compare and find whether set A contains the same coefficients as those generated by the operation in step 6. If so, move the same coefficients in set A to set B and delete them from set A.

[0067] Step 8: Determine whether there are any coefficients to be moved into set B. If yes, return to step 5: calculate the coefficients in set B that can produce a cost of 0. If no, execute the subsequent process, i.e., step 9: determine whether set A is empty.

[0068] Step 9, determine whether set A is empty: that is, determine whether set A is an empty set after step 8 is executed. If so, end the entire code generation process and exit the loop; if not, execute step 10: add new auxiliary coefficients to set B;

[0069] Step 10, add new auxiliary coefficients to set B: that is, repeat steps 5 to 9. If you enter step 10, delete the auxiliary coefficients originally added, and then add new auxiliary coefficients to set B until you exit the loop after judging in step 9.

[0070] It should be noted that the coding optimization method based on graph theory representation, that is, using the correlation between the coefficients to complete the coding optimization of the floating-point coefficient fixed-point unit in the downsampling digital filter, needs to be considered in two situations: if the intermediate coefficients are correlated with each other, then the optimal coding result can be obtained directly; if additional variables need to be added between the coefficients to establish a connection, this part is random.

[0071] In addition, it should be noted that if variables are added blindly to pursue relevance, negative optimization may result. Therefore, the present invention only considers the case of adding an additional variable, and does not process other cases.

[0072] Specifically, the optimal encoding algorithm can be divided into two steps:

[0073] In the first step, all coefficients that satisfy the associated attributes are optimized until all relationships are covered.

[0074] In the second step, if there are still cases not covered by the results of the first step, the second step needs to optimize the case of an additional variable separately. If there are still some left after the second step, it means that the probability of negative optimization has increased, and this part should be discarded.

[0075] In addition, it should be noted that since the coding optimization results based on graph theory are closely related to the floating-point coefficients required for encoding, the optimization effect is random and there may be negative optimization of factorization. Therefore, it is necessary to compare the coding optimization results based on graph theory with the results of the best regular signed CSD encoding to obtain the best encoding result.

[0076] For further information, see Figure 2 , where the mixed coding combination method is as follows:

[0077] The first step is to compare the coding optimization effects of the two coding methods on the filter coefficients: that is, to compare the results of the coefficient coding based on graph theory with the best regular signed CSD coding results;

[0078] The second step is to determine whether the performance of graph theory coding is better than the best CSD coding: that is, to compare and determine, if yes, then execute the third step: adopt the best coding based on graph theory; if not, then execute the fourth step: adopt the best regular signed CSD coding;

[0079] The third step is to use the optimal coding based on graph theory;

[0080] The fourth step is to use the best regular signed CSD encoding;

[0081] In the fifth step, the hybrid coding is completed and the coding result is obtained: that is, through the above coefficient solution method that has selected only positive optimization, the hybrid coding that only can be positively optimized is completed.

[0082] Furthermore, the optimal coefficient hybrid coding method has been realized on the basis of hybrid coding, and the total number of adders required for the fixed-point unit of floating-point coefficients in the down-sampling digital filter and the number of adders on the critical path have been optimized. Then, the performance of the multiplication and addition operation unit required in the fixed-point unit of floating-point coefficients in the down-sampling digital filter is optimized from the multiplication and addition operation level.

[0083] Specifically, the multiplication operation is replaced by shift addition, thereby eliminating the need for a dedicated multiplier, that is, all operations are reduced to addition, and only the re-addition operation needs to be optimized.

[0084] Among them, the optimization design is based on the carry-lookahead adder and used in full parallel mode. The hierarchical grouping method is adopted. On the basis of the traditional generation function and transfer function, the group generation signal G is introduced. i:j and group propagation signal P i:j And calculate according to the following formula:

[0085] G i:j =G i:k +P i:k ×G k-1:j

[0086] P i:j =P i:k ×P k-1:j

[0087] It should be noted that when the group generates a signal G i:j and group propagation signal P i:j In the special case of values ​​on the diagonal, they can be simplified and calculated as follows:

[0088] G i:i =G i =A×B

[0089] P i:i =P i =A⊕B

[0090] It should be noted that the calculation operation after defining a group is calculated as follows:

[0091] (G,P)×(G`,P`)=(G+P×G`,P×P`)

[0092] This operation satisfies the associative law. The associative law is used to rearrange the G and P functions and arrange them in a tree structure to further shorten the critical path.

[0093] See also Figure 3 , where the optimized multiplication and addition operation optimization method is operated as follows:

[0094] The first step is to replace the multiplication operation with shift addition;

[0095] The second step is to initialize the group generation signal and the group propagation signal according to the generation function and the transfer function;

[0096] The third step is to calculate the signal generated by each individual group and the signal propagated by the group;

[0097] The fourth step is to use the partial group pre-calculation in the Brent-Kung structure to generate odd carry;

[0098] The fifth step is to gradually reduce the number of additional PG units required in the subsequent Kogge-Stone structure;

[0099] Step 6. The last level uses the odd carry to calculate the even carry.

[0100] Step 7: Complete the calculation of local sum and carry output.

[0101] It should be noted that the carry chain rearrangement method is improved based on three classic structures: Brent-Kung, Sklansky and Kogge-Stone.

[0102] Specifically, the Brent-Kung structure generates some groups too quickly, which leads to the problem that the connection between the remaining odd bits and the zeroth bit is weakened, and the logic level is too long; the Kogge-Stone structure calculates 2 i The carry of -1 (i=1,2,...,log2N) positions leads to increased wiring and resource consumption; the Sklansky structure calculates the middle leading bits together, resulting in a compromise between high fan-out and layout difficulties.

[0103] It should be noted that, when the number of logic levels increases slightly, the maximum fan-out number and the number of connections can be optimized by compromising the number of logic levels L, the maximum fan-out number Fanout, and the number of connections. The final number of logic levels is log2N+2, the maximum fan-out is 2, and the number of connections is 1;

[0104] Where N is the number of addition bits.

[0105] For further information, see Figure 4 , the overall optimization design method is as follows:

[0106] Among them, the optimal fixed-point coding method composed of the optimal coding based on graph theory and the hybrid coding is as follows:

[0107] The first step is to perform fixed-point encoding operations based on the floating-point coefficients of the target filter characteristics;

[0108] The second step is to initialize the input set A and the graph set B;

[0109] The third step is to convert all elements of set A into positive singular numbers: that is, convert the input coefficient set A into positive singular numbers, that is, divide each coefficient in the input coefficient set A by the greatest divisor of the power of 2 to obtain positive singular numbers of each coefficient and rewrite the set A;

[0110] The fourth step is to calculate the required addition cost of the coefficients in set A: that is, to delete the powers of 2 and the number of repetitions in the positive odd-numbered input coefficient set A, and then calculate the required addition cost of each coefficient, that is, the number of additions required;

[0111] Step 5: Move the coefficients with a cost of 1 in set A to set B: that is, move the coefficients with an addition cost of 1 obtained in step 3 to set B, and delete the coefficients in set A.

[0112] Step 6: Calculate the coefficients in set B that can produce a cost of 0: that is, calculate the power of 2 of the coefficients in graph set B;

[0113] Step 7: Store the generated coefficients in set C and perform random addition and subtraction: store the coefficients calculated in step 5 in set C, and perform an addition and subtraction operation on two random coefficients in set C;

[0114] Step 8: Move the coefficients with the value in set A to set B: that is, compare and find whether set A contains the same coefficients as those generated by the operation in step 6. If so, move the same coefficients in set A to set B and delete them from set A.

[0115] Step 9: Determine whether there are any coefficients to be moved into set B. If yes, return to step 6: calculate the coefficients in set B that can produce a cost of 0. If no, execute the subsequent process, i.e., step 10: determine whether set A is empty.

[0116] Step 10, determine whether set A is empty: that is, determine whether set A is an empty set after step 9 is executed. If so, end the entire code generation process and exit the loop; if not, execute step 11: add new auxiliary coefficients to set B;

[0117] Step 11, add new auxiliary coefficients to set B: that is, repeat steps 5 to 9. If you enter step 10, delete the auxiliary coefficients originally added, and then add new auxiliary coefficients to set B until you exit the loop after judging in step 9.

[0118] Step 12, compare the coding optimization effects of the two coding methods on the filter coefficients: that is, compare the results of the coefficient coding based on graph theory with the best regular signed CSD coding results;

[0119] Step 13: Determine whether the performance of graph theory coding is better than the best CSD coding: that is, make a comparison and determine, if yes, then execute step 14: adopt the best coding based on graph theory; if no, then execute step 15: adopt the best regular signed CSD coding;

[0120] Step 14: Use optimal coding based on graph theory;

[0121] Step 15, using the best regular signed CSD encoding;

[0122] In the sixteenth step, the hybrid coding is completed and the coding result is obtained: that is, through the above coefficient solving method that has selected only positive optimization, the hybrid coding that only can be positively optimized is completed.

[0123] It should be noted that

[0124] Among them, the operation mode of the optimized multiplication and addition operation optimization method is as follows:

[0125] The first step is to replace the multiplication operation with shift addition;

[0126] The second step is to initialize the group generation signal and the group propagation signal according to the generation function and the transfer function;

[0127] The third step is to calculate the signal generated by each individual group and the signal propagated by the group;

[0128] The fourth step is to use the partial group pre-calculation in the Brent-Kung structure to generate odd carry;

[0129] The fifth step is to gradually reduce the number of additional PG units required in the subsequent Kogge-Stone structure;

[0130] Step 6. The last level uses the odd carry to calculate the even carry.

[0131] Step 7: Complete the calculation of local sum and carry output.

[0132] Specifically, the total amount of adders required for the fixed-point unit of floating-point coefficients in the down-sampling digital filter and the number of adders on the critical path have been optimized through the optimal fixed-point encoding method. The performance of the multiplication and addition unit in the fixed-point unit has been improved through the optimization of multiplication and addition operations. The performance of the fixed-point unit of floating-point coefficients in the down-sampling digital filter has been improved by optimizing the design from both the overall structure and the individual unit levels.

[0133] It should be noted that through constraints and synthesis, the RTL design circuit implementation code can be converted into a gate-level netlist hardware circuit under specific restrictions. The power consumption and delay of the floating-point coefficient fixed-point unit circuit in the synthesized downsampling digital filter are significantly improved while the area remains almost unchanged.

Claims

1. A method for designing a fixed-point unit for floating-point coefficients of a Σ-Δ ADC downsampling digital filter, characterized in that: include: Optimal fixed-point encoding method and multiplication-addition operation optimization method; Among them, The floating-point coefficients required by the Σ-ΔADC downsampling digital filter are input into the optimal fixed-point encoding method, and the optimal encoded fixed-point quantization parameters are output to obtain the optimal floating-point coefficient fixed-point unit structure. The multiplication and addition operation optimization method is used to optimize the operation unit structure in the floating-point coefficient fixed-point unit of the Σ-ΔADC downsampling digital filter.

2. The method for designing a floating-point coefficient fixed-point unit for a Σ-Δ ADC downsampling digital filter according to claim 1, characterized in that: The optimal fixed-point encoding method comprises: Optimal coding method based on graph theory and hybrid coding combination method; among them, The optimal coding method based on graph theory is connected with the hybrid coding combination method; the floating-point coefficients required by the Σ-ΔADC downsampling digital filter are input into the optimal coding method based on graph theory, and the optimized code is output; the optimized code output by the optimal coding method based on graph theory is input into the hybrid coding combination method, and finally the fixed-point quantization parameter of the optimal code is output.

3. The method for designing a floating-point coefficient fixed-point unit for a Σ-Δ ADC downsampling digital filter according to claim 1, characterized in that: The multiplication-addition operation optimization method comprises the following steps: The first step is to replace the multiplication operation with shift addition; The second step is to initialize the group generation signal and the group propagation signal according to the generation function and the transfer function; The third step is to calculate the signal generated by each individual group and the signal propagated by the group; The fourth step is to use the partial group pre-calculation in the Brent-Kung structure to generate odd carry; The fifth step is to gradually reduce the number of additional PG units required in the subsequent Kogge-Stone structure; Step 6, the last level uses the odd carry to calculate the even carry; Step 7: Complete the calculation of local sum and carry output.

4. The method for designing a floating-point coefficient fixed-point unit for a Σ-Δ ADC downsampling digital filter according to claim 2, characterized in that: The optimal coding method based on graph theory, The following steps are involved: The first step is to initialize the input set A and the graph set B; The second step is to make all elements of set A positive and singular; The third step is to calculate the required additive cost of the coefficients in set A; Step 4: Move the coefficients with a cost of 1 in set A to set B; Step 5: Calculate the coefficients in set B that can produce a cost of 0; Step 6: The generated coefficients are stored in set C and randomly added or subtracted; Step 7: Move the coefficients with the value in set A to set B; Step 8: Determine whether there are any coefficients to be moved into set B. If yes, return to step 5: calculate the coefficients in set B that can produce a cost of 0. If no, execute the subsequent process, i.e., step 9: determine whether set A is empty. Step 9: Determine whether set A is empty: if so, end the entire code generation process and exit the loop; If not, then execute step 10: add new auxiliary coefficients to set B; Step 10: Add new auxiliary coefficients to set B.

5. The method for designing a floating-point coefficient fixed-point unit for a Σ-Δ ADC downsampling digital filter according to claim 2, characterized in that: The hybrid coding combination method, The following steps are involved: The first step is to compare the coding optimization effects of the two coding methods on the filter coefficients; The second step is to determine whether the performance of graph theory coding is better than the best CSD coding: if so, then execute the third step: adopt the best coding based on graph theory; if not, then execute the fourth step: adopt the best regular signed CSD coding; The third step is to use the optimal coding based on graph theory; The fourth step is to use the best regular signed CSD encoding; Step 5: The mixed coding is completed and the coding result is obtained.

6. The method for designing a floating-point coefficient fixed-point unit for a Σ-Δ ADC downsampling digital filter according to claim 1, characterized in that: The multiplication-addition operation optimization method uses carry chain rearrangement to optimize the maximum fan-out number and the number of connections, configures the logic level to be log2N+2, the maximum fan-out to be 2, and the number of connections to be 1; Where N is the number of addition bits.

7. The method for designing a floating-point coefficient fixed-point unit for a Σ-Δ ADC downsampling digital filter according to claim 3, characterized in that: The multiplication operation is replaced by shift addition, and the multiplication and addition operation is realized by full addition operation.

8. The method for designing a floating-point coefficient fixed-point unit for a Σ-Δ ADC downsampling digital filter according to claim 4, characterized in that: When new auxiliary coefficients are added to the set B, if the intermediate coefficients are correlated with each other, the optimal encoding result can be directly obtained; otherwise, new auxiliary coefficients need to be added between the coefficients to establish a connection.

9. The method for designing a floating-point coefficient fixed-point unit for a Σ-Δ ADC downsampling digital filter according to claim 5, characterized in that: The method determines that the performance of graph theory coding is better than the best CSD coding, compares the coding optimization result based on graph theory with the result of using the best regular signed CSD coding, and adopts the best coding result of the two.

10. The method for designing a floating-point coefficient fixed-point unit for a Σ-Δ ADC downsampling digital filter according to claim 7, characterized in that: The adding of the new auxiliary coefficient only considers the case of adding an additional variable, and the other cases are not processed.

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