SiC MOSFET gate drive circuit with low turn-off loss

Abstract

The embodiment of the invention relates to the technical field of electronic circuits, and provides a SiC MOSFET gate drive circuit with low turn-off loss, the SiC MOSFET gate drive circuit comprises a digital microcontroller, a push-pull circuit, a control circuit and a charge processing circuit, two parallel paths are led out from the signal output end of the digital microcontroller, one path is connected with the push-pull circuit, and the other path is connected with the control circuit and the charge processing circuit; the digital microcontroller selectively outputs a high-level signal and a low-level signal; the push-pull circuit provides a turn-on bias voltage VCC and a turn-off bias voltage VEE according to high and low level signal options; the control circuit provides an auxiliary turn-off voltage Vneg when receiving a low-level signal, so that the charge processing circuit extracts a certain amount of charges from the gate of the SiC MOSFET. According to the embodiment of the invention, the control circuit is used for providing the negative voltage for the charge processing circuit to enable the charge processing circuit to extract a certain amount of grid charges, and the drain channel current is quickly reduced, so that the turn-off low heat loss is reduced, the turn-off speed is increased, and the safety is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic circuits, and in particular to a SiC MOSFET gate drive circuit with low turn-off loss. Background Art

[0002] SiC MOSFET is a metal oxide semiconductor field effect transistor made of the third-generation semiconductor material silicon carbide SiC. It has the significant advantages of high voltage resistance, high temperature resistance, high frequency and low loss. Compared with IGBT made of Si material, it has smaller on-resistance and almost no tail current, higher switching frequency, and lower requirements for energy storage elements. It helps to reduce the size of equipment and increase power density, and can promote the high-efficiency, lightweight and high-reliability transformation of power electronic equipment.

[0003] For SiC MOSFET, higher switching speed means smaller switching loss, which requires the drive circuit to provide a sufficiently large gate drive current. The traditional gate drive circuit charges and discharges the SiC MOSFET gate through an external gate resistor connected in series between the push-to-disconnect circuit and the SiC MOSFET gate. The switching speed can be controlled by adjusting the external gate resistor, but at the same time it will increase the switching loss or bring additional voltage and current stress, which is not conducive to the reliable operation of the device.

[0004] The existing SiC MOSFET gate drive circuit introduces additional control means, such as using sampling feedback circuits and logic circuits or directly applying digital microcontrollers, etc., to dynamically adjust the drive circuit parameters during the switching transient process for the switching transient waveform of the SiC MOSFET to achieve better switching performance. For example, the variable gate resistance type circuit dynamically adjusts the equivalent external gate resistance value of the drive circuit to change the drive current size at each stage of the switching transient, and adjusts the SiC MOSFET turn-on and turn-off speed in stages; the variable drive voltage type circuit selects different gate drive voltages at different switching stages to control the device switching speed in stages; the current source type drive controls the drive current, and usually uses energy storage inductors to provide a relatively stable current drive switch device.

[0005] However, due to the limitations of the chip structure and gate materials of the current existing technology, SiC MOSFET has a relatively high internal gate resistance (about 4Ω to 10Ω). The use of voltage source drive circuits such as variable gate resistance and variable drive voltage types may not provide a large enough drive current and cannot fully utilize the high switching speed characteristics of SiC devices, or a rash increase in the drive voltage will increase the risk of gate breakdown. The use of current source drive circuits may cause the charge and discharge current to act for too long, resulting in the gate voltage being too high or too low, posing a large safety risk and being unable to ensure that the device gate voltage is always within the safe voltage range. Summary of the invention

[0006] The purpose of the embodiments of the present disclosure is to provide a SiC MOSFET gate drive circuit with low turn-off loss to solve the problems in the related art of slow turn-off speed of SiC MOSFET, insufficient drive current of SiC MOSFET or low safety.

[0007] In order to solve the above technical problems, an embodiment of the present disclosure provides a SiC MOSFET gate drive circuit with low turn-off loss, wherein the gate drive circuit includes a digital microcontroller, a push-pull circuit, a control circuit, and a charge processing circuit.

[0008] The signal output end of the digital microcontroller leads to a first branch and a second branch connected in parallel, the first branch includes the push-pull circuit, the second branch includes the control circuit and the charge processing circuit connected in series, and the junction point of the first branch and the second branch is connected to the gate of the SiC MOSFET.

[0009] The digital microcontroller selectively outputs a high level signal and a low level signal.

[0010] The push-pull circuit provides a positive voltage as a turn-on bias voltage VCC to the gate of the SiC MOSFET when receiving a high-level signal, and provides a negative voltage as a turn-off bias voltage VEE to the gate of the SiC MOSFET when receiving a low-level signal.

[0011] The control circuit includes a logic processing unit and a voltage output end, the charge processing circuit includes a charge extraction unit and a first diode, the voltage output end of the control circuit is connected to the charge extraction unit and then connected in series to the cathode of the first diode, the anode of the first diode is connected to the gate of the SiC MOSFET, and the control circuit provides an auxiliary turn-off voltage Vneg to turn on the first diode when receiving a low-level signal, and enables the charge extraction unit to extract a certain amount of charge from the gate of the SiC MOSFET.

[0012] The auxiliary turn-off voltage Vneg is less than the turn-off bias voltage VEE.

[0013] In some embodiments, the charge extraction unit includes a first capacitor and a current mirror.

[0014] One end of the first capacitor is connected to the first pin of the voltage output end of the control circuit, the other end of the first capacitor is connected to the input side of the current mirror, the output side of the current mirror is connected to the cathode of the first diode, and the emitter of the current mirror is connected to the second pin of the voltage output end of the control circuit.

[0015] When the control circuit receives a low level signal, a potential difference is formed between the first pin and the second pin, and the control unit outputs an auxiliary shutdown voltage Vneg.

[0016] In some embodiments, the current mirror includes a first transistor and a second transistor connected to each other at their emitters, the collector and base of the first transistor are short-circuited, and the emitter connected to the first transistor and the second transistor is connected to the second pin of the voltage output terminal of the control circuit; or,

[0017] The first transistor and the second transistor are replaced by a MOS driving transistor and a MOS load transistor.

[0018] In some embodiments, a charge regulating resistor is connected in series between the current mirror and the first capacitor.

[0019] In some embodiments, the charge extraction unit includes a switched capacitor integrator, a current sampling resistor, and a first switch tube.

[0020] One end of the switch capacitor integrator is connected to the first pin of the voltage output end of the control circuit, the other end of the switch capacitor integrator is connected to the cathode of the first diode, and the anode of the first diode is connected to the gate of the SiCMOSFET;

[0021] One end of the first switch tube is connected to the second pin of the voltage output end of the control circuit, the other end of the first switch tube is connected in series to one end of the current sampling resistor, the other end of the current sampling resistor is connected to the cathode of the first diode, and the third end of the first switch tube is connected to the third pin of the control circuit. When the control circuit receives a low-level signal, a potential difference is formed between the third pin and the second pin, providing an auxiliary shutdown voltage Vneg to turn on the first switch tube.

[0022] In some embodiments, the first switch tube is selected from one of an NMOS tube, a triode, and a field effect tube.

[0023] In some embodiments, the gate drive circuit further includes a variable gate resistance circuit, wherein the variable gate resistance circuit is arranged between the voltage output terminal of the push-pull circuit and the gate of the SiC MOSFET.

[0024] The variable gate resistance circuit includes a gate turn-on resistor and a gate turn-off resistor connected in parallel. The branch where the gate turn-on resistor is located is provided with a second switch tube for controlling on and off, and the branch where the gate turn-off resistor is located is provided with a third diode for controlling on and off.

[0025] In some embodiments, the cathode of the third diode is connected to the voltage output end of the push-pull circuit, the anode of the third diode is connected to one end of the gate turn-off resistor, the other end of the gate turn-off resistor is connected to the SiC MOSFET gate, and the third diode is turned off by the reverse voltage when the control voltage outputs the auxiliary turn-off voltage Vneg.

[0026] In some embodiments, the second switch tube is a PMOS tube or a triode, a first end of the second switch tube is connected to the voltage output end of the push-pull circuit, the other end of the second switch tube is connected to one end of the gate turn-on resistor, the other end of the gate turn-on resistor is connected to the SiC MOSFET gate, the second switch tube is turned on when the push-pull circuit outputs a positive driving voltage VCC, and is turned off when the push-pull circuit outputs a negative driving voltage VEE.

[0027] In some embodiments, the gate-on resistor Rgon has a resistance value greater than the gate-off resistor Rgoff.

[0028] According to the gate charge characteristic curve of SiC MOSFET, the disclosed embodiment controls the gate charge through a driving circuit, extracts the gate charge when the SiC MOSFET is turned off, thereby realizing control of the internal gate-source voltage, thereby reducing the internal gate-source voltage, quickly reducing the magnitude of the drain channel current, and realizing reduction of the switching loss of the SiC MOSFET; by applying an auxiliary turn-off voltage Vneg lower than the conventional negative turn-off voltage VEE, a higher gate turn-off current is realized to obtain a faster SiC MOSFET turn-off speed, and further reduce the switching loss of the SiC MOSFET; by using a gate charge processing circuit provided with a diode, automatic switching of the turn-off drive voltage from Vneg to VEE is realized, and the operation is safe and reliable; from a general point of view, by increasing the turn-off drive current, the gate-source voltage drop speed of the MOSFET is accelerated, the charging and discharging characteristics of the parasitic capacitor Coss are fully utilized, the total switching loss of the SiC MOSFET is reduced, and the safety is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0030] Figure 1 Schematic diagram of the overall structure of a SiC MOSFET gate drive circuit with low turn-off loss according to an embodiment of the present disclosure;

[0031] Figure 2 Schematic diagram of the structure of a SiC MOSFET gate drive circuit with low turn-off loss according to an embodiment of the present disclosure;

[0032] Figure 3 Schematic diagram of the working waveform of the SiC MOSFET gate drive circuit with low turn-off loss according to the embodiment of the present disclosure;

[0033] Figure 4 Schematic diagram of SiC MOSFET channel current and drain current;

[0034] Figure 5 Schematic diagram of the gate charge characteristic curve of SiC MOSFET;

[0035] Figure 6 It is a schematic structural diagram of a SiC MOSFET gate drive circuit with low turn-off loss according to another implementation of the embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Various aspects and features of the present disclosure are described herein with reference to the drawings.

[0037] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present disclosure will occur to those skilled in the art.

[0038] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.

[0039] These and other characteristics of the present disclosure will become apparent from the following description of a preferred form of embodiment given as a non-limiting example, with reference to the attached drawings.

[0040] It should also be understood that, although the present disclosure has been described with reference to some specific examples, those skilled in the art will be able to realize many other equivalent forms of the present disclosure that have the features described in the claims and are therefore within the scope of protection defined thereby.

[0041] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

[0042] Specific embodiments of the present disclosure are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments claimed are merely examples of the present disclosure, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant details. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present disclosure in a variety of ways with substantially any suitable detailed structure.

[0043] This specification may use the phrases "in one embodiment," "in another embodiment," "in a further embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present disclosure.

[0044] It is worth explaining in advance that studies have shown that SiC MOSFET has parasitic capacitance, that is, the equivalent capacitance caused by its own structure. The equivalent capacitance cannot be considered as the actual capacitance structure. The following parasitic capacitances are mentioned in this specification and the drawings, including: gate-source capacitance Cgs, gate-drain capacitance Cgd and drain-source capacitance Cds, which can be divided into input capacitance Ciss (equal to the sum of gate-source capacitance Cgs and drain-source capacitance Cds), output capacitance Coss (equal to the sum of gate-drain capacitance Cgd and drain-source capacitance Cds), and reverse transfer capacitance Crss (equal to gate-drain capacitance Cgd).

[0045] Embodiment 1

[0046] See also Figure 1 , Figure 2 The embodiment of the present disclosure provides a SiC MOSFET gate drive circuit with low turn-off loss (hereinafter referred to as “gate drive circuit”). The source of the SiC MOSFET 10 is grounded, and the gate G is provided with a gate drive circuit.

[0047] The gate drive circuit includes: a digital microcontroller for outputting PWM level signals, a push-pull circuit 20, a control circuit 1, and a charge processing circuit 2. The signal output end of the digital microcontroller leads to a first branch and a second branch connected in parallel, the first branch is connected to the push-pull circuit 20, the second branch is connected to the control circuit 1 and the charge processing circuit 2, and the junction of the two branches is connected to the gate of the SiCMOSFET 10.

[0048] Among them, the push-pull circuit 20 has a signal input terminal and a voltage output terminal, the signal input terminal is connected to the digital microcontroller to receive the PWM level signal, and the voltage output terminal is connected to the SiC MOSFET gate, which is used to amplify the drive current according to the PWM level signal, and can provide a turn-on bias voltage VCC for the SiC MOSFET gate when the PWM level signal is high, and provide a turn-off bias voltage VEE for the SiC MOSFET gate when the PWM level signal is low. Specifically, the push-pull circuit 20 is a transistor push-pull circuit or a MOS tube push-pull circuit, and can also be replaced by a MOSFET half-bridge circuit, which realizes output of different levels and power amplification capabilities by alternately turning on the upper and lower tubes of the half-bridge through complementary drive signals.

[0049] The control circuit 1 has a signal input terminal and a voltage output terminal, the signal input terminal is connected to a digital microcontroller to receive a PWM level signal, and the voltage output terminal is connected to a charge processing circuit 2. The control circuit 1 includes a logic processing element such as a DSP processor or an FPGA processor, which can perform logic processing on the PWM level signal transmitted from the signal input terminal, and when the received PWM level signal is a low level, a negative voltage is provided for a certain period of time as an auxiliary shutdown voltage Vneg for the charge processing circuit 2, which will be described below in conjunction with the charge processing circuit 2.

[0050] The charge processing circuit 2 includes a charge extraction unit and a first diode D1 , and is capable of extracting a certain amount of charge from the gate of the SiC MOSFET when the control circuit 1 provides an auxiliary turn-off voltage Vneg.

[0051] In this embodiment, the charge extraction unit includes a first capacitor Cq and a current mirror.

[0052] Specifically, one end of the first capacitor Cq is connected to the first pin of the voltage output end of the control circuit 1, the other end of the first capacitor Cq is connected to the input side (Q1 side) of the current mirror, the output side (Q2 side) of the current mirror is connected to the cathode of the first diode D1, and the anode of the first diode D1 is connected to the gate of the SiC MOSFET.

[0053] The current mirror includes a paired first transistor Q1 and a second transistor Q2. The collector and base of the first transistor Q1 are short-circuited. The emitters of the first transistor Q1 and the second transistor Q2 in the current mirror are connected to the second pin of the voltage output terminal of the control circuit 1. During a period of time when the PWM level signal is at a low level, there is a potential difference between the first pin and the second pin of the voltage output terminal of the control circuit 1, which can apply a negative voltage for a certain period of time to the first capacitor Cq and the input side of the current mirror as an auxiliary shutdown voltage Vneg.

[0054] In a specific embodiment, the first transistor Q1 and the second transistor Q2 in the current mirror are bipolar transistors. A charge regulating resistor Rq is connected in series between the first capacitor Cq and the control circuit to limit the current size, thereby realizing quantitative charge extraction. In other specific embodiments, the current mirror can use a MOSFET tube current mirror or other current amplifier circuit. Any circuit that can track or amplify the charge and discharge current of the capacitor Cq can be used for quantitative gate charge extraction.

[0055] Figure 3 The working waveform of the SiC MOSFET gate drive circuit of the embodiment of the present disclosure is shown, and specifically the timing diagram of the PWM level signal, the SiC MOSFET gate drive voltage Vdr, the external gate-source voltage Vgs(ext) of the SiC MOSFET, the internal gate-source voltage Vgs(int) of the SiC MOSFET, the drain voltage Vds of the SiC MOSFET, the drain channel current ich of the SiC MOSFET, and the drain current id of the SiC MOSFET are shown. Figure 3 As shown:

[0056] like Figure 3 As shown, t0~t4 is the process of SiC MOSFET turning on:

[0057] At time t0, the PWM level signal changes from low level to high level, and the push-pull circuit outputs a positive drive voltage VCC. At this time, the gate drive voltage Vdr is the positive drive voltage VCC;

[0058] During the time period t0 to t1, the gate drive voltage Vdr starts to charge the gate capacitance Cgs, and the external gate-source voltage Vgs(ext) and the internal gate-source voltage Vgs(int) of the SiC MOSFET start to rise.

[0059] At time t1, the internal gate-source voltage Vgs(int) reaches the threshold;

[0060] In the time period from t1 to t2, the drain current id of the SiC MOSFET begins to rise, the drain voltage Vds begins to decrease, and the SiC MOSFET begins to turn on and enter the saturation region;

[0061] At time t2, the internal gate-source voltage vgs(int) reaches the threshold, and the drain current id approaches the threshold;

[0062] During the time period t2 to t3, due to the Miller platform effect, the internal gate-source voltage vgs(int) remains unchanged at the Miller platform Vmiller, and the drain voltage Vds decreases to charge the gate-drain capacitance Cgd;

[0063] At time t3, the drain voltage Vds drops to 0, the gate-drain capacitance Cgd is fully charged, and the drain current id reaches the load current value IL;

[0064] During the time period from t3 to t4, the internal gate-source voltage Vgs(int) continues to rise;

[0065] At time t4, the internal gate-source voltage Vgs(int) reaches the threshold, after which the SiC MOSFET is fully turned on.

[0066] like Figure 3 As shown, t5 to t8 are the process of SiC MOSFET turning off:

[0067] At time t5, the PWM level signal changes from high level to low level. At this time, the push-pull circuit 20 provides a turn-off bias voltage VEE to the SiC MOSFET gate, and the control circuit 1 provides a negative voltage lower than the turn-off bias voltage VEE to the charge processing circuit 2 as an auxiliary turn-off voltage Vneg. At this time, the gate drive voltage Vdr drops to the auxiliary turn-off voltage Vneg.

[0068] In the time period t5-t6, under the action of the auxiliary turn-off voltage Vneg, the first capacitor Cq is charged, and the current mirror extracts the same amount of charge as the first capacitor Cq from the gate of the SiCMOSFET to form a mirror current, so that the external gate-source voltage Vgs(ext) of the SiC MOSFET drops to a negative value until the auxiliary turn-off voltage Vneg, thereby causing the internal gate-source voltage Vgs(int) to drop rapidly, and the drain channel current ich to drop rapidly;

[0069] At time t6, the voltage provided by the control circuit 1 to the charge processing circuit 2 becomes 0V, the first diode D1 is turned off, the current mirror stops working, and the SiC MOSFET gate drive voltage Vdr becomes the turn-off bias voltage VEE provided by the push-pull circuit 20. At this time, the drain channel current ich has dropped to almost zero;

[0070] During the time period t6 to t7, the SiC MOSFET gate drive voltage Vdr remains at the off bias voltage VEE, the external gate-source voltage Vgs(ext) is still negative, the internal gate-source voltage Vgs(int) continues to decrease, the gate-drain capacitance Cgd discharges, the drain voltage Vds increases, and the drain current id decreases;

[0071] At time t7, the drain voltage Vds reaches the threshold, and the drain current id drops to almost zero;

[0072] During the time period from t7 to t8, the external gate-source voltage Vgs(ext) and the internal gate-source voltage Vgs(int) of the SiC MOSFET gradually decrease to synchronization, and when reaching a steady state, they are equal to the turn-off bias voltage VEE, and the SiC MOSFET is completely turned off.

[0073] The disclosed embodiment uses the control circuit 1 to provide a negative voltage to the charge processing circuit 2 so that it extracts a certain amount of gate charge, and before the drain voltage Vds increases, the drain channel current ich ( Figure 3 In the t5-t6 period), it is possible to achieve extremely low heat loss during the shutdown process and accelerate the shutdown speed of SiC MOSFET. Figure 4 , Figure 5 A brief description of the relevant research:

[0074] See also Figure 4 , the drain current id of SiC MOSFET is the sum of the drain channel current ich and the charge and discharge current ioss of the output capacitor Coss. The drain channel current ich is generated by the asynchronous change of the external gate-source voltage Vgs(ext) and the internal gate-source voltage Vgs(int) of SiC MOSFET, and the current is the current that actually generates heat loss. Reducing the drain channel current ich can reduce the switching loss of SiC MOSFET.

[0075] See also Figure 5 The provided SiC MOSFET gate charge characteristic curve characterizes the relationship between the total charge injected / extracted by the drive circuit into the device gate and the actual device internal gate-source voltage Vgs. Specifically, for MOSFET devices, when the operating voltage remains unchanged and the load current iL changes, the Miller platform voltage of the charge characteristic curve changes. The greater the load current, the higher the Miller platform voltage, but the total gate charge required for full turn-on remains unchanged; when the operating voltage changes but the load current iL remains unchanged, the Miller platform of the charge characteristic curve does not change, but the total gate charge increases. The SiC MOSFET gate charge Qg satisfies the following formula (where Rds_on is the MOSFET on-resistance, gm is the device transconductance, and since Rds_on is generally at the milliohm level, its effect on the gate charge characteristics can be ignored):

[0076] Q g =(V dc +VCC-VEE-I L ·R ds_on )C gd +(VCC-VEE)C gs

[0077] V miller =I L / g m

[0078] That is to say, under the premise that the operating voltage provided to the device is stable, even if the load current conditions are different, the SiC MOSFET gate charge Qg required to turn the device on and off is quantitative. In other words, as long as the SiC MOSFET gate charge Qg is controlled, the internal gate-source voltage Vgs(int) can be controlled.

[0079] Therefore, in the process of turning off the SiC MOSFET, when the PWM level signal changes from a high level to a low level, the control circuit 1 is used to provide a voltage to the first capacitor Cq in the charge processing circuit 2 to charge it, and the current mirror in the charge processing circuit 2 can be used to quickly extract the gate charge of the SiC MOSFET, that is, the internal gate-source voltage Vgs(int) can be reduced, thereby quickly reducing the size of the drain channel current ich, thereby reducing the switching loss of the SiC MOSFET.

[0080] At the same time, it is affected by the internal gate resistance Rg(in) of SiC MOSFET, see Figure 3 During the start-up process of SiC MOSFET, its internal gate-source voltage Vgs(int) lags behind the external gate voltage Vgs(ext). Therefore, during the shutdown process, a higher driving voltage (i.e., auxiliary shutdown voltage Vneg) is applied in a short time, and the internal gate-source voltage is switched back to a safer low driving voltage (i.e., shutdown bias voltage VEE) before the internal gate-source voltage exceeds the safety range. This can not only achieve a faster shutdown speed, but also ensure shutdown safety, which significantly improves the shutdown performance of SiC MOSFET.

[0081] As long as the amount of gate charge extracted is controlled within a safe range, no matter how large the drive voltage and drive current are during the extraction of gate charge, the internal gate-source voltage of the SiC MOSFET will not exceed the safe range and cause gate breakdown damage, which has higher safety.

[0082] like Figure 1 , Figure 2 As shown, preferably, the gate drive circuit of the embodiment of the present disclosure further includes a variable gate resistance circuit 30. The variable gate resistance circuit 30 is connected in series between the voltage output terminal of the push-pull circuit and the gate G of the SiC MOSFET, and is used to adjust the external gate resistance value according to the working characteristics of the SiC MOSFET, thereby adjusting the push-pull current when the SiC MOSFET is turned on and off.

[0083] The variable gate resistance circuit 30 includes a gate turn-on resistor Rgon and a gate turn-off resistor Rgoff connected in parallel. The branch where the gate turn-on resistor Rgon is located is provided with a second switch tube S2 for controlling on and off. The branch where the gate turn-off resistor Rgoff is located is provided with a third diode D3 for controlling on and off.

[0084] Specifically, Figure 2 As shown, two paths are led out from the voltage output end of the push-pull circuit, one path is connected in series with the second switch tube S2 and the gate turn-on resistor Rgon, and the other path is connected in series with the third diode D3 and the gate turn-off resistor Rgoff. The intersection of the variable gate resistor circuit 30 is connected to the gate of the SiC MOSFET.

[0085] Furthermore, the second switch tube S2 is a PMOS tube with a grounded gate, the source of the second switch tube S2 is connected to the voltage output end of the push-pull circuit 20, the drain of the second switch tube S2 is connected to the gate turn-on resistor Rgon, and the second switch tube S2 can be turned on when the PWM level signal is high and the push-pull circuit outputs a positive driving voltage VCC, and can be turned off when the PWM level signal is low and the push-pull circuit outputs a negative driving voltage VEE.

[0086] The cathode of the third diode D3 is connected to the voltage output end of the push-pull circuit 20 , the anode of the third diode D3 is connected to one end of the gate turn-off resistor Rgoff, and the other end of the gate turn-off resistor Rgoff is connected to the gate of the SiC MOSFET.

[0087] Furthermore, the resistance value of the gate turn-on resistor Rgon is greater than the gate turn-off resistor Rgoff. Setting a larger gate turn-on resistor Rgon can protect the SiC MOSFET gate to avoid turn-on oscillation and overcurrent and overvoltage phenomena. Setting a smaller gate turn-off resistor Rgoff can maximize the turn-off speed of the SiC MOSFET, thereby reducing the turn-off loss.

[0088] See also Figure 3 , during the switching process of the SiC MOSFET of this preferred embodiment:

[0089] In the time period t0 to t4, the PWM level signal is at a high level, and the push-pull circuit 20 provides a positive voltage (turn-on bias voltage VCC), so that the second switch tube S2 is turned on, and the third diode D3 is turned off, and the push-pull current flows through the gate turn-on resistor Rgon to charge the gate capacitor Cgs until the SiC MOSFET is turned on;

[0090] In the time period of t5-t6, the push-pull circuit 20 provides the turn-off bias voltage VEE, and the control circuit 1 provides a voltage more negative than the turn-off bias voltage VEE (auxiliary turn-off voltage Vneg), so that the second switch tube S2 is turned off, and D1 is turned off by the reverse voltage, and the gate charge of the SiC MOSFET is extracted by the charge processing circuit 2, and no current flows through the gate turn-on resistor Rgon and the gate turn-off resistor Rgoff;

[0091] During the time period t6 to t8, the push-pull circuit 20 provides a negative voltage (off bias voltage VEE), and the control circuit 1 no longer provides voltage, so that the second switch tube S2 is turned off, and D1 is turned on, and current flows through the gate off resistor Rgoff.

[0092] The disclosed embodiment can not only adjust the size of the external gate resistance of the SiC MOSFET according to the characteristics of the SiC MOSFET to make the SiC MOSFET have higher switching performance, but also when the control circuit 1 provides the auxiliary turn-off voltage Vneg (time period t5-t6), the third diode D3 can be used to temporarily isolate the gate turn-off resistance Rgoff to prevent the auxiliary turn-off voltage Vneg from affecting the circuit, further ensuring that the internal gate voltage Vgs(int) of the SiC MOSFET is always within a safe range, thereby improving the turn-off safety of the SiC MOSFET.

[0093] The present invention utilizes the correspondence between the gate-source voltage and the gate charge inside the MOSFET. Under the premise of ensuring safety through gate charge control, the drive circuit of the present invention adopts an auxiliary turn-off voltage Vneg that is lower than the conventional negative turn-off voltage VEE, which can provide a larger drive current, has a stronger driving capability, can achieve a higher turn-off speed, and lower switching loss.

[0094] In summary, the disclosed embodiment controls the gate charge through the driving circuit according to the gate charge characteristic curve of SiC MOSFET, extracts the gate charge when the SiC MOSFET is turned off, thereby realizing the control of the internal gate-source voltage, thereby reducing the internal gate-source voltage Vgs(int), quickly reducing the size of the drain channel current ich, and realizing the reduction of the switching loss of the SiC MOSFET; by applying an auxiliary turn-off voltage Vneg lower than the conventional negative turn-off voltage VEE, a higher gate turn-off current is realized to obtain a faster SiC MOSFET turn-off speed, and further reduce the switching loss of the SiC MOSFET; by using a gate charge processing circuit provided with a diode to realize the automatic switching of the turn-off drive voltage from Vneg to VEE, the operation is safe and reliable; from a general point of view, by increasing the turn-off drive current to accelerate the drop speed of the internal gate-source voltage of the MOSFET, the charging and discharging characteristics of the parasitic capacitor Coss are fully utilized, the total switching loss of the SiC MOSFET is reduced, and the safety is improved.

[0095] Embodiment 2

[0096] like Figure 6 As shown, the gate drive circuit of the embodiment of the present disclosure includes a digital microcontroller and a push-pull circuit 20 and a variable gate resistance circuit 30 for outputting PWM level signals, which are the same as those in the first embodiment, and also includes another control circuit 1a and a charge processing circuit 2a which are different in structure from those in the first embodiment.

[0097] In the charge processing circuit 2a, the charge extraction unit includes a switched capacitor integrator 201, a current sampling resistor Rsense, and a first switch tube S1.

[0098] Specifically, one end of the switched capacitor integrator 201 is connected to the first pin of the voltage output end of the control circuit 1a, and the other end of the switched capacitor integrator 201 is connected to the cathode of the first diode D1a, and the anode of the first diode D1a is connected to the gate of the SiCMOSFET. The switched capacitor integrator 201 is a common circuit structure, which includes switches and capacitors, and can be charged and discharged according to the signal sent by the control circuit 1a.

[0099] In this embodiment, the first switch tube S1 is an NMOS tube, the gate of the first switch tube S1 is connected to the second pin of the voltage output terminal of the control circuit 1a, the drain of the first switch tube S1 is connected in series with one end of the current sampling resistor Rsense, and the other end of the current sampling resistor Rsense is connected to the cathode of the first diode D1a. The resistance of the current sampling resistor Rsense is very small and can be ignored, and is used to sample the current in the path where it is located, so that the control circuit 1a can control the switch capacitor integrator 201 to extract a certain amount of charge from the gate of the SiC MOSFET according to the sampled value.

[0100] The source of the first switch tube S1 is connected to the third pin of the output end of the control circuit 1a, and the gate of the first switch tube S1 is connected to the second pin of the voltage output end of the control circuit 1a. When the control circuit 1a receives a low-level PWM level signal, a potential difference is formed between the third pin and the second pin to provide a negative voltage as an auxiliary turn-off voltage Vneg to turn on the first switch tube S1. In other specific embodiments, the switch tube S2 can also be a triode or other types of field effect tubes.

[0101] During the time when the PWM level signal is at a low level, there is a potential difference between the second pin and the third pin of the voltage output end of the control circuit 1a, which can apply a negative voltage between the gate-source of the first switch tube S1 for a certain period of time to make it turn on; when the first switch tube S1 is turned on, the switched capacitor integrator 201 is connected in parallel with the current sampling resistor Rsense, so the switched capacitor integrator 201 can extract a certain amount of charge according to the sampling value of the current sampling resistor Rsense.

[0102] The operating waveform of the SiC MOSFET gate drive circuit in the embodiment of the present disclosure is the same as that in the first embodiment, and can also be used Figure 3 Indicates. Figure 3 As shown, t5 to t8 are the process of SiC MOSFET turning off:

[0103] At time t5, the PWM level signal changes from high level to low level. At this time, the push-pull circuit 20 provides the turn-off bias voltage VEE to the SiC MOSFET gate, and the control circuit 1a provides the charge processing circuit 2a with a negative voltage lower than the turn-off bias voltage VEE as the auxiliary turn-off voltage Vneg to turn on the first diode D1a and the first switch tube S1, and current begins to flow through the current sampling resistor Rsense, and the control circuit 1a turns on the switch capacitor integrator 201. At this time, because the auxiliary turn-off voltage Vneg is less than the turn-off bias voltage VEE, the gate drive voltage Vdr drops to the auxiliary turn-off voltage Vneg;

[0104] In the time period t5 to t6, the switch capacitor integrator 201 calculates the amount of charge extracted, so that the external gate-source voltage Vgs(ext) of the SiC MOSFET drops to a negative value until the auxiliary turn-off voltage Vneg, thereby causing the internal gate-source voltage Vgs(int) to drop rapidly, and the drain channel current ich to drop rapidly;

[0105] At time t6, the switched capacitor integrator 201 reaches the expected charge amount, the control circuit 1a turns off the switched capacitor integrator 201, and no longer provides the auxiliary turn-off voltage Vneg, the first diode D1a and the first switch tube S1 are turned off, and the SiC MOSFET gate drive voltage Vdr becomes the turn-off bias voltage VEE provided by the push-pull circuit 20. At this time, the drain channel current ich has dropped to almost zero.

[0106] This embodiment adopts a circuit structure different from that of the first embodiment, and achieves the same beneficial effects, which will not be described in detail here.

[0107] In addition, any circuit solution that can monitor and control the amount of charge can be applied to the gate drive circuit to achieve the same function as the gate charge controlled SiC MOSFET drive technology proposed in the present invention.

[0108] In the description of the present disclosure, it is necessary to understand that the orientation or positional relationship indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the scope of protection of the present disclosure; the directional words "inside and outside" refer to the inside and outside relative to the outline of each component itself.

[0109] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0110] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present disclosure.

[0111] The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. For those skilled in the art, the present disclosure may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

[0112] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other to form a technical solution.

[0113] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0114] Although the subject matter has been described in language specific to structural features and / or methodological logical actions, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. On the contrary, the specific features and actions described above are merely example forms of implementing the claims.

[0115] Multiple embodiments of the present disclosure are described in detail above, but the present disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concepts of the present disclosure, and these variations and modifications should all fall within the scope of protection required by the present disclosure.

Claims

1. A low turn-off loss SiC MOSFET gate drive circuit, characterized in that: The gate drive circuit includes a digital microcontroller, a push-pull circuit, a control circuit, and a charge processing circuit; The signal output terminal of the digital microcontroller leads to a first branch and a second branch connected in parallel, the first branch includes the push-pull circuit, the second branch includes the control circuit and the charge processing circuit connected in series, and the junction point of the first branch and the second branch is connected to the gate of the SiC MOSFET; The digital microcontroller selectively outputs a high level signal and a low level signal; The push-pull circuit provides a positive voltage as a turn-on bias voltage VCC to the gate of the SiC MOSFET when receiving a high-level signal, and provides a negative voltage as a turn-off bias voltage VEE to the gate of the SiC MOSFET when receiving a low-level signal; The control circuit includes a logic processing unit and a voltage output terminal, the charge processing circuit includes a charge extraction unit and a first diode, the voltage output terminal of the control circuit is connected to the charge extraction unit and then connected in series to the cathode of the first diode, the anode of the first diode is connected to the gate of the SiC MOSFET, and the control circuit provides an auxiliary turn-off voltage Vneg to turn on the first diode when receiving a low-level signal, and enables the charge extraction unit to extract a certain amount of charge from the gate of the SiC MOSFET; The auxiliary turn-off voltage Vneg is less than the turn-off bias voltage VEE.

2. The low turn-off loss SiC MOSFET gate drive circuit according to claim 1, characterized in that: The charge extraction unit includes a first capacitor and a current mirror; One end of the first capacitor is connected to a first pin of a voltage output terminal of the control circuit, the other end of the first capacitor is connected to an input side of the current mirror, an output side of the current mirror is connected to a cathode of a first diode, and an emitter of the current mirror is connected to a second pin of a voltage output terminal of the control circuit; When the control circuit receives a low level signal, a potential difference is formed between the first pin and the second pin, and the control unit outputs an auxiliary shutdown voltage Vneg.

3. The low turn-off loss SiC MOSFET gate drive circuit according to claim 2, characterized in that: The current mirror comprises a first transistor and a second transistor connected at their emitters, the collector and base of the first transistor are short-circuited, and the emitters of the first transistor and the second transistor connected are connected to the second pin of the voltage output terminal of the control circuit; or, The first transistor and the second transistor are replaced by a MOS driving transistor and a MOS load transistor.

4. The low turn-off loss SiC MOSFET gate drive circuit according to claim 2, characterized in that: A charge regulating resistor is connected in series between the current mirror and the first capacitor.

5. The low turn-off loss SiC MOSFET gate drive circuit according to claim 1, characterized in that: The charge extraction unit includes a switched capacitor integrator, a current sampling resistor, and a first switch tube. One end of the switch capacitor integrator is connected to the first pin of the voltage output end of the control circuit, the other end of the switch capacitor integrator is connected to the cathode of the first diode, and the anode of the first diode is connected to the gate of the SiCMOSFET; One end of the first switch tube is connected to the second pin of the voltage output end of the control circuit, the other end of the first switch tube is connected in series to one end of the current sampling resistor, the other end of the current sampling resistor is connected to the cathode of the first diode, and the third end of the first switch tube is connected to the third pin of the control circuit. When the control circuit receives a low-level signal, a potential difference is formed between the third pin and the second pin, providing an auxiliary shutdown voltage Vneg to turn on the first switch tube.

6. The low turn-off loss SiC MOSFET gate drive circuit according to claim 5, characterized in that: The first switch tube is selected from one of an NMOS tube, a triode, and a field effect tube.

7. The low turn-off loss SiC MOSFET gate drive circuit according to any one of claims 5 and 6, characterized in that: The gate drive circuit further includes a variable gate resistance circuit, which is arranged between the voltage output terminal of the push-pull circuit and the gate of the SiC MOSFET. The variable gate resistance circuit includes a gate turn-on resistor and a gate turn-off resistor connected in parallel. The branch where the gate turn-on resistor is located is provided with a second switch tube for controlling on and off, and the branch where the gate turn-off resistor is located is provided with a third diode for controlling on and off.

8. The low turn-off loss SiC MOSFET gate drive circuit according to claim 7, characterized in that: The cathode of the third diode is connected to the voltage output end of the push-pull circuit, the anode of the third diode is connected to one end of the gate turn-off resistor, the other end of the gate turn-off resistor is connected to the SiC MOSFET gate, and the third diode is turned off by the reverse voltage when the control voltage outputs the auxiliary turn-off voltage Vneg.

9. The low turn-off loss SiC MOSFET gate drive circuit according to claim 7, characterized in that: The second switch tube is a PMOS tube or a triode, a first end of the second switch tube is connected to the voltage output end of the push-pull circuit, the other end of the second switch tube is connected to one end of the gate turn-on resistor, the other end of the gate turn-on resistor is connected to the SiC MOSFET gate, the second switch tube is turned on when the push-pull circuit outputs a positive driving voltage VCC, and is turned off when the push-pull circuit outputs a negative driving voltage VEE.

10. The low turn-off loss SiC MOSFET gate drive circuit according to claim 7, characterized in that: The resistance value of the gate turn-on resistor Rgon is greater than the gate turn-off resistor Rgoff.

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