Assembly line SAR ADC digital background calibration method based on pseudorandom sequence injection

Abstract

The invention relates to an assembly line SAR ADC digital background calibration method based on pseudorandom sequence injection, and belongs to the technical field of analog integrated circuits. After a residual error signal is obtained through quantization of a first-stage SAR ADC, a pseudo-random sequence is injected into the residual error signal, a superposed signal is sampled and converted by a rear-stage ADC, a nonlinear error is finally caused in a digital output code, then correlation operation is carried out on an input sequence and the digital output code to obtain error information of non-ideal factors in a circuit, and the error information of the non-ideal factors in the circuit is calculated. And finally, an actual inter-stage gain value in the circuit is approximated through a variable-step iterative algorithm to be used for digital code reconstruction analog signals, and the calibration effect is finally achieved. According to the method, the influence of the step in the iteration process on the speed and the precision can be avoided, the method is used for calibrating inter-stage gain errors caused by capacitor mismatch and finite gain of an operational amplifier, better speed and precision are achieved in the calibration iteration process, the performance of the ADC is obviously improved, the signal-to-noise ratio is increased, and the spurious-free dynamic range is widened.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits and relates to a pipeline SARADC digital background calibration method based on pseudo-random sequence injection. Background Art

[0002] Analog to Digital Converter (ADC) is an indispensable part of the signal conversion link in modern electronic systems, and it is also one of the research hotspots in the field of integrated circuits in recent years. There are many types of analog to digital converters. The traditional pipeline analog to digital converter (Pipeline ADC) has the advantages of high speed and high precision, but has the problem of high power consumption; although the successive approximation register ADC (SAR ADC) can meet the low power consumption requirements, its speed and accuracy can only be limited to 100MS / s and 10-bit accuracy. The pipeline SAR ADC is a new structure that combines SAR ADC and pipeline ADC. Compared with the traditional SAR ADC, it can have higher speed and accuracy, and lower power consumption than the traditional pipeline ADC, integrating the advantages of both. The structure of the pipeline SAR ADC is to connect multiple SAR ADCs in series, and insert a residual amplifier between every two sub-ADCs to amplify the residual value generated after the quantization of the previous sub-ADC is completed, and send it to the next sub-ADC for further quantization.

[0003] There are various non-ideal factors in the ADC, which will affect the noise and linearity of the ADC and limit the performance of the ADC. Therefore, calibration technology is needed to calibrate the errors caused by non-ideal factors in the pipeline SAR ADC. ADC calibration technology is mainly divided into analog domain and digital domain calibration. Analog domain calibration mainly achieves the purpose of calibration by adding or modifying specific circuit structures in the analog circuit. This method usually greatly increases the complexity of the circuit structure and the complexity of the circuit working timing. At the same time, the working rate of the ADC will also be subject to certain restrictions; digital domain calibration mainly places the calibration module in the digital circuit, and the modification of the analog circuit structure is relatively small. Generally, it is only necessary to add a simple auxiliary structure to the analog circuit. Its basic principle is to estimate the error caused by non-ideal factors in the analog circuit system based on the final digital output signal, and then perform error extraction and other processing on the digital output signal to finally achieve the purpose of calibrating the error. With the advancement of technology, the characteristic size of the tube is reduced, and the adaptability and portability of digital domain calibration are stronger, and the integration is also higher.

[0004] Digital calibration technology mainly includes two core stages: error measurement and signal calibration. According to the difference in execution process, this technology can be divided into two categories: foreground calibration and background calibration. Among them, foreground calibration follows the principle of sequential execution, first measuring the error, and then calibrating the signal; while background calibration adopts a parallel processing method, that is, the error measurement and signal calibration are carried out simultaneously. When using the foreground calibration method, the circuit system generally needs to add an independent calibration cycle. The calibration process in this cycle cannot be synchronized with the ADC conversion process. The specific workflow is described as follows: Once the circuit switches to the calibration mode, the first step is to introduce the calibration signal. Then the calibration DAC will take on the task of detecting the capacitor mismatch error and store the detected data in a dedicated memory. After completing this calibration step, the system immediately enters the normal quantization link. At this stage, the ADC will perform corresponding compensation processing based on the previously stored capacitor mismatch error information, and finally achieve the established calibration goal. When using the background calibration method, there is no need for additional clock signal control, and the normal conversion work of the ADC will not be interrupted. This feature greatly improves the conversion rate of the ADC, so the background digital calibration technology is widely used in various types of analog-to-digital converters. Background digital calibration technology can be divided into LMS algorithm of adaptive filter, pseudo-random sequence injection calibration algorithm, signal-related pseudo-random sequence injection calibration algorithm, code domain equalization background digital calibration algorithm and time-interleaving-based background digital calibration algorithm.

[0005] However, the problem faced by digital calibration technology is that due to process reasons, there is a manufacturing deviation between the two capacitors in the actual ADC circuit, that is, capacitor mismatch, which will cause inter-stage gain errors in the pipeline SAR ADC. Secondly, the design of the operational amplifier is the focus of the pipeline SAR ADC design. In theoretical analysis, it is often assumed that the gain of the operational amplifier is infinite, but in actual circuits, the gain of the operational amplifier is limited. Compared with the ideal transmission characteristics, an error coefficient will be introduced. As the process size is proportionally reduced, the intrinsic gain of the transistor is also reduced, resulting in the design of high-gain operational amplifiers. It is increasingly difficult to achieve, resulting in a larger error coefficient. These two factors will cause inter-stage gain errors, so the traditional digital calibration method is no longer suitable for error calibration of the smaller pipeline SAR ADC. Summary of the invention

[0006] In view of this, the object of the present invention is to provide a pipeline SAR ADC digital background calibration method based on pseudo-random sequence (i.e., pseudo-random noise, PN) injection, which is used to calibrate the inter-stage gain error caused by capacitor mismatch and limited gain of operational amplifier, and to achieve better speed and accuracy in the iterative process of calibration.

[0007] In order to achieve the above object, the present invention provides the following technical solutions:

[0008] A pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection, wherein the pipeline SAR ADC includes a first-stage SAR ADC, a residual amplifier, and a second-stage SAR ADC. The method includes the following steps:

[0009] S1, the analog input signal to be processed is sent to the first stage SAR ADC. In this stage, the SAR ADC uses its binary search algorithm to accurately sample the input signal and convert it into a digital code.

[0010] S2, when the first stage SAR ADC completes the conversion, the PN sequence (usually called m-sequence or maximum length sequence) generated by the linear feedback shift register is superimposed on the residual signal generated during the first stage SAR ADC conversion process. This superposition operation is intended to introduce a known but random disturbance to facilitate the identification and correction of potential errors in subsequent processing.

[0011] S3, the residual signal modulated by the m sequence is sent to the second-stage SAR ADC for further sampling and conversion. This stage of ADC also uses the successive approximation method. After the conversion is completed, the digital code is obtained.

[0012] S4. In the digital domain, the overall digital output D of the pipelined SAR ADC is out The digital codes (composed of the digital codes output by the first and second stage SAR ADCs) are processed for correlation analysis with the PN sequence introduced previously.

[0013] Since the PN sequence is not corrected in the analog-to-digital converter, it will eventually cause nonlinear errors in the final digital output code. This error includes the result of the non-ideal factors in the circuit acting on the PN signal. Under the condition that the PN sequence is long enough, the error is only related to the PN signal and has nothing to do with the input signal. Therefore, according to the characteristics of the PN sequence signal, it is only necessary to correct the input PN sequence and the digital output code D. out By performing correlation operations, the error information of non-ideal factors in the circuit can be obtained, which is reflected in the correlation coefficient Ecor.

[0014] S5. In view of the inter-stage gain error problem that the pipeline SAR ADC may encounter in practical applications, these errors will cause the actual gain to deviate from the ideal value, and this deviation is often unpredictable. In order to deal with this problem, an iterative method is used to estimate and adjust the gain value. Specifically, according to the correlation coefficient calculated in step S4, through an iterative process, the estimated value rG of the gain gradually approaches the true gain value. In addition, a logarithmic sigmoid function is introduced in the iterative process to dynamically adjust the iteration step size to ensure that the convergence process is both fast and stable.

[0015] S6. Finally, the gain estimation value rG obtained through iterative optimization is applied to the digital code reconstruction process of the pipeline SAR ADC, and rG is used to correct the digital code output by the ADC, thereby reconstructing an analog signal that is closer to the original.

[0016] Ideally, the inter-stage gain of the pipeline SAR ADC is an integer power of 2, and the codewords output by each stage are synthesized into the final digital code by staggered addition. When there is an influence of inter-stage gain error, the inter-stage gain is no longer an integer power of 2, and it is necessary to calculate the weight corresponding to each sub-stage digital code, and add the product of the digital code of each stage and the weight to get the final digital output. When the digital code reconstructs the analog signal in the last step of the calibration process, the estimated value rG of the actual gain is used to calculate the weight at this time for the final digital output of the ADC, and then used to reconstruct the analog signal.

[0017] Further, in step S4, D out The correlation operation with PN sequence is generally realized by accumulating data and then taking the average. The more times the accumulation is performed, the closer the average is to the expected value. However, in the circuit implementation process, this method has high computational complexity and huge resource consumption. Therefore, the sign bit is used instead of the product value for accumulation, that is, sign[D out (i)*PN(i)], the updating process of the correlation coefficient can be expressed as:

[0018] Ecor=Ecor+sign[D out (i)*PN(i)]

[0019] In the formula, Ecor represents the correlation coefficient, sign(·) represents the sign function, and D out It represents the digital signal finally output by the pipeline SAR ADC, PN represents the pseudo-random sequence, and i represents the number of calibration samples.

[0020] Furthermore, in step S5, the iterative process of making the estimated value rG of the gain gradually approach the actual gain value is expressed by the following formula:

[0021] rG(k+1)=rG(k)-step(k)*Ecor(k)

[0022] Where step represents the iteration step size, and k represents the number of calibration cycles.

[0023] Furthermore, the convergence time and offset accuracy of the algorithm are controlled by the step size. The iteration step size is an extremely important parameter. The convergence time is inversely proportional to the step size, and the offset accuracy is directly proportional to the step size. That is, the smaller the step size, the longer the convergence time. The smaller the offset, the larger the step size, the shorter the convergence time, but the larger the offset.

[0024] Therefore, in step S5, in the iterative process of achieving the convergence of the estimated value rG of the gain to the actual gain value, a logarithmic Sigmoid function is used to adjust the step size step according to the number of current calibration cycles, thereby achieving a compromise between the speed and accuracy of the adjustment iteration process. In the initial stage of calibration, the step size step is large in order to quickly approach the target value. As the calibration cycle proceeds, the step size gradually decreases, making the calibration more accurate.

[0025] Wherein, the logarithmic sigmoid function can be expressed as:

[0026] step(k)=2β{1.4+log[1+exp(|Ecor(k)| -2 ]}

[0027] Where α and β represent control coefficients, α is used to control the shape of the function, and β is used to control the value range of the function.

[0028] The beneficial effects of the present invention are as follows: the present invention can avoid the influence of the step length of the iterative process on the speed and accuracy, and is used to calibrate the inter-stage gain error caused by the capacitor mismatch and the limited gain of the operational amplifier, and achieves better speed and accuracy in the iterative process of calibration, significantly improves the performance of the ADC, and improves the signal-to-noise ratio and the spurious-free dynamic range.

[0029] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0031] Figure 1 It is a schematic diagram of the process of the method of the present invention;

[0032] Figure 2 Schematic diagram of the generation principle of m-sequence;

[0033] Figure 3 This is a simulation diagram of the logarithmic sigmoid function;

[0034] Figure 4 This is the FFT simulation comparison chart before and after calibration. Figure 4 (a) is the simulation result before calibration. Figure 4 (b) is the simulation result after calibration. DETAILED DESCRIPTION

[0035] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0036] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0037] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0038] The present invention aims at the inter-stage gain error caused by capacitor mismatch and limited gain of operational amplifier, and proposes a pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection. Among them, the pseudo-random sequence, that is, pseudo-random noise, is a well-designed and distinctive sequence, and its uniqueness is reflected in two main aspects. First, it is predictable and repeatable, that is, these sequences are not randomly generated, but generated according to certain deterministic rules or algorithms. Therefore, each element of the sequence can be calculated in advance if these rules or algorithms are known, and the sequence can be repeatedly generated and copied as needed without losing its original structure and characteristics; secondly, the pseudo-random sequence exhibits a random characteristic similar to that of a true random sequence, which is mainly reflected in their statistical characteristics, such as the expectation E[PN]=0, variance σ[PN]=1, and autocorrelation characteristics of the pseudo-random sequence. Cross-correlation characteristics Most pseudo-random sequences are generated by shift registers plus feedback, and have a simple structure, are easy to implement, and can easily generate sequences with extremely long periods. Common pseudo-random sequences include m-sequences, M-sequences, and Gold-sequences, and the most widely used pseudo-random sequence is the m-sequence. Meanwhile, this embodiment also uses the m-sequence.

[0039] The m sequence is mainly composed of elements 0 and 1 or 1 and -1. In the m sequence, for any one bit, the probability of occurrence of two different elements (such as 0 and 1, or 1 and -1) is equal, and the distribution of this probability is independent and unaffected between different bits. This characteristic is called the balance of the m sequence. The m sequence also has a very important autocorrelation characteristic. In addition, when the m sequence is long enough, its power spectrum characteristics tend to the power spectrum characteristics of white noise, so the m sequence also has a cross-correlation characteristic that is unrelated to other signals. The m sequence is generally generated by a linear feedback shift register, in which the feedback shift register is composed of multiple registers, and the output of each register is used as the input of the next one to form a shift chain. The feedback line (C0, C1, ..., Cn) is connected to the input of the register to form a feedback loop. When Ci is 1, it indicates that the i-th register is connected to the feedback loop. When it is 0, it indicates that the i-th register is not connected to the feedback loop. Generally, the values ​​of C0 and Cn are determined to be 1. The feedback connection state of the linear feedback shift register is described by a characteristic polynomial. When designing the characteristic polynomial that generates the m-sequence, a specific primitive polynomial is generally selected.

[0040] For a two-stage pipeline SAR ADC using MDAC modulation, such as Figure 1 As shown, a pseudo-random sequence is injected at the first-level residual, and the corresponding digital ideal value of the final output is expressed as:

[0041]

[0042] Where D1 is the digital code generated by the first-stage SAR ADC quantization, V res is the input signal of the back end, r is the coefficient of the PN sequence, and since the inter-stage gain value in the actual circuit is unknown, the gain estimation value is used. express. Figure 1 Where D2 is the digital code actually quantized by the second-stage ADC. D1 and D2 are expressed in the analog domain as:

[0043] D1=V in -Q1

[0044] D2=V res +Q2=G·(Q1+r·PN)+Q2

[0045] Where Q1 is the quantization error of the first stage, Q2 is the error caused by the second stage quantization, G is the equivalent inter-stage gain value related to the open-loop gain and capacitance ratio of the op amp, and D2 is used instead of V res Then D out It can also be expressed as:

[0046]

[0047] Then D out Correlation processing with PN sequence is According to the autocorrelation and cross-correlation characteristics of the PN sequence, we can obtain: When implementing the algorithm, using the symbolic function sign instead of multiplication can solve the problem of large amount of calculation and high resource consumption. Finally, the relevant result is used as the error coefficient (or correlation coefficient) to achieve the process of gain estimation value gradually converging to the actual gain value through an iterative method, that is:

[0048]

[0049] Based on this, an embodiment of the present invention is directed to Figure 1 The pipeline SAR ADC shown in FIG. 1 is used for error calibration. The pipeline SAR ADC is a 12-bit 100MS / S pipeline ADC, which uses a 12V power supply voltage and includes a 6-bit sub-stage SAR ADC and a 7-bit sub-stage SAR ADC, a residual amplifier, and a digital code reconstruction analog signal module. The pipeline ADC uses one-bit inter-stage redundancy. If the two-stage SAR ADC is designed with the same reference voltage, a 32-fold inter-stage gain is required. In order to reduce the difficulty in circuit design, the reference voltage of the second stage is reduced by half, and only a 16-fold inter-stage gain is required.

[0050] Figure 1In the example, the analog signal is sampled and converted by the first sub-stage SAR ADC to obtain the residual signal. At this time, a pseudo-random sequence is injected into the P terminal and the N terminal respectively. The pseudo-random sequence added here is given by Figure 2 The m-sequence generated by the linear feedback shift register shown in the figure, wherein the feedback shift register is composed of a plurality of registers connected in series, and the output of each register is directly supplied to the input of its subsequent register, forming a data shift chain. The system also includes a set of feedback lines (C0, C1, ..., Cn), and each feedback line determines whether to feed back the output of a specific register to the starting input of the chain according to its own state (1 indicates connection, 0 indicates disconnection), thereby forming a feedback loop. This feedback connection mode can be accurately described by a characteristic polynomial, which can reflect whether the register participates in the feedback process. When constructing a linear feedback shift register for generating an m-sequence, it is usually necessary to select a specific primitive polynomial as the characteristic polynomial to ensure the optimal properties of the generated sequence. In this embodiment, the linear shift registers used contain a total of 16, and the maximum length of the pseudo-random sequence that can be generated is (2 16 -1) bits, providing 6 groups of such linear shift registers in total, and the primitive polynomials of these linear shift registers are the same, but the initial values ​​are different, so the pseudo-random sequences generated are also different and unrelated. Any one of the 6 groups of linear shift registers can be selected to generate the m sequence.

[0051] The residual signal superimposed with the PN signal passes through the amplifier and then enters the second sub-stage SAR ADC for sampling and quantization. Since the PN signal is not corrected during the operation of the analog-to-digital converter, it will eventually cause nonlinear errors in the final digital output code. This error includes the results caused by the non-ideal factors in the circuit acting on the PN signal.

[0052] The digital code reconstruction analog signal module of the pipeline SAR ADC is divided into two reconstruction modules, one for subtracting the PN signal from the digital code, and the other for calculating the actual weight of the capacitor for calibration. Finally, the results of these two modules are used to compare the calibration effect of the PN signal. After obtaining the digital code output of the pipeline SAR ADC, the digital code is correlated with the PN signal using the sign function to obtain an error coefficient (correlation coefficient), and then the iterative process of the residual amplifier gain estimation value rG of the pipeline SAR ADC converges to the actual gain value is performed:

[0053] rG(k+1)=rG(k)-step(k)*Ecor(k)

[0054] Specifically, the pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection proposed by the present invention comprises the following steps:

[0055] Step 1: The analog input signal to be processed is fed into the first stage 6-bit SAR ADC. At this stage, the SAR ADC uses its binary search algorithm to accurately sample the input signal and convert it into a 6-bit digital code D. 1,i , where i is the bit index, ranging from 1 to 6, representing each bit in the 6-bit code.

[0056] Step 2: Next, when the first-stage SAR ADC completes its conversion task, the system enters the next step of processing. At this time, the m-sequence generated by the linear feedback shift register is superimposed on the residual signal generated during the first-stage conversion process.

[0057] Step 3: The residual signal modulated by the m sequence is sent to the second-stage 7-bit SAR ADC for further sampling and conversion. This stage of ADC also uses the successive approximation method. After the conversion is completed, a 7-bit digital code D is obtained. 2,j , where j is the bit index, ranging from 1 to 7, representing each bit of the second-stage SAR ADC 7-bit quantization result.

[0058] Step 4: In the digital domain, calculate the overall digital output D of the pipelined SAR ADC. out This step is processed to perform correlation analysis with the previously introduced PN sequence. out This is achieved by using the correlation coefficient between the PN sequence and the pipeline SAR ADC system. The correlation coefficient actually plays the role of an error parameter and can reflect the nonlinear error and other problems existing in the pipeline SAR ADC system.

[0059] Step 5: Estimate and adjust the gain value through iteration. Specifically, according to the correlation coefficient calculated in step 4, the iteration process is started to make the estimated value rG of the gain gradually approach the real gain value.

[0060] Step 6: Finally, the gain estimate rG obtained through iterative optimization is applied to the digital code reconstruction process of the pipeline SAR ADC. This step uses rG to correct the digital code output by the ADC, thereby reconstructing an analog signal that is closer to the original.

[0061] In step 5, the present invention proposes to use the logarithmic Sigmoid function to control the iteration step size step to ensure that the convergence process is both fast and stable. Specifically, based on the advantages of the series LMS algorithm of the sigmoid line, the convergence speed is fast and the calculation is simple. From the step size adjustment function u(k) = β[1-exp(-α|e(k)| 2 )], firstly, the control parameter β in the step-size adjustment function is separated to obtain the compensation adjustment function of single parameter control u(k)=1-exp(-α|e(k)| 2), and after negative logarithm operation (keeping the original function characteristics), we get u(k) = -log[1-exp(-α|e(k)| 2 ], combined with the monotonic convergence characteristics of the logarithmic function, and then negating the exponential part in the formula, we can get u(k) = -log[1+exp(-α|e(k)| 2 ]. In order to make the new adjustment function conform to the step size adjustment principle of the variable step size adaptive LMS (VSSALMS) algorithm, the inverse of the independent variable part is taken to obtain a new nonlinear function model: u(k) = -log[1+exp(-α|e(k)| -2 ], and then by flipping and translating and introducing β again, the shape of the function can be controlled. The sigmoid step size change control function model after logarithmic function reinforcement is: u(k)=2β{1.4+log[1+exp(-α|e(k)| -2 ]}.

[0062] Therefore, by replacing e(k) in the sigmoid step change control function model with the correlation coefficient Ecor(k), and replacing u(k) in the function model with step(k), a function model is obtained:

[0063] step(k)=2β{1.4+log[1+exp(-α|Ecor(k)| -2 ]}

[0064] In the iterative process in which the estimated gain value rG converges to the actual gain value through this function model, the step size is dynamically adjusted so that speed and accuracy are compromised in the iterative process. That is, the step size step is large in the initial stage of calibration in order to quickly approach the target value. As the calibration cycle proceeds, the step size gradually decreases, making the calibration more accurate.

[0065] like Figure 3 Shown is a function simulation diagram of the control step length. When the absolute value of the independent variable correlation coefficient en is large, the dependent variable step length u is also large. As the absolute value of en gradually approaches 0, the value of u also gradually decreases. This achieves a large step length in the initial stage of calibration when the error coefficient is large, and the convergence speed is fast at this time. In the later stage, when the error coefficient gradually decreases, the step length also decreases, and the accuracy is higher at this time.

[0066] Adding capacitor mismatch and finite gain, as well as amplifier offset voltage, etc. to the pipelined SAR ADC module, Figure 4 represents the output spectrum of the pipeline SAR ADC before and after calibration, where Figure 4 (a) is the simulation result before calibration. Figure 4(b) is the simulation result after calibration. It can be seen that without calibration, the SNDR is 54.71dB, the SFDR is 75.01dB, and the ENOB is 8.8bit. After calibration, the SNDR is increased to 70.68dB, the SFDR is increased to 75.86dB, and the ENOB is 11.45bit.

[0067] In summary, the pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection provided by the present invention is verified on MATLAB to be able to calibrate the capacitor mismatch and finite gain error in the pipeline SAR ADC, significantly improve the performance of the ADC, and increase the signal-to-noise ratio and spurious-free dynamic range.

[0068] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A pipeline SAR ADC digital background calibration method based on pseudo-random sequence injection, wherein the pipeline SAR ADC comprises a first-stage SAR ADC and a second-stage SAR ADC, wherein the first-stage SAR ADC and the second-stage SAR ADC are connected via a residual amplifier, wherein: The method includes: The input analog signal is sampled by the first-stage SAR ADC, and then the sampled input signal is converted into a digital code; After the first-stage SAR ADC conversion is completed, the pseudo-random sequence generated by the linear feedback shift register is superimposed on the residual signal of the first-stage SAR ADC; The residual signal of the superimposed pseudo-random sequence is amplified and input into the second-stage SAR ADC for sampling and conversion to obtain a quantized digital code; In the digital domain, a correlation operation is performed between the digital signal finally output by the pipeline SAR ADC and the pseudo-random sequence to obtain a correlation coefficient; According to the correlation coefficient, the estimated value of the inter-stage gain is made to converge to the actual value of the inter-stage gain through an iterative method; During this iteration, the iteration step size is dynamically adjusted through the logarithmic sigmoid function; The iteratively obtained inter-stage gain estimation value is used to obtain the final digital code output of the pipeline SAR ADC.

2. The method according to claim 1, characterized in that: The correlation operation between the digital signal finally output by the pipeline SAR ADC and the pseudo-random sequence is realized by taking the sign bit and accumulating it, as shown in the following formula: Ecor=Ecor+sign[D out (i)*PN(i)] In the formula, Ecor represents the correlation coefficient, sign(·) represents the sign function, and D out represents the digital signal finally output by the pipeline SAR ADC, PN represents the pseudo-random sequence, and i represents the number of calibration samples.

3. The method according to claim 1, characterized in that: The process of converging the estimated value of the inter-stage gain to the actual value of the inter-stage gain by an iterative method is expressed as: rG(k+1)=rG(k)-step(k)*Ecor(k) Where rG is the estimated value of the inter-stage gain, step is the iteration step, Ecor is the correlation coefficient, and k is the number of calibration cycles.

4. The method according to claim 1 or 3, characterized in that: The iteration step size step is dynamically adjusted by the logarithmic sigmoid function, and the logarithmic sigmoid function is expressed as: step(k)=2β{1.4+log[1+exp(-α|Ecor(k)| -2 ]} Where α and β represent control coefficients, α is used to control the shape of the function, β is used to control the value range of the function, and Ecor represents the correlation coefficient.

Images