Capacitor mismatch foreground calibration method suitable for SAR ADC

By using LMS algorithm and random jitter signals in SAR ADCs for capacitance mismatch calibration, the problem of excessive calibration dependence on input signals and slow convergence speed in the prior art is solved, and fast and effective capacitance mismatch calibration is achieved, which improves the performance of the ADC.

CN119727722AActive Publication Date: 2025-03-28TONGJI UNIV
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Patent Information

Application Number
CN202411776077.8
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-12-04
Publication Date
2025-03-28
Estimated Expiration
2044-12-04

AI Technical Summary

Technical Problem

The capacitance mismatch calibration technology of existing SAR ADCs relies on excessive input signals and has a slow convergence speed, which affects the conversion process and is not conducive to deep calibration.

Method used

A capacitor mismatch front-end digital calibration method is adopted. By matching the analog input signal, random jitter signal and dynamic components with a common input capacitance digital-to-analog converter CDAC, the LMS algorithm is used to iterate the capacitance weight and random signals according to the error size until the error is within the allowable range.

Benefits of technology

Fast capacitance mismatch calibration without additional circuitry is achieved, increasing the effective number of bits and spurious dynamic range of the SAR ADC, and improving calibration results.

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Abstract

The invention relates to a capacitor mismatch foreground calibration method suitable for an SARADC, and the method comprises the steps: S1, enabling an analog input signal, a random jitter signal and a dynamic element to be matched with each other, and jointly inputting the signals into a capacitive digital-to-analog converter; s2, comparing the output of the capacitive digital-to-analog converter with a reference point through a comparator, and storing to obtain an output digital code; s3, calculating an evaluation value of the corresponding output digital code; s4, obtaining an error between the actual output value and the reference output value estimation value; s5, iterating the capacitance weight and the random signal according to the size of the error by utilizing an LMS (Least Mean Square) algorithm; and S6, continuously changing the capacitance weight and the random signal to enable the error to be within an allowable range, and obtaining more accurate output. According to the invention, no additional analog circuit needs to be added for capacitor mismatch calibration, and parameters such as the significant bit number and the spurious-free dynamic range of the ADC are obviously improved.
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