Half-sampling successive approximation analog-to-digital converter and working method thereof

Abstract

The invention discloses a half-sampling successive approximation type analog-to-digital converter and a working method thereof, upper pole plates of a first MSB capacitor array and a first LSB capacitor array are connected with gnd through a switch SP, a lower pole plate of the first MSB capacitor array is connected with a positive input signal VINP and reference voltages Vaq and gnd, and a lower pole plate of the first LSB capacitor array is connected with reference voltages VREF, Vaq and gnd; upper pole plates of the second MSB capacitor array and the second LSB capacitor array are connected with gnd, a lower pole plate of the second MSB capacitor array is connected with a negative input signal VINN and reference voltages Vaq and gnd, and a lower pole plate of the second LSB capacitor array is connected with reference voltages VREF, Vaq and gnd; vREF and a high-energy-efficiency single-side double-level switch algorithm are switched through a third bit conversion period, and consumed switch energy is reduced by 97.16% compared with that of a traditional structure; a lower pole plate half-sampling method is adopted, the establishment time is reduced by 87.5% compared with that of a traditional structure, and meanwhile the reset energy consumption is zero.

Description

Technical Field

[0001] The invention relates to the technical field of analog-digital mixed signal integrated circuits, and in particular to a half-sampling successive approximation analog-to-digital converter and a working method thereof. Background Art

[0002] The successive approximation analog-to-digital converter has a simple structure, low power consumption and small area. It is widely used in wearable devices, CMOS image sensors and other fields with high power consumption and speed requirements. The traditional successive approximation analog-to-digital converter usually includes a comparator, a DAC capacitor array and a control logic circuit. The comparator is used to compare the input analog signal with the voltage output by the DAC. The DAC is used to convert the digital signal into a corresponding analog signal. The control logic circuit is responsible for coordinating the work of the comparator and the DAC, controlling the connection between the DAC capacitor array and the switch, and controlling the execution of the successive approximation algorithm. The DAC capacitor array is the core device. However, the traditional DAC capacitor array occupies a large area and consumes a lot of energy in the successive approximation analog-to-digital converter. Therefore, it is necessary to reduce the energy consumption of the capacitor array switch, reduce the area of ​​the DAC capacitor array, reduce the chip manufacturing cost, and improve the economic benefits. The traditional 10-bit structure, such as the literature "McCreary JL, Gray P R. All-MOS charge redistribution analog-to-digital conversion techniques. I [J]. IEEE Journal of Solid-State Circuits, 1975, 10 (6): 371-379." published a method that only uses V REF The traditional structure switching strategy with gnd as the reference voltage only introduces V REF With gnd as the reference voltage, successive approximations are made through trial and error. When the attempt is successful, the corresponding capacitor switching is retained; when the attempt fails, it is necessary to restore the connection state before the corresponding capacitor switching, which increases the switching energy consumption. Although the traditional structure switch switching strategy method is simple and does not require reset power consumption, the power consumption is very high and there is still a lot of room for improvement.

[0003] The number of unit capacitors in the DAC capacitor array increases exponentially with the increase in SAR ADC accuracy. Therefore, the input signal settling time will increase, and high-frequency sampling will become increasingly difficult to achieve. This can be achieved using a high-speed input driver buffer, but the power consumption is high; a non-binary DAC capacitor array can be used to reduce the input signal settling time, but the layout of the DAC capacitor array becomes difficult; a digital error calibration logic circuit can be used, but it will increase the power consumption significantly.

[0004] Therefore, there is an urgent need for a new half-sampling successive approximation analog-to-digital converter and its working method to reduce power consumption. Summary of the invention

[0005] In order to solve the above problems, the present invention provides a half-sampling successive approximation analog-to-digital converter and its working method, introducing V REF 、V aq (equal to V REF / 4) and gnd three reference voltages, the DAC capacitor area is reduced by 75% compared with the traditional structure; the third bit conversion cycle introduces V REF , starting from the fourth bit conversion cycle, a high-efficiency single-sided dual-level switching algorithm is used. If the MSB is 1, V DACN The capacitance at V aq and gnd, if the MSB is 0, then V DACP The capacitance at V aq The switching energy consumed is reduced by 97.16% compared with the traditional structure. The lower plate half sampling method is adopted, that is, the lower plate is used for the input signal V INP and V INN Sampling is performed separately, and the setup time is reduced by 87.5% compared with the traditional structure, while the reset energy consumption is 0.

[0006] The technical solution adopted by the present invention is:

[0007] The present invention provides a half-sampling successive approximation analog-to-digital converter, comprising a comparator, a DAC capacitor array and a control logic circuit, wherein the DAC capacitor array is used to be connected to the control logic circuit and one end of the comparator, and the other end of the comparator is connected to the control logic circuit, and the DAC capacitor array comprises a forward capacitor array and a reverse capacitor array, wherein the forward capacitor array is connected to the positive input end of the comparator, and the reverse capacitor array is connected to the negative input end of the comparator;

[0008] The forward capacitor array includes a first MSB capacitor array and a first LSB capacitor array, the reverse capacitor array includes a second MSB capacitor array and a second LSB capacitor array, the first and second MSB capacitor arrays have the same structure, the maximum capacitors are both composed of binary weight sub-capacitor arrays, the first and second LSB capacitor arrays have the same structure, both are residual capacitor arrays, the accuracy of the successive approximation analog-to-digital converter is N, the accuracy of the first MSB capacitor array, the first LSB capacitor array, the second MSB capacitor array and the second LSB capacitor array are all N-2, and all include 2 N-3 Unit capacitance;

[0009] The upper plates of the first MSB capacitor array and the first LSB capacitor array are connected via switches S P Connected to gnd, the lower plate of the first MSB capacitor array is connected to the sampling switch and the positive input signal V INP Connect, through the selection switch with the reference voltage V aqand gnd, the lower plate of the first LSB capacitor array is connected to the reference voltage V REF 、V aq and gnd connection; the upper plate of the second MSB capacitor array and the second LSB capacitor array is connected through the switch S N Connected to gnd, the lower plate of the second MSB capacitor array is connected to the negative input signal V INN Connect, through the selection switch with the reference voltage V aq and gnd, the lower plate of the second LSB capacitor array is connected to the reference voltage V REF 、V aq and gnd connection.

[0010] The present invention also provides a working method based on the above-mentioned half-sampling successive approximation analog-to-digital converter, comprising the following steps:

[0011] S1: The forward capacitor array and the reverse capacitor array sample V in real time INP and V INN , the connection relationship between the DAC capacitor array and the switch is: the lower plate of the first LSB capacitor array in the forward capacitor array is connected to gnd, the upper plates of the first MSB capacitor array and the first LSB capacitor array are connected to gnd, and the positive input voltage V INP The lower plate of the MSB capacitor array in the forward capacitor array is connected to the conduction of the sampling switch; the lower plate of the second LSB capacitor array in the reverse capacitor array is connected to gnd, and the upper plates of the second MSB capacitor array and the second LSB capacitor array are connected to gnd. The negative input voltage V INN Connected to the lower plate of the MSB capacitor array in the reverse capacitor array through the conduction of the sampling switch;

[0012] S2: The forward capacitor array and the reverse capacitor array perform an initial comparison on the sampled voltage signal. The connection relationship between the DAC capacitor array and the switch is: Switch S P and switch S N The lower plates of the first MSB capacitor array and the second MSB capacitor array are connected to gnd, and the lower plates of the first LSB capacitor array and the second LSB capacitor array remain connected to gnd. INP and V INN The first comparison gets the most significant bit MSB. The comparison process is as follows:

[0013] If V INP >V INN , the lower plates of the first MSB capacitor array and the first LSB capacitor array in the forward capacitor array are connected to V aq , the comparator positive input voltage V DACP Increase V REF / 4, the connection relationship between the lower plates of the second MSB capacitor array and the second LSB capacitor array in the reverse capacitor array is the same as step S1, and continues to be connected to gnd; if V INP ≤V INN , the lower plates of the second MSB capacitor array and the second LSB capacitor array in the reverse capacitor array are connected to V aq , the negative input voltage of the comparator V DACN Increase V REF / 4, the connection relationship between the lower plates of the first MSB capacitor array and the first LSB capacitor array in the forward capacitor array is the same as step S1, and continues to be connected to gnd;

[0014] S3: The forward capacitor array and the reverse capacitor array compare the sampled voltage signal for the second time. The connection relationship between the DAC capacitor array and the switch is: if V INP >V INN +VBEF / 2, the lower plate of the first MSB capacitor array in the forward capacitor array is connected from V aq Switching to gnd, the lower plate of the first LSB capacitor array in the forward capacitor array is connected from V aq Switch to V REF , the comparator positive input voltage V DACP Increase V REF / 4, the second MSB capacitor array connection in the reverse capacitor array is switched from gnd to V aq , the lower plate connection gnd of the second LSB capacitor array in the reverse capacitor array remains unchanged, and the negative input voltage V DACN Increase V REF / 8;

[0015] If V INP ≤V INN +V REF / 2 and V INP >V INN , then the connection relationship between the first MSB capacitor array and the first LSB capacitor array in the forward capacitor array is the same as that in step S2. INP V INN When connected to V aq , the lower plate connection of the second MSB capacitor array in the reverse capacitor array is switched from gnd to V aq , the lower plate connection gnd of the second LSB capacitor array in the reverse capacitor array remains unchanged, and the negative input voltage V DACN Increase V REF / 8;

[0016] If V INP >V INN -V REF / 2 and V INP ≤VINN , the lower plate connection of the first MSB capacitor array in the forward capacitor array is switched from gnd to V aq , the lower plate of the first LSB capacitor array in the forward capacitor array continues to connect to the reference voltage gnd, and the positive input voltage V DACP Increase V REF / 8, the lower plates of the second MSB capacitor array and the second LSB capacitor array in the reverse capacitor array are connected to V aq remains unchanged, the negative input voltage of the comparator V DACN remain unchanged;

[0017] If V INP ≤V INN -V REF / 2, the lower plate connection of the first MSB capacitor array in the forward capacitor array is switched from gnd to V aq , the lower plate of the first LSB capacitor array in the forward capacitor array is connected to the reference voltage gnd, and the positive input voltage of the comparator is V DACP Increased V REF / 8, the lower plate of the second MSB capacitor array in the reverse capacitor array is connected from V aq Switch to gnd, the lower plate of the second LSB capacitor array in the reverse capacitor array is connected from V aq Switch to V REF , the negative input voltage of the comparator V DACN Increase V REF / 4;

[0018] S4: The forward capacitor array and the reverse capacitor array compare the sampled voltage signal for the third time. The connection relationship between the DAC capacitor array and the switch is: Then the corresponding capacitor in the second MSB capacitor array in the reverse capacitor array, that is, the lower plate of the maximum capacitor, is from V aq Switching to gnd, the negative input voltage of the comparator V DACN Reduce V REF / 16, the positive input voltage of the comparator is V DACP remain unchanged;

[0019] like and Then the lower plate voltage of the second LSB capacitor array corresponding capacitor in the reverse capacitor array, that is, the largest capacitor, switches from gnd to V aq , the negative input voltage of the comparator V DACN Increase V REF / 16, the positive input voltage of the comparator is V DACP remain unchanged;

[0020] like and Then the corresponding capacitor in the second MSB capacitor array in the reverse capacitor array, that is, the lower plate of the maximum capacitor, is from V aq Switching to gnd, the negative input voltage of the comparator V DACN Reduce V REF / 16, the voltage of the lower plate of the forward capacitor array remains unchanged;

[0021] like And V INP >V INN , then the lower plate voltage of the second LSB capacitor array corresponding capacitor in the reverse capacitor array, that is, the largest capacitor, switches from gnd to V aq , the negative input voltage of the comparator V DACN Increase V REF / 16, the positive input voltage of the comparator is V DACP remain unchanged;

[0022] like And V INP ≤V INN , then the corresponding capacitor in the first LSB capacitor array in the forward capacitor array, that is, the lower plate of the maximum capacitor, switches from gnd to V aq , the comparator positive input voltage V DACP Increase V REF / 16, the negative input voltage of the comparator is V DACN remain unchanged;

[0023] like and Then the voltage of the lower plate of the first MSB capacitor array corresponding to the capacitor in the forward capacitor array, that is, the largest capacitor, changes from V aq Switching to gnd, the comparator positive input voltage V DACP Reduce V REF / 16, the negative input voltage of the comparator is V DACN remain unchanged;

[0024] like and Then the corresponding capacitor in the first LSB capacitor array in the forward capacitor array, that is, the lower plate of the maximum capacitor, switches from gnd to V aq , positive input voltage V DACP Increase V REF / 16, the negative input voltage of the comparator is V DACN remain unchanged;

[0025] like Then the voltage of the lower plate of the first MSB capacitor array corresponding to the capacitor in the forward capacitor array, that is, the largest capacitor, changes from V aq Switch to gnd, the positive input voltage V DACP Reduce V REF / 16, the negative input voltage of the comparator is V DACN remain unchanged;

[0026] S5: Perform the i-th comparison, 4≤i≤n-1: The connection relationship between the DAC capacitor array and the switch is: If V INP >V INN If the comparison result is 0, the corresponding capacitor lower plate in the second MSB capacitor array in the reverse capacitor array is changed from V aq Switch to connect gnd, the negative input voltage of the comparator V DACN Reduce V REF / 2 i , the comparator positive input voltage V DACP Remain unchanged; if V INP >V INN If the comparison result is 1, the corresponding capacitor lower plate in the second LSB capacitor array in the reverse capacitor array switches from gnd to V aq , the negative input voltage of the comparator V DACN Increase V REF / 2 i , the comparator positive input voltage V DACP remain unchanged;

[0027] If V INP ≤V INN If the comparison result is 1, the corresponding capacitor lower plate in the second LSB capacitor array in the forward capacitor array switches from gnd to V aq , the comparator positive input voltage V DACP Increase V REF / 2 i , the negative input voltage of the comparator V DACN remain unchanged;

[0028] If V INP ≤V INN If the comparison result is 0, the corresponding capacitor lower plate in the second MSB capacitor array in the reverse capacitor array is changed from V aq Switch to connect gnd, the comparator positive input voltage V DACP Reduce V REF / 2 i , the negative input voltage of the comparator V DACN remain unchanged;

[0029] The analog-to-digital conversion is completed until the least significant bit (LSB) is obtained.

[0030] Beneficial effects of the present invention:

[0031] Compared with the 10-bit traditional structure, the half-sampling successive approximation analog-to-digital converter and its working method of the present application reduce the capacitor area by 97.5%, the power consumption generated during the switching process is reduced by 97.16%, the input signal setup time is reduced by 87.5%, and the total capacitor area is saved by 75%, which has good economic benefits. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a structural diagram of an N-bit successive approximation analog-to-digital converter.

[0034] Figure 2 The schematic diagram of the DAC capacitor array switching operation for the sampling phase and the first and second comparisons of a 4-bit successive approximation analog-to-digital converter is shown in FIG.

[0035] Figure 3 The diagram is a schematic diagram of the switching operation principle of the DAC capacitor array for the third and fourth comparisons of a 4-bit successive approximation analog-to-digital converter (D3=1).

[0036] Figure 4 The diagram is a schematic diagram of the switching operation principle of the DAC capacitor array for the third and fourth comparisons of a 4-bit successive approximation analog-to-digital converter (D3=0).

[0037] Figure 5 This is a MATLAB simulation result diagram of the switching power consumption changing with the output code during the conversion process of a 10-bit successive approximation analog-to-digital converter in a specific embodiment of the present invention. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the present invention more clear, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings and a preferred implementation manner.

[0039] Example 1

[0040] The present invention provides a half-sampling successive approximation analog-to-digital converter, such as Figure 1 As shown, taking an N-bit successive approximation analog-to-digital converter as an example, it includes a comparator, a control logic circuit and a DAC capacitor array, the DAC capacitor array is used to connect to the control logic circuit and one end of the comparator, and the other end of the comparator is connected to the control logic circuit, wherein the DAC capacitor array includes a positive capacitor array connected to the positive input end of the comparator and a reverse capacitor array connected to the negative input end of the comparator;

[0041] The forward capacitor array includes a first MSB capacitor array and a first LSB capacitor array, and the reverse capacitor array includes a second MSB capacitor array and a second LSB capacitor array. The first and second MSB capacitor arrays have the same structure, and the maximum capacitors are both composed of binary weighted sub-capacitor arrays. The first and second LSB capacitor arrays have the same structure, and are both residual capacitor arrays, each including 2 N-3 The maximum capacitance increases exponentially with the increase of the accuracy of the analog-to-digital converter, which is 2 N-4 C, the accuracy of the successive approximation analog-to-digital converter is N, and the accuracy of the first and second LSB capacitor arrays is N-2, such as Figure 1 When N=4, the maximum capacitance is C. A 4-bit successive approximation analog-to-digital converter is taken as an example, namely, the first MSB array CC, the first LSB array CC, the second MSB array CC, and the second LSB array CC.

[0042] The upper plates of the first MSB capacitor array and the first LSB capacitor array are connected via switches S P Connected to gnd, the lower plate of the first MSB capacitor array is connected to the sampling switch and the positive input signal V INP Connect, through the selection switch with the reference voltage V aq and gnd, the lower plate of the first LSB capacitor array is connected to the reference voltage V REF 、V aq and gnd connection; the upper plate of the second MSB capacitor array and the second LSB capacitor array is connected through the switch S N Connected to gnd, the lower plate of the second MSB capacitor array is connected to the negative input signal V INN Connect, through the selection switch with the reference voltage V aq and gnd, the lower plate of the second LSB capacitor array is connected to the reference voltage V REF 、V aq and gnd connection.

[0043] Example 2

[0044] The present invention also provides a working method based on the above-mentioned half-sampling successive approximation analog-to-digital converter, which includes a sampling stage and a comparison stage.

[0045] Sampling stage

[0046] Step S1: Figure 2 As shown in (a), switches SP and SN are turned on, and the input signal V INP and V INNThe first and second MSB capacitor array lower plates in the forward capacitor array and the reverse capacitor array are sampled respectively. At the same time, the first and second LSB capacitor array lower plates in the forward capacitor array and the reverse capacitor array are connected to gnd; all capacitor upper plates in the forward capacitor array and the reverse capacitor array are connected to gnd.

[0047] Comparison Phase

[0048] Step S2: After sampling, the switch S connected to the upper plate of the capacitor array P and S N When it is turned on, the lower plates of the first and second MSB capacitor arrays in the forward capacitor array and the reverse capacitor array are disconnected from the input signal and switched to gnd. The switching energy consumed in this process is 0, as shown in Figure 2 (b) as shown.

[0049] Start the first comparison, if V INP -V INN Greater than 0, that is, V INP >V INN The converter outputs digital code D3 as 1; if V INP -V INN Less than or equal to 0, that is, V INP ≤V INN , then the output digital code D3 is 0; after the initial comparison, the MSB is obtained, which is the highest bit of the converted digital signal. The subsequent multiple comparison results are each subsequent bit in turn until the LSB is finally obtained. The LSB is the least important bit. The more comparisons are made, the closer the result is to the actual input voltage signal.

[0050] like Figure 2 (c) As shown in INP -V INN Greater than 0, that is, V INP >V INN , D3 is 1, all lower plates in the forward capacitor array are switched from gnd to Vaq, and the reverse capacitor array remains unchanged. The switching energy consumed in this process is 0; if V INP -V INN Less than or equal to 0, that is, V INP ≤V INN , the output digital code D3 is 0, and at the same time all the lower plates in the reverse capacitor array are switched from gnd to V aq , the forward capacitance array remains unchanged, and the switching energy consumed in this process is 0;

[0051] Step S3: Next, perform a second comparison to obtain the output digital code D2. When D3 = 1, if V INP -V INN Greater than V REF / 2, that is, VINP >V INN +V REF / 2, then the output digital code D2 = 1; when D3 = 1, if V INP -V INN Less than or equal to V REF / 2, then the output digital code D2 = 0; when D3 = 0, if V INP -V INN Greater than -V REF / 2, that is, V INP ≤V INN +V REF / 2, then the output digital code D2 = 1; when D3 = 0, if V INP -V INN Less than or equal to -V REF / 2, that is, if V INP ≤V INN -B REF / 2, then the output digital code D2 = 0;

[0052] like Figure 3 As shown in (a), when D3D2=11, the lower plate of the first MSB capacitor array in the forward capacitor array is connected from V aq Switching to gnd, the lower plate of the first LSB capacitor array in the forward capacitor array changes from V aq Switch to V REF , the lower plate connection of the second MSB capacitor array in the reverse capacitor array is switched from gnd to V aq , the lower plate connection of the second LSB capacitor array in the reverse capacitor array remains unchanged, and the switching energy consumed in this process is 17 / 16V REF 2 ; When D3D2 = 10, the lower plate connection of the second MSB capacitor array in the reverse capacitor array is switched from gnd to V aq , the lower plate connection of the second LSB capacitor array in the reverse capacitor array remains unchanged, and the lower plate connections of the first MSB capacitor array and the first LSB capacitor array in the forward capacitor array remain unchanged. The switching energy consumed in this process is 1 / 16V REF 2 ;

[0053] like Figure 4 As shown in (a), when D3D2=01, the lower plate connection of the first MSB capacitor array in the forward capacitor array is switched from gnd to V aq , the lower plate connection of the first LSB capacitor array in the forward capacitor array remains unchanged, and the lower plate connections of the first MSB capacitor array and the first LSB capacitor array in the forward capacitor array remain unchanged. The switching energy consumed in this process is 1 / 16V REF 2; When D3D2 = 00, the lower plate of the second MSB capacitor array in the reverse capacitor array is connected from V aq Switching to gnd, the lower plate of the second LSB capacitor array in the reverse capacitor array changes from V aq Switch to V REF , the lower plate connection of the first MSB capacitor array in the forward capacitor array is switched from gnd to V aq , the lower plate connection of the first LSB capacitor array in the forward capacitor array remains unchanged, and the switching energy consumed in this process is 17 / 16V REF 2 ;

[0054] Step S4: Next, perform the third comparison to obtain D1; when D3D2=11, if V INP -V INN Greater than (3 / 4)V REF , then the output digital code D1=1; when D3D2=11, if V INP -V INN Less than or equal to (3 / 4)V REF , then the output digital code D1=0; when D3D2=10, if V INP -V INN Greater than (1 / 4)V REF , then the output digital code D1=1; when D3D2=10, if V INP -V INN Less than or equal to (1 / 4)V REF , then the output digital code D1=0; when D3D2=01, if V INP -V INN Greater than (-1 / 4)V REF , then the output digital code D1=1; when D3D2=01, if V INP -V INN Less than or equal to (-1 / 4)V REF , then the output digital code D1=0; when D3D2=00, if V INP -V INN Greater than (-3 / 4)V REF , then the output digital code D1=1; when D3D2=00, if V INP -V INN Less than or equal to (-3 / 4)V REF , then the output digital code D1 = 0;

[0055] like Figure 3 As shown in (b), when D3D2D1=111, the lower plate of the corresponding capacitor (maximum capacitor C) in the second MSB capacitor array in the reverse capacitor array changes from V aqSwitch to gnd, the connection of the lower plates of the remaining capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1=110, the lower plate of the corresponding capacitor (maximum capacitor C) in the second LSB capacitor array in the reverse capacitor array switches from gnd to V aq , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1 = 101, the lower plate of the corresponding capacitor (maximum capacitor C) in the second MSB capacitor array in the reverse capacitor array changes from V aq Switch to gnd, the connection of the lower plates of the remaining capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1=100, the lower plate of the corresponding capacitor (maximum capacitor C) in the second LSB capacitor array in the reverse capacitor array switches from gnd to V aq , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ;

[0056] like Figure 4 As shown in (b), when D3D2D1=011, the lower plate of the corresponding capacitor (maximum capacitor C) in the first LSB capacitor array in the forward capacitor array switches from gnd to V aq , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1=010, the lower plate of the corresponding capacitor (maximum capacitor C) in the first MSB capacitor array in the forward capacitor array is switched from Vaq to gnd, and the lower plate connections of the remaining capacitors remain unchanged. The switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1=001, the lower plate of the corresponding capacitor (maximum capacitor C) in the first LSB capacitor array in the forward capacitor array switches from gnd to V aq , the connection of the lower plates of the other capacitors remains unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; When D3D2D1=000, the lower plate of the corresponding capacitor in the first MSB capacitor array in the forward capacitor array changes from V aq Switch to gnd, the lower plates of the remaining capacitors remain unchanged, and the switching energy consumed in this process is (1 / 64)CV REF 2 ; That is, the third bit conversion cycle introduces V REF，

[0057] Next, the fourth comparison is performed to obtain D0; when D3D2D1=111, if V INP -V INN Greater than (7 / 8)V REF , then the output digital code D0=1; when D3D2D1=111, if V INP -V INN Less than or equal to (7 / 8)V REF , then the output digital code D0=0; when D3D2D1=110, if V INP -V INN Greater than (5 / 8)V REF , then the output digital code D0=1; when D3D2D1=110, if V INP -V INN Less than or equal to (5 / 8)V REF , then the output digital code D0=0; when D3D2D1=101, if V INP -V INN Greater than (3 / 8)V REF , then the output digital code D0=1; when D3D2D1=101, if V INP -V INN Less than or equal to (3 / 8)V REF , then the output digital code D0=0; when D3D2D1=100, if V INP -V INN Greater than (1 / 8)V REF , then the output digital code D0=1; when D3D2D1=100, if V INP -V INN Less than or equal to (1 / 8)V REF , then the output digital code D0=0; when D3D2D1=011, if V INP -V INN Greater than (-1 / 8)V REF , then the output digital code D0=1; when D3D2D1=011, if V INP -V INN Less than or equal to (-1 / 8)V REF , then the output digital code D0=0; when D3D2D1=010, if V INP -V INN Greater than (-3 / 8)V REF , then the output digital code D0=1; when D3D2D1=010, if V INP -V INN Less than or equal to (-3 / 8)V REF , then the output digital code D0=0; when D3D2D1=001, if VINP -V INN Greater than (-5 / 8)V REF , then the output digital code D0=1; when D3D2D1=001, if V INP -V INN Less than or equal to (-5 / 8)V REF , then the output digital code D0=0; when D3D2D1=000, if V INP -V INN Greater than (-7 / 8)V REF , then the output digital code D0=1; when D3D2D1=000, if V INP -V INN Less than or equal to (-7 / 8)V REF , then the output digital code D0 = 0;

[0058] Step S5: Perform the i-th comparison, 4≤i≤n-1: The connection relationship between the DAC capacitor array and the switch is: If V INP >V INN If the comparison result is 0, the corresponding capacitor in the second MSB capacitor array in the reverse capacitor array (decreasing binary weight in sequence) has its lower plate changed from V aq Switch to connect gnd, the negative input voltage of the comparator V DACN Reduce V REF / 2 i , the comparator positive input voltage V DACP Remain unchanged; if V INP >V INN If the comparison result is 1, the corresponding capacitor in the second LSB capacitor array in the reverse capacitor array (decreasing binary weight in sequence) switches the lower plate from gnd to V aq , the negative input voltage of the comparator V DACN Increase V REF / 2 i , the comparator positive input voltage V DACP remain unchanged;

[0059] If V INP ≤V INN If the comparison result is 1, the corresponding capacitor in the second LSB capacitor array in the forward capacitor array (decreasing binary weight in sequence) switches the lower plate from gnd to V aq , the comparator positive input voltage V DACP Increase V REF / 2 i , the negative input voltage of the comparator V DACN remain unchanged;

[0060] If V INP ≤V INNIf the comparison result is 0, the corresponding capacitor in the second MSB capacitor array in the reverse capacitor array (decreasing binary weight in sequence) has its lower plate changed from V aq Switch to connect gnd, the comparator positive input voltage V DACP Reduce V REF / 2 i , the negative input voltage of the comparator V DACN remain unchanged;

[0061] The analog-to-digital conversion is completed until the least significant bit (LSB) is obtained.

[0062] like Figure 5 As shown in the figure, taking a 10-bit successive approximation analog-to-digital converter as an example, the MATLAB simulation result of the switching energy consumption during the conversion process changes with the digital output code. The horizontal axis represents the output code, where 100 corresponds to the binary digital code 0001100100, 1000 corresponds to the binary digital code 1111101000, and 1023 corresponds to the binary digital code 1111111111. The digital code corresponding to the output code 0-1023 is 0000000000 (0) ~ 1111111111 (1023). The vertical axis represents the switching energy consumption, unit CV REF 2 .

[0063] Through the half-sampling successive approximation analog-to-digital converter and its working method of the present application, the capacitor area is reduced by 97.5%, the power consumption generated during the switching process is reduced by 97.16%, the input signal setup time is reduced by 87.5%, and the total capacitor area is saved by 75%, which has good economic benefits.

[0064] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications are also within the protection scope of the present invention.

Claims

1. A half-sampling successive approximation analog-to-digital converter, comprising a comparator, a DAC capacitor array and a control logic circuit, wherein the DAC capacitor array is used to connect to the control logic circuit and one end of the comparator, and the other end of the comparator is connected to the control logic circuit, characterized in that: The DAC capacitor array includes a forward capacitor array and a reverse capacitor array, the forward capacitor array is connected to the positive input terminal of the comparator, and the reverse capacitor array is connected to the negative input terminal of the comparator; The forward capacitor array includes a first MSB capacitor array and a first LSB capacitor array, the reverse capacitor array includes a second MSB capacitor array and a second LSB capacitor array, the first and second MSB capacitor arrays have the same structure, the maximum capacitors are both composed of binary weight sub-capacitor arrays, the first and second LSB capacitor arrays have the same structure, both are residual capacitor arrays, the accuracy of the successive approximation analog-to-digital converter is N, the accuracy of the first MSB capacitor array, the first LSB capacitor array, the second MSB capacitor array and the second LSB capacitor array are all N-2, and all include 2 N-3 Unit capacitance; The upper plates of the first MSB capacitor array and the first LSB capacitor array are connected via switches S P Connected to gnd, the lower plate of the first MSB capacitor array is connected to the sampling switch and the positive input signal V INP Connect, through the selection switch with the reference voltage V aq and gnd, the lower plate of the first LSB capacitor array is connected to the reference voltage V REF 、V aq and gnd connection; the upper plate of the second MSB capacitor array and the second LSB capacitor array is connected through the switch S N Connected to gnd, the lower plate of the second MSB capacitor array is connected to the negative input signal V INN Connect, through the selection switch with the reference voltage V aq and gnd, the lower plate of the second LSB capacitor array is connected to the reference voltage V REF 、V aq and gnd connection.

2. The working method of the half-sampling successive approximation analog-to-digital converter according to claim 1, characterized in that: The steps include: S1: The forward capacitor array and the reverse capacitor array sample V in real time INP and V INN , the connection relationship between the DAC capacitor array and the switch is: the lower plate of the first LSB capacitor array in the forward capacitor array is connected to gnd, the upper plates of the first MSB capacitor array and the first LSB capacitor array are connected to gnd, and the positive input voltage V INP The lower plate of the MSB capacitor array in the forward capacitor array is connected to the conduction of the sampling switch; the lower plate of the second LSB capacitor array in the reverse capacitor array is connected to gnd, and the upper plates of the second MSB capacitor array and the second LSB capacitor array are connected to gnd. The negative input voltage V INN Connected to the lower plate of the MSB capacitor array in the reverse capacitor array by conducting the sampling switch; S2: The forward capacitor array and the reverse capacitor array perform an initial comparison on the sampled voltage signal. The connection relationship between the DAC capacitor array and the switch is: Switch S P and switch S N The lower plates of the first MSB capacitor array and the second MSB capacitor array are connected to gnd, and the lower plates of the first LSB capacitor array and the second LSB capacitor array remain connected to gnd. INP and V INN The first comparison gets the most significant bit MSB. The comparison process is as follows: If V INP >V INN , the lower plates of the first MSB capacitor array and the first LSB capacitor array in the forward capacitor array are connected to V aq , the comparator positive input voltage V DACP Increase V REF / 4, the connection relationship between the lower plates of the second MSB capacitor array and the second LSB capacitor array in the reverse capacitor array is the same as step S1, and continues to be connected to gnd; if V INP ≤V INN , the lower plates of the second MSB capacitor array and the second LSB capacitor array in the reverse capacitor array are connected to V aq , the negative input voltage of the comparator V DACN Increase V REF / 4, the connection relationship between the lower plates of the first MSB capacitor array and the first LSB capacitor array in the forward capacitor array is the same as step S1, and continues to be connected to gnd; S3: The forward capacitor array and the reverse capacitor array compare the sampled voltage signal for the second time. The connection relationship between the DAC capacitor array and the switch is: if V INP >V INN +V REF / 2, the lower plate of the first MSB capacitor array in the forward capacitor array is connected from V aq Switching to gnd, the lower plate of the first LSB capacitor array in the forward capacitor array is connected from V aq Switch to V REF , the comparator positive input voltage V DACP Increase V REF / 4, the second MSB capacitor array connection in the reverse capacitor array is switched from gnd to V aq , the lower plate connection gnd of the second LSB capacitor array in the reverse capacitor array remains unchanged, and the negative input voltage V DACN Increase V REF / 8; If V INP ≤V INN +V REF / 2 and V INP >V INN , then the connection relationship between the first MSB capacitor array and the first LSB capacitor array in the forward capacitor array is the same as that in step S2. INP V INN When connected to V aq , the lower plate connection of the second MSB capacitor array in the reverse capacitor array is switched from gnd to V aq , the lower plate connection gnd of the second LSB capacitor array in the reverse capacitor array remains unchanged, and the negative input voltage V DACN Increase V REF / 8; If V INP >V INN -V REF / 2 and V INP ≤V INN , the lower plate connection of the first MSB capacitor array in the forward capacitor array is switched from gnd to V aq , the lower plate of the first LSB capacitor array in the forward capacitor array continues to connect to the reference voltage gnd, and the positive input voltage V DACP Increase V REF / 8, the lower plates of the second MSB capacitor array and the second LSB capacitor array in the reverse capacitor array are connected to V aq remains unchanged, the negative input voltage of the comparator V DACN remain unchanged; If V INP ≤V INN -V REF / 2, the lower plate connection of the first MSB capacitor array in the forward capacitor array is switched from gnd to V aq , the lower plate of the first LSB capacitor array in the forward capacitor array is connected to the reference voltage gnd, and the positive input voltage of the comparator is V DACP Increased V REF / 8, the lower plate of the second MSB capacitor array in the reverse capacitor array is connected from V aq Switch to gnd, the lower plate of the second LSB capacitor array in the reverse capacitor array is connected from V aq Switch to V REF , the negative input voltage of the comparator V DACN Increase V REF / 4; S4: The forward capacitor array and the reverse capacitor array compare the sampled voltage signal for the third time. The connection relationship between the DAC capacitor array and the switch is: Then the corresponding capacitor in the second MSB capacitor array in the reverse capacitor array, that is, the lower plate of the maximum capacitor, is from V aq Switching to gnd, the negative input voltage of the comparator V DACN Reduce V REF / 16, the positive input voltage of the comparator is V DACP remain unchanged; like and Then the lower plate voltage of the second LSB capacitor array corresponding capacitor in the reverse capacitor array, that is, the largest capacitor, switches from gnd to V aq , the negative input voltage of the comparator V DACN Increase V REF / 16, the positive input voltage of the comparator is V DACP remain unchanged; like and Then the corresponding capacitor in the second MSB capacitor array in the reverse capacitor array, that is, the lower plate of the maximum capacitor, is from V aq Switching to gnd, the negative input voltage of the comparator V DACN Reduce V REF / 16, the voltage of the lower plate of the forward capacitor array remains unchanged; like And V INP >V INN , then the lower plate voltage of the second LSB capacitor array corresponding capacitor in the reverse capacitor array, that is, the largest capacitor, switches from gnd to V aq , the negative input voltage of the comparator V DACN Increase V REF / 16, the positive input voltage of the comparator is V DACP remain unchanged; like And V INP ≤V INN , then the corresponding capacitor in the first LSB capacitor array in the forward capacitor array, that is, the lower plate of the maximum capacitor, switches from gnd to V aq , the comparator positive input voltage V DACP Increase V REF / 16, the negative input voltage of the comparator is V DACN remain unchanged; like and Then the voltage of the lower plate of the first MSB capacitor array corresponding to the capacitor in the forward capacitor array, that is, the largest capacitor, changes from V aq Switching to gnd, the comparator positive input voltage V DACP Reduce V REF / 16, the negative input voltage of the comparator is V DACN remain unchanged; like and Then the corresponding capacitor in the first LSB capacitor array in the forward capacitor array, that is, the lower plate of the maximum capacitor, switches from gnd to V aq , positive input voltage V DACP Increase V REF / 16, the negative input voltage of the comparator is V DACN remain unchanged; like Then the voltage of the lower plate of the first MSB capacitor array corresponding to the capacitor in the forward capacitor array, that is, the largest capacitor, changes from V aq Switch to gnd, the positive input voltage V DACP Reduce V REF / 16, the negative input voltage of the comparator is V DACN remain unchanged; S5: Perform the i-th comparison, 4≤i≤n-1: The connection relationship between the DAC capacitor array and the switch is: If V INP >V INN If the comparison result is 0, the corresponding capacitor lower plate in the second MSB capacitor array in the reverse capacitor array is changed from V aq Switch to connect gnd, the negative input voltage of the comparator V DACN Reduce V REF / 2 i , the comparator positive input voltage V DACP Remain unchanged; if V INP >V INN If the comparison result is 1, the corresponding capacitor lower plate in the second LSB capacitor array in the reverse capacitor array switches from gnd to V aq , the negative input voltage of the comparator V DACN Increase V REF / 2 i , the comparator positive input voltage V DACP remain unchanged; If V INP ≤V INN If the comparison result is 1, the corresponding capacitor lower plate in the second LSB capacitor array in the forward capacitor array switches from gnd to V aq , the comparator positive input voltage V DACP Increase V REF / 2 i , the negative input voltage of the comparator V DACN remain unchanged; If V INP ≤V INN If the comparison result is 0, the corresponding capacitor lower plate in the second MSB capacitor array in the reverse capacitor array is changed from V aq Switch to connect gnd, the comparator positive input voltage V DACP Reduce V REF / 2 i , the negative input voltage of the comparator V DACN Remain unchanged until the least significant bit (LSB) is obtained and the analog-to-digital conversion is completed.

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