Time synchronization with multi-chassis link aggregation

Abstract

The embodiment of the invention relates to time synchronization with multi-chassis link aggregation. In some examples, a system provides multi-chassis link aggregation by a first electronic device and a second electronic device that are part of a logic device that supports MCLAG, where the first electronic device includes a first time clock and the second electronic device includes a second time clock. As part of a time synchronization process in the system, the first time clock and the second time clock perform a clock source selection process through a link between the first electronic device and the second electronic device of the logic device to select one of the first time clock and the second time clock as a clock source, and selecting the other one of the first time clock and the second time clock as a clock sink.

Description

Background Art

[0001] An electronic device in a distributed system of multiple electronic devices includes a time clock that generates time, which can be wall clock time or any other representation of time. The time generated by the time clocks in the multiple electronic devices allows transactions occurring across the multiple electronic devices to be time-aligned with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Some embodiments of the present disclosure are described with reference to the following drawings.

[0003] Figure 1 is a block diagram of an arrangement including a multi-chassis link aggregation group (MCLAG) logical device connected to various other electronic devices, according to some examples.

[0004] Figure 2A and Figure 2B is a timing diagram illustrating the exchange of timing messages according to the Precision Time Protocol (PTP), according to some examples.

[0005] Figure 3 is a flow chart of a process involving identifying a clock source and a clock sink between boundary time clocks of a MCLAG logic device and processing timing messages by the clock source and the clock sink, according to some examples.

[0006] Figure 4 and Figure 6 is a flow chart of a process for a secondary boundary time clock according to some examples.

[0007] Figure 5 and Figure 7 is a flow chart of a process for a master boundary time clock according to some examples.

[0008] Figure 8 is a flow chart of a process of a primary boundary time clock and a secondary boundary time clock according to another example.

[0009] Fig. 9 is a flow chart of a process of a master boundary time clock according to another example.

[0010] Fig.10 is a block diagram of a storage medium storing machine-readable instructions according to some examples.

[0011] Fig.11 is a block diagram of a system according to some examples.

[0012] Fig.12 is a flow diagram of a process according to some examples.

[0013] Throughout the drawings, the same reference numerals designate similar, but not necessarily identical, elements. The drawings are not necessarily drawn to scale, and the size of certain components may be exaggerated to more clearly illustrate the examples shown. In addition, the drawings provide examples and / or implementations consistent with the description; however, the description is not limited to the examples and / or implementations provided in the drawings. DETAILED DESCRIPTION

[0014] In order to maintain synchronization between time clocks (or more simply, "clocks") between electronic devices of a distributed system, a time synchronization process may be employed. In some examples, the time synchronization process may be based on a time synchronization protocol, such as the Precision Time Protocol (PTP) described by the Institute of Electrical and Electronics Engineers (IEEE) 1588 specification.

[0015] A distributed system may include a network for interconnecting electronic devices. The network includes physical network links (or more simply "network links") between electronic devices. In some cases, link aggregation may be employed, where multiple network links are aggregated into logical links (sometimes referred to as link aggregation groups or LAGs) between electronic devices. In some examples, link aggregation may be in accordance with the IEEE 802.3ad specification. Link aggregation allows packets to be load balanced on the network links of the LAG between two electronic devices. With load balancing, a source electronic device may send different packets to a target electronic device using different network links of the LAG.

[0016] Multi-chassis link aggregation provides a logical LAG between an electronic device and multiple (e.g., two or more than two) multi-chassis link aggregation group (MCLAG) peer devices (such as switches). Multiple MCLAG peer devices form a "MCLAG logical device" that appears as a single device to other electronic devices, where the MCLAG logical device presents a LAG with multiple network links. A given electronic device is connected to multiple MCLAG peer devices through a logical LAG, and any network link of the logical LAG (also referred to as an MCLAG) can be used for communication by the given electronic device. Multiple MCLAG peer devices are located in separate chassis, where "chassis" can refer to any physical boundary or outline. Electronic devices in separate chassis are physically separate devices that can operate independently of each other, so that one of the electronic devices can continue to operate even if another electronic device cannot work. MCLAG provides redundancy and load balancing between multiple MCLAG peer devices.

[0017] PTP uses timing messages exchanged between electronic devices (or more specifically, between clocks of electronic devices) to perform time synchronization. Due to various problems associated with timing messages of time synchronization protocols exchanged in a multi-chassis link aggregation environment, implementing a time synchronization protocol such as PTP in a multi-chassis link aggregation environment may produce inaccurate results. The following refers to a multi-chassis link aggregation environment, which includes a master device and a slave device, which are peer devices of an MCLAG logical device. There may be problems with transmitting timing messages of the time synchronization protocol to the master device and the slave device of the MCLAG logical device. For example, some problems are associated with the master device and the slave device sending redundant messages of the time synchronization protocol, which may cause confusion at the electronic device receiving the redundant messages. Other problems are associated with consecutive different messages of the time synchronization protocol that arrive at different devices in the master device and the slave device. For example, a first timing message of a time synchronization process may arrive at a master device of the MCLAG logical device, and a second timing message of the time synchronization process may arrive at a slave device of the MCLAG logical device. If the slave device determines that it has not previously received the first timing message, the slave device may incorrectly process the second timing message (e.g., discard the second timing message).

[0018] According to some embodiments of the present disclosure, a MCLAG logic device including a first electronic device and a second electronic device having corresponding first time clocks and second time clocks can perform a clock source selection process between the first time clock and the second time clock through a link between the first electronic device and the second electronic device of the MCLAG logic device to select one of the first time clock and the second time clock as a clock source, and select the other of the first time clock and the second time clock as a clock sink. The clock source provides a time reference for the time clock of the other electronic device. The clock sink uses the time clock of the other electronic device as a reference. According to PTP, the clock source is a master clock and the clock sink is a slave clock. The first electronic device of the MCLAG logic device can be a master device of the MCLAG logic device, and the second electronic device of the MCLAG logic device can be a slave device of the MCLAG logic device (or vice versa). In other examples, the MCLAG logic device can include more than two electronic devices with corresponding time clocks.

[0019] In another example, the first time clock and the second time clock in the MCLAG logic device are boundary time clocks. More specifically, the MCLAG logic device includes a first boundary time clock (in the first electronic device) and a second boundary time clock (in the second electronic device). A "boundary time clock" (or more simply, a "boundary clock") refers to a time clock in an electronic device that is synchronized with a clock source upstream of the boundary time clock and serves as a clock source for a clock sink downstream of the boundary time clock. In response to the first boundary time clock of the MCLAG logic device receiving a first timing message from the clock sink, the first boundary time clock determines whether the second boundary time clock is a clock source for the first boundary time clock, and based on determining that the second boundary time clock is a clock source for the first boundary time clock, the first boundary time clock forwards the first timing message to the second boundary time clock. In another example, in response to a first boundary time clock of the MCLAG logic device receiving a second timing message from a clock source, the first boundary time clock checks a data structure of the second boundary time clock to determine whether the second boundary time clock has received a third timing message from the clock source, and based on determining that the second boundary time clock has received the third timing message from the clock source, the first boundary time clock forwards the second timing message to the second boundary time clock.

[0020] Specific issues related to the MCLAG logic device and timing synchronization process

[0021] The following further describes five issues (Issue 1, Issue 2, Issue 3, Issue 4, and Issue 5) that MCLAG logic devices may encounter in connection with a timing synchronization process (such as a PTP process). Figure 1 , which depicts an example arrangement including a MCLAG logic device 102 having a master device 102-1 and a slave device 102-2. Examples of master device 102-1 and slave device 102-2 include switches, routers, or other types of network devices through which data can be communicated and forwarded in a network. Although referred to as "master" and "slave" devices, it is noted that both device 102-1 and device 102-2 of MCLAG logic device 102 are active (e.g., operating in an active-active configuration) and support communications with other electronic devices.

[0022] In accordance with Figure 1In some examples, the MCLAG logical device 102 is part of an aggregation layer that performs link aggregation. In some examples, the MCLAG logical device 102 is based on a distributed resilient network interconnect (DRNI) model. DRNI virtualizes two physical devices (two MCLAG peer devices) into one logical device through multi-chassis link aggregation to provide node redundancy, link redundancy, and load sharing. DRNI is described by the IEEE 802.1AXbq specification. An example of an electronic device that can operate in a manner consistent with DRNI is a virtual switch extension (VSX) switch provided by Hewlett Packard Enterprise (HPE). The VSX switch is an example of a master device 102-1 and a slave device 102-2 of a MCLAG logical device. In other examples, the master device 102-1 and the slave device 102-2 can come from other suppliers.

[0023] More generally, the MCLAG logical device 102 may be based on any technology in which multiple physical devices cooperate to provide a virtual entity that supports link aggregation.

[0024] Figure 1 The arrangement also includes a core device 105 between the MCLAG logic device 102 and a remote device 106. The remote device 106 may include an electronic device that is part of a cloud, an arrangement of one or more servers, a data center, or any other computing environment. The remote device 106 may include a grand clock source 108, which is a clock source having (for example, Figure 1 The senior clock source is a clock source of higher clock quality than other clocks in the arrangement and it has direct access to the reference clock. The reference clock may include a high frequency oscillator, a global positioning system (GPS) clock, or any other time reference. According to PTP, the senior clock source is the senior master clock.

[0025] The master device 102-1 includes a boundary time clock 104-1 (referred to as "master BTC 104-1"), and the slave device 102-2 includes a boundary time clock 104-2 (referred to as "slave BTC 104-2"). BTC (boundary time clock) 104-1 and BTC 104-2 are synchronized with a grand clock source 108 (or another clock source in other examples).

[0026] The core device 105 includes a transparent time clock 110, which is an intermediate time clock that can calculate time delays, but the transparent time clock is not synchronized with other time clocks. The core device 105 can be an electronic device that provides a bridge between the remote device 106 and the MCLAG logic device 102. For example, the core device 105 can include a gateway, a router, or any other type of intermediate device. In other examples, the core device 105 can be omitted. Although Figure 1One core device 105 is shown between the remote device 106 and the MCLAG logic device 102 , but in other examples, there may be multiple core devices between the remote device 106 and the MCLAG logic device 102 .

[0027] Figure 1 Also shown are various client devices 112 having ordinary time clocks 114. An ordinary time clock is a time clock that is not connected to any downstream time clock (i.e., the ordinary time clock does not serve as a clock source for another time clock). A "client device" may refer to an electronic device that accesses a remote service in the system, such as a service in the cloud, on a server, in a data center, or in any other computing platform. The ordinary time clock 114 is synchronized with the primary BTC 104-1 and / or the secondary BTC 104-2.

[0028] Figure 1 The arrangement also includes an access device 116 (or multiple access devices), and the client device 112 is connected to the access device 116 to access the remote service. For example, the access device 116 may include an access point (AP) of a wireless local area network (WLAN), a base station of a cellular network, or any other type of access device. The access device 116 includes a transparent time clock 117. In other examples, the access device 116 may be omitted, and the client device 112 may be connected to the master device 102-1 and the slave device 102-2 of the MCLAG logical device 102. In another example, the time clock in the core device 105 and / or the access device 116 may be a boundary time clock or an advanced clock source. More generally, the core device 105 and / or the access device 116 are time synchronization protocol aware devices that support time synchronization processes (such as PTP processes).

[0029] The MCLAG logic device 102 presents a core-side MCLAG 118 to the core device 105, and the MCLAG logic device 102 presents an access-side MCLAG 120 to the access device 116. The core-side MCLAG 118 includes a set of network links connected to interfaces of the primary device 102-1 and the secondary device 102-2, and to interfaces of the core device 105. The access-side MCLAG 120 includes a set of network links connected to interfaces of the primary device 102-1 and the secondary device 102-2, and to interfaces of the access device 116. Interfaces of a device are also referred to as "ports," and an interface may be connected to a corresponding network link of a LAG. An interface connected to a network link of a LAG is referred to as a "LAG interface" (or "LAG port").

[0030] The MCLAG logic device 102 also includes an inter-device link 122 between the main device 102-1 and the auxiliary device 102-2. If the main device 102-1 and the auxiliary device 102-2 are switches, the inter-device link 122 can be referred to as an inter-switch link. The inter-device link 122 can refer to any communication path between the main device 102-1 and the auxiliary device 102-2. The inter-device link 122 is used to exchange information between the main device 102-1 and the auxiliary device 102-2. The main device 102-1 and the auxiliary device 102-2 can also be synchronized with each other through the inter-device link 122.

[0031] Figure 2A is a timing diagram illustrating the exchange of PTP timing messages between a clock source 202 and a clock sink 204 employing an end-to-end delay mechanism. Figure 2B is a timing diagram illustrating the exchange of timing messages between a clock source 222 and a clock sink 224 employing a peer-to-peer delay mechanism. The IEEE 1588 specification describes timing messages and how the timing messages are processed.

[0032] Figure 2A The timing message of the clock source 202 includes a synchronization message 206 (e.g., a PTP synchronization message) sent from the clock source 202 to the clock sink 204. The synchronization message 206 is sent by the clock source 202 to the clock sink 204 to initiate the time synchronization process. The clock source 202 can record the exit time (T1), which is the time when the synchronization message 206 is sent. If the clock source 202 is a single-step clock, then T1 can be carried in the synchronization message 206. If the clock source 202 is a two-step clock, then T1 can be carried in a subsequent message 208 (PTP Follow-Up message) sent after the synchronization message 206. Upon receiving the synchronization message 206 (or subsequent message if applicable), the clock sink 204 records the entry time (T2) when the clock sink 204 receives the synchronization message 206. The clock sink 204 also records the exit time (T1) from the clock source 202, where T1 can be included in the synchronization message 206 or the subsequent message 208.

[0033] The clock sink 204 sends a delay request message 210 (e.g., a PTP DelayReq message) to the clock source 202. The clock sink 204 may record the egress time (T3) when the delay request message 210 is sent from the clock sink 204. The clock source 202 receives the delay request message 210 and records the ingress time (T4) when the delay request message 210 is received at the clock source 202. The clock source 202 then sends a delay response message 212 (e.g., a PTP DelayResp) to the clock sink 204. The delay response message 212 includes the ingress time (T4) of the delay request message 210.

[0034] Using T1, T2, T3, and T4, clock sink 204 can determine a time offset of clock sink 204 relative to clock source 202, such as using a calculation according to PTP. Time offset refers to the time difference between a clock source and a clock sink based on various delays between the clock source and the clock sink.

[0035] Figure 2B The exchange of timing messages according to a peer-to-peer delay mechanism is illustrated.Clock source 222 sends a synchronization message 226 to clock sink 224 (and possibly a subsequent message 228 if the clock source is a two-step clock source). Figure 2B Also shown is a Pdelay-request message 230 sent from the clock source 222 to the clock sink 224, which responds with a Pdelay-response message 232 (and a Pdelay-resp-fup message 234 if the clock sink 224 is a two-step clock) from the clock sink 224 to the clock source 222. The details of the Pdelay-request message, the Pdelay-response message, and the Pdelay-resp-fup message are discussed in the PTP specification.

[0036] In addition to the timed messages discussed above, Figure 2A and Figure 2B Prior to the exchange of the timing messages depicted in , another timing message exchanged between the time clocks is a notification message. The notification message contains quality attributes about the time clock that sent the notification message. For example, the quality attributes include the category, priority and / or quality of the time clock. The notification messages exchanged between the first time clock and the second time clock can be used by the first time clock and the second time clock (based on a comparison of the quality attributes) to determine which of the first time clock and the second time clock is a clock source and which of the first time clock and the second time clock is a clock sink.

[0037] The first time clock sends a first notification message to the second time clock, and the second time clock sends a second notification message to the first time clock. The first time clock and the second time clock may implement an optimal clock source algorithm to select which of the first time clock and the second time clock is a clock source and the other of the first time clock and the second time clock is a clock sink based on quality information in the first notification message and the second notification message. The optimal clock source algorithm of PTP is called the Best Master Clock Algorithm (BMCA).

[0038] Question 1

[0039] Problem 1 involves a situation where the boundary time clocks 104-1 and 104-2 of the respective master device 102-1 and slave device 102-2 send redundant announcement messages to a clock sink (e.g., the ordinary time clock 114 in the client device 112 or another clock sink). Problem 1 affects time clocks that employ an end-to-end delay mechanism or a peer delay mechanism.

[0040] The advanced clock source 108 generates an announcement message, which is sent to the boundary time clock (one of 104-1 and 104-2) of the MCLAG logic device 102 via the transparent time clock 110 of the core device 105. The core device 105 is connected to the MCLAG logic device 102 through the core-side MCLAG 118. The core device 105 can use the LAG hash algorithm on the packet header content of the announcement message to select which LAG interface connected to the MCLAG 118 to transmit the announcement message. The announcement message takes the form of a packet containing a header and a payload. "Packet" can refer to a data packet carrying data or a control packet carrying control information. The payload carries data or control information, while the header includes fields used to forward the packet in the network and for identifying information of one or more communication protocols associated with the packet.

[0041] The LAG hash algorithm involves applying a hash function to certain fields of the packet's header to obtain a hash value, and the hash value is used to select from a plurality of LAG interfaces of the LAG. After the core device 105 has selected the LAG interface through which to send the notification message on the core-side MCLAG 118, the core device 105 sends the notification message with the updated correction field to the master device 102-1 or the slave device 102-2 (depending on which LAG interface is selected) through the selected LAG interface and on the network link of the MCLAG 118. The correction field (e.g., PTP CorrectionField) is updated with the residence time of the notification message in the transparent time clock 110 of the core device 105. The residence time is the egress time of the notification message (as sent to the MCLAG logic device 102) and the ingress time of the notification message (as received from the advanced clock source 108).

[0042] In the example, assume that an announcement message is received at the master device 102-1. The master BTC 104-1 in the master device 102-1 uses the announcement message to apply the best clock source algorithm and select the senior clock source 108 as the clock source, so that the master BTC 104-1 is a clock sink that uses the senior clock source 108 as a time reference. The master device 102-1 indicates the LAG interface of the master device 102-1 that received the announcement message from the senior clock source 108 as the clock sink LAG interface.

[0043] Master BTC 104-1 generates its announcement message (updated with information from grand clock source 108) and sends it to slave device 102-2 and downstream devices via access-side MCLAG 120. The announcement message generated by master BTC 104-1 is received by client device 112.

[0044] The secondary BTC 104-2 in the secondary device 102-2 receives the announcement message from the primary device 102-1, and the secondary BTC 104-2 also generates its announcement message (updated with the information of the senior clock source 108). The secondary device 102-2 sends the announcement message generated by the secondary BTC 104-2 to the downstream devices through the access-side MCLAG 120. As a result, the client device 112 may receive redundant announcement messages from the boundary time clocks 104-1 and 104-2 (both containing the information of the senior clock source 108). Client devices that receive redundant announcement messages associated with a common clock source may cause problem 1.

[0045] Question 2 and Question 3

[0046] Problem 2 involves a situation where the boundary time clock of MCLAG logic device 102 does not properly process a synchronization message or a subsequent message from a clock source (eg, senior clock source 108 or another clock source).

[0047] Problem 3 involves a situation where boundary time clocks 104 - 1 and 104 - 2 of MCLAG logic device 102 send redundant sync or follow-up messages to a clock sink (eg, ordinary time clock 114 in client device 112 or another clock sink).

[0048] Problems 2 and 3 affect time clocks that use end-to-end delay mechanisms or peer delay mechanisms.

[0049] After executing the best clock source algorithm based on the announcement message, the senior clock source 108 sends a synchronization message to select a clock source and a clock sink between the senior clock source 108 and each boundary time clock 104-1 and 104-2. If the senior clock source 108 is a two-step clock, the senior clock source 108 sends a subsequent message after the synchronization message. If the senior clock source 108 is a single-step clock, the senior clock source 108 does not send a subsequent message after the synchronization message.

[0050] The sync message from grand clock source 108 is passed to MCLAG logic device 102 via transparent time clock 110 of core device 105. Transparent time clock 110 updates the correction field in the sync message with the residence time of the sync message through transparent time clock 110.

[0051] If applicable, subsequent messages from grand clock source 108 are passed to MCLAG logic device 102 via transparent time clock 110 of core device 105. Transparent time clock 110 does not update the correction field in subsequent messages, which are forwarded from grand clock source 108 to MCLAG logic device 102 unmodified.

[0052] The core device 105 applies the LAG hash algorithm to select a LAG interface to transmit the synchronization message (and similarly applies the LAG hash algorithm to select a LAG interface to transmit subsequent messages, if applicable).

[0053] Continuing with the example discussed in connection with Problem 1, assume that an announcement message from grand clock source 108 is received by master BTC 104 - 1 , and therefore master BTC 104 - 1 utilizes grand clock source 108 to execute an optimal clock source algorithm.

[0054] If the Sync or Subsequent message from the Grand Clock Source 108 also arrives at the Master BTC 104-1, no problem arises because the Sync or Subsequent message is received at the same Master BTC 104-1 as the Announce message.

[0055] However, if the Sync or Subsequent message reaches secondary BTC 104-2, secondary BTC 104-2 may discard the Sync or Subsequent message because secondary BTC 104-2 has not received a matching Announce message from senior clock source 108. The discarding of the Sync or Subsequent message constitutes incorrect handling of the Sync or Subsequent message, which raises Problem 2.

[0056] Note that in the example where the grand clock source 108 is a two-step clock, it is possible that the sync message from the grand clock source 108 is received by the master BTC 104-1, but the subsequent message from the grand clock source 108 is received by the slave BTC 104-2. In this case, the slave BTC 104-2 may discard the subsequent message, which raises Problem 2. Alternatively, the sync message from the grand clock source 108 is received by the slave BTC 104-2, but the subsequent message from the grand clock source 108 is received by the master BTC 104-1. In this case, the master BTC 104-1 may discard the subsequent message, which also raises Problem 2.

[0057] After receiving the synchronization message or subsequent message from the senior clock source 108, each BTC in the primary BTC 104-1 and the secondary BTC 104-2 will generate its own synchronization message or subsequent message. The primary BTC 104-1 and the secondary BTC 104-2 send redundant synchronization messages or subsequent messages that are received at the client device 112. The presence of redundant synchronization messages or subsequent messages at the client device 112 can cause the time offset calculation of the ordinary time clock 114 of the client device 112 to be inaccurate, which leads to problem 3.

[0058] Question 4 and Question 5

[0059] Problem 4 involves a situation where the boundary time clock of the MCLAG logic device 102 does not properly handle a delayed response message from a clock source (eg, the senior clock source 108 or another clock source).

[0060] Problem 5 involves a situation in which the boundary time clock of the MCLAG logic device 102 does not properly process a delay request message from a clock sink (eg, the ordinary time clock 114 in the client device 112 or another clock sink).

[0061] Issues 4 and 5 affect time clocks that use end-to-end delay mechanisms.

[0062] Continuing the example discussed above in conjunction with Questions 1 to 3, assume that the LAG interface of the master device 102-1 has been identified as a clock sink interface. Assuming that an end-to-end delay mechanism is adopted, the master BTC 104-1 in the master device 102-1 sends a delay request message toward the advanced clock source 108 through the core-side MCLAG 118. The delay request is delivered through the transparent time clock 110 of the core device 105, and the core device 105 updates the correction field of the delay request with the residence time of the delay request through the transparent time clock 110.

[0063] The senior clock source 108 receives the delay request message, and in response to the delay request message, the senior clock source 108 sends a delay response message toward the MCLAG logic device 102. The delay response message is passed through the transparent time clock 110 of the core device 105. Based on the LAG hash algorithm applied by the core device 105, the delay response message can be sent through the selected LAG interface of the core device 105 connected to the master device 102-1 or the slave device 102-2.

[0064] If the delay response message reaches the master device 102 - 1 , the master BTC 104 - 1 is able to process the delay response message because the master BTC 104 - 1 sends the delay request message to the grand clock source 108 .

[0065] However, if the Delay Response message arrives at secondary device 102-2, secondary BTC 104-2 discards the Delay Response message because there will be no matching Delay Request sent from secondary BTC 104-2. This leads to Problem 4.

[0066] At the client device 112 , after the ordinary time clock 114 in the client device 112 receives the synchronization message from the boundary time clock ( 104 - 1 or 104 - 2 ), the client device 112 indicates the LAG interface of the client device 112 that received the synchronization message as the clock source interface.

[0067] The ordinary time clock 114 in the client device 112 generates a delay request message and sends the delay request message toward the MCLAG logical device 102 on the LAG interface (clock source interface) through the access device 116. The transparent time clock 117 in the access device 116 updates the correction field of the delay request message using the residence time through the transparent time clock 117. Additionally, the access device applies a LAG hash algorithm to select a LAG interface connected to the access-side MCLAG 120 to send the delay request message with the updated correction field. Depending on which LAG interface of the access device 116 selected by the LAG hash algorithm, the delay request message can reach the master device 102-1 or the slave device 102-2. If the delay request message reaches the slave device 102-2, the slave BTC 104-2 can discard the delay request message because no matching synchronization message is found at the slave device 102-2. Alternatively, the slave device 102-2 can respond to the delay request message with a delay response message. The ordinary time clock 114 in the client device 112 receiving the delay response message may discard the delay response message because the ordinary time clock 114 expects the delay response message from the master device 102-1. Problem 5 arises when the slave device 102-2 discards the delay request message or the slave device 102-2 responds to the delay request message with a delay response message.

[0068] In another example, if there are multiple access-side MCLAGs between the access device 116 and the MCLAG logical device 102, different client devices 112 may be connected to the MCLAG logical device 102 through different access-side MCLAGs. This may result in delay request packets from different common time clocks 114 being sent on different access-side MCLAGs, and as a result, some delay request packets may not reach the target device of the MCLAG logical device 102. This may cause the time synchronization process to fail, which leads to Problem 5.

[0069] Problems 2, 4, and 5 discussed above are caused by the application of the LAG hash algorithm, which may result in unpredictability as to which of the master device 102-1 and the slave device 102-2 of the MCLAG logical device 102 receives a particular timing message. In other words, due to the LAG hash algorithm, the timing message may not reach the intended destination, which may be the master device or the slave device of the MCLAG logical device 102. Incorrect processing of the timing message (such as by discarding the timing message) may result in errors in the time synchronization process and / or result in inaccurate time offset calculations.

[0070] The presence of multiple access-side MCLAGs can lead to unpredictability and errors in the time synchronization process. In addition, sending redundant messages such as redundant announcement, synchronization or follow-up messages to the clock sink can reduce time offset accuracy and increase unpredictability at the clock sink.

[0071] Example implementations for solving various problems

[0072] Various examples for addressing the issues discussed above are described below. In some examples, a boundary time clock in MCLAG logic device 102 includes a time protocol engine and a MCLAG timing control engine.

[0073] As used herein, an "engine" may refer to one or more hardware processing circuits, which may include any or some combination of a microprocessor, a core of a multi-core microprocessor, a microcontroller, a programmable integrated circuit, a programmable gate array, or other hardware processing circuits. Alternatively, an "engine" may refer to a combination of one or more hardware processing circuits and machine-readable instructions (software and / or firmware) executable on the one or more hardware processing circuits. Figure 1 In the example of , the engine in the corresponding boundary time clock is implemented by a part of the hardware processing circuit of the corresponding boundary time clock or by machine-readable instructions executable by the corresponding boundary time clock.

[0074] The primary BTC 104-1 includes a time protocol engine 130-1, and the secondary BTC 104-2 includes a time protocol engine 130-2. To support the calculation of the time offset between the clock source and the clock sink, the time protocol engine, which acts as a boundary time clock in the time clock, consumes timing messages (according to the time synchronization protocol) (note that the boundary time clock can act as a clock source relative to the downstream time clock and as a clock sink relative to the upstream time clock).

[0075] The primary BTC 104-1 also includes a MCLAG timing control engine 132-1, and the secondary BTC 104-2 also includes a MCLAG timing control engine 132-2. The MCLAG timing control engine changes the behavior of the time protocol engine in the corresponding boundary time clock so that a specific timing message is processed in a manner that deviates from the expected processing of the specific timing message according to the time synchronization protocol. This change in the processing of the specific timing message solves problems 1 to 5 discussed above.

[0076] like Figure 1 As further shown in FIG. 1 , the master device 102-1 includes a memory 140-1 and the slave device 102-2 includes a memory 140-2. The memory may be implemented with one or more memory devices, such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or other types of memory devices. The memories 140-1 and 140-2 store various information to be used by the corresponding MCLAG timing control engines 132-1 and 132-2 (discussed further below).

[0077] Implementation methods for solving problems 1 and 3

[0078] To solve Problem 1 and Problem 3, the primary BTC 104-1 and the secondary BTC 104-2 of the MCLAG logic device 102 perform an exchange of announcement messages over the inter-device link 122. The MCLAG timing control engine 132-1132-2 determines which of the primary BTC 104-1 and the secondary BTC 104-2 should act as a clock source and which should act as a clock sink.

[0079] For the purpose of controlling the behavior of primary BTC 104-1 and secondary BTC 104-2 with respect to the transmission of certain timing messages (such as announcement, synchronization and / or follow-up messages), a first one of BTC 104-1 and 104-2 is designated as a clock source and the other one of boundary time clocks 104-1 and 104-2 is designated as a clock sink on inter-device link 122.

[0080] Figure 3 is a flow chart of a process performed by the primary BTC 104-1 in the primary device 102-1 and the secondary BTC 104-2 in the secondary device 102-2. Figure 3 A specific order of tasks is shown, but in other examples, the tasks may be performed in a different order, some tasks may be omitted, and / or other tasks may be added.

[0081] The primary BTC 104-1 sends (at 302) an announcement message to the secondary BTC 104-2 via the inter-device link 122 of the MCLAG logical device 102. Based on the announcement message from the primary BTC 104-1, the MCLAG timing control engine 132-2 in the secondary BTC 104-2 determines whether the secondary BTC 104-2 is a clock source or a clock sink. In this example, it is assumed that the MCLAG timing control engine 132-2 determines (at 304) that the secondary BTC 104-2 is a clock sink on the inter-device link 122 of the MCLAG logical device 102.

[0082] Secondary BTC 104-2 sends (at 306) an announcement message to primary BTC 104-1. Based on the announcement message from secondary BTC 104-2, MCLAG timing control engine 132-1 in primary BTC 104-1 determines whether primary BTC 104-1 is a clock source or a clock sink. Figure 3 In the example of , assume that the MCLAG timing control engine 132 - 1 determines (at 308 ) that the master BTC 104 - 1 is the clock source on the inter-device link 122 of the MCLAG logic device 102 .

[0083] In some examples, the selection of the clock source and the clock sink between the boundary time clocks 104 - 1 and 104 - 2 is according to a best clock source algorithm (such as BMCA of PTP) based on the quality information included in the announcement message.

[0084] After MCLAG timing control engine 132-2 has designated secondary BTC 104-2 as a clock sink, time protocol engine 130-2 in secondary BTC 104-2 refrains (at 310) from sending selected timing messages through a MCLAG, such as access-side MCLAG 120. Selected timing messages not sent by the clock sink include announcement messages, synchronization messages, and follow-up messages.

[0085] Since the MCLAG timing control engine 132-1 has designated the master BTC 104-1 as the clock source, the time protocol engine 130-1 in the master BTC 104-1 continues (at 312) to send selected timing messages (including announce messages, sync messages, and follow-up messages) through the MCLAG (such as the access-side MCLAG 120).

[0086] Since only one of the boundary time clocks 104-1 and 104-2 in the MCLAG logic device 102 will send the selected timing message through the access-side MCLAG 120, an external clock sink (such as the client device 112 ( Figure 1) will not receive redundant announcement messages, synchronization messages, or follow-up messages from multiple different boundary time clocks in the MCLAG logic device 102, which solves Problem 1 and Problem 3. Note that if a time clock is external to the MCLAG logic device 102, then the time clock (clock source or clock sink) is "external".

[0087] Using the ability of MCLAG timing control engines 132-1 and 132-2 to select one of boundary time clocks 104-1 and 104-2 of MCLAG logical device 102 as a clock source and the other of boundary time clocks 104-1 and 104-2 as a clock sink on inter-device link 122, the behavior of boundary time clocks 104-1 and 104-2 can be modified from the expected behavior according to the time synchronization protocol. Although the boundary time clock is expected to send the selected timing message to the downstream time clock according to the time synchronization protocol, if the boundary time clock is identified as a clock sink on inter-device link 122, the boundary time clock will avoid sending the selected timing to the downstream time clock.

[0088] Implementation method for solving problem 2

[0089] To address issue 2, the MCLAG timing control engine in the boundary time clock of the MCLAG logic device 102 can change the clock role of the boundary time clock (which receives synchronization messages or subsequent messages intended for the peer boundary time clock) to the hybrid transparent time clock role. Unless the clock role of the boundary time clock is changed, the time protocol engine in the boundary time clock consumes timing messages according to the time synchronization protocol to support the calculation of the time offset for the synchronization time clock. However, if the clock role of the boundary time clock is changed to the hybrid transparent time clock role, then the boundary time clock behaves as a transparent time clock, and the time protocol engine processes timing messages in the role of the transparent time clock.

[0090] Alternatively, to address issue 2, the MCLAG timing control engine in the boundary time clock of MCLAG logic device 102 can change the time clock role of the boundary time clock (which receives synchronization messages intended for the peer boundary time clock) from the clock sink role to the clock source role.

[0091] like Figure 1As shown in , the memory 140-1 in the master device 102-1 of the MCLAG logic device 102 stores an external clock source table 142-1, and the memory 140-2 in the slave device 102-2 stores an external clock source table 142-2. The external clock source table includes one or more entries corresponding to one or more different external clock sources identified by the corresponding boundary time clock. More specifically, the entries of the external clock source table 142-1 include information of the external clock source identified by the master BTC 104-1, and the entries of the external clock source table 142-2 include information of the external clock source identified by the slave BTC 104-2. An "external" clock source refers to a clock source external to the boundary time clock, and it is identified based on the exchange of notification messages according to the time synchronization protocol.

[0092] In other examples, the information of the external clock source table may be contained in a different type of data structure (ie, other than a table). The data structure may be in the form of a file, a region of memory, a register, or any other type of data structure.

[0093] Examples of information in an entry of the external clock source table include any or some combination of the following: a source interface identifier of a LAG interface (port) of an electronic device including an external clock source associated with the entry (e.g., sourcePortIdentity according to PTP); an identifier of the external clock source (e.g., clockIdentity according to PTP); a priority of the external clock source; a category of the external clock source, an accuracy of the external clock source, or other information. In some examples, the information added to the entry of the external clock source table can be extracted from a notification message received from the external clock source.

[0094] In the discussion that follows, it is assumed that senior clock source 108 has exchanged announcement messages with master BTC 104-1 of master device 102-1, and that a clock source and a clock sink have been selected according to the best clock source algorithm. After applying the best clock source algorithm, senior clock source 108 sends synchronization messages intended for master BTC 104-1 of MCLAG logic device 102. However, due to the application of the LAG hash algorithm at core device 105, the LAG interface connected to slave device 102-2 through core-side MCLAG 118 is selected so that the synchronization message intended for master BTC 104-1 arrives at slave BTC 104-2 instead.

[0095] Figure 4 is a flow chart of a process 400 performed by secondary BTC 104-2 for solving Problem 2 using the first technique. Figure 4 A specific order of tasks is shown, but in other examples, the tasks may be performed in a different order, some tasks may be omitted, and / or other tasks may be added.

[0096] See also Figure 4 , the secondary BTC 104-2 of the secondary device 102-2 receives (at 402) a synchronization message sent by an upstream clock source (e.g., the senior clock source 108). The secondary BTC 104-2 checks whether the synchronization message is for itself or for the peer primary BTC 104-1. This check is performed as follows.

[0097] The MCLAG timing control engine 132-2 of the secondary BTC 104-2 extracts (at 404) a source interface identifier (e.g., sourcePortIdentity of PTP) from the header of the synchronization message and checks (at 406) whether the extracted source interface identifier exists in any entry of the external clock source table 142-2. According to PTP, portIdentity contains two attributes: clockIdentity (to identify the time clock) and PortNumber (to identify the port). When the time clock transmits a timing message, portIdentity is copied to the sourcePortIdentity field of the PTP message header of the timing message.

[0098] The check at 406 is performed by comparing the extracted source interface identifier with the source interface identifier(s) in one or more entries of the (local) external clock source table 142-2. The external clock source table 142-2 is "local" relative to the secondary BTC 104-2 that received the synchronization message. A match between the extracted source interface identifier and the source interface identifier in the entry of the (local) external clock source table 142-2 indicates that the extracted source interface identifier is present in the external clock source table 142-2.

[0099] The extracted source interface identifier in the entry of the (local) external clock source table 142-2 indicates that the secondary BTC 104-2 previously received a notification message (from an upstream clock source) for the source interface identifier. If the MCLAG timing control engine 132-2 determines that the extracted source interface identifier is present in the entry of the (local) external clock source table 142-2, then the behavior of the secondary BTC 104-2 (regarding how the secondary BTC 104-2 operates according to the time synchronization protocol) is not modified, and the time protocol engine 130-2 in the secondary BTC 104-2 processes (at 408) the synchronization message according to the time synchronization protocol.

[0100] However, if the MCLAG timing control engine 132-2 determines that the extracted source interface identifier is not present in any entry of the (local) external clock source table 142-2, then the MCLAG timing control engine 132-2 checks (at 410) to determine if the extracted source interface identifier is present in any entry of the (peer) external clock source table 142-1 of the peer master BTC 104-1. The external clock source table 142-1 is a "peer" external clock source table because it is associated with the master BTC 104-1 (from the perspective of the slave BTC 104-2).

[0101] In some examples, a copy (e.g., a cached copy) of the external clock source table 142-1 may be stored in the memory 140-2 of the slave device 102-2. The check at 410 may be performed against the copy of the (peer) external clock source table 142-1. In other examples, the check at 410 may be performed by accessing the (peer) external clock source table 142-1 in the memory 140-1 of the master device 102-1 via the inter-device link 122.

[0102] In examples where copies of the external clock source table are maintained at the master device 102 - 1 and the slave device 102 - 2 , the MCLAG timing control engines 132 - 1 and 132 - 2 may synchronize the copies of the external clock source table to maintain consistency with the original external clock source table.

[0103] If the MCLAG timing control engine 132-2 determines (at 410) that the extracted source interface identifier is not present in any entry of the (peer) external clock source table 142-1, the MCLAG timing control engine 132-2 causes the time protocol engine 130-2 of the secondary BTC 104-2 to discard (at 412) the synchronization message, which causes the time synchronization process between the upstream clock source (e.g., the senior clock source 108) and the boundary time clock in the MCLAG logic device 102 to fail. In some examples, the MCLAG timing control engine 132-2 may send an indication to the time protocol engine 130-2 that the source interface identifier is not present in any entry of the (peer) external clock source table 142-1. The indication may cause the timing control engine 132-2 to discard the synchronization message. An "indication" may refer to a signal, an information element, or any other type of indicator.

[0104] If the MCLAG timing control engine 132-2 determines (at 410) that the extracted source interface identifier is present in an entry of the (peer) external clock source table 142-1 of the peer master BTC 104-1, the MCLAG timing control engine 132-2 changes (at 414) the clock role of the secondary BTC 104-2 to a hybrid transparent time clock role for processing synchronization messages. In some examples, the MCLAG timing control engine 132-2 may send a hybrid transparent time clock role indication to the time protocol engine 130-2 to change the role of the time protocol engine 130-2. The hybrid transparent time clock role indication causes the time protocol engine 130-2 to process the synchronization message in the manner in which the transparent time clock processes the synchronization message.

[0105] In response to the hybrid transparent time clock role indication, the time protocol engine 130-2 updates (at 416) the correction field in the synchronization message with the dwell time of the synchronization message in the secondary BTC 104-2. The dwell time is the difference between the egress time of the updated synchronization message (with the updated correction field) (as transmitted from the secondary BTC 104-2 to the peer primary BTC 104-1 via the inter-device link 122) and the ingress time of the synchronization message (as received at the secondary BTC 104-2).

[0106] The secondary BTC 104-2 sends (at 418) the updated Sync message (with the updated Correction field) to the peer primary BTC 104-1 via the inter-device link 122.

[0107] Figure 5 is a flow chart of an example process 500 performed by master BTC 104-1 of master device 102-1 to solve Problem 2. Figure 5 A specific order of tasks is shown, but in other examples, the tasks may be performed in a different order, some tasks may be omitted, and / or other tasks may be added.

[0108] The master BTC 104-1 receives (at 502) an updated synchronization message (with an updated correction field) from the peer secondary BTC 104-2. According to the time synchronization protocol, the master BTC 104-1 does not expect to receive any synchronization messages via the inter-device link 122. However, according to some examples of the present disclosure, the MCLAG timing control engine 132-1 of the master BTC 104-1 modifies the behavior of the master BTC 104-1 with respect to the updated synchronization message from the peer secondary BTC 104-2 so that the master BTC 104-1 can correctly process the updated synchronization message.

[0109] The MCLAG timing control engine 132-1 of the master BTC 104-1 extracts (at 504) the source interface identifier from the received updated synchronization message from the peer slave BTC 104-2. The MCLAG timing control engine 132-1 checks (at 506) whether the extracted source interface identifier is present in any entry of the (local) external clock source table 142-1. If the extracted source interface identifier is in an entry of the external clock source table 142-1, it indicates that the master BTC 104-1 previously received a notification message (from an upstream clock source) for the source interface identifier.

[0110] In response to determining (at 506) that the extracted source interface identifier is present in the entry of the external clock source table 142-1, the MCLAG timing control engine 132-1 maps (at 508) the updated synchronization message to a given LAG interface (of the MCLAG) at which the boundary time clock 102-1 received the announce message from the upstream clock source (e.g., the senior clock source 108), and causes the time protocol engine 130-1 to process (at 510) the updated synchronization message in accordance with the time synchronization protocol. For example, the MCLAG timing control engine 132-1 may send an indication to the time protocol engine 130-1 that the updated synchronization message is associated with the given LAG interface. Mapping the updated synchronization message to the given LAG interface means associating the updated synchronization message to the given LAG interface such that any additional timing message transmissions by the time protocol engine 130-1 are from the given LAG interface.

[0111] In response to determining (at 506) that the extracted source interface identifier is not present in any entry of the external clock source table 142-1, the MCLAG timing control engine 132-1 causes the time protocol engine 130-1 of the master BTC 104-1 to discard (at 512) the updated synchronization message, which causes the time synchronization process between the upstream clock source (e.g., the senior clock source 108) and the boundary time clock in the MCLAG logic device 102 to fail.

[0112] If the upstream clock source (e.g., senior clock source 108) is a two-step clock, the upstream clock source will send a subsequent message after the synchronization message. If the subsequent message is received by the secondary BTC 104-2 of the secondary device 102-2, the subsequent message is processed similarly to the synchronization message according to Figure 4 One difference is that the processing of subsequent messages will not involve updating of the correction field in the subsequent messages (e.g., the subsequent messages will omit the Figure 4 As a result, subsequent messages sent from secondary BTC 104-2 to peer primary BTC 104-1 will be unmodified with respect to subsequent messages received at secondary BTC 104-2.

[0113] The processing of subsequent messages received by the primary BTC 104-1 from the peer secondary BTC 104-2 includes the following: Figure 5 Tasks similar to the ones depicted in .

[0114] Alternatively, to solve problem 2, the MCLAG timing control engine 132-2 in the secondary BTC 104-2 can change its time clock role from the clock sink role to the clock source role via the inter-device link 122. In response to receiving a synchronization message from an upstream clock source (e.g., the senior clock source 108), the MCLAG timing control engine 132-2 of the secondary BTC 104-2 performs tasks similar to tasks 404, 406, and 410 discussed above. If the MCLAG timing control engine 132-2 determines (similar to task 410) that the extracted source interface identifier (from the synchronization message) is present in an entry of the (peer) external clock source table 142-1 of the peer primary BTC 104-1, the secondary BTC 104-2 sends a receipt indication of the synchronization message to the primary BTC 104-1. The indication may be in the form of a message or an information element and contains information of the synchronization message (e.g., the source interface identifier). In response to the indication, the master BTC 104-1 determines from its local external clock source table 142-1 that the source interface identifier of the synchronization message is located in the entry of the external clock source table 142-1. In response, the master BTC 104-1 forwards the previously received notification message from the upstream clock source (without modification) to the auxiliary BTC 104-2. The master BTC 104-1 also changes its clock role from the clock source role to the clock sink role through the inter-device link 122. The auxiliary BTC 104-2 compares the source interface identifier (e.g., PTPsourcePortIdentity) of the forwarded notification message with the source interface identifier of the previously received synchronization message that has been stored. The forwarded notification message is mapped to the corresponding LAG interface (of the MCLAG) that receives the synchronization message. The MCLAG timing control engine 132-2 in the auxiliary BTC 104-2 changes its clock role from the clock sink role to the clock source role through the inter-device link 122. At this point, the auxiliary BTC 104-2 is able to consume the synchronization message. Using this alternative approach, the secondary BTC 104-2 does not transition to the hybrid transparent time clock role.

[0115] Implementation method for solving problem 4

[0116] To solve problem 4, the MCLAG timing control engine in the boundary time clock of the MCLAG logic device 102 is capable of changing the clock role of the boundary time clock to a hybrid transparent time clock role (similar to the process discussed above for solving problem 2) for the purpose of processing delayed response messages from an external clock source (such as the advanced clock source 108).

[0117] In the discussion that follows, it is assumed that the master BTC 104-1 of the master device 102-1 of the MCLAG logic device 102 has sent a delay request message to an upstream clock source (e.g., the senior clock source 108). In response to the delay request message from the master BTC 104-1, the upstream clock source generates a delay response message intended for the master BTC 104-1. However, due to the application of the LAG hash algorithm at the core device 105, the LAG interface connected to the slave device 102-2 through the core-side MCLAG 118 is selected so that the delay response message intended for the master BTC 104-1 arrives at the slave BTC 104-2 instead.

[0118] Figure 6 is a flow chart of an example process 600 performed by secondary BTC 104-2 to solve Problem 4. Figure 6 A specific order of tasks is shown, but in other examples, the tasks may be performed in a different order, some tasks may be omitted, and / or other tasks may be added.

[0119] See also Figure 6 , the secondary BTC 104-2 of the secondary device 102-2 receives (at 602) a delay response message sent by an upstream clock source (e.g., the senior clock source 108). The secondary BTC 104-2 checks whether the delay response message is for itself or for the peer primary BTC 104-1. This check is performed as follows.

[0120] The MCLAG timing control engine 132-2 of the secondary BTC 104-2 extracts (at 604) a source interface identifier (eg, sourcePortIdentity of PTP) from the header of the delay response message and checks (at 606) any entry existing in the (local) external clock source table 142-2 above the extracted source interface identifier.

[0121] If the extracted source interface identifier is in the entry of the (local) external clock source table 142-2, it indicates that the secondary BTC 104-2 has participated in the time synchronization process (including the exchange of announcement messages, the reception of synchronization messages, and the transmission of delay request messages) with the upstream clock source (e.g., the senior clock source 108) for the source interface identifier. If the MCLAG timing control engine 132-2 determines that the extracted source interface identifier is present in the entry of the (local) external clock source table 142-2, the behavior of the secondary BTC 104-2 (with respect to how the secondary BTC 104-2 will act according to the time synchronization protocol) is not modified, and the time protocol engine 130-2 in the secondary BTC 104-2 processes (at 608) the delay response message according to the time synchronization protocol.

[0122] However, if the MCLAG timing control engine 132-2 determines that the extracted source interface identifier does not exist in any entry of the external clock source table 142-2, then the MCLAG timing control engine 132-2 checks (at 610) to determine whether the extracted source interface identifier exists in any entry of the (peer) external clock source table 142-1 of the peer master BTC 104-1. If the MCLAG timing control engine 132-2 determines (at 610) that the extracted source interface identifier does not exist in any entry of the (peer) external clock source table 142-1, then the MCLAG timing control engine 132-2 causes the time protocol engine 130-2 of the secondary BTC 104-2 to discard (at 612) the delay response message, which causes the time synchronization process between the upstream clock source (e.g., senior clock source 108) and the boundary time clock in the MCLAG logic device 102 to fail.

[0123] If the MCLAG timing control engine 132-2 determines (at 610) that the extracted source interface identifier is present in an entry of the (peer) external clock source table 142-1 of the peer master BTC 104-1, the MCLAG timing control engine 132-2 changes (at 614) the clock role of the secondary BTC 104-2 to the hybrid transparent time clock role for processing the delay response message. In some examples, the MCLAG timing control engine 132-2 may send a hybrid transparent time clock role indication to the time protocol engine 130-2 to change the clock role of the time protocol engine 130-2.

[0124] In response to the hybrid transparent time clock role indication, the time protocol engine 130-2 sends (at 616) a delay response message to the peer master BTC 104-1 over the inter-device link 122. Note that the delay response message sent over the inter-device link is not modified (e.g., the correction field of the delay response message is not updated).

[0125] Figure 7 is a flow chart of an example process 700 performed by master BTC 104-1 of master device 102-1 to solve Problem 4. Figure 7 A specific order of tasks is shown, but in other examples, the tasks may be performed in a different order, some tasks may be omitted, and / or other tasks may be added.

[0126] The master BTC 104-1 receives (at 702) a delay response message from the peer slave BTC 104-2. The MCLAG timing control engine 132-1 of the master BTC 104-1 extracts (at 704) a source interface identifier from the delay response message received from the peer slave BTC 104-2. The MCLAG timing control engine 132-1 checks (at 706) whether the extracted source interface identifier exists in any entry of the (local) external clock source table 142-1. The extracted source interface identifier in the entry of the external clock source table 142-1 indicates that the master BTC 104-1 has participated in a time synchronization process (with an upstream clock source (e.g., the senior clock source 108)) for the source interface identifier.

[0127] In response to determining (at 706) that the extracted source interface identifier is present in an entry in the (local) external clock source table 142-1, the MCLAG timing control engine 132-1 maps (at 708) the delay response message to a given LAG interface (of the MCLAG) at which the boundary time clock 102-1 has exchanged timing messages with an upstream clock source (e.g., the advanced clock source 108), and causes the time protocol engine 130-1 to process (at 710) the delay response message in accordance with the time synchronization protocol.

[0128] In response to determining (at 706) that the extracted source interface identifier is not present in any entry of the (local) external clock source table 142-1, the MCLAG timing control engine 132-1 causes the time protocol engine 130-1 of the master BTC 104-1 to discard (at 712) the delay response message, which causes the time synchronization process between the upstream clock source (e.g., senior clock source 108) and the boundary time clock in the MCLAG logic device 102 to fail.

[0129] Embodiment for solving problem 5

[0130] To address issue 5, the MCLAG timing control engine in the boundary time clock of MCLAG logic device 102 can change the clock role of the boundary time clock to the hybrid transparent time clock role for the purpose of processing delay request messages from a clock sink (such as client device 112).

[0131] Figure 8is a flow chart of an example process performed by primary BTC 104-1 and secondary BTC 104-2 to solve Problem 5. Figure 8 A specific order of tasks is shown, but in other examples, the tasks may be performed in a different order, some tasks may be omitted, and / or other tasks may be added.

[0132] Figure 8 Also shown are additional information stored in memory 140-1 accessible by master BTC 104-1 and memory 140-2 accessible by master BTC 104-2. The additional information stored in memory 140-1 includes a local interface identification table (IIT) 802-1, a peer IIT 804-1, a local clock role indicator 806-1, and a peer MCLAG status indicator 808-1. Similarly, the additional information stored in memory 140-2 includes a local IIT 802-2, a peer IIT 804-2, a local clock role indicator 806-2, and a peer MCLAG status indicator 808-2.

[0133] The local clock role indicator 806-1 or 806-2 indicates whether the corresponding BTC (104-1 or 104-2) is a clock source or a clock sink. An "indicator" may refer to a flag (e.g., a bit or a set of bits) or any other type of information element that may be set to different values ​​(e.g., a first value is used to specify that the corresponding BTC of the MCLAG logic device 102 is a clock source, and a different second value is used to specify that the corresponding BTC of the MCLAG logic device 102 is a clock sink).

[0134] The peer MCLAG state indicator 808-1 or 808-2 indicates whether the link state (or forwarding state) of the peer BTC to the MCLAG is open (operable) or closed (inoperable). For example, the peer MCLAG state indicator 808-1 (accessible by the primary BTC 104-1) is set to a first value to indicate that the link state of the peer secondary BTC 104-2 to the MCLAG is open (i.e., the peer secondary BTC 104-2 has an operational link state to the MCLAG). However, the peer MCLAG state indicator 808-1 is set to a different second value to indicate that the link state of the peer secondary BTC 104-2 to the MCLAG is closed (i.e., the peer secondary BTC 104-2 has an inoperable link state to the MCLAG). Peer MCLAG status indicator 808-2 (accessible by secondary BTC 104-2) is set to a first value indicating that the peer master BTC 104-1 to MCLAG link status is up, and peer MCLAG status indicator 808-2 is set to a different second value indicating that the peer master BTC 104-1 to MCLAG link status is down.

[0135] The local IIT 802-1 is a table maintained by the MCLAG timing control engine 132-1 of the master BTC 104-1. The entries of the local IIT 802-1 map an interface identifier (e.g., portIdentity of PTP) that identifies a LAG interface at which a delay request message is transmitted from a clock sink to the MCLAG to which the LAG interface is connected. The interface identifier may be based on the identity of the clock sink that sends the delay request message and the identity of the LAG interface from which the clock sink sends the delay request message. Mapping the interface identifier to the entry of the local IIT 802-1 of the MCLAG effectively maps the clock sink to the MCLAG. When additional delay request messages are received by the master BTC 104-1 via the MCLAG, the MCLAG timing control engine 132-1 adds corresponding additional entries to the local IIT 802-1. Note that the BTC of the MCLAG logical device 102 may be connected to multiple MCLAGs, so the entries of the local IIT 802-1 may map the interface identifier to the corresponding MCLAG.

[0136] Adding entries to the local IIT 802-1 in response to receipt of delay request messages is part of a delay request clock sink learning process, where the MCLAG timing control engine 132-1 tracks incoming delay request messages and maps the clock sink sending the delay request message to the corresponding access-side MCLAG(s).

[0137] The local IIT 802-2 is a table maintained by the MCLAG timing control engine 132-2 of the secondary BTC 104-2. As part of the delay request clock sink learning process, when the secondary BTC 104-2 receives a delay request message from the clock sink, an entry is added to the local IIT 802-2 by the MCLAG timing control engine 132-2. The peer IIT 804-1 in the memory 140-1 accessible by the primary BTC 104-1 is a copy of the local IIT 802-2. Similarly, the peer IIT 804-2 in the memory 140-2 accessible by the secondary BTC 104-2 is a copy of the local IIT 802-1.

[0138] The MCLAG timing control engines 132-1 and 132-2 may synchronize the peer IIT 804-1 with the local IIT 802-2 (so that updates to the local IIT 802-2 are reflected in the peer IIT 804-1). Similarly, the MCLAG timing control engines 132-1 and 132-2 may synchronize the peer IIT 804-2 with the local IIT 802-1 (so that updates to the local IIT 802-1 are reflected in the peer IIT 804-2).

[0139] In other examples, instead of tables, IITs 802-1, 804-1, 802-2, and 804-2 may be implemented with other types of data structures.

[0140] A delay request message (such as according to PTP) does not have a field for specifically identifying a clock source that is the target of the delay request message. As a result, a BTC that receives a delay request message cannot determine whether the delay request message is for the BTC based on the field in the delay request message. To address the above problem, a given BTC of the MCLAG logic device 102 that receives a delay request message from a clock sink (e.g., the ordinary time clock 114 of the client device 112) can determine whether the given BTC is the target of the delay request message based on the additional information (discussed above) in the memory 140-1 or 140-2, and if not, the given BTC can forward the delay request message to a peer BTC of the MCLAG logic device 102 for processing. The peer BTC that receives the forwarded delay request message can map the forwarded delay request message to the LAG interface of the peer BTC, so that the peer BTC can send a delay response message in response to the forwarded delay request message to the clock sink via the LAG interface.

[0141] Figure 8 Concerning such an example, a delay request message intended for primary BTC 104-1 of MCLAG logic device 102 arrives at secondary BTC 104-2 based on applying a LAG hash algorithm at an electronic device including an external clock sink that transmits the delay request message. For example, the electronic device including the external clock sink is client device 112, which includes ordinary time clock 114.

[0142] Secondary BTC 104-2 receives a delay request message from an external clock sink at a LAG interface connected to access-side MCLAG 120 (at 810). MCLAG timing control engine 132-2 of secondary BTC 104-2 determines whether secondary BTC 104-2 should forward the delay request message to peer BTC 104-1. This determination is based on local clock role indicator 806-2 and peer MCLAG status indicator 808-2. MCLAG timing control engine 132-2 determines whether both conditions 1 and 2 below are true. If MCLAG timing control engine 132-2 determines that secondary BTC 104-2 is a clock sink relative to primary BTC 104-1 based on local clock role indicator 806-2, condition 1 is true. Condition 2 is true if the MCLAG timing control engine 132-2 determines from the peer MCLAG status indicator 808-2 that the link status of the peer master BTC 104-1 to the MCLAG (eg, the access-side MCLAG 120 or another access-side MCLAG if multiple access-side MCLAGs exist) is up.

[0143] If the MCLAG timing control engine 132-2 determines (at 812) whether the secondary BTC 104-2 is a clock sink based on the local clock role indicator 806-2. If not (condition 1 is false), the secondary BTC 104-2 is a clock source and the MCLAG timing control engine 132-2 locally processes (at 814) the delay request message. For example, if the MCLAG timing control engine 132-2 determines that the secondary BTC 104-2 is a clock source relative to the primary BTC 104-1 based on the local clock role indicator 806-2, then the MCLAG timing control engine 132-2 causes the time protocol engine 130-2 of the secondary BTC 104-2 to consume the delay request message, which causes the time protocol engine 130-2 to send a delay response message to the clock sink that sent the delay request message (e.g., the normal time clock 114 of the client device 112).

[0144] On the other hand, if the MCLAG timing control engine 132-2 determines (at 812) that the secondary BTC 104-2 is the clock sink (condition 1 is true) based on the local clock role indicator 806-2, the MCLAG timing control engine 132-2 determines (at 816) whether the link status of the peer primary BTC 104-1 to the MCLAG is up based on the peer MCLAG status indicator 808-2.

[0145] If not (condition 2 is false, although condition 1 is true), it indicates that peer master BTC 104-1 does not have an open link state to the MCLAG, and therefore master BTC 104-1 will not be able to process the delay request message - even if forwarded. In this case, secondary BTC 104-2 processes (at 814) the delay request message locally - in this case, secondary BTC 104-2 can respond to the delay request message, even if the delay request message is intended for primary BTC 104-1, or alternatively, secondary BTC 104-2 can discard the delay request message.

[0146] If the MCLAG timing control engine 132-2 determines (at 816) from the peer MCLAG state indicator 808-2 that the link state of the peer primary BTC 104-1 to the MCLAG is up (condition 2 is true and condition 1 is true), the MCLAG timing control engine 132-2 changes (at 818) the clock role of the secondary BTC 104-2 to the hybrid transparent time clock role for processing the delay request message. In some examples, the MCLAG timing control engine 132-2 may send a hybrid transparent time clock role indication to the time protocol engine 130-2 to change the clock role of the time protocol engine 130-2. The hybrid transparent time clock role indication causes the time protocol engine 130-2 to process the delay request message in the manner in which the transparent time clock would process the delay request message.

[0147] In response to the hybrid transparent time clock role indication, the time protocol engine 130-2 updates (at 820) the correction field in the delay request message with the dwell time of the delay request message in the secondary BTC 104-2. The dwell time is the difference between the egress time of the updated delay request message (with the updated correction field) (as transmitted from the secondary BTC 104-2 to the peer primary BTC 104-1 via the inter-device link 122) and the ingress time of the delay request message (as received at the secondary BTC 104-2).

[0148] Secondary BTC 104-2 sends (at 822) an updated delay request message to peer primary BTC 104-1 via inter-device link 122. In response to receiving the updated delay request message via inter-device link 122, primary BTC 104-1 performs, according to some examples of the present disclosure: Fig. 9 The process described in .

[0149] Fig. 9 is a flow chart of an example process 900 performed by master BTC 104-1 to solve Problem 5. Fig. 9A specific order of tasks is shown, but in other examples, the tasks may be performed in a different order, some tasks may be omitted, and / or other tasks may be added.

[0150] The primary BTC 104-1 receives (at 902) an updated delay request message (e.g., at Figure 8 104-2 at 822 in FIG. 104). There are two possible scenarios (A and B) associated with a delay request message received over inter-device link 122. In scenario A, the delay request message originates from (is generated by) peer secondary BTC 104-2 (in its role as a clock sink on inter-device link 122). In scenario A, the delay request message originated by secondary BTC 104-2 is not received from an external clock sink (e.g., ordinary time clock 114 in client device 112). In scenario B, the delay request message is received by peer secondary BTC 104-2 from an external clock sink and forwarded by peer secondary BTC 104-2 to primary BTC 104-1 after the correction field of the delay request message is updated at secondary BTC 104-2.

[0151] The MCLAG timing control engine 132-1 of the master BTC 104-1 extracts (at 904) the interface identifier (eg, portIdentity for PTP) as extracted from the header of the updated delay request message.

[0152] Based on the extracted interface identifier, the MCLAG timing control engine 132-1 determines (at 906) which of the scenarios A and B is applicable. The determination (at 906) is based on a comparison of the extracted interface identifier (as extracted from the delay request message) with a stored interface identifier, the stored interface identifier identifying the interface of the secondary device 102-2 including the secondary BTC 104-2 from which the primary BTC 104-1 previously received a timing message (e.g., an announcement message). As noted above, the primary BTC 104-1 and the secondary BTC 104-2 may exchange announcement messages over the inter-device link 122 to select a clock source and a clock sink. The announcement message has a header that includes an interface identifier. For example, the header of the announcement message sent by the secondary BTC 104-2 includes an interface identifier of the interface (port) of the secondary device 102-2 from which the announcement message is sent. The primary BTC 104-1 may record the interface identifier of the announcement message as the stored interface identifier compared at 904.

[0153] If the interface identifier extracted from the delay request message matches the stored interface identifier, then the MCLAG timing control engine 132-1 determines that scenario A applies (i.e., the delay request message originated from the secondary BTC 104-2). If scenario A applies, then the MCLAG timing control engine 132-1 causes the time protocol engine 130-1 of the primary BTC 104-1 to process (at 908) the updated delay request message for the purpose of responding to the peer secondary BTC 104-2 with a delay response message over the inter-device link 122.

[0154] If scenario B applies, the MCLAG timing control engine 132-1 performs a lookup (at 910) of the peer IIT 604-1 (which is a copy of the local IIT 602-2) to identify which MCLAG (the "identified MCLAG") is to be used to respond to the external clock sink. If there are multiple access-side MCLAGs between the MCLAG logic device 102 and the access device 116 (or multiple access devices), then the identified MCLAG is one of the multiple access-side MCLAGs.

[0155] Lookup of the peer IIT 604-1 includes a search to determine (at 912) whether any entry of the peer IIT 604-1 includes the extracted interface identifier extracted from the delay request message received over the inter-device link 122.

[0156] If the MCLAG timing control engine 132-1 determines (at 912) that a match for the extracted interface identifier is found in an entry of the peer IIT 604-1, the MCLAG timing control engine 132-1 maps (at 914) the updated delay request message to the LAG interface (of the MCLAG) identified by the extracted interface identifier, which is the LAG interface of the network link connected to the identified MCLAG. The MCLAG timing control engine 132-1 causes the time protocol engine 130-1 to process (at 908) the updated delay request message and respond with a delay response message that is sent over the LAG interface to the external clock sink.

[0157] If the MCLAG timing control engine 132-1 determines (at 912) that a match for the extracted interface identifier is not found in any entry of the peer IIT 604-1, the MCLAG timing control engine 132-1 discards (at 916) the delay request message.

[0158] By using the various example implementations discussed above, the boundary time clock in the MCLAG logic device 102 can maintain accurate and stable time synchronization with one or more other time clocks while supporting (multiple) MCLAGs. The various example implementations do not rely on new timing messages or new information elements for timing messages. A "new" timing message or new information element refers to a timing message or information element that is not currently defined by a time synchronization protocol such as PTP.

[0159] Various example embodiments can work with time clocks that employ end-to-end and peer-to-peer delay mechanisms. In addition, various example embodiments can work with single-step and two-step clocks.

[0160] Additional Examples

[0161] Fig.10 is a block diagram of a non-transitory machine-readable or computer-readable storage medium 1000 storing machine-readable instructions that, when executed, cause a system including a first electronic device and a second electronic device to perform various tasks. As an example, the first electronic device may be Figure 1 The main device 102-1, and the second electronic device may be Figure 1 For example, a system including a first electronic device and a second electronic device may be Figure 1 The MCLAG logic device 102. Alternatively, the system may be a larger system including additional components.

[0162] The machine-readable instructions include multi-chassis link aggregation instructions 1002 for providing multi-chassis link aggregation by a first electronic device and a second electronic device, the first electronic device and the second electronic device being part of a logical device supporting MCLAG. The first electronic device includes a first time clock (e.g., Figure 1 The master BTC 104-1), and the second electronic device includes a second time clock (e.g., Figure 1 Auxiliary BTC 104-2).

[0163] The machine-readable instructions include clock source selection instructions 1004 in the logic device, for performing a clock source selection process between a first time clock and a second time clock through a link between a first electronic device and a second electronic device in the logic device as part of a time synchronization process in the system to select one of the first time clock and the second time clock as a clock source, and select the other of the first time clock and the second time clock as a clock sink. For example, the clock source selection process may be an optimal clock source algorithm, such as PTP BMCA, such as Figure 3The ability to perform clock source selection within a logic device allows one of the time clocks of the MCLAG logic device to be designated as a clock source and another of the time clocks of the MCLAG logic device to be designated as a clock sink.

[0164] Based on the clock source selection process, the first time clock is selected as the clock sink, and the first time clock avoids sending a timing message for a time synchronization process by the first time clock to a time clock outside the logical device. The timing message can be a message (e.g., a notification message) used for a clock source selection process between a time clock in the logical device and a time clock outside the logical device. Alternatively, the timing message is a message (e.g., a synchronization message or a subsequent message) used to determine a time offset between a time clock in the logical device and a time clock outside the logical device. As a result, the time clock of the MCLAG logical device does not send redundant timing messages, which solves Problem 1 or Problem 3 discussed above.

[0165] In some examples, based on execution of the machine-readable instructions, the first time clock is a first boundary time clock and the second time clock is a second boundary time clock. The first and second boundary time clocks can perform a time synchronization process with at least one additional time clock external to the logical device. The first boundary time clock receives a first timing message from an external clock sink (e.g., a delay request message from the ordinary time clock 114 of the client device 112). The first boundary time clock determines whether the second boundary time clock is a clock source for the first boundary time clock. Based on determining that the second boundary time clock is a clock source for the first boundary time clock, the first boundary time clock forwards the first timing message from the first boundary time clock via a link between the first electronic device and the second electronic device of the logical device (e.g., Figure 8 822 in ) to the second boundary time clock. If the first timing message processed in the above manner is a delay request message, problem 5 is solved.

[0166] In some examples, based on execution of the machine-readable instructions, the first boundary time clock determines whether the second boundary time clock has an operational link status to the MCLAG. Forwarding the first timing message from the first boundary time clock to the second boundary time clock over the link is also based on determining (e.g., Figure 8 816) The second boundary time clock has an operational link status to MCLAG.

[0167] In some examples, based on determining that the second boundary time clock is a clock source for the first boundary time clock, the clock role of the first boundary time clock is changed from the boundary time clock role (e.g., Figure 8818 in the hybrid transparent time clock role. Forwarding the first timing message from the first boundary time clock to the second boundary time clock through the link occurs in the hybrid transparent time clock role.

[0168] In some examples, based on determining that the second boundary time clock is a clock source for the first boundary time clock, updating (eg, Figure 8 820) a header field (e.g., a correction field) of the first timing message, the time information being based on an ingress time of the first timing message at the first electronic device and an egress time when the first timing message is forwarded from the first electronic device to the second electronic device. The first timing message forwarded from the first boundary time clock to the second boundary time clock includes the updated header field.

[0169] In some examples, the second boundary time clock receives (e.g., Fig. 9 902 in) a first timing message forwarded from a first boundary time clock via a link, and a second boundary time clock determines (eg, Fig. 9 906) Whether the first timing message is received from the external clock sink at the first boundary time clock.

[0170] In some examples, determining whether a first timing message is received from an external clock sink at a first boundary time clock includes determining whether an interface identifier (e.g., portIdentity of PTP) extracted from the first timing message matches an interface identifier of an interface of a first electronic device with which a second boundary time clock has exchanged timing messages.

[0171] In some examples, based on determining at the second boundary time clock that the first timing message was received at the first boundary time clock from the external clock sink, the second boundary time clock accesses an interface identifier data structure for the first boundary time clock (e.g., at Fig. 9 The second boundary time clock processes the first timing message at the second boundary time clock based on the identification of the MCLAG using the interface identifier data structure, and sends a second timing message (e.g., a delay response message) in response to the first timing message (e.g., a delay request message) to the external clock sink through the MCLAG.

[0172] In some examples, based on the execution of the machine-readable instructions, the first time clock receives a timing message (e.g., a delayed response message) from an external clock source (e.g., the advanced clock source 108). The first time clock (e.g., 104-2) checks a data structure for the second time clock (e.g., the external clock source table 142-1) to determine whether the second time clock (e.g., 104-1) has previously identified the external clock source. Based on determining that the second time clock has previously identified the external clock source, the first time clock forwards the timing message from the first time clock to the second time clock via the link. This capability can address Problem 4 discussed above.

[0173] Fig.11 1 is a block diagram of a system 1100 including a first electronic device 1102 having a first boundary time clock 1104 and a second electronic device 1106 having a second boundary time clock 1108. The first electronic device 1102 and the second electronic device 1106 are part of a logic device 1110 that supports MCLAG. For example, the logic device 1110 may be Figure 1 The first boundary time clock 1104 and the second boundary time clock 1108 perform a time synchronization process with at least one other time clock external to the logic device 1110 .

[0174] The first boundary time clock 1104 can perform various tasks. These tasks include a timing message receiving task 1112 for receiving (e.g., Figure 4 402 or Figure 6 602) timing message (e.g., a synchronization message, a follow-up message, or a delayed response message).

[0175] These tasks include a data structure check task 1114 for checking (e.g., Figure 4 410 or Figure 6 610) for a data structure (eg, a peer external clock source table) of the second boundary time clock 1108 to determine whether the second boundary time clock 1108 has previously identified a clock source.

[0176] The tasks include a timing message forwarding task 1116 for forwarding a timing message or a receipt indication of a timing message from the first boundary time clock 1104 via a link 1118 between the first electronic device and the second electronic device 1102 and 1106 of the logic device 1110 based on determining that the second boundary time clock 1108 has previously identified a clock source (e.g., Figure 4 418 or Figure 6 616) to the second boundary time clock 1108.

[0177] In some examples, based on determining that the second boundary time clock has previously identified the clock source, the first boundary time clock 1104 may change the clock role of the first boundary time clock 1104 (eg, Figure 4 414 or Figure 6 616) is a hybrid transparent time clock role.

[0178] In some examples, in response to changing the clock role of the first boundary time clock 1104 to the hybrid transparent time clock role, the first boundary time clock 1104 forwards the timing message to the second boundary time clock 1108 via the link 1118 .

[0179] In some examples, in response to receiving a timing message at the second boundary time clock 1108 from the first boundary time clock 1104, the second boundary time clock 1108 extracts (eg, Figure 5 504 or Figure 7 704) source interface identifier (e.g., sourcePortIdentity according to PTP).

[0180] In some examples, the second boundary time clock 1108 determines (e.g., Figure 5 506 or Figure 7 The second boundary time clock 1108 determines whether the source interface identifier extracted by the second boundary time clock 1108 is present in the local external clock source table. If not, the second boundary time clock 1108 discards the timing message. If the extracted source interface identifier is present in the local external clock source table, the second boundary time clock 1108 maps the timing message to the given LAG interface and processes the timing message including responding through the given LAG interface.

[0181] In another example, the timing message is a synchronization message. Based on determining that the second boundary time clock has previously identified the clock source, the first boundary time clock 1104 forwards the receipt indication of the synchronization message to the second boundary time clock 1106. The first boundary time clock 1104 changes its clock role from the clock sink role to the clock source role. The first boundary time clock 1104 receives a notification message corresponding to the synchronization message from the second boundary time clock 1106 in response to the indication. The first boundary time clock 1104 maps the notification message to the corresponding LAG interface (of the MCLAG) that received the synchronization message at the first boundary time clock 1104. The first boundary time clock 1104 then processes (consumes) the synchronization message.

[0182] Fig.1212 is a flow diagram of a process 1200 that may be performed by a system including a first electronic device and a second electronic device. The process 1200 includes providing (at 1202) multi-chassis link aggregation by a first electronic device and a second electronic device that are part of a logic device that supports MCLAG. The first electronic device includes a first time clock, and the second electronic device includes a second time clock. The MCLAG includes a first set of network links connected to the first electronic device and a second set of network links connected to the second electronic device.

[0183] As part of the clock source selection process, process 1200 includes sending (at 1204) a first timing message including quality information associated with the first time clock from a first time clock to a second time clock via a link between a first electronic device and a second electronic device of a logic device. The first timing message may be a first announcement message.

[0184] As part of the clock source selection process, process 1200 includes sending (at 1206) a second timing message including quality information associated with the second time clock from the second time clock to the first time clock over the link. The second timing message may be a second announcement message.

[0185] As part of a clock source selection process, process 1200 includes selecting (at 1208) one of the first time clock and the second time clock as a clock source by the first time clock and the second time clock, and selecting the other of the first time clock and the second time clock as a clock sink for use in a time synchronization process in the system.

[0186] In another example, a system includes a first electronic device and a second electronic device. The system provides multi-chassis link aggregation through the first electronic device and the second electronic device as part of a logical device that supports MCLAG. The first electronic device includes a first time clock, and the second electronic device includes a second time clock. As part of a time synchronization process in the system, the first time clock and the second time clock perform a clock source selection process through a link between the first electronic device and the second electronic device of the logical device to select one of the first time clock and the second time clock as a clock source, and select the other of the first time clock and the second time clock as a clock sink.

[0187] In another example, a non-transitory machine-readable or computer-readable storage medium stores machine-readable instructions that, when executed, cause a system including a first electronic device and a second electronic device to perform various tasks. The first electronic device includes a first boundary time clock, and the second electronic device includes a second boundary time clock. The first electronic device and the second electronic device are part of a logic device that supports MCLAG. The first boundary time clock and the second boundary time clock are used to perform a time synchronization process with at least one other time clock outside the logic device. The time synchronization process includes the exchange of timing messages. The machine-readable instructions, when executed, cause the first time clock to receive a timing message from a clock source, check a data structure for the second boundary time clock to determine whether the second boundary time clock has previously identified the clock source, and based on determining that the second boundary time clock has previously identified the clock source, forward the timing message from the first boundary time clock to the second boundary time clock through a link between the first electronic device and the second electronic device of the logic device.

[0188] In another example, a process is performed by a system including a first electronic device and a second electronic device, wherein the first electronic device includes a first boundary time clock and the second electronic device includes a second boundary time clock, and the first electronic device and the second electronic device are part of a logic device that supports MCLAG. The process includes receiving a timing message from a clock source by the first boundary time clock, and checking a data structure for the second boundary time clock by the first boundary time clock to determine whether the second boundary time clock has previously identified the clock source. Based on determining that the second boundary time clock has previously identified the clock source, the process includes forwarding the timing message from the first boundary time clock to the second boundary time clock through a link between the first electronic device and the second electronic device of the logic device.

[0189] Storage media (e.g. Fig.101000) may include any or some combination of the following: semiconductor memory devices such as DRAM or SRAM, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), and flash memory; magnetic disks, such as fixed disks, floppy disks, and removable disks; another magnetic medium, including tape; optical media, such as compact disks (CDs) or digital video disks (DVDs); or other types of storage devices. Note that the instructions discussed above may be provided on one computer-readable or machine-readable storage medium, or alternatively, may be provided on multiple computer-readable or machine-readable storage media distributed in a large system that may have multiple nodes. Such one or more computer-readable or machine-readable storage media are considered to be part of an article (or manufactured article). An article or manufactured article may refer to any manufactured single component or multiple components. One or more storage media may be located in a machine that runs machine-readable instructions, or at a remote site from which machine-readable instructions may be downloaded over a network for execution.

[0190] In the present disclosure, unless the context clearly indicates otherwise, the use of the terms "a", "an" or "the" is also intended to include plural forms. In addition, when used in the present disclosure, the terms "comprises", "comprising", or "having" specify the presence of the elements described, but do not exclude the presence or addition of other elements.

[0191] In the foregoing description, many details are set forth to provide an understanding of the subject matter disclosed herein. However, these embodiments may be practiced without some of these details. Other embodiments may include modifications and variations to the details discussed above. The appended claims are intended to cover such modifications and variations.

Claims

1. A non-transitory machine-readable storage medium comprising instructions that, when executed, cause a system comprising a first electronic device and a second electronic device to: providing multi-chassis link aggregation by the first electronic device and the second electronic device, the first electronic device and the second electronic device being part of a logical device supporting a multi-chassis link aggregation group (MCLAG), wherein the first electronic device includes a first time clock and the second electronic device includes a second time clock; and As part of a time synchronization process in the system, a clock source selection process is performed between the first time clock and the second time clock through a link between the first electronic device and the second electronic device of the logic device to select one of the first time clock and the second time clock as a clock source, and to select the other of the first time clock and the second time clock as a clock sink.

2. The non-transitory machine-readable storage medium of claim 1 , wherein the first time clock is a first boundary time clock, the second time clock is a second boundary time clock, and the instructions when executed cause the system to: performing, by the first boundary time clock and the second boundary time clock, a time synchronization process with at least one other time clock external to the logic device, the time synchronization process comprising an exchange of timing messages; receiving a first timing message from an external clock sink at said first boundary time clock; determining, at the first boundary time clock, whether the second boundary time clock is a clock source for the first boundary time clock; as well as Based on determining that the second boundary time clock is the clock source for the first boundary time clock, the first timing message is forwarded from the first boundary time clock to the second boundary time clock through the link between the first electronic device and the second electronic device of the logic device.

3. The non-transitory machine-readable storage medium of claim 2, wherein the instructions, when executed, cause the system to: determining at the first boundary time clock whether the second boundary time clock has an operational link status to the MCLAG, Wherein forwarding the first timing message from the first boundary time clock to the second boundary time clock over the link is further based on determining that the second boundary time clock has an operational link status to the MCLAG.

4. The non-transitory machine-readable storage medium of claim 2, wherein determining at the first boundary time clock whether the second boundary time clock is the clock source for the first boundary time clock is based on a clock role indicator of the first boundary time clock, the clock role indicator being set by the clock source selection process.

5. The non-transitory machine-readable storage medium of claim 2, wherein the instructions, when executed, cause the system to: based on determining that the second boundary time clock is the clock source for the first boundary time clock, changing a clock role of the first boundary time clock from a boundary time clock role to a hybrid transparent time clock role, Wherein forwarding the first timing message from the first boundary time clock to the second boundary time clock via the link occurs in the hybrid transparent time clock role.

6. The non-transitory machine-readable storage medium of claim 2, wherein the instructions, when executed, cause the system to: based on determining that the second boundary time clock is the clock source for the first boundary time clock, updating a header field of the first timing message with time information based on an ingress time of the first timing message at the first electronic device and an egress time at which the first timing message is forwarded from the first electronic device to the second electronic device, The first timing message forwarded from the first boundary time clock to the second boundary time clock includes the updated header field. 7 . The non-transitory machine-readable storage medium of claim 6 , wherein the time information is based on a difference between the exit time and the entry time.

8. The non-transitory machine-readable storage medium of claim 2, wherein the instructions, when executed, cause the system to: receiving, at the second boundary time clock, the first timing message forwarded from the first boundary time clock over the link; and A determination is made at the second boundary time clock whether the first timing message is received from the external clock sink at the first boundary time clock.

9. The non-transitory machine-readable storage medium of claim 8, wherein determining whether the first timing message is received from the external clock sink at the first boundary time clock comprises: A determination is made as to whether the interface identifier extracted from the first timing message matches an interface identifier of an interface of the first electronic device with which the second boundary time clock has exchanged timing messages.

10. The non-transitory machine-readable storage medium of claim 8, wherein the instructions, when executed, cause the system to: based on determining at the second boundary time clock that the first timing message was received from the external clock sink at the first boundary time clock, accessing an interface identifier data structure for the first boundary time clock to identify the MCLAG; and Based on identifying the MCLAG using the interface identifier data structure, the first timing message is processed at the second boundary time clock, and a second timing message responsive to the first timing message is sent to the external clock sink through the MCLAG.

11. The non-transitory machine-readable storage medium of claim 10, wherein the first timing message is a delay request message used to calculate a time offset between a boundary time clock of the logic device and the external clock sink, wherein the instructions when executed cause the system to: As part of the learning process, the interface identifier data structure is updated in response to receipt of a delay request message to track the mapping of external clock sinks to one or more MCLAGs.

12. The non-transitory machine-readable storage medium of claim 2, wherein the first timing message comprises a delay request message according to a Precision Time Protocol (PTP).

13. The non-transitory machine-readable storage medium of claim 1 , wherein the instructions, when executed, cause the system to: Based on the selection of the first time clock as the clock sink by the clock source selection process, the first time clock is prevented from sending a timing message for a time synchronization process to a time clock outside the logic device.

14. The non-transitory machine-readable storage medium of claim 13, wherein the timing message is a message used in a clock source selection process between a time clock in the logic device and the time clock external to the logic device.

15. The non-transitory machine-readable storage medium of claim 13, wherein the timing message is a message used to determine a time offset between a time clock in the logic device and the time clock external to the logic device.

16. The non-transitory machine-readable storage medium of claim 1, wherein the instructions, when executed, cause the system to: receiving, at said first time clock, a timing message from an external clock source; checking a data structure for the second time clock to determine whether the second time clock has previously identified the external clock source; as well as The timing message or an indication of receipt of the timing message is forwarded from the first time clock to the second time clock over the link based on determining that the second time clock has previously identified the external clock source.

17. A system comprising: A first electronic device including a first boundary time clock; a second electronic device including a second boundary time clock, wherein the first electronic device and the second electronic device are part of a logical device supporting a multi-chassis link aggregation group MCLAG, wherein the first boundary time clock and the second boundary time clock are used to perform a time synchronization process with at least one other time clock external to the logic device, the time synchronization process comprising the exchange of timing messages, and The first boundary time clock is used for: Receive timing messages from a clock source, checking a data structure for the second boundary time clock to determine whether the second boundary time clock has previously identified the clock source, and Based on determining that the second boundary time clock has previously identified the clock source, the timing message or an indication of receipt of the timing message is forwarded from the first boundary time clock to the second boundary time clock via a link between the first electronic device and the second electronic device of the logic device.

18. The system of claim 17, wherein the timing message comprises a synchronization message, or a follow-up message, or a delayed response message.

19. A method of a system including a first electronic device and a second electronic device, the method comprising: providing multi-chassis link aggregation by the first electronic device and the second electronic device, the first electronic device and the second electronic device being part of a logical device supporting a multi-chassis link aggregation group MCLAG, wherein the first electronic device includes a first time clock and the second electronic device includes a second time clock, wherein the MCLAG includes a first set of network links connected to the first electronic device and a second set of network links connected to the second electronic device; and As part of the clock source selection process: sending a first timing message including quality information associated with the first time clock from the first time clock to the second time clock via a link between the first electronic device and the second electronic device of the logic device, sending a second timing message including quality information associated with the second time clock from the second time clock to the first time clock via the link, and One of the first time clock and the second time clock is selected by the first time clock and the second time clock as a clock source, and the other of the first time clock and the second time clock is selected as a clock sink for a time synchronization process in the system.

20. The method of claim 19, wherein the first timing message comprises a first announce message of a Precision Time Protocol (PTP), and the second timing message comprises a second announce message of the PTP.

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